Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	7408999	1			T1	68855		T3	20926		T8	42
all_levels[1]	1456268	1			T1	1546		T2	28		T3	10009
all_levels[2]	266600	1			T1	1506		T2	1186		T3	3431
all_levels[3]	227204	1			T1	1528		T3	3160		T8	2
all_levels[4]	290840	1			T1	1983		T3	2346		T8	391
all_levels[5]	182210	1			T1	1516		T3	3377		T9	1359
all_levels[6]	333971	1			T1	1514		T3	3243		T9	1353
all_levels[7]	286612	1			T1	1517		T3	2798		T9	1118
all_levels[8]	191660	1			T1	1504		T3	2029		T9	1680
all_levels[9]	594748	1			T1	1508		T3	2777		T9	1679
all_levels[10]	214377	1			T1	1512		T3	2561		T9	23427
all_levels[11]	238538	1			T1	1511		T3	2109		T9	49324
all_levels[12]	269081	1			T1	1521		T3	2260		T9	1249
all_levels[13]	201422	1			T1	1566		T3	1892		T9	1083
all_levels[14]	172587	1			T1	2153		T3	634		T9	1357
all_levels[15]	172410	1			T1	1514		T3	431		T9	682
all_levels[16]	215219	1			T1	1490		T3	669		T9	1000
all_levels[17]	164203	1			T1	1523		T3	587		T9	1107
all_levels[18]	315920	1			T1	1503		T3	421		T9	866
all_levels[19]	338694	1			T1	1495		T3	546		T9	1130
all_levels[20]	175061	1			T1	1503		T3	753		T9	945
all_levels[21]	270086	1			T1	1505		T3	685		T9	893
all_levels[22]	392427	1			T1	1503		T3	594		T9	880
all_levels[23]	169997	1			T1	1508		T3	557		T9	1219
all_levels[24]	154340	1			T1	1505		T3	707		T9	1094
all_levels[25]	150358	1			T1	1500		T3	617		T9	742
all_levels[26]	225925	1			T1	1513		T3	529		T9	1154
all_levels[27]	402018	1			T1	1511		T3	637		T9	942
all_levels[28]	209942	1			T1	1476		T3	521		T9	1226
all_levels[29]	288296	1			T1	16243		T3	622		T9	890
all_levels[30]	136557	1			T1	517		T3	630		T9	873
all_levels[31]	544282	1			T1	534		T3	1124		T9	3859
all_levels[32]	11888392	1			T1	19073		T3	89283		T9	40920

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28545106

1

T1

148648

T2

1187

T3

163453

auto[1]

4138

1

T1

8

T2

27

T3

12

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	7406583	1			T1	68854		T3	20915		T8	7
all_levels[0]	auto[1]	2416	1			T1	1		T3	11		T8	35
all_levels[1]	auto[0]	1455977	1			T1	1545		T2	1		T3	10009
all_levels[1]	auto[1]	291	1			T1	1		T2	27		T30	1
all_levels[2]	auto[0]	266568	1			T1	1506		T2	1186		T3	3431
all_levels[2]	auto[1]	32	1			T326	1		T327	1		T328	1
all_levels[3]	auto[0]	227077	1			T1	1528		T3	3160		T8	1
all_levels[3]	auto[1]	127	1			T8	1		T18	1		T95	3
all_levels[4]	auto[0]	290824	1			T1	1983		T3	2346		T8	391
all_levels[4]	auto[1]	16	1			T122	1		T302	1		T329	3
all_levels[5]	auto[0]	182160	1			T1	1516		T3	3377		T9	1359
all_levels[5]	auto[1]	50	1			T18	1		T30	1		T59	22
all_levels[6]	auto[0]	333954	1			T1	1514		T3	3243		T9	1353
all_levels[6]	auto[1]	17	1			T125	1		T94	1		T256	2
all_levels[7]	auto[0]	286482	1			T1	1517		T3	2798		T9	1118
all_levels[7]	auto[1]	130	1			T33	1		T242	7		T319	1
all_levels[8]	auto[0]	191635	1			T1	1504		T3	2029		T9	1680
all_levels[8]	auto[1]	25	1			T16	1		T107	1		T197	1
all_levels[9]	auto[0]	594731	1			T1	1508		T3	2777		T9	1679
all_levels[9]	auto[1]	17	1			T322	1		T304	1		T217	2
all_levels[10]	auto[0]	214352	1			T1	1512		T3	2561		T9	23427
all_levels[10]	auto[1]	25	1			T263	1		T125	1		T76	1
all_levels[11]	auto[0]	238513	1			T1	1511		T3	2109		T9	49323
all_levels[11]	auto[1]	25	1			T9	1		T256	1		T319	1
all_levels[12]	auto[0]	269059	1			T1	1521		T3	2260		T9	1249
all_levels[12]	auto[1]	22	1			T33	1		T94	1		T149	1
all_levels[13]	auto[0]	201399	1			T1	1566		T3	1892		T9	1083
all_levels[13]	auto[1]	23	1			T78	1		T314	1		T330	1
all_levels[14]	auto[0]	172564	1			T1	2153		T3	634		T9	1357
all_levels[14]	auto[1]	23	1			T16	1		T106	2		T331	1
all_levels[15]	auto[0]	172261	1			T1	1509		T3	431		T9	682
all_levels[15]	auto[1]	149	1			T1	5		T267	3		T27	3
all_levels[16]	auto[0]	215202	1			T1	1490		T3	669		T9	1000
all_levels[16]	auto[1]	17	1			T163	2		T271	1		T121	2
all_levels[17]	auto[0]	164193	1			T1	1523		T3	587		T9	1107
all_levels[17]	auto[1]	10	1			T30	1		T123	1		T314	1
all_levels[18]	auto[0]	315904	1			T1	1503		T3	421		T9	866
all_levels[18]	auto[1]	16	1			T332	1		T151	1		T180	3
all_levels[19]	auto[0]	338672	1			T1	1495		T3	546		T9	1130
all_levels[19]	auto[1]	22	1			T106	1		T125	1		T264	1
all_levels[20]	auto[0]	175047	1			T1	1503		T3	753		T9	945
all_levels[20]	auto[1]	14	1			T333	1		T102	4		T156	1
all_levels[21]	auto[0]	270067	1			T1	1505		T3	685		T9	893
all_levels[21]	auto[1]	19	1			T256	1		T117	1		T175	1
all_levels[22]	auto[0]	392409	1			T1	1503		T3	594		T9	880
all_levels[22]	auto[1]	18	1			T169	1		T170	2		T334	1
all_levels[23]	auto[0]	169976	1			T1	1508		T3	557		T9	1219
all_levels[23]	auto[1]	21	1			T263	2		T116	4		T320	1
all_levels[24]	auto[0]	154315	1			T1	1505		T3	707		T9	1094
all_levels[24]	auto[1]	25	1			T203	3		T186	1		T150	2
all_levels[25]	auto[0]	150343	1			T1	1500		T3	617		T9	742
all_levels[25]	auto[1]	15	1			T118	2		T335	3		T133	1
all_levels[26]	auto[0]	225915	1			T1	1513		T3	529		T9	1154
all_levels[26]	auto[1]	10	1			T336	1		T139	1		T337	1
all_levels[27]	auto[0]	402002	1			T1	1511		T3	637		T9	942
all_levels[27]	auto[1]	16	1			T163	2		T17	1		T295	1
all_levels[28]	auto[0]	209930	1			T1	1476		T3	521		T9	1226
all_levels[28]	auto[1]	12	1			T18	1		T158	1		T338	1
all_levels[29]	auto[0]	288282	1			T1	16243		T3	622		T9	890
all_levels[29]	auto[1]	14	1			T202	3		T177	2		T194	1
all_levels[30]	auto[0]	136541	1			T1	517		T3	630		T9	873
all_levels[30]	auto[1]	16	1			T33	2		T262	1		T322	1
all_levels[31]	auto[0]	544256	1			T1	534		T3	1124		T9	3859
all_levels[31]	auto[1]	26	1			T136	1		T122	4		T217	1
all_levels[32]	auto[0]	11887913	1			T1	19072		T3	89282		T9	40920
all_levels[32]	auto[1]	479	1			T1	1		T3	1		T11	1