Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	536	1			T9	4		T15	4		T16	7
all_values[1]	536	1			T9	4		T15	4		T16	7
all_values[2]	536	1			T9	4		T15	4		T16	7
all_values[3]	536	1			T9	4		T15	4		T16	7
all_values[4]	536	1			T9	4		T15	4		T16	7
all_values[5]	536	1			T9	4		T15	4		T16	7
all_values[6]	536	1			T9	4		T15	4		T16	7
all_values[7]	536	1			T9	4		T15	4		T16	7
all_values[8]	536	1			T9	4		T15	4		T16	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2615

1

T9

22

T15

21

T16

36

auto[1]

2209

1

T9

14

T15

15

T16

27

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1569

1

T9

15

T15

10

T16

27

auto[1]

3255

1

T9

21

T15

26

T16

36

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2860

1

T9

23

T15

22

T16

41

auto[1]

1964

1

T9

13

T15

14

T16

22

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	183	1			T9	1		T15	1		T16	2
all_values[0]	auto[0]	auto[1]	auto[1]	137	1			T9	1		T15	1		T16	3
all_values[0]	auto[1]	auto[0]	auto[1]	115	1			T9	2		T15	2		T59	1
all_values[0]	auto[1]	auto[1]	auto[1]	101	1			T16	2		T59	4		T98	2
all_values[1]	auto[0]	auto[0]	auto[0]	150	1			T9	3		T15	1		T16	3
all_values[1]	auto[0]	auto[1]	auto[0]	155	1			T16	3		T59	6		T98	2
all_values[1]	auto[1]	auto[0]	auto[1]	144	1			T15	2		T98	4		T99	5
all_values[1]	auto[1]	auto[1]	auto[1]	87	1			T9	1		T15	1		T16	1
all_values[2]	auto[0]	auto[0]	auto[0]	113	1			T15	1		T16	3		T99	1
all_values[2]	auto[0]	auto[0]	auto[1]	51	1			T15	1		T98	2		T100	1
all_values[2]	auto[0]	auto[1]	auto[0]	98	1			T9	1		T16	2		T59	4
all_values[2]	auto[0]	auto[1]	auto[1]	47	1			T59	2		T99	1		T101	2
all_values[2]	auto[1]	auto[0]	auto[1]	110	1			T9	2		T15	1		T59	1
all_values[2]	auto[1]	auto[1]	auto[1]	117	1			T9	1		T15	1		T16	2
all_values[3]	auto[0]	auto[0]	auto[0]	119	1			T9	2		T15	2		T16	2
all_values[3]	auto[0]	auto[0]	auto[1]	65	1			T16	1		T59	2		T98	2
all_values[3]	auto[0]	auto[1]	auto[0]	88	1			T9	2		T15	1		T16	1
all_values[3]	auto[0]	auto[1]	auto[1]	47	1			T98	1		T101	1		T102	2
all_values[3]	auto[1]	auto[0]	auto[1]	136	1			T16	2		T59	2		T99	3
all_values[3]	auto[1]	auto[1]	auto[1]	81	1			T15	1		T16	1		T59	1
all_values[4]	auto[0]	auto[0]	auto[0]	119	1			T9	1		T16	1		T59	7
all_values[4]	auto[0]	auto[0]	auto[1]	48	1			T9	1		T15	1		T99	1
all_values[4]	auto[0]	auto[1]	auto[0]	98	1			T9	1		T16	1		T98	2
all_values[4]	auto[0]	auto[1]	auto[1]	53	1			T15	2		T16	2		T59	1
all_values[4]	auto[1]	auto[0]	auto[1]	112	1			T9	1		T15	1		T16	2
all_values[4]	auto[1]	auto[1]	auto[1]	106	1			T16	1		T59	2		T98	2
all_values[5]	auto[0]	auto[0]	auto[0]	109	1			T15	2		T16	4		T59	1
all_values[5]	auto[0]	auto[0]	auto[1]	56	1			T99	2		T103	1		T104	2
all_values[5]	auto[0]	auto[1]	auto[0]	98	1			T15	1		T16	1		T59	1
all_values[5]	auto[0]	auto[1]	auto[1]	46	1			T9	1		T59	2		T102	2
all_values[5]	auto[1]	auto[0]	auto[1]	121	1			T9	1		T15	1		T59	3
all_values[5]	auto[1]	auto[1]	auto[1]	106	1			T9	2		T16	2		T59	4
all_values[6]	auto[0]	auto[0]	auto[0]	118	1			T9	2		T16	3		T59	5
all_values[6]	auto[0]	auto[0]	auto[1]	68	1			T15	2		T16	1		T59	3
all_values[6]	auto[0]	auto[1]	auto[0]	94	1			T98	1		T102	4		T100	6
all_values[6]	auto[0]	auto[1]	auto[1]	53	1			T15	1		T101	1		T102	5
all_values[6]	auto[1]	auto[0]	auto[1]	111	1			T9	2		T15	1		T16	3
all_values[6]	auto[1]	auto[1]	auto[1]	92	1			T59	1		T101	1		T102	1
all_values[7]	auto[0]	auto[0]	auto[0]	118	1			T9	1		T15	1		T16	3
all_values[7]	auto[0]	auto[0]	auto[1]	55	1			T59	1		T98	1		T102	1
all_values[7]	auto[0]	auto[1]	auto[0]	92	1			T9	2		T15	1		T59	4
all_values[7]	auto[0]	auto[1]	auto[1]	61	1			T15	1		T59	2		T99	2
all_values[7]	auto[1]	auto[0]	auto[1]	114	1			T9	1		T16	3		T59	1
all_values[7]	auto[1]	auto[1]	auto[1]	96	1			T15	1		T16	1		T59	3
all_values[8]	auto[0]	auto[0]	auto[1]	157	1			T9	2		T15	1		T16	1
all_values[8]	auto[0]	auto[1]	auto[1]	164	1			T9	2		T15	1		T16	4
all_values[8]	auto[1]	auto[0]	auto[1]	123	1			T16	2		T59	3		T98	1
all_values[8]	auto[1]	auto[1]	auto[1]	92	1			T15	2		T59	2		T98	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal