Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.11 99.10 97.65 100.00 98.38 100.00 99.55


Total test records in report: 1234
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T1034 /workspace/coverage/default/1.uart_intr.3585614493 Jun 11 12:28:47 PM PDT 24 Jun 11 12:29:07 PM PDT 24 32546653276 ps
T1035 /workspace/coverage/default/27.uart_rx_oversample.1862254421 Jun 11 12:30:10 PM PDT 24 Jun 11 12:30:46 PM PDT 24 6080804405 ps
T1036 /workspace/coverage/default/5.uart_fifo_full.4122571270 Jun 11 12:29:03 PM PDT 24 Jun 11 12:29:20 PM PDT 24 18170420513 ps
T1037 /workspace/coverage/default/19.uart_rx_start_bit_filter.1110437330 Jun 11 12:29:40 PM PDT 24 Jun 11 12:29:45 PM PDT 24 6624031502 ps
T1038 /workspace/coverage/default/297.uart_fifo_reset.191743226 Jun 11 12:32:28 PM PDT 24 Jun 11 12:32:45 PM PDT 24 8983426303 ps
T1039 /workspace/coverage/default/25.uart_long_xfer_wo_dly.2950390954 Jun 11 12:30:10 PM PDT 24 Jun 11 12:33:19 PM PDT 24 320649233870 ps
T1040 /workspace/coverage/default/27.uart_smoke.2706486954 Jun 11 12:29:52 PM PDT 24 Jun 11 12:30:05 PM PDT 24 6033134900 ps
T1041 /workspace/coverage/default/4.uart_stress_all.3253196587 Jun 11 12:29:16 PM PDT 24 Jun 11 12:44:22 PM PDT 24 150426712993 ps
T1042 /workspace/coverage/default/18.uart_perf.867918915 Jun 11 12:29:47 PM PDT 24 Jun 11 12:42:15 PM PDT 24 24727536931 ps
T1043 /workspace/coverage/default/35.uart_smoke.3120894274 Jun 11 12:30:29 PM PDT 24 Jun 11 12:30:33 PM PDT 24 935723805 ps
T1044 /workspace/coverage/default/128.uart_fifo_reset.3237009837 Jun 11 12:31:44 PM PDT 24 Jun 11 12:31:56 PM PDT 24 41629645072 ps
T1045 /workspace/coverage/default/34.uart_intr.4105719172 Jun 11 12:30:29 PM PDT 24 Jun 11 12:36:25 PM PDT 24 161378963061 ps
T1046 /workspace/coverage/default/58.uart_stress_all_with_rand_reset.466045923 Jun 11 12:31:13 PM PDT 24 Jun 11 12:39:41 PM PDT 24 20175073883 ps
T1047 /workspace/coverage/default/4.uart_rx_start_bit_filter.1070338186 Jun 11 12:29:02 PM PDT 24 Jun 11 12:29:06 PM PDT 24 6434856201 ps
T1048 /workspace/coverage/default/28.uart_alert_test.1940575195 Jun 11 12:30:14 PM PDT 24 Jun 11 12:30:17 PM PDT 24 32789277 ps
T1049 /workspace/coverage/default/62.uart_stress_all_with_rand_reset.1135013997 Jun 11 12:31:27 PM PDT 24 Jun 11 12:46:55 PM PDT 24 62233888146 ps
T1050 /workspace/coverage/default/134.uart_fifo_reset.3139324916 Jun 11 12:31:53 PM PDT 24 Jun 11 12:32:13 PM PDT 24 11444810684 ps
T1051 /workspace/coverage/default/7.uart_fifo_overflow.2583260353 Jun 11 12:29:05 PM PDT 24 Jun 11 12:29:58 PM PDT 24 112467727838 ps
T1052 /workspace/coverage/default/285.uart_fifo_reset.2468462766 Jun 11 12:32:18 PM PDT 24 Jun 11 12:32:38 PM PDT 24 38500063100 ps
T1053 /workspace/coverage/default/95.uart_fifo_reset.882531291 Jun 11 12:31:40 PM PDT 24 Jun 11 12:32:09 PM PDT 24 178618914876 ps
T1054 /workspace/coverage/default/278.uart_fifo_reset.2803482092 Jun 11 12:32:18 PM PDT 24 Jun 11 12:33:20 PM PDT 24 32205025822 ps
T1055 /workspace/coverage/default/251.uart_fifo_reset.2079226128 Jun 11 12:32:16 PM PDT 24 Jun 11 12:33:04 PM PDT 24 57730206129 ps
T1056 /workspace/coverage/default/272.uart_fifo_reset.4267854945 Jun 11 12:32:16 PM PDT 24 Jun 11 12:34:01 PM PDT 24 64969345356 ps
T1057 /workspace/coverage/default/45.uart_fifo_full.3697814669 Jun 11 12:31:01 PM PDT 24 Jun 11 12:31:52 PM PDT 24 124817300824 ps
T1058 /workspace/coverage/default/44.uart_loopback.1513177758 Jun 11 12:31:01 PM PDT 24 Jun 11 12:31:04 PM PDT 24 116075262 ps
T1059 /workspace/coverage/default/11.uart_rx_start_bit_filter.220495735 Jun 11 12:29:42 PM PDT 24 Jun 11 12:29:56 PM PDT 24 25980371330 ps
T1060 /workspace/coverage/default/57.uart_fifo_reset.2922602249 Jun 11 12:31:14 PM PDT 24 Jun 11 12:31:53 PM PDT 24 21839508611 ps
T1061 /workspace/coverage/default/0.uart_fifo_overflow.2916548343 Jun 11 12:29:02 PM PDT 24 Jun 11 12:29:26 PM PDT 24 14501590583 ps
T1062 /workspace/coverage/default/120.uart_fifo_reset.2280639772 Jun 11 12:31:39 PM PDT 24 Jun 11 12:32:53 PM PDT 24 28593921190 ps
T1063 /workspace/coverage/default/5.uart_loopback.2179576244 Jun 11 12:29:00 PM PDT 24 Jun 11 12:29:02 PM PDT 24 3039255386 ps
T1064 /workspace/coverage/default/23.uart_stress_all.2081691934 Jun 11 12:29:48 PM PDT 24 Jun 11 12:31:42 PM PDT 24 272241076042 ps
T1065 /workspace/coverage/default/17.uart_smoke.3439419984 Jun 11 12:29:44 PM PDT 24 Jun 11 12:29:49 PM PDT 24 669721610 ps
T1066 /workspace/coverage/default/39.uart_fifo_overflow.2711619407 Jun 11 12:30:46 PM PDT 24 Jun 11 12:33:04 PM PDT 24 159948502907 ps
T1067 /workspace/coverage/default/42.uart_loopback.1267356612 Jun 11 12:31:10 PM PDT 24 Jun 11 12:31:16 PM PDT 24 7432190645 ps
T1068 /workspace/coverage/default/18.uart_loopback.2188993496 Jun 11 12:29:24 PM PDT 24 Jun 11 12:29:33 PM PDT 24 9433003227 ps
T1069 /workspace/coverage/default/28.uart_rx_parity_err.1575258877 Jun 11 12:30:04 PM PDT 24 Jun 11 12:32:23 PM PDT 24 72560267196 ps
T1070 /workspace/coverage/default/40.uart_perf.3834541266 Jun 11 12:30:49 PM PDT 24 Jun 11 12:34:32 PM PDT 24 17514275086 ps
T1071 /workspace/coverage/default/28.uart_loopback.861707442 Jun 11 12:30:11 PM PDT 24 Jun 11 12:30:18 PM PDT 24 6138725792 ps
T1072 /workspace/coverage/default/0.uart_tx_ovrd.1733592327 Jun 11 12:28:48 PM PDT 24 Jun 11 12:29:06 PM PDT 24 7113164181 ps
T1073 /workspace/coverage/default/8.uart_rx_oversample.372064827 Jun 11 12:29:10 PM PDT 24 Jun 11 12:29:56 PM PDT 24 5242514301 ps
T1074 /workspace/coverage/default/38.uart_rx_start_bit_filter.1129268349 Jun 11 12:30:47 PM PDT 24 Jun 11 12:30:50 PM PDT 24 1609616687 ps
T1075 /workspace/coverage/default/18.uart_fifo_full.4057859704 Jun 11 12:29:46 PM PDT 24 Jun 11 12:30:18 PM PDT 24 281743342646 ps
T1076 /workspace/coverage/default/64.uart_stress_all_with_rand_reset.3794285186 Jun 11 12:31:27 PM PDT 24 Jun 11 12:33:07 PM PDT 24 120582098124 ps
T1077 /workspace/coverage/default/18.uart_stress_all.3060653822 Jun 11 12:29:46 PM PDT 24 Jun 11 12:44:36 PM PDT 24 537953990910 ps
T1078 /workspace/coverage/default/44.uart_tx_rx.866062181 Jun 11 12:31:02 PM PDT 24 Jun 11 12:32:36 PM PDT 24 98387807604 ps
T1079 /workspace/coverage/default/35.uart_fifo_full.2055061460 Jun 11 12:30:30 PM PDT 24 Jun 11 12:31:52 PM PDT 24 232531609057 ps
T1080 /workspace/coverage/default/32.uart_fifo_overflow.643858048 Jun 11 12:30:18 PM PDT 24 Jun 11 12:31:15 PM PDT 24 30089927650 ps
T1081 /workspace/coverage/default/29.uart_fifo_overflow.2939487233 Jun 11 12:30:16 PM PDT 24 Jun 11 12:31:08 PM PDT 24 26892731072 ps
T233 /workspace/coverage/default/286.uart_fifo_reset.500852010 Jun 11 12:32:17 PM PDT 24 Jun 11 12:32:34 PM PDT 24 30170966785 ps
T1082 /workspace/coverage/default/167.uart_fifo_reset.743946947 Jun 11 12:31:49 PM PDT 24 Jun 11 12:32:18 PM PDT 24 35863901817 ps
T1083 /workspace/coverage/default/40.uart_loopback.2427938431 Jun 11 12:30:48 PM PDT 24 Jun 11 12:30:51 PM PDT 24 640953748 ps
T1084 /workspace/coverage/default/13.uart_fifo_full.5200719 Jun 11 12:29:37 PM PDT 24 Jun 11 12:31:09 PM PDT 24 53049428333 ps
T230 /workspace/coverage/default/4.uart_fifo_reset.3629121760 Jun 11 12:29:04 PM PDT 24 Jun 11 12:29:38 PM PDT 24 30509434299 ps
T1085 /workspace/coverage/default/20.uart_rx_start_bit_filter.1154271867 Jun 11 12:29:48 PM PDT 24 Jun 11 12:29:58 PM PDT 24 4527307651 ps
T1086 /workspace/coverage/default/47.uart_tx_ovrd.3898151510 Jun 11 12:31:14 PM PDT 24 Jun 11 12:31:27 PM PDT 24 9073554745 ps
T1087 /workspace/coverage/default/46.uart_fifo_full.2683145291 Jun 11 12:31:02 PM PDT 24 Jun 11 12:32:54 PM PDT 24 67228176822 ps
T1088 /workspace/coverage/default/16.uart_fifo_full.3280206563 Jun 11 12:29:27 PM PDT 24 Jun 11 12:35:07 PM PDT 24 121374893555 ps
T1089 /workspace/coverage/default/15.uart_loopback.1424069649 Jun 11 12:29:24 PM PDT 24 Jun 11 12:29:40 PM PDT 24 6807862187 ps
T1090 /workspace/coverage/default/6.uart_rx_parity_err.152981472 Jun 11 12:30:05 PM PDT 24 Jun 11 12:30:48 PM PDT 24 79907017785 ps
T1091 /workspace/coverage/default/7.uart_fifo_full.1864512069 Jun 11 12:30:17 PM PDT 24 Jun 11 12:31:25 PM PDT 24 47988223382 ps
T1092 /workspace/coverage/default/10.uart_intr.2353229718 Jun 11 12:29:15 PM PDT 24 Jun 11 12:29:52 PM PDT 24 20055781195 ps
T1093 /workspace/coverage/default/293.uart_fifo_reset.4026713752 Jun 11 12:32:20 PM PDT 24 Jun 11 12:32:35 PM PDT 24 33002879712 ps
T1094 /workspace/coverage/default/188.uart_fifo_reset.1106344604 Jun 11 12:31:54 PM PDT 24 Jun 11 12:32:03 PM PDT 24 14031766187 ps
T1095 /workspace/coverage/default/9.uart_perf.1384153197 Jun 11 12:29:36 PM PDT 24 Jun 11 12:32:38 PM PDT 24 16930957968 ps
T1096 /workspace/coverage/default/71.uart_fifo_reset.2075287385 Jun 11 12:31:29 PM PDT 24 Jun 11 12:33:51 PM PDT 24 148918818119 ps
T1097 /workspace/coverage/default/30.uart_stress_all.3561330505 Jun 11 12:30:13 PM PDT 24 Jun 11 12:33:19 PM PDT 24 112166327471 ps
T1098 /workspace/coverage/default/34.uart_stress_all.394338905 Jun 11 12:30:42 PM PDT 24 Jun 11 12:31:20 PM PDT 24 10743802221 ps
T1099 /workspace/coverage/default/0.uart_smoke.729618707 Jun 11 12:29:09 PM PDT 24 Jun 11 12:29:12 PM PDT 24 524619544 ps
T1100 /workspace/coverage/default/26.uart_alert_test.745398881 Jun 11 12:29:51 PM PDT 24 Jun 11 12:29:54 PM PDT 24 40298743 ps
T60 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.4118811050 Jun 11 12:25:02 PM PDT 24 Jun 11 12:25:06 PM PDT 24 110284776 ps
T49 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1867783109 Jun 11 12:25:11 PM PDT 24 Jun 11 12:25:14 PM PDT 24 80483217 ps
T1101 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.1784071118 Jun 11 12:21:31 PM PDT 24 Jun 11 12:21:33 PM PDT 24 131493594 ps
T61 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.764423345 Jun 11 12:25:03 PM PDT 24 Jun 11 12:25:07 PM PDT 24 195962929 ps
T50 /workspace/coverage/cover_reg_top/6.uart_csr_rw.3823984198 Jun 11 12:24:52 PM PDT 24 Jun 11 12:24:55 PM PDT 24 37559859 ps
T62 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.2939291368 Jun 11 12:25:16 PM PDT 24 Jun 11 12:25:18 PM PDT 24 174493996 ps
T1102 /workspace/coverage/cover_reg_top/46.uart_intr_test.1147277787 Jun 11 12:25:24 PM PDT 24 Jun 11 12:25:25 PM PDT 24 73332166 ps
T1103 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3888747005 Jun 11 12:25:02 PM PDT 24 Jun 11 12:25:05 PM PDT 24 89842864 ps
T1104 /workspace/coverage/cover_reg_top/2.uart_tl_errors.3001347041 Jun 11 12:24:55 PM PDT 24 Jun 11 12:25:00 PM PDT 24 39726672 ps
T105 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.637108018 Jun 11 12:24:55 PM PDT 24 Jun 11 12:24:59 PM PDT 24 106716286 ps
T1105 /workspace/coverage/cover_reg_top/30.uart_intr_test.3373134622 Jun 11 12:25:11 PM PDT 24 Jun 11 12:25:13 PM PDT 24 13916181 ps
T67 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3324805710 Jun 11 12:24:53 PM PDT 24 Jun 11 12:24:57 PM PDT 24 69101988 ps
T1106 /workspace/coverage/cover_reg_top/5.uart_intr_test.4209900332 Jun 11 12:25:01 PM PDT 24 Jun 11 12:25:04 PM PDT 24 16003968 ps
T1107 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.729985920 Jun 11 12:21:09 PM PDT 24 Jun 11 12:21:12 PM PDT 24 175211758 ps
T1108 /workspace/coverage/cover_reg_top/29.uart_intr_test.682206383 Jun 11 12:25:12 PM PDT 24 Jun 11 12:25:14 PM PDT 24 11044938 ps
T1109 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3970749413 Jun 11 12:25:01 PM PDT 24 Jun 11 12:25:05 PM PDT 24 178962298 ps
T1110 /workspace/coverage/cover_reg_top/23.uart_intr_test.185972487 Jun 11 12:25:16 PM PDT 24 Jun 11 12:25:18 PM PDT 24 37568051 ps
T1111 /workspace/coverage/cover_reg_top/14.uart_tl_errors.2754659202 Jun 11 12:25:03 PM PDT 24 Jun 11 12:25:08 PM PDT 24 355882570 ps
T38 /workspace/coverage/cover_reg_top/2.uart_csr_rw.1540893427 Jun 11 12:25:04 PM PDT 24 Jun 11 12:25:08 PM PDT 24 186027182 ps
T1112 /workspace/coverage/cover_reg_top/8.uart_tl_errors.1278483411 Jun 11 12:24:56 PM PDT 24 Jun 11 12:25:01 PM PDT 24 505100397 ps
T51 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.2472730426 Jun 11 12:24:57 PM PDT 24 Jun 11 12:25:01 PM PDT 24 30744521 ps
T1113 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1782690366 Jun 11 12:24:55 PM PDT 24 Jun 11 12:24:59 PM PDT 24 52071115 ps
T1114 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.4257506127 Jun 11 12:25:03 PM PDT 24 Jun 11 12:25:07 PM PDT 24 19991726 ps
T1115 /workspace/coverage/cover_reg_top/16.uart_intr_test.3743390255 Jun 11 12:25:14 PM PDT 24 Jun 11 12:25:16 PM PDT 24 15364864 ps
T52 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3780355246 Jun 11 12:24:53 PM PDT 24 Jun 11 12:24:55 PM PDT 24 37532054 ps
T39 /workspace/coverage/cover_reg_top/18.uart_csr_rw.4229179371 Jun 11 12:25:12 PM PDT 24 Jun 11 12:25:15 PM PDT 24 13001602 ps
T1116 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.2961517874 Jun 11 12:25:05 PM PDT 24 Jun 11 12:25:10 PM PDT 24 97181707 ps
T53 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.202304247 Jun 11 12:22:27 PM PDT 24 Jun 11 12:22:29 PM PDT 24 81157241 ps
T1117 /workspace/coverage/cover_reg_top/25.uart_intr_test.1532196212 Jun 11 12:25:08 PM PDT 24 Jun 11 12:25:11 PM PDT 24 46054253 ps
T1118 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2027421729 Jun 11 12:22:52 PM PDT 24 Jun 11 12:22:55 PM PDT 24 33424599 ps
T1119 /workspace/coverage/cover_reg_top/39.uart_intr_test.3426630748 Jun 11 12:25:16 PM PDT 24 Jun 11 12:25:18 PM PDT 24 15350102 ps
T1120 /workspace/coverage/cover_reg_top/12.uart_intr_test.832300749 Jun 11 12:24:54 PM PDT 24 Jun 11 12:24:57 PM PDT 24 12319106 ps
T54 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2781668654 Jun 11 12:24:55 PM PDT 24 Jun 11 12:24:59 PM PDT 24 113265651 ps
T1121 /workspace/coverage/cover_reg_top/9.uart_intr_test.155077024 Jun 11 12:24:53 PM PDT 24 Jun 11 12:24:55 PM PDT 24 38083860 ps
T1122 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.1581355627 Jun 11 12:24:53 PM PDT 24 Jun 11 12:24:56 PM PDT 24 46180228 ps
T1123 /workspace/coverage/cover_reg_top/6.uart_tl_errors.4146572557 Jun 11 12:24:52 PM PDT 24 Jun 11 12:24:55 PM PDT 24 73412068 ps
T1124 /workspace/coverage/cover_reg_top/3.uart_intr_test.266971966 Jun 11 12:25:04 PM PDT 24 Jun 11 12:25:08 PM PDT 24 12373242 ps
T1125 /workspace/coverage/cover_reg_top/21.uart_intr_test.1988171136 Jun 11 12:25:24 PM PDT 24 Jun 11 12:25:26 PM PDT 24 26542635 ps
T55 /workspace/coverage/cover_reg_top/17.uart_csr_rw.529819200 Jun 11 12:25:10 PM PDT 24 Jun 11 12:25:13 PM PDT 24 29990574 ps
T56 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.1124652482 Jun 11 12:25:09 PM PDT 24 Jun 11 12:25:11 PM PDT 24 49803703 ps
T57 /workspace/coverage/cover_reg_top/3.uart_csr_rw.829900501 Jun 11 12:25:03 PM PDT 24 Jun 11 12:25:07 PM PDT 24 15995824 ps
T1126 /workspace/coverage/cover_reg_top/0.uart_intr_test.4224478336 Jun 11 12:22:55 PM PDT 24 Jun 11 12:22:59 PM PDT 24 45181438 ps
T68 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.3507525362 Jun 11 12:24:53 PM PDT 24 Jun 11 12:24:57 PM PDT 24 1153424929 ps
T40 /workspace/coverage/cover_reg_top/12.uart_csr_rw.2716296980 Jun 11 12:25:02 PM PDT 24 Jun 11 12:25:06 PM PDT 24 51206708 ps
T1127 /workspace/coverage/cover_reg_top/15.uart_intr_test.1741757946 Jun 11 12:25:11 PM PDT 24 Jun 11 12:25:13 PM PDT 24 38141306 ps
T1128 /workspace/coverage/cover_reg_top/2.uart_intr_test.145891351 Jun 11 12:25:05 PM PDT 24 Jun 11 12:25:10 PM PDT 24 28951899 ps
T1129 /workspace/coverage/cover_reg_top/14.uart_intr_test.1232351499 Jun 11 12:24:58 PM PDT 24 Jun 11 12:25:01 PM PDT 24 133010795 ps
T1130 /workspace/coverage/cover_reg_top/17.uart_intr_test.4234399303 Jun 11 12:25:13 PM PDT 24 Jun 11 12:25:15 PM PDT 24 49156969 ps
T1131 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3567874296 Jun 11 12:24:53 PM PDT 24 Jun 11 12:24:56 PM PDT 24 62855351 ps
T1132 /workspace/coverage/cover_reg_top/10.uart_intr_test.3039469109 Jun 11 12:25:03 PM PDT 24 Jun 11 12:25:06 PM PDT 24 45051992 ps
T1133 /workspace/coverage/cover_reg_top/17.uart_tl_errors.1396549738 Jun 11 12:25:09 PM PDT 24 Jun 11 12:25:13 PM PDT 24 42361906 ps
T65 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1559661881 Jun 11 12:24:51 PM PDT 24 Jun 11 12:24:54 PM PDT 24 77856247 ps
T1134 /workspace/coverage/cover_reg_top/20.uart_intr_test.3456721320 Jun 11 12:25:06 PM PDT 24 Jun 11 12:25:10 PM PDT 24 15257104 ps
T1135 /workspace/coverage/cover_reg_top/9.uart_tl_errors.2272535795 Jun 11 12:24:51 PM PDT 24 Jun 11 12:24:54 PM PDT 24 178463355 ps
T66 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.4040099905 Jun 11 12:24:54 PM PDT 24 Jun 11 12:24:58 PM PDT 24 339368025 ps
T69 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.1039432635 Jun 11 12:22:30 PM PDT 24 Jun 11 12:22:35 PM PDT 24 309889598 ps
T1136 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.673415208 Jun 11 12:24:54 PM PDT 24 Jun 11 12:24:58 PM PDT 24 65393263 ps
T1137 /workspace/coverage/cover_reg_top/1.uart_tl_errors.1352896212 Jun 11 12:22:29 PM PDT 24 Jun 11 12:22:33 PM PDT 24 161603681 ps
T1138 /workspace/coverage/cover_reg_top/42.uart_intr_test.4125333979 Jun 11 12:25:24 PM PDT 24 Jun 11 12:25:26 PM PDT 24 20688534 ps
T1139 /workspace/coverage/cover_reg_top/14.uart_csr_rw.1135298789 Jun 11 12:25:02 PM PDT 24 Jun 11 12:25:05 PM PDT 24 48101164 ps
T1140 /workspace/coverage/cover_reg_top/11.uart_tl_errors.3969572121 Jun 11 12:25:02 PM PDT 24 Jun 11 12:25:06 PM PDT 24 49061472 ps
T1141 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.4061796804 Jun 11 12:24:53 PM PDT 24 Jun 11 12:24:56 PM PDT 24 166814169 ps
T1142 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1447505188 Jun 11 12:25:10 PM PDT 24 Jun 11 12:25:13 PM PDT 24 111707039 ps
T1143 /workspace/coverage/cover_reg_top/38.uart_intr_test.61691688 Jun 11 12:25:24 PM PDT 24 Jun 11 12:25:26 PM PDT 24 22784707 ps
T1144 /workspace/coverage/cover_reg_top/37.uart_intr_test.221729234 Jun 11 12:25:14 PM PDT 24 Jun 11 12:25:16 PM PDT 24 28314997 ps
T1145 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2951722953 Jun 11 12:24:56 PM PDT 24 Jun 11 12:25:00 PM PDT 24 52068402 ps
T1146 /workspace/coverage/cover_reg_top/15.uart_tl_errors.1997000300 Jun 11 12:25:08 PM PDT 24 Jun 11 12:25:11 PM PDT 24 163517707 ps
T1147 /workspace/coverage/cover_reg_top/41.uart_intr_test.1302324744 Jun 11 12:25:13 PM PDT 24 Jun 11 12:25:15 PM PDT 24 36812975 ps
T1148 /workspace/coverage/cover_reg_top/16.uart_tl_errors.2464681464 Jun 11 12:25:12 PM PDT 24 Jun 11 12:25:15 PM PDT 24 199904687 ps
T1149 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.728865263 Jun 11 12:25:02 PM PDT 24 Jun 11 12:25:06 PM PDT 24 23337206 ps
T1150 /workspace/coverage/cover_reg_top/11.uart_csr_rw.2617637923 Jun 11 12:24:50 PM PDT 24 Jun 11 12:24:53 PM PDT 24 32086509 ps
T1151 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.4267603084 Jun 11 12:24:56 PM PDT 24 Jun 11 12:25:00 PM PDT 24 126498782 ps
T1152 /workspace/coverage/cover_reg_top/16.uart_csr_rw.3498479616 Jun 11 12:25:17 PM PDT 24 Jun 11 12:25:19 PM PDT 24 48230716 ps
T1153 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2340064625 Jun 11 12:25:09 PM PDT 24 Jun 11 12:25:11 PM PDT 24 22554765 ps
T1154 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1321060651 Jun 11 12:25:01 PM PDT 24 Jun 11 12:25:05 PM PDT 24 18119837 ps
T1155 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2698671216 Jun 11 12:24:54 PM PDT 24 Jun 11 12:24:58 PM PDT 24 95190175 ps
T43 /workspace/coverage/cover_reg_top/4.uart_csr_rw.3324554451 Jun 11 12:24:55 PM PDT 24 Jun 11 12:24:58 PM PDT 24 12550941 ps
T1156 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1521888324 Jun 11 12:25:02 PM PDT 24 Jun 11 12:25:06 PM PDT 24 19908434 ps
T1157 /workspace/coverage/cover_reg_top/33.uart_intr_test.572453256 Jun 11 12:25:17 PM PDT 24 Jun 11 12:25:19 PM PDT 24 17858763 ps
T1158 /workspace/coverage/cover_reg_top/22.uart_intr_test.2672712627 Jun 11 12:25:10 PM PDT 24 Jun 11 12:25:14 PM PDT 24 13633786 ps
T63 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.3052577150 Jun 11 12:22:30 PM PDT 24 Jun 11 12:22:36 PM PDT 24 88002920 ps
T1159 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.444775826 Jun 11 12:22:30 PM PDT 24 Jun 11 12:22:34 PM PDT 24 39937266 ps
T1160 /workspace/coverage/cover_reg_top/7.uart_tl_errors.1748201877 Jun 11 12:24:51 PM PDT 24 Jun 11 12:24:55 PM PDT 24 78989509 ps
T1161 /workspace/coverage/cover_reg_top/43.uart_intr_test.3197614923 Jun 11 12:25:24 PM PDT 24 Jun 11 12:25:25 PM PDT 24 32406627 ps
T1162 /workspace/coverage/cover_reg_top/36.uart_intr_test.2818234517 Jun 11 12:25:09 PM PDT 24 Jun 11 12:25:12 PM PDT 24 14269132 ps
T1163 /workspace/coverage/cover_reg_top/47.uart_intr_test.959362956 Jun 11 12:25:32 PM PDT 24 Jun 11 12:25:34 PM PDT 24 22256807 ps
T1164 /workspace/coverage/cover_reg_top/13.uart_csr_rw.2223303242 Jun 11 12:24:57 PM PDT 24 Jun 11 12:25:01 PM PDT 24 25214579 ps
T1165 /workspace/coverage/cover_reg_top/13.uart_tl_errors.3735385200 Jun 11 12:24:54 PM PDT 24 Jun 11 12:24:59 PM PDT 24 365545613 ps
T64 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2002687105 Jun 11 12:25:07 PM PDT 24 Jun 11 12:25:10 PM PDT 24 318777054 ps
T1166 /workspace/coverage/cover_reg_top/40.uart_intr_test.2988972860 Jun 11 12:25:12 PM PDT 24 Jun 11 12:25:14 PM PDT 24 17895805 ps
T41 /workspace/coverage/cover_reg_top/7.uart_csr_rw.1497989492 Jun 11 12:24:58 PM PDT 24 Jun 11 12:25:01 PM PDT 24 24786474 ps
T1167 /workspace/coverage/cover_reg_top/11.uart_intr_test.3484532489 Jun 11 12:25:02 PM PDT 24 Jun 11 12:25:05 PM PDT 24 40908055 ps
T1168 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.3360100485 Jun 11 12:24:56 PM PDT 24 Jun 11 12:25:00 PM PDT 24 41178173 ps
T1169 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.1922115739 Jun 11 12:25:06 PM PDT 24 Jun 11 12:25:10 PM PDT 24 266646294 ps
T1170 /workspace/coverage/cover_reg_top/48.uart_intr_test.3808625311 Jun 11 12:25:20 PM PDT 24 Jun 11 12:25:22 PM PDT 24 17835809 ps
T1171 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.92989729 Jun 11 12:24:55 PM PDT 24 Jun 11 12:24:58 PM PDT 24 97135208 ps
T1172 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.716584368 Jun 11 12:24:49 PM PDT 24 Jun 11 12:24:52 PM PDT 24 74283934 ps
T1173 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.372627549 Jun 11 12:25:04 PM PDT 24 Jun 11 12:25:08 PM PDT 24 16195782 ps
T1174 /workspace/coverage/cover_reg_top/9.uart_csr_rw.3943585800 Jun 11 12:24:49 PM PDT 24 Jun 11 12:24:52 PM PDT 24 24409159 ps
T1175 /workspace/coverage/cover_reg_top/49.uart_intr_test.1382906715 Jun 11 12:25:23 PM PDT 24 Jun 11 12:25:25 PM PDT 24 18148282 ps
T1176 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2097366722 Jun 11 12:24:54 PM PDT 24 Jun 11 12:24:58 PM PDT 24 17909862 ps
T1177 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.2998957879 Jun 11 12:24:55 PM PDT 24 Jun 11 12:24:59 PM PDT 24 44890253 ps
T1178 /workspace/coverage/cover_reg_top/18.uart_intr_test.1105034007 Jun 11 12:25:10 PM PDT 24 Jun 11 12:25:13 PM PDT 24 12488222 ps
T1179 /workspace/coverage/cover_reg_top/35.uart_intr_test.834452512 Jun 11 12:25:11 PM PDT 24 Jun 11 12:25:13 PM PDT 24 21866049 ps
T1180 /workspace/coverage/cover_reg_top/28.uart_intr_test.4156040710 Jun 11 12:25:08 PM PDT 24 Jun 11 12:25:11 PM PDT 24 16986681 ps
T1181 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2940984072 Jun 11 12:24:55 PM PDT 24 Jun 11 12:24:59 PM PDT 24 17711482 ps
T42 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2120882434 Jun 11 12:22:25 PM PDT 24 Jun 11 12:22:27 PM PDT 24 15146000 ps
T1182 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.925209176 Jun 11 12:25:04 PM PDT 24 Jun 11 12:25:08 PM PDT 24 15855488 ps
T1183 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.42463833 Jun 11 12:25:04 PM PDT 24 Jun 11 12:25:09 PM PDT 24 85033449 ps
T44 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1718739561 Jun 11 12:24:52 PM PDT 24 Jun 11 12:24:54 PM PDT 24 59358351 ps
T1184 /workspace/coverage/cover_reg_top/19.uart_csr_rw.371747487 Jun 11 12:25:13 PM PDT 24 Jun 11 12:25:15 PM PDT 24 14837787 ps
T1185 /workspace/coverage/cover_reg_top/19.uart_tl_errors.405785385 Jun 11 12:25:09 PM PDT 24 Jun 11 12:25:13 PM PDT 24 54048181 ps
T1186 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1957736697 Jun 11 12:24:57 PM PDT 24 Jun 11 12:25:00 PM PDT 24 29275742 ps
T1187 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1837043518 Jun 11 12:24:58 PM PDT 24 Jun 11 12:25:01 PM PDT 24 24324491 ps
T1188 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3606197377 Jun 11 12:24:49 PM PDT 24 Jun 11 12:24:52 PM PDT 24 71004862 ps
T1189 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2599193689 Jun 11 12:25:24 PM PDT 24 Jun 11 12:25:26 PM PDT 24 36210154 ps
T1190 /workspace/coverage/cover_reg_top/6.uart_intr_test.4293126350 Jun 11 12:24:54 PM PDT 24 Jun 11 12:24:58 PM PDT 24 12122076 ps
T1191 /workspace/coverage/cover_reg_top/32.uart_intr_test.906778084 Jun 11 12:25:24 PM PDT 24 Jun 11 12:25:26 PM PDT 24 44627377 ps
T1192 /workspace/coverage/cover_reg_top/13.uart_intr_test.3185744735 Jun 11 12:24:53 PM PDT 24 Jun 11 12:24:55 PM PDT 24 169061942 ps
T1193 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3262164734 Jun 11 12:24:52 PM PDT 24 Jun 11 12:24:55 PM PDT 24 18824481 ps
T1194 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1767755313 Jun 11 12:25:02 PM PDT 24 Jun 11 12:25:06 PM PDT 24 16935151 ps
T1195 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.252249831 Jun 11 12:25:24 PM PDT 24 Jun 11 12:25:26 PM PDT 24 122576319 ps
T1196 /workspace/coverage/cover_reg_top/7.uart_intr_test.2943435632 Jun 11 12:24:53 PM PDT 24 Jun 11 12:24:56 PM PDT 24 15315916 ps
T1197 /workspace/coverage/cover_reg_top/12.uart_tl_errors.97264982 Jun 11 12:25:02 PM PDT 24 Jun 11 12:25:07 PM PDT 24 483548566 ps
T1198 /workspace/coverage/cover_reg_top/3.uart_tl_errors.1557276399 Jun 11 12:25:07 PM PDT 24 Jun 11 12:25:12 PM PDT 24 38213977 ps
T1199 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3434210080 Jun 11 12:24:54 PM PDT 24 Jun 11 12:24:57 PM PDT 24 34575347 ps
T1200 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.3735554215 Jun 11 12:25:13 PM PDT 24 Jun 11 12:25:16 PM PDT 24 139404573 ps
T1201 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1894016291 Jun 11 12:24:55 PM PDT 24 Jun 11 12:24:59 PM PDT 24 26689744 ps
T1202 /workspace/coverage/cover_reg_top/8.uart_csr_rw.3222685277 Jun 11 12:24:55 PM PDT 24 Jun 11 12:24:59 PM PDT 24 13560453 ps
T1203 /workspace/coverage/cover_reg_top/1.uart_csr_rw.1066018225 Jun 11 12:18:15 PM PDT 24 Jun 11 12:18:16 PM PDT 24 48396360 ps
T1204 /workspace/coverage/cover_reg_top/4.uart_tl_errors.3869026150 Jun 11 12:24:57 PM PDT 24 Jun 11 12:25:01 PM PDT 24 61331736 ps
T1205 /workspace/coverage/cover_reg_top/27.uart_intr_test.281706321 Jun 11 12:25:12 PM PDT 24 Jun 11 12:25:15 PM PDT 24 31936119 ps
T1206 /workspace/coverage/cover_reg_top/1.uart_intr_test.2185925160 Jun 11 12:19:39 PM PDT 24 Jun 11 12:19:40 PM PDT 24 13530563 ps
T1207 /workspace/coverage/cover_reg_top/19.uart_intr_test.3891078317 Jun 11 12:25:10 PM PDT 24 Jun 11 12:25:12 PM PDT 24 14346940 ps
T1208 /workspace/coverage/cover_reg_top/18.uart_tl_errors.4162755941 Jun 11 12:25:10 PM PDT 24 Jun 11 12:25:13 PM PDT 24 34768650 ps
T1209 /workspace/coverage/cover_reg_top/26.uart_intr_test.106241436 Jun 11 12:25:17 PM PDT 24 Jun 11 12:25:18 PM PDT 24 26247433 ps
T1210 /workspace/coverage/cover_reg_top/5.uart_tl_errors.3039695940 Jun 11 12:24:55 PM PDT 24 Jun 11 12:25:00 PM PDT 24 86577384 ps
T45 /workspace/coverage/cover_reg_top/15.uart_csr_rw.1958284055 Jun 11 12:25:16 PM PDT 24 Jun 11 12:25:18 PM PDT 24 40980455 ps
T1211 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.4044033021 Jun 11 12:24:54 PM PDT 24 Jun 11 12:24:58 PM PDT 24 166393888 ps
T1212 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.3976101867 Jun 11 12:25:02 PM PDT 24 Jun 11 12:25:07 PM PDT 24 108561492 ps
T48 /workspace/coverage/cover_reg_top/5.uart_csr_rw.2468168896 Jun 11 12:24:54 PM PDT 24 Jun 11 12:24:57 PM PDT 24 11555124 ps
T1213 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.3743968707 Jun 11 12:24:51 PM PDT 24 Jun 11 12:24:53 PM PDT 24 103386616 ps
T1214 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.1756752475 Jun 11 12:24:54 PM PDT 24 Jun 11 12:24:58 PM PDT 24 32001765 ps
T1215 /workspace/coverage/cover_reg_top/31.uart_intr_test.2150042272 Jun 11 12:25:10 PM PDT 24 Jun 11 12:25:13 PM PDT 24 37434243 ps
T1216 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.2228351328 Jun 11 12:23:17 PM PDT 24 Jun 11 12:23:19 PM PDT 24 44881391 ps
T46 /workspace/coverage/cover_reg_top/0.uart_csr_rw.4004989710 Jun 11 12:17:28 PM PDT 24 Jun 11 12:17:29 PM PDT 24 77140207 ps
T1217 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2132438794 Jun 11 12:24:51 PM PDT 24 Jun 11 12:24:54 PM PDT 24 107214577 ps
T1218 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3710493379 Jun 11 12:25:13 PM PDT 24 Jun 11 12:25:15 PM PDT 24 88447042 ps
T1219 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3414417021 Jun 11 12:25:09 PM PDT 24 Jun 11 12:25:12 PM PDT 24 39852741 ps
T1220 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3159105236 Jun 11 12:25:13 PM PDT 24 Jun 11 12:25:15 PM PDT 24 32717161 ps
T1221 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2399257396 Jun 11 12:25:11 PM PDT 24 Jun 11 12:25:14 PM PDT 24 91666803 ps
T1222 /workspace/coverage/cover_reg_top/4.uart_intr_test.4166240211 Jun 11 12:24:53 PM PDT 24 Jun 11 12:24:55 PM PDT 24 33016532 ps
T1223 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.1402225081 Jun 11 12:25:02 PM PDT 24 Jun 11 12:25:05 PM PDT 24 39625540 ps
T1224 /workspace/coverage/cover_reg_top/0.uart_tl_errors.3354040874 Jun 11 12:22:58 PM PDT 24 Jun 11 12:23:04 PM PDT 24 155865770 ps
T1225 /workspace/coverage/cover_reg_top/45.uart_intr_test.2077291305 Jun 11 12:25:24 PM PDT 24 Jun 11 12:25:26 PM PDT 24 13634276 ps
T1226 /workspace/coverage/cover_reg_top/8.uart_intr_test.586518995 Jun 11 12:24:51 PM PDT 24 Jun 11 12:24:54 PM PDT 24 52176900 ps
T1227 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.2807470018 Jun 11 12:24:53 PM PDT 24 Jun 11 12:24:56 PM PDT 24 260889121 ps
T1228 /workspace/coverage/cover_reg_top/10.uart_tl_errors.1055780985 Jun 11 12:25:01 PM PDT 24 Jun 11 12:25:05 PM PDT 24 163687535 ps
T1229 /workspace/coverage/cover_reg_top/10.uart_csr_rw.4035529761 Jun 11 12:25:02 PM PDT 24 Jun 11 12:25:05 PM PDT 24 58554698 ps
T1230 /workspace/coverage/cover_reg_top/24.uart_intr_test.519997382 Jun 11 12:25:10 PM PDT 24 Jun 11 12:25:13 PM PDT 24 43506013 ps
T47 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1207957618 Jun 11 12:24:55 PM PDT 24 Jun 11 12:24:58 PM PDT 24 47176069 ps
T1231 /workspace/coverage/cover_reg_top/34.uart_intr_test.2664618980 Jun 11 12:25:09 PM PDT 24 Jun 11 12:25:16 PM PDT 24 16321299 ps
T1232 /workspace/coverage/cover_reg_top/44.uart_intr_test.3099052702 Jun 11 12:25:11 PM PDT 24 Jun 11 12:25:13 PM PDT 24 12120556 ps
T1233 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.598910080 Jun 11 12:25:10 PM PDT 24 Jun 11 12:25:13 PM PDT 24 26665816 ps
T1234 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1790970738 Jun 11 12:25:02 PM PDT 24 Jun 11 12:25:06 PM PDT 24 18894066 ps

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.4180712055
Short name T3
Test name
Test status
Simulation time 135313955004 ps
CPU time 1031.09 seconds
Started Jun 11 12:31:28 PM PDT 24
Finished Jun 11 12:48:41 PM PDT 24
Peak memory 229048 kb
Host smart-c22198fc-067b-4313-b166-5f07b89f8f6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180712055 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.4180712055
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_stress_all.508208814
Short name T59
Test name
Test status
Simulation time 315305446835 ps
CPU time 545.39 seconds
Started Jun 11 12:30:05 PM PDT 24
Finished Jun 11 12:39:12 PM PDT 24
Peak memory 200336 kb
Host smart-6d4dddb1-6d43-4a92-af95-ca61cd18ce8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508208814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.508208814
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all.405140040
Short name T1
Test name
Test status
Simulation time 310923956514 ps
CPU time 370.29 seconds
Started Jun 11 12:29:01 PM PDT 24
Finished Jun 11 12:35:14 PM PDT 24
Peak memory 200324 kb
Host smart-4279796c-5890-4ef3-b630-63b7968be0e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405140040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.405140040
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.705384164
Short name T58
Test name
Test status
Simulation time 30631945604 ps
CPU time 14.39 seconds
Started Jun 11 12:31:52 PM PDT 24
Finished Jun 11 12:32:08 PM PDT 24
Peak memory 200092 kb
Host smart-64c60499-cd80-4328-ae0b-613d2016d025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705384164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.705384164
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.1850540423
Short name T16
Test name
Test status
Simulation time 108607384664 ps
CPU time 967.77 seconds
Started Jun 11 12:29:36 PM PDT 24
Finished Jun 11 12:45:45 PM PDT 24
Peak memory 216824 kb
Host smart-b136094f-0d83-46f4-b588-8fc3178d7247
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850540423 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.1850540423
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_stress_all.162988684
Short name T247
Test name
Test status
Simulation time 635530464290 ps
CPU time 1221.47 seconds
Started Jun 11 12:31:04 PM PDT 24
Finished Jun 11 12:51:28 PM PDT 24
Peak memory 200288 kb
Host smart-f35c50c9-5f86-4e57-b14b-13bd09c899d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162988684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.162988684
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.3672121133
Short name T274
Test name
Test status
Simulation time 72317232416 ps
CPU time 253.56 seconds
Started Jun 11 12:29:43 PM PDT 24
Finished Jun 11 12:33:59 PM PDT 24
Peak memory 200148 kb
Host smart-e7fbc1c2-6449-4804-87d2-7b08aeaa7f54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3672121133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.3672121133
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.2803255418
Short name T25
Test name
Test status
Simulation time 290289964589 ps
CPU time 279.86 seconds
Started Jun 11 12:28:47 PM PDT 24
Finished Jun 11 12:33:29 PM PDT 24
Peak memory 216760 kb
Host smart-6ba93622-3745-4691-bee0-9721fae57d12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803255418 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.2803255418
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_sec_cm.2032475404
Short name T22
Test name
Test status
Simulation time 234580353 ps
CPU time 0.8 seconds
Started Jun 11 12:28:49 PM PDT 24
Finished Jun 11 12:28:52 PM PDT 24
Peak memory 218656 kb
Host smart-abe38c76-1cfa-43f7-8f97-71d1a25c229d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032475404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.2032475404
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.1940121571
Short name T13
Test name
Test status
Simulation time 232504718556 ps
CPU time 310.77 seconds
Started Jun 11 12:31:18 PM PDT 24
Finished Jun 11 12:36:32 PM PDT 24
Peak memory 209784 kb
Host smart-6aa84d92-c6bb-49bb-8e7b-bdbf05594dfa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940121571 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.1940121571
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_stress_all.1575370940
Short name T120
Test name
Test status
Simulation time 268501162446 ps
CPU time 1768.51 seconds
Started Jun 11 12:29:38 PM PDT 24
Finished Jun 11 12:59:08 PM PDT 24
Peak memory 200152 kb
Host smart-34ad5c19-f801-4d21-92a6-5d69cecc2186
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575370940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.1575370940
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.3626949400
Short name T74
Test name
Test status
Simulation time 343976356231 ps
CPU time 75.06 seconds
Started Jun 11 12:30:02 PM PDT 24
Finished Jun 11 12:31:19 PM PDT 24
Peak memory 200352 kb
Host smart-5f75a66e-baca-4055-935d-1a046a31d2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626949400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.3626949400
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_stress_all.584894276
Short name T158
Test name
Test status
Simulation time 444933658816 ps
CPU time 295.81 seconds
Started Jun 11 12:29:50 PM PDT 24
Finished Jun 11 12:34:48 PM PDT 24
Peak memory 200244 kb
Host smart-63646b49-9cdf-49fc-86f0-6d5f824a66ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584894276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.584894276
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.3663688029
Short name T145
Test name
Test status
Simulation time 599390800558 ps
CPU time 347.02 seconds
Started Jun 11 12:29:46 PM PDT 24
Finished Jun 11 12:35:35 PM PDT 24
Peak memory 216804 kb
Host smart-36de45f5-178b-47f9-8bb6-d8038c6b5c27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663688029 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.3663688029
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.2223585095
Short name T125
Test name
Test status
Simulation time 196734190861 ps
CPU time 82.64 seconds
Started Jun 11 12:31:52 PM PDT 24
Finished Jun 11 12:33:16 PM PDT 24
Peak memory 200308 kb
Host smart-bb275b92-917d-4ec5-b2d3-ab3a5745c83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223585095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.2223585095
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_fifo_full.788486565
Short name T291
Test name
Test status
Simulation time 366952927645 ps
CPU time 1201.67 seconds
Started Jun 11 12:29:49 PM PDT 24
Finished Jun 11 12:49:52 PM PDT 24
Peak memory 200168 kb
Host smart-b8a9c148-32d9-429d-a77d-49a907eb71ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788486565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.788486565
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.4040099905
Short name T66
Test name
Test status
Simulation time 339368025 ps
CPU time 1.25 seconds
Started Jun 11 12:24:54 PM PDT 24
Finished Jun 11 12:24:58 PM PDT 24
Peak memory 199980 kb
Host smart-36278328-a5b9-47d2-a128-8746747dae85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040099905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.4040099905
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.1611346554
Short name T102
Test name
Test status
Simulation time 388485156576 ps
CPU time 474.59 seconds
Started Jun 11 12:30:49 PM PDT 24
Finished Jun 11 12:38:46 PM PDT 24
Peak memory 217016 kb
Host smart-ba0be45c-4d12-4342-8279-51045c7e2176
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611346554 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.1611346554
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_alert_test.2528938435
Short name T361
Test name
Test status
Simulation time 47629735 ps
CPU time 0.52 seconds
Started Jun 11 12:29:08 PM PDT 24
Finished Jun 11 12:29:10 PM PDT 24
Peak memory 195664 kb
Host smart-4b91d1c6-4527-4824-8fee-5805edbd2778
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528938435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.2528938435
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.4268871855
Short name T27
Test name
Test status
Simulation time 166927784067 ps
CPU time 1008.25 seconds
Started Jun 11 12:29:13 PM PDT 24
Finished Jun 11 12:46:03 PM PDT 24
Peak memory 224964 kb
Host smart-c88bf796-06c1-406e-bdb3-3df88fd8e196
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268871855 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.4268871855
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_perf.2121404469
Short name T77
Test name
Test status
Simulation time 20191916050 ps
CPU time 211.57 seconds
Started Jun 11 12:29:21 PM PDT 24
Finished Jun 11 12:32:55 PM PDT 24
Peak memory 200256 kb
Host smart-dec48072-6fc2-4d7c-aea5-26268c36ab1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2121404469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.2121404469
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/38.uart_stress_all.2119332254
Short name T33
Test name
Test status
Simulation time 192156121577 ps
CPU time 241.02 seconds
Started Jun 11 12:30:47 PM PDT 24
Finished Jun 11 12:34:50 PM PDT 24
Peak memory 200272 kb
Host smart-e8ffe239-2bba-4c52-8c28-cae6cd5437e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119332254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.2119332254
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.4004989710
Short name T46
Test name
Test status
Simulation time 77140207 ps
CPU time 0.61 seconds
Started Jun 11 12:17:28 PM PDT 24
Finished Jun 11 12:17:29 PM PDT 24
Peak memory 196296 kb
Host smart-8a26cc9b-2476-403d-93c5-00ebc3ea3d3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004989710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.4004989710
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.202304247
Short name T53
Test name
Test status
Simulation time 81157241 ps
CPU time 0.72 seconds
Started Jun 11 12:22:27 PM PDT 24
Finished Jun 11 12:22:29 PM PDT 24
Peak memory 195872 kb
Host smart-5008b6ba-e9e4-4648-8e89-3c69e9527376
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202304247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr_
outstanding.202304247
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.1717524099
Short name T116
Test name
Test status
Simulation time 93858073247 ps
CPU time 41.6 seconds
Started Jun 11 12:31:54 PM PDT 24
Finished Jun 11 12:32:37 PM PDT 24
Peak memory 200352 kb
Host smart-ae89327a-f472-4a9b-bb69-c780736a380b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717524099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.1717524099
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_stress_all.920101616
Short name T111
Test name
Test status
Simulation time 172058887650 ps
CPU time 1088.4 seconds
Started Jun 11 12:29:48 PM PDT 24
Finished Jun 11 12:47:59 PM PDT 24
Peak memory 200384 kb
Host smart-7e1da790-96d2-4f5a-96d9-7964578efea9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920101616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.920101616
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.3052577150
Short name T63
Test name
Test status
Simulation time 88002920 ps
CPU time 1.26 seconds
Started Jun 11 12:22:30 PM PDT 24
Finished Jun 11 12:22:36 PM PDT 24
Peak memory 198756 kb
Host smart-8fa4f84d-00f7-4664-bb0c-d8caed11b11f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052577150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.3052577150
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.1406742538
Short name T114
Test name
Test status
Simulation time 108231194791 ps
CPU time 182.63 seconds
Started Jun 11 12:29:47 PM PDT 24
Finished Jun 11 12:32:52 PM PDT 24
Peak memory 200164 kb
Host smart-92eca0c4-f2d8-44d1-a4ec-f07e8384aa62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406742538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.1406742538
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_perf.299111425
Short name T251
Test name
Test status
Simulation time 29712184801 ps
CPU time 305.89 seconds
Started Jun 11 12:29:49 PM PDT 24
Finished Jun 11 12:34:57 PM PDT 24
Peak memory 200256 kb
Host smart-bb16cb08-3c8e-440f-aaaf-467b583063ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=299111425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.299111425
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.1217325727
Short name T76
Test name
Test status
Simulation time 57611952402 ps
CPU time 80.24 seconds
Started Jun 11 12:31:27 PM PDT 24
Finished Jun 11 12:32:49 PM PDT 24
Peak memory 200256 kb
Host smart-b612ad91-6afb-4e0f-be3c-0634d96c3b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217325727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.1217325727
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.2848312080
Short name T136
Test name
Test status
Simulation time 70829496347 ps
CPU time 31.27 seconds
Started Jun 11 12:32:06 PM PDT 24
Finished Jun 11 12:32:38 PM PDT 24
Peak memory 200184 kb
Host smart-5718bcd3-561f-4926-939b-1872e1455165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848312080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.2848312080
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_stress_all.824110356
Short name T156
Test name
Test status
Simulation time 429682638486 ps
CPU time 1033.67 seconds
Started Jun 11 12:30:35 PM PDT 24
Finished Jun 11 12:47:50 PM PDT 24
Peak memory 200296 kb
Host smart-95be1808-a12f-45b4-8c28-28bd354eab90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824110356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.824110356
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all.161900217
Short name T186
Test name
Test status
Simulation time 205408554149 ps
CPU time 94.79 seconds
Started Jun 11 12:28:57 PM PDT 24
Finished Jun 11 12:30:33 PM PDT 24
Peak memory 200316 kb
Host smart-1ea7aba7-9d6b-4cba-a2b1-98f0420689b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161900217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.161900217
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.4274902340
Short name T142
Test name
Test status
Simulation time 183739609668 ps
CPU time 90.32 seconds
Started Jun 11 12:32:08 PM PDT 24
Finished Jun 11 12:33:39 PM PDT 24
Peak memory 200172 kb
Host smart-00a7b5d2-604b-402e-b8fb-517dde0937f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274902340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.4274902340
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.2310015335
Short name T131
Test name
Test status
Simulation time 89282361293 ps
CPU time 36.86 seconds
Started Jun 11 12:31:43 PM PDT 24
Finished Jun 11 12:32:21 PM PDT 24
Peak memory 200124 kb
Host smart-4edf27b6-d29a-4c90-b627-7d343797c7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310015335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.2310015335
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.358196367
Short name T191
Test name
Test status
Simulation time 55159061745 ps
CPU time 33.31 seconds
Started Jun 11 12:31:52 PM PDT 24
Finished Jun 11 12:32:26 PM PDT 24
Peak memory 200252 kb
Host smart-7cab64c2-9730-48a2-930a-c7fff61d97f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358196367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.358196367
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.3041312541
Short name T180
Test name
Test status
Simulation time 131175508220 ps
CPU time 52.23 seconds
Started Jun 11 12:31:50 PM PDT 24
Finished Jun 11 12:32:43 PM PDT 24
Peak memory 200332 kb
Host smart-9490dca0-064d-4ffb-9856-c2377517dbb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041312541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.3041312541
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_fifo_full.1838766633
Short name T11
Test name
Test status
Simulation time 267269698497 ps
CPU time 132.51 seconds
Started Jun 11 12:30:09 PM PDT 24
Finished Jun 11 12:32:24 PM PDT 24
Peak memory 200144 kb
Host smart-de311847-95c4-4586-bba2-0c598b036a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838766633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.1838766633
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.443319024
Short name T36
Test name
Test status
Simulation time 36242833279 ps
CPU time 421.15 seconds
Started Jun 11 12:31:29 PM PDT 24
Finished Jun 11 12:38:32 PM PDT 24
Peak memory 216828 kb
Host smart-2fc6643d-9d16-4fe4-a8c5-03da5223b96b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443319024 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.443319024
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.152935235
Short name T206
Test name
Test status
Simulation time 37502829636 ps
CPU time 16.35 seconds
Started Jun 11 12:29:45 PM PDT 24
Finished Jun 11 12:30:04 PM PDT 24
Peak memory 200336 kb
Host smart-b30bd2aa-2ee9-4234-af6c-47671a1717aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152935235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.152935235
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_fifo_full.257324576
Short name T149
Test name
Test status
Simulation time 49204338499 ps
CPU time 18.99 seconds
Started Jun 11 12:28:47 PM PDT 24
Finished Jun 11 12:29:08 PM PDT 24
Peak memory 200284 kb
Host smart-f8c8fcb8-4ef4-40ae-848c-5c877179dc68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257324576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.257324576
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_stress_all.14391068
Short name T224
Test name
Test status
Simulation time 184042598859 ps
CPU time 523.76 seconds
Started Jun 11 12:28:54 PM PDT 24
Finished Jun 11 12:37:40 PM PDT 24
Peak memory 200400 kb
Host smart-bb96330f-9e8d-4932-8427-ca088441c99d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14391068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.14391068
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.944437999
Short name T171
Test name
Test status
Simulation time 87835019212 ps
CPU time 45.36 seconds
Started Jun 11 12:31:45 PM PDT 24
Finished Jun 11 12:32:32 PM PDT 24
Peak memory 200316 kb
Host smart-1ea71a00-a1b8-45b6-bb21-a2a0b15a0429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944437999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.944437999
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.3485767114
Short name T200
Test name
Test status
Simulation time 168331774189 ps
CPU time 67.94 seconds
Started Jun 11 12:31:54 PM PDT 24
Finished Jun 11 12:33:03 PM PDT 24
Peak memory 200364 kb
Host smart-c95861a7-3c1c-4a96-8cf2-3cb97c0ed248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485767114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.3485767114
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.4101483154
Short name T194
Test name
Test status
Simulation time 14014091852 ps
CPU time 26.11 seconds
Started Jun 11 12:29:49 PM PDT 24
Finished Jun 11 12:30:17 PM PDT 24
Peak memory 200340 kb
Host smart-7b65e8da-99eb-45b0-ada3-ece6a53fb506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101483154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.4101483154
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.1329295789
Short name T121
Test name
Test status
Simulation time 58429538718 ps
CPU time 25.6 seconds
Started Jun 11 12:32:07 PM PDT 24
Finished Jun 11 12:32:33 PM PDT 24
Peak memory 200328 kb
Host smart-a9bc92fa-eed0-49cd-a4e5-17a0064040e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329295789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.1329295789
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_fifo_full.357586225
Short name T1009
Test name
Test status
Simulation time 137606168023 ps
CPU time 71.32 seconds
Started Jun 11 12:28:50 PM PDT 24
Finished Jun 11 12:30:03 PM PDT 24
Peak memory 200324 kb
Host smart-abe6a826-26b9-4c60-838b-6fc8b19d31c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357586225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.357586225
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.3165638000
Short name T190
Test name
Test status
Simulation time 173765879615 ps
CPU time 30.13 seconds
Started Jun 11 12:31:27 PM PDT 24
Finished Jun 11 12:31:59 PM PDT 24
Peak memory 200208 kb
Host smart-b52e0cd3-0ce0-4bb3-91fc-12e64a89d694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165638000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.3165638000
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.2326532890
Short name T103
Test name
Test status
Simulation time 92586436943 ps
CPU time 1562.41 seconds
Started Jun 11 12:29:03 PM PDT 24
Finished Jun 11 12:55:08 PM PDT 24
Peak memory 224972 kb
Host smart-6003f816-e137-44d0-8a5a-cf9a6a827f71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326532890 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.2326532890
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.2516238053
Short name T212
Test name
Test status
Simulation time 6164340985 ps
CPU time 9.86 seconds
Started Jun 11 12:31:55 PM PDT 24
Finished Jun 11 12:32:06 PM PDT 24
Peak memory 199988 kb
Host smart-b702512d-ad3d-488a-8f83-54964b95fd57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516238053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.2516238053
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.2281910103
Short name T217
Test name
Test status
Simulation time 107587573508 ps
CPU time 34.41 seconds
Started Jun 11 12:29:39 PM PDT 24
Finished Jun 11 12:30:17 PM PDT 24
Peak memory 200264 kb
Host smart-cda81d6c-57a4-483c-8272-fda4a379e95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281910103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.2281910103
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.2138410030
Short name T178
Test name
Test status
Simulation time 149923189716 ps
CPU time 82.34 seconds
Started Jun 11 12:32:16 PM PDT 24
Finished Jun 11 12:33:40 PM PDT 24
Peak memory 200372 kb
Host smart-a0bcc5ca-d55b-4b77-969f-e0248f2bd020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138410030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.2138410030
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.500852010
Short name T233
Test name
Test status
Simulation time 30170966785 ps
CPU time 13.78 seconds
Started Jun 11 12:32:17 PM PDT 24
Finished Jun 11 12:32:34 PM PDT 24
Peak memory 200364 kb
Host smart-2a14705b-6229-4b31-8a6f-6e5128b3829c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500852010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.500852010
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.2807470018
Short name T1227
Test name
Test status
Simulation time 260889121 ps
CPU time 1.68 seconds
Started Jun 11 12:24:53 PM PDT 24
Finished Jun 11 12:24:56 PM PDT 24
Peak memory 199868 kb
Host smart-f88871cc-eb2a-4948-b58c-dbc362d0a84d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807470018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.2807470018
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_stress_all.4208174710
Short name T938
Test name
Test status
Simulation time 136243943038 ps
CPU time 459.23 seconds
Started Jun 11 12:28:57 PM PDT 24
Finished Jun 11 12:36:44 PM PDT 24
Peak memory 200240 kb
Host smart-7f9efdc6-5279-49f1-885c-b609b5341a38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208174710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.4208174710
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.2029827027
Short name T258
Test name
Test status
Simulation time 104199125815 ps
CPU time 372.75 seconds
Started Jun 11 12:28:52 PM PDT 24
Finished Jun 11 12:35:07 PM PDT 24
Peak memory 200260 kb
Host smart-be2c6d24-229d-4782-960c-b3c0e981d027
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2029827027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.2029827027
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.1141948395
Short name T506
Test name
Test status
Simulation time 254677771214 ps
CPU time 489.3 seconds
Started Jun 11 12:29:15 PM PDT 24
Finished Jun 11 12:37:26 PM PDT 24
Peak memory 200372 kb
Host smart-bbc12f68-6d99-468e-bf9b-435e181df775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141948395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.1141948395
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.3241412344
Short name T104
Test name
Test status
Simulation time 204661687854 ps
CPU time 707.41 seconds
Started Jun 11 12:29:18 PM PDT 24
Finished Jun 11 12:41:07 PM PDT 24
Peak memory 216776 kb
Host smart-ea1178ea-28cd-4fd1-8b58-6f192489e436
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241412344 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.3241412344
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.3572549847
Short name T930
Test name
Test status
Simulation time 26424325970 ps
CPU time 29 seconds
Started Jun 11 12:31:39 PM PDT 24
Finished Jun 11 12:32:09 PM PDT 24
Peak memory 200140 kb
Host smart-cd31edc4-757c-4eff-892b-d70f3205fbda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572549847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.3572549847
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.3085421320
Short name T231
Test name
Test status
Simulation time 74200509246 ps
CPU time 34.6 seconds
Started Jun 11 12:31:39 PM PDT 24
Finished Jun 11 12:32:14 PM PDT 24
Peak memory 200316 kb
Host smart-2badf57d-be2e-4919-a50e-15c39bd224c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085421320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.3085421320
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.68862960
Short name T840
Test name
Test status
Simulation time 102741606103 ps
CPU time 86.22 seconds
Started Jun 11 12:31:43 PM PDT 24
Finished Jun 11 12:33:10 PM PDT 24
Peak memory 200328 kb
Host smart-d48eebf9-b1f7-4e4e-b0f1-89058d94282a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68862960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.68862960
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.247113755
Short name T234
Test name
Test status
Simulation time 113534817251 ps
CPU time 31.4 seconds
Started Jun 11 12:31:46 PM PDT 24
Finished Jun 11 12:32:18 PM PDT 24
Peak memory 200264 kb
Host smart-aacbbdf0-d3d6-45ac-ae05-4df7a6b1b896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247113755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.247113755
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.326555104
Short name T166
Test name
Test status
Simulation time 65860390315 ps
CPU time 126.24 seconds
Started Jun 11 12:29:19 PM PDT 24
Finished Jun 11 12:31:27 PM PDT 24
Peak memory 200224 kb
Host smart-1984a65d-3504-4599-98b9-61bc5660fadf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326555104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.326555104
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.2434425509
Short name T226
Test name
Test status
Simulation time 22756840448 ps
CPU time 39.01 seconds
Started Jun 11 12:31:51 PM PDT 24
Finished Jun 11 12:32:32 PM PDT 24
Peak memory 200212 kb
Host smart-02e4bcc5-1a7a-4d3c-8446-118fe221cbc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434425509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.2434425509
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.3419591966
Short name T239
Test name
Test status
Simulation time 54167577768 ps
CPU time 44.51 seconds
Started Jun 11 12:31:52 PM PDT 24
Finished Jun 11 12:32:38 PM PDT 24
Peak memory 200216 kb
Host smart-00e47806-bc49-4360-a609-69b2e7ff7b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419591966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.3419591966
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.2188638267
Short name T185
Test name
Test status
Simulation time 117708409634 ps
CPU time 97.88 seconds
Started Jun 11 12:31:53 PM PDT 24
Finished Jun 11 12:33:33 PM PDT 24
Peak memory 200164 kb
Host smart-15e73c13-e2f1-46a1-b85a-e593b1a62e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188638267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.2188638267
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.4217383554
Short name T195
Test name
Test status
Simulation time 82083004028 ps
CPU time 25.7 seconds
Started Jun 11 12:32:13 PM PDT 24
Finished Jun 11 12:32:39 PM PDT 24
Peak memory 200336 kb
Host smart-9ca1fef2-6f4a-4705-9437-8bd4136b536d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217383554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.4217383554
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.329398867
Short name T236
Test name
Test status
Simulation time 126874153645 ps
CPU time 20.39 seconds
Started Jun 11 12:32:06 PM PDT 24
Finished Jun 11 12:32:28 PM PDT 24
Peak memory 200296 kb
Host smart-d6065e93-8176-4032-b04a-a45f7ac43b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329398867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.329398867
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.780001421
Short name T151
Test name
Test status
Simulation time 18861717340 ps
CPU time 14.34 seconds
Started Jun 11 12:32:07 PM PDT 24
Finished Jun 11 12:32:22 PM PDT 24
Peak memory 200300 kb
Host smart-73560d38-46bc-489a-940c-71a74aefd818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780001421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.780001421
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.650533688
Short name T229
Test name
Test status
Simulation time 33449729560 ps
CPU time 54.02 seconds
Started Jun 11 12:30:47 PM PDT 24
Finished Jun 11 12:31:43 PM PDT 24
Peak memory 200240 kb
Host smart-486d9341-5da3-4675-8cc9-50b71ca45817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650533688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.650533688
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.134672918
Short name T225
Test name
Test status
Simulation time 10409614749 ps
CPU time 20.92 seconds
Started Jun 11 12:30:47 PM PDT 24
Finished Jun 11 12:31:10 PM PDT 24
Peak memory 200272 kb
Host smart-ab609086-fa13-4448-801c-8dfcd0740aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134672918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.134672918
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.3629121760
Short name T230
Test name
Test status
Simulation time 30509434299 ps
CPU time 31.65 seconds
Started Jun 11 12:29:04 PM PDT 24
Finished Jun 11 12:29:38 PM PDT 24
Peak memory 200312 kb
Host smart-9148842b-0512-4128-b3c3-e60138f7da54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629121760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.3629121760
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.3677508302
Short name T159
Test name
Test status
Simulation time 138848635788 ps
CPU time 49.75 seconds
Started Jun 11 12:31:16 PM PDT 24
Finished Jun 11 12:32:09 PM PDT 24
Peak memory 200164 kb
Host smart-fb69cf74-6e61-4b25-afd9-dedb34f4ec76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677508302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.3677508302
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.3139235372
Short name T211
Test name
Test status
Simulation time 11846577518 ps
CPU time 8.92 seconds
Started Jun 11 12:29:21 PM PDT 24
Finished Jun 11 12:29:31 PM PDT 24
Peak memory 200312 kb
Host smart-069a90ff-5ee3-495c-8ba3-619a29427fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139235372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.3139235372
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.34939052
Short name T148
Test name
Test status
Simulation time 44565016934 ps
CPU time 19.92 seconds
Started Jun 11 12:31:18 PM PDT 24
Finished Jun 11 12:31:41 PM PDT 24
Peak memory 199308 kb
Host smart-76d1034c-d79a-4aca-a26c-b12cd163411f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34939052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.34939052
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.1998078927
Short name T196
Test name
Test status
Simulation time 91100445932 ps
CPU time 35.47 seconds
Started Jun 11 12:31:54 PM PDT 24
Finished Jun 11 12:32:31 PM PDT 24
Peak memory 200340 kb
Host smart-8b1367d8-2de3-4a47-912d-e3d9ff7b6774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998078927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.1998078927
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.2228351328
Short name T1216
Test name
Test status
Simulation time 44881391 ps
CPU time 0.74 seconds
Started Jun 11 12:23:17 PM PDT 24
Finished Jun 11 12:23:19 PM PDT 24
Peak memory 195752 kb
Host smart-ccfa7809-6d8e-4a3e-973e-a30104596024
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228351328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.2228351328
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.1784071118
Short name T1101
Test name
Test status
Simulation time 131493594 ps
CPU time 1.32 seconds
Started Jun 11 12:21:31 PM PDT 24
Finished Jun 11 12:21:33 PM PDT 24
Peak memory 198216 kb
Host smart-cceabc49-b753-42e0-b006-472c424eb316
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784071118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.1784071118
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.444775826
Short name T1159
Test name
Test status
Simulation time 39937266 ps
CPU time 0.61 seconds
Started Jun 11 12:22:30 PM PDT 24
Finished Jun 11 12:22:34 PM PDT 24
Peak memory 194156 kb
Host smart-be9cd2b3-db87-4f77-83be-7bcd3e58b1be
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444775826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.444775826
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2027421729
Short name T1118
Test name
Test status
Simulation time 33424599 ps
CPU time 0.88 seconds
Started Jun 11 12:22:52 PM PDT 24
Finished Jun 11 12:22:55 PM PDT 24
Peak memory 199356 kb
Host smart-ebcd773e-4691-460d-8942-9125ef5b8c4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027421729 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.2027421729
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.4224478336
Short name T1126
Test name
Test status
Simulation time 45181438 ps
CPU time 0.57 seconds
Started Jun 11 12:22:55 PM PDT 24
Finished Jun 11 12:22:59 PM PDT 24
Peak memory 194112 kb
Host smart-3fa2d28b-a4e1-46d0-a592-31edbfebb960
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224478336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.4224478336
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.3354040874
Short name T1224
Test name
Test status
Simulation time 155865770 ps
CPU time 1.84 seconds
Started Jun 11 12:22:58 PM PDT 24
Finished Jun 11 12:23:04 PM PDT 24
Peak memory 200416 kb
Host smart-b5f892fd-0699-4939-8eed-a8d2b82f262b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354040874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.3354040874
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.1039432635
Short name T69
Test name
Test status
Simulation time 309889598 ps
CPU time 1.31 seconds
Started Jun 11 12:22:30 PM PDT 24
Finished Jun 11 12:22:35 PM PDT 24
Peak memory 198060 kb
Host smart-5b752bfe-8c50-439f-9c71-80143204eade
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039432635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.1039432635
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.372627549
Short name T1173
Test name
Test status
Simulation time 16195782 ps
CPU time 0.74 seconds
Started Jun 11 12:25:04 PM PDT 24
Finished Jun 11 12:25:08 PM PDT 24
Peak memory 196956 kb
Host smart-6fef1921-8622-40c3-9104-a06f78c729ae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372627549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.372627549
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.729985920
Short name T1107
Test name
Test status
Simulation time 175211758 ps
CPU time 2.3 seconds
Started Jun 11 12:21:09 PM PDT 24
Finished Jun 11 12:21:12 PM PDT 24
Peak memory 198200 kb
Host smart-7560b912-6a37-49f3-b68a-baa82c7c655a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729985920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.729985920
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2120882434
Short name T42
Test name
Test status
Simulation time 15146000 ps
CPU time 0.56 seconds
Started Jun 11 12:22:25 PM PDT 24
Finished Jun 11 12:22:27 PM PDT 24
Peak memory 195668 kb
Host smart-5e6f699b-83f6-46c0-b8e5-132529b5e94c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120882434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.2120882434
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3262164734
Short name T1193
Test name
Test status
Simulation time 18824481 ps
CPU time 0.64 seconds
Started Jun 11 12:24:52 PM PDT 24
Finished Jun 11 12:24:55 PM PDT 24
Peak memory 198060 kb
Host smart-e4fea7ac-c140-4aa9-8b5b-d31bce9f927d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262164734 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.3262164734
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.1066018225
Short name T1203
Test name
Test status
Simulation time 48396360 ps
CPU time 0.63 seconds
Started Jun 11 12:18:15 PM PDT 24
Finished Jun 11 12:18:16 PM PDT 24
Peak memory 195888 kb
Host smart-b444b5f2-b881-436b-b829-e065979f3e19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066018225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.1066018225
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.2185925160
Short name T1206
Test name
Test status
Simulation time 13530563 ps
CPU time 0.59 seconds
Started Jun 11 12:19:39 PM PDT 24
Finished Jun 11 12:19:40 PM PDT 24
Peak memory 195036 kb
Host smart-a4aa8fd4-eb80-4821-b50e-89a6df2d23c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185925160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.2185925160
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2097366722
Short name T1176
Test name
Test status
Simulation time 17909862 ps
CPU time 0.7 seconds
Started Jun 11 12:24:54 PM PDT 24
Finished Jun 11 12:24:58 PM PDT 24
Peak memory 197480 kb
Host smart-bfb24816-70d5-45c8-a344-3364dfd80a19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097366722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.2097366722
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.1352896212
Short name T1137
Test name
Test status
Simulation time 161603681 ps
CPU time 1.74 seconds
Started Jun 11 12:22:29 PM PDT 24
Finished Jun 11 12:22:33 PM PDT 24
Peak memory 200360 kb
Host smart-08ac6a7a-13ca-413f-94ca-81164ce13663
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352896212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.1352896212
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1521888324
Short name T1156
Test name
Test status
Simulation time 19908434 ps
CPU time 0.9 seconds
Started Jun 11 12:25:02 PM PDT 24
Finished Jun 11 12:25:06 PM PDT 24
Peak memory 200516 kb
Host smart-076693fe-5a6c-442b-aa98-6645ed440044
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521888324 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.1521888324
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.4035529761
Short name T1229
Test name
Test status
Simulation time 58554698 ps
CPU time 0.59 seconds
Started Jun 11 12:25:02 PM PDT 24
Finished Jun 11 12:25:05 PM PDT 24
Peak memory 196428 kb
Host smart-b06b1035-2cf6-4de4-92af-ddbde8d8d7d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035529761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.4035529761
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.3039469109
Short name T1132
Test name
Test status
Simulation time 45051992 ps
CPU time 0.56 seconds
Started Jun 11 12:25:03 PM PDT 24
Finished Jun 11 12:25:06 PM PDT 24
Peak memory 195076 kb
Host smart-4aabd57b-ac08-4873-acbe-c0a9a0710df4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039469109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.3039469109
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1767755313
Short name T1194
Test name
Test status
Simulation time 16935151 ps
CPU time 0.64 seconds
Started Jun 11 12:25:02 PM PDT 24
Finished Jun 11 12:25:06 PM PDT 24
Peak memory 196416 kb
Host smart-ffc77011-9756-4859-bdbd-1b32ad186de8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767755313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.1767755313
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.1055780985
Short name T1228
Test name
Test status
Simulation time 163687535 ps
CPU time 1.38 seconds
Started Jun 11 12:25:01 PM PDT 24
Finished Jun 11 12:25:05 PM PDT 24
Peak memory 200736 kb
Host smart-988a88fe-5d89-4006-bca1-2682de2a57ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055780985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.1055780985
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.764423345
Short name T61
Test name
Test status
Simulation time 195962929 ps
CPU time 0.9 seconds
Started Jun 11 12:25:03 PM PDT 24
Finished Jun 11 12:25:07 PM PDT 24
Peak memory 199688 kb
Host smart-f5197ae1-1c0e-4700-aba0-38019d2e41ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764423345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.764423345
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.92989729
Short name T1171
Test name
Test status
Simulation time 97135208 ps
CPU time 0.69 seconds
Started Jun 11 12:24:55 PM PDT 24
Finished Jun 11 12:24:58 PM PDT 24
Peak memory 199240 kb
Host smart-06dfaa16-feb2-440d-b884-83b320f55b5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92989729 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.92989729
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.2617637923
Short name T1150
Test name
Test status
Simulation time 32086509 ps
CPU time 0.57 seconds
Started Jun 11 12:24:50 PM PDT 24
Finished Jun 11 12:24:53 PM PDT 24
Peak memory 196132 kb
Host smart-0c46301f-85c4-4f40-9bd5-a583feb0ad55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617637923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.2617637923
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.3484532489
Short name T1167
Test name
Test status
Simulation time 40908055 ps
CPU time 0.53 seconds
Started Jun 11 12:25:02 PM PDT 24
Finished Jun 11 12:25:05 PM PDT 24
Peak memory 195008 kb
Host smart-1535f8cc-3e79-4ff7-9078-4d7b8e197c2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484532489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.3484532489
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1321060651
Short name T1154
Test name
Test status
Simulation time 18119837 ps
CPU time 0.6 seconds
Started Jun 11 12:25:01 PM PDT 24
Finished Jun 11 12:25:05 PM PDT 24
Peak memory 196216 kb
Host smart-cbe4b0ea-7d44-4321-9e81-2ea385950eaf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321060651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.1321060651
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.3969572121
Short name T1140
Test name
Test status
Simulation time 49061472 ps
CPU time 1.05 seconds
Started Jun 11 12:25:02 PM PDT 24
Finished Jun 11 12:25:06 PM PDT 24
Peak memory 200512 kb
Host smart-8cddb812-a061-4897-a4af-b4354d622e82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969572121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.3969572121
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.4118811050
Short name T60
Test name
Test status
Simulation time 110284776 ps
CPU time 1.39 seconds
Started Jun 11 12:25:02 PM PDT 24
Finished Jun 11 12:25:06 PM PDT 24
Peak memory 199984 kb
Host smart-7b20ccbe-6762-4093-9fef-a15ca59a4880
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118811050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.4118811050
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.728865263
Short name T1149
Test name
Test status
Simulation time 23337206 ps
CPU time 1.07 seconds
Started Jun 11 12:25:02 PM PDT 24
Finished Jun 11 12:25:06 PM PDT 24
Peak memory 200084 kb
Host smart-45794279-5ba9-4066-ab25-aff3ceb4860e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728865263 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.728865263
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.2716296980
Short name T40
Test name
Test status
Simulation time 51206708 ps
CPU time 0.58 seconds
Started Jun 11 12:25:02 PM PDT 24
Finished Jun 11 12:25:06 PM PDT 24
Peak memory 195592 kb
Host smart-3ea79b9c-dbf7-4a47-b216-ea06fbc613ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716296980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.2716296980
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.832300749
Short name T1120
Test name
Test status
Simulation time 12319106 ps
CPU time 0.6 seconds
Started Jun 11 12:24:54 PM PDT 24
Finished Jun 11 12:24:57 PM PDT 24
Peak memory 194988 kb
Host smart-37c76a0f-890f-4368-b50d-9a66ce60a66c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832300749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.832300749
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3780355246
Short name T52
Test name
Test status
Simulation time 37532054 ps
CPU time 0.62 seconds
Started Jun 11 12:24:53 PM PDT 24
Finished Jun 11 12:24:55 PM PDT 24
Peak memory 196276 kb
Host smart-de5c6be8-c17b-4841-baf6-864b614d57a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780355246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.3780355246
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.97264982
Short name T1197
Test name
Test status
Simulation time 483548566 ps
CPU time 2.56 seconds
Started Jun 11 12:25:02 PM PDT 24
Finished Jun 11 12:25:07 PM PDT 24
Peak memory 200692 kb
Host smart-05e52e96-adb8-4a5d-ad64-815aafb60d28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97264982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.97264982
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3970749413
Short name T1109
Test name
Test status
Simulation time 178962298 ps
CPU time 1 seconds
Started Jun 11 12:25:01 PM PDT 24
Finished Jun 11 12:25:05 PM PDT 24
Peak memory 200668 kb
Host smart-79be8636-13fe-4049-b72e-ce9cb3f238c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970749413 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.3970749413
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.2223303242
Short name T1164
Test name
Test status
Simulation time 25214579 ps
CPU time 0.58 seconds
Started Jun 11 12:24:57 PM PDT 24
Finished Jun 11 12:25:01 PM PDT 24
Peak memory 196072 kb
Host smart-b0dcbac1-7503-4b01-be91-6ab441dbe9c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223303242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.2223303242
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.3185744735
Short name T1192
Test name
Test status
Simulation time 169061942 ps
CPU time 0.54 seconds
Started Jun 11 12:24:53 PM PDT 24
Finished Jun 11 12:24:55 PM PDT 24
Peak memory 195008 kb
Host smart-467ca13b-3a4b-41a7-89b9-2830fc5fe3f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185744735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.3185744735
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.2472730426
Short name T51
Test name
Test status
Simulation time 30744521 ps
CPU time 0.79 seconds
Started Jun 11 12:24:57 PM PDT 24
Finished Jun 11 12:25:01 PM PDT 24
Peak memory 197540 kb
Host smart-9351a2da-292d-4ced-8176-e07170897431
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472730426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.2472730426
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.3735385200
Short name T1165
Test name
Test status
Simulation time 365545613 ps
CPU time 1.91 seconds
Started Jun 11 12:24:54 PM PDT 24
Finished Jun 11 12:24:59 PM PDT 24
Peak memory 200556 kb
Host smart-248156f0-ab7a-4218-80f8-ca04aa4fc7d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735385200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.3735385200
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3606197377
Short name T1188
Test name
Test status
Simulation time 71004862 ps
CPU time 0.92 seconds
Started Jun 11 12:24:49 PM PDT 24
Finished Jun 11 12:24:52 PM PDT 24
Peak memory 199892 kb
Host smart-eb1580de-b867-4fc3-97f7-3086fa6bc23a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606197377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.3606197377
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.1402225081
Short name T1223
Test name
Test status
Simulation time 39625540 ps
CPU time 1 seconds
Started Jun 11 12:25:02 PM PDT 24
Finished Jun 11 12:25:05 PM PDT 24
Peak memory 200444 kb
Host smart-a0410c60-56fb-4c50-b49b-1ddb7bfc927e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402225081 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.1402225081
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.1135298789
Short name T1139
Test name
Test status
Simulation time 48101164 ps
CPU time 0.58 seconds
Started Jun 11 12:25:02 PM PDT 24
Finished Jun 11 12:25:05 PM PDT 24
Peak memory 196000 kb
Host smart-01535658-3f25-4d28-8d15-0546ccc44d6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135298789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.1135298789
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.1232351499
Short name T1129
Test name
Test status
Simulation time 133010795 ps
CPU time 0.62 seconds
Started Jun 11 12:24:58 PM PDT 24
Finished Jun 11 12:25:01 PM PDT 24
Peak memory 195024 kb
Host smart-90d0d105-c93b-4167-9f8e-0a0602a3d960
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232351499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.1232351499
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3434210080
Short name T1199
Test name
Test status
Simulation time 34575347 ps
CPU time 0.59 seconds
Started Jun 11 12:24:54 PM PDT 24
Finished Jun 11 12:24:57 PM PDT 24
Peak memory 196128 kb
Host smart-6ed91a04-338d-4b46-b06f-eebba8205a50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434210080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.3434210080
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.2754659202
Short name T1111
Test name
Test status
Simulation time 355882570 ps
CPU time 1.87 seconds
Started Jun 11 12:25:03 PM PDT 24
Finished Jun 11 12:25:08 PM PDT 24
Peak memory 200660 kb
Host smart-c9bada06-532c-4f06-b3dc-4583fa754fa4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754659202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.2754659202
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2340064625
Short name T1153
Test name
Test status
Simulation time 22554765 ps
CPU time 0.63 seconds
Started Jun 11 12:25:09 PM PDT 24
Finished Jun 11 12:25:11 PM PDT 24
Peak memory 198348 kb
Host smart-fd757aa9-fe39-4428-b672-6ba58fa358c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340064625 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.2340064625
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.1958284055
Short name T45
Test name
Test status
Simulation time 40980455 ps
CPU time 0.57 seconds
Started Jun 11 12:25:16 PM PDT 24
Finished Jun 11 12:25:18 PM PDT 24
Peak memory 196184 kb
Host smart-3691387c-15f4-43f1-aa99-a8bf8b52a73f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958284055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.1958284055
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.1741757946
Short name T1127
Test name
Test status
Simulation time 38141306 ps
CPU time 0.52 seconds
Started Jun 11 12:25:11 PM PDT 24
Finished Jun 11 12:25:13 PM PDT 24
Peak memory 195012 kb
Host smart-c1cc37c4-d2d0-41bd-9271-4e86e0dc9f1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741757946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.1741757946
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1447505188
Short name T1142
Test name
Test status
Simulation time 111707039 ps
CPU time 0.64 seconds
Started Jun 11 12:25:10 PM PDT 24
Finished Jun 11 12:25:13 PM PDT 24
Peak memory 196544 kb
Host smart-c9680e48-d7da-4964-875a-f411fd88bce1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447505188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.1447505188
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.1997000300
Short name T1146
Test name
Test status
Simulation time 163517707 ps
CPU time 1.17 seconds
Started Jun 11 12:25:08 PM PDT 24
Finished Jun 11 12:25:11 PM PDT 24
Peak memory 200696 kb
Host smart-df9a2a0a-c7a9-405a-81da-9878ae1274c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997000300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.1997000300
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2002687105
Short name T64
Test name
Test status
Simulation time 318777054 ps
CPU time 0.89 seconds
Started Jun 11 12:25:07 PM PDT 24
Finished Jun 11 12:25:10 PM PDT 24
Peak memory 199676 kb
Host smart-e18f590a-e617-4132-a63e-2b9e1280ef49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002687105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.2002687105
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.598910080
Short name T1233
Test name
Test status
Simulation time 26665816 ps
CPU time 1.08 seconds
Started Jun 11 12:25:10 PM PDT 24
Finished Jun 11 12:25:13 PM PDT 24
Peak memory 200688 kb
Host smart-64d89827-0725-47f5-b901-fada438d3d55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598910080 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.598910080
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.3498479616
Short name T1152
Test name
Test status
Simulation time 48230716 ps
CPU time 0.6 seconds
Started Jun 11 12:25:17 PM PDT 24
Finished Jun 11 12:25:19 PM PDT 24
Peak memory 196444 kb
Host smart-012ea708-3011-4a92-af03-975c38d7f2be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498479616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.3498479616
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.3743390255
Short name T1115
Test name
Test status
Simulation time 15364864 ps
CPU time 0.53 seconds
Started Jun 11 12:25:14 PM PDT 24
Finished Jun 11 12:25:16 PM PDT 24
Peak memory 195072 kb
Host smart-564f5bf2-38ce-4f41-b3b0-c27afb46376d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743390255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.3743390255
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.3735554215
Short name T1200
Test name
Test status
Simulation time 139404573 ps
CPU time 0.74 seconds
Started Jun 11 12:25:13 PM PDT 24
Finished Jun 11 12:25:16 PM PDT 24
Peak memory 197724 kb
Host smart-60c3ea06-8ab1-45cc-b12b-d7c7ea72a0d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735554215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.3735554215
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.2464681464
Short name T1148
Test name
Test status
Simulation time 199904687 ps
CPU time 1.03 seconds
Started Jun 11 12:25:12 PM PDT 24
Finished Jun 11 12:25:15 PM PDT 24
Peak memory 200612 kb
Host smart-7a952837-4148-40b4-99fc-9393b709b23d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464681464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.2464681464
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.1922115739
Short name T1169
Test name
Test status
Simulation time 266646294 ps
CPU time 1.24 seconds
Started Jun 11 12:25:06 PM PDT 24
Finished Jun 11 12:25:10 PM PDT 24
Peak memory 200116 kb
Host smart-9c68a147-9320-42ec-b96f-6ac77f2e044a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922115739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.1922115739
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3710493379
Short name T1218
Test name
Test status
Simulation time 88447042 ps
CPU time 0.74 seconds
Started Jun 11 12:25:13 PM PDT 24
Finished Jun 11 12:25:15 PM PDT 24
Peak memory 199552 kb
Host smart-ec43f951-c918-48a3-a97c-10b0a3642166
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710493379 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.3710493379
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.529819200
Short name T55
Test name
Test status
Simulation time 29990574 ps
CPU time 0.6 seconds
Started Jun 11 12:25:10 PM PDT 24
Finished Jun 11 12:25:13 PM PDT 24
Peak memory 195932 kb
Host smart-d9ff6c6a-05d1-44aa-8fdc-5b111b7d4be8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529819200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.529819200
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.4234399303
Short name T1130
Test name
Test status
Simulation time 49156969 ps
CPU time 0.61 seconds
Started Jun 11 12:25:13 PM PDT 24
Finished Jun 11 12:25:15 PM PDT 24
Peak memory 195352 kb
Host smart-5e74650c-8514-4495-a77d-01364e1af9b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234399303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.4234399303
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.1124652482
Short name T56
Test name
Test status
Simulation time 49803703 ps
CPU time 0.77 seconds
Started Jun 11 12:25:09 PM PDT 24
Finished Jun 11 12:25:11 PM PDT 24
Peak memory 197524 kb
Host smart-806065a7-1c87-4297-8346-129bbe3ac9f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124652482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.1124652482
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.1396549738
Short name T1133
Test name
Test status
Simulation time 42361906 ps
CPU time 1.97 seconds
Started Jun 11 12:25:09 PM PDT 24
Finished Jun 11 12:25:13 PM PDT 24
Peak memory 200636 kb
Host smart-2a713039-78f0-45f5-81d9-6aa0d24d3818
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396549738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.1396549738
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.2939291368
Short name T62
Test name
Test status
Simulation time 174493996 ps
CPU time 0.89 seconds
Started Jun 11 12:25:16 PM PDT 24
Finished Jun 11 12:25:18 PM PDT 24
Peak memory 199592 kb
Host smart-81771575-6c52-4d32-b671-e9d7a6611d92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939291368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.2939291368
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3159105236
Short name T1220
Test name
Test status
Simulation time 32717161 ps
CPU time 0.74 seconds
Started Jun 11 12:25:13 PM PDT 24
Finished Jun 11 12:25:15 PM PDT 24
Peak memory 199172 kb
Host smart-6be8ca14-1825-4fef-bedf-568773d4946c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159105236 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.3159105236
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.4229179371
Short name T39
Test name
Test status
Simulation time 13001602 ps
CPU time 0.66 seconds
Started Jun 11 12:25:12 PM PDT 24
Finished Jun 11 12:25:15 PM PDT 24
Peak memory 196408 kb
Host smart-e8d558e6-fbe0-4ab4-9110-c5f9e7c5f390
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229179371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.4229179371
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.1105034007
Short name T1178
Test name
Test status
Simulation time 12488222 ps
CPU time 0.55 seconds
Started Jun 11 12:25:10 PM PDT 24
Finished Jun 11 12:25:13 PM PDT 24
Peak memory 195056 kb
Host smart-e98122ed-d1ad-4d5f-83a7-612067e15258
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105034007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.1105034007
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2599193689
Short name T1189
Test name
Test status
Simulation time 36210154 ps
CPU time 0.64 seconds
Started Jun 11 12:25:24 PM PDT 24
Finished Jun 11 12:25:26 PM PDT 24
Peak memory 196164 kb
Host smart-4b33a91c-58e1-445a-b721-d14f3f91f2b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599193689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.2599193689
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.4162755941
Short name T1208
Test name
Test status
Simulation time 34768650 ps
CPU time 0.93 seconds
Started Jun 11 12:25:10 PM PDT 24
Finished Jun 11 12:25:13 PM PDT 24
Peak memory 200444 kb
Host smart-677d6c16-e8dc-4254-8bef-06b6c5d9bf53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162755941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.4162755941
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.252249831
Short name T1195
Test name
Test status
Simulation time 122576319 ps
CPU time 1 seconds
Started Jun 11 12:25:24 PM PDT 24
Finished Jun 11 12:25:26 PM PDT 24
Peak memory 199640 kb
Host smart-b4fbe032-ef06-43da-8549-d81e22ab5514
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252249831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.252249831
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3414417021
Short name T1219
Test name
Test status
Simulation time 39852741 ps
CPU time 0.64 seconds
Started Jun 11 12:25:09 PM PDT 24
Finished Jun 11 12:25:12 PM PDT 24
Peak memory 198368 kb
Host smart-afca1b10-a105-42b6-a20f-922c83053aed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414417021 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.3414417021
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.371747487
Short name T1184
Test name
Test status
Simulation time 14837787 ps
CPU time 0.55 seconds
Started Jun 11 12:25:13 PM PDT 24
Finished Jun 11 12:25:15 PM PDT 24
Peak memory 195988 kb
Host smart-341179d9-bc17-481b-ad28-daffce9a0a96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371747487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.371747487
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.3891078317
Short name T1207
Test name
Test status
Simulation time 14346940 ps
CPU time 0.58 seconds
Started Jun 11 12:25:10 PM PDT 24
Finished Jun 11 12:25:12 PM PDT 24
Peak memory 195020 kb
Host smart-9ba08592-6869-4017-9d73-e3c1a241de15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891078317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.3891078317
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1867783109
Short name T49
Test name
Test status
Simulation time 80483217 ps
CPU time 0.69 seconds
Started Jun 11 12:25:11 PM PDT 24
Finished Jun 11 12:25:14 PM PDT 24
Peak memory 197480 kb
Host smart-978fae48-e8a1-4356-b3fc-31cacf5cfe72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867783109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.1867783109
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.405785385
Short name T1185
Test name
Test status
Simulation time 54048181 ps
CPU time 1.25 seconds
Started Jun 11 12:25:09 PM PDT 24
Finished Jun 11 12:25:13 PM PDT 24
Peak memory 200640 kb
Host smart-594edf66-8640-4a7b-b3b5-86872a2c7f8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405785385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.405785385
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2399257396
Short name T1221
Test name
Test status
Simulation time 91666803 ps
CPU time 1.29 seconds
Started Jun 11 12:25:11 PM PDT 24
Finished Jun 11 12:25:14 PM PDT 24
Peak memory 200148 kb
Host smart-7e2ecf93-5bed-4ccf-9704-a1e0470c8c15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399257396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.2399257396
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.1581355627
Short name T1122
Test name
Test status
Simulation time 46180228 ps
CPU time 0.7 seconds
Started Jun 11 12:24:53 PM PDT 24
Finished Jun 11 12:24:56 PM PDT 24
Peak memory 196764 kb
Host smart-9454f50a-31ca-447c-9453-7c47aaf5d13d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581355627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.1581355627
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.4267603084
Short name T1151
Test name
Test status
Simulation time 126498782 ps
CPU time 1.33 seconds
Started Jun 11 12:24:56 PM PDT 24
Finished Jun 11 12:25:00 PM PDT 24
Peak memory 198684 kb
Host smart-443edb3d-8fac-4a44-9fac-1816eeb9f9bd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267603084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.4267603084
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2951722953
Short name T1145
Test name
Test status
Simulation time 52068402 ps
CPU time 0.58 seconds
Started Jun 11 12:24:56 PM PDT 24
Finished Jun 11 12:25:00 PM PDT 24
Peak memory 196052 kb
Host smart-f7c1a4a0-8e2f-43f2-8068-90f88a8577fc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951722953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.2951722953
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.2961517874
Short name T1116
Test name
Test status
Simulation time 97181707 ps
CPU time 1.28 seconds
Started Jun 11 12:25:05 PM PDT 24
Finished Jun 11 12:25:10 PM PDT 24
Peak memory 200704 kb
Host smart-3b32685a-8a1c-4a2b-aa27-ec7f9e8b95da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961517874 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.2961517874
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.1540893427
Short name T38
Test name
Test status
Simulation time 186027182 ps
CPU time 0.59 seconds
Started Jun 11 12:25:04 PM PDT 24
Finished Jun 11 12:25:08 PM PDT 24
Peak memory 196048 kb
Host smart-33e2d56d-5abb-4e26-a43d-c00978a03110
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540893427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.1540893427
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.145891351
Short name T1128
Test name
Test status
Simulation time 28951899 ps
CPU time 0.57 seconds
Started Jun 11 12:25:05 PM PDT 24
Finished Jun 11 12:25:10 PM PDT 24
Peak memory 195080 kb
Host smart-93f77b68-bf68-4da2-9076-c0071075e51e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145891351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.145891351
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.1756752475
Short name T1214
Test name
Test status
Simulation time 32001765 ps
CPU time 0.75 seconds
Started Jun 11 12:24:54 PM PDT 24
Finished Jun 11 12:24:58 PM PDT 24
Peak memory 197508 kb
Host smart-aafff9a0-7436-43cd-8489-add529ff0a69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756752475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.1756752475
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.3001347041
Short name T1104
Test name
Test status
Simulation time 39726672 ps
CPU time 1.99 seconds
Started Jun 11 12:24:55 PM PDT 24
Finished Jun 11 12:25:00 PM PDT 24
Peak memory 200620 kb
Host smart-cf99462b-9463-4de2-bd3e-f6109338e5c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001347041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.3001347041
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.3507525362
Short name T68
Test name
Test status
Simulation time 1153424929 ps
CPU time 0.97 seconds
Started Jun 11 12:24:53 PM PDT 24
Finished Jun 11 12:24:57 PM PDT 24
Peak memory 199768 kb
Host smart-95e56cc6-c7dd-44de-8d45-2d2f12443dfe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507525362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.3507525362
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.3456721320
Short name T1134
Test name
Test status
Simulation time 15257104 ps
CPU time 0.52 seconds
Started Jun 11 12:25:06 PM PDT 24
Finished Jun 11 12:25:10 PM PDT 24
Peak memory 194820 kb
Host smart-0e8a60b9-7c35-43b9-82f7-db789edd3377
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456721320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.3456721320
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.1988171136
Short name T1125
Test name
Test status
Simulation time 26542635 ps
CPU time 0.59 seconds
Started Jun 11 12:25:24 PM PDT 24
Finished Jun 11 12:25:26 PM PDT 24
Peak memory 194844 kb
Host smart-09e413af-e104-407e-a6fb-1234e7a6fdb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988171136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.1988171136
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.2672712627
Short name T1158
Test name
Test status
Simulation time 13633786 ps
CPU time 0.58 seconds
Started Jun 11 12:25:10 PM PDT 24
Finished Jun 11 12:25:14 PM PDT 24
Peak memory 195080 kb
Host smart-9284375f-91bb-4b44-8fda-59d13928658b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672712627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.2672712627
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.185972487
Short name T1110
Test name
Test status
Simulation time 37568051 ps
CPU time 0.53 seconds
Started Jun 11 12:25:16 PM PDT 24
Finished Jun 11 12:25:18 PM PDT 24
Peak memory 195064 kb
Host smart-892d2d8c-0c06-41b9-be61-184c6e772ffc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185972487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.185972487
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.519997382
Short name T1230
Test name
Test status
Simulation time 43506013 ps
CPU time 0.52 seconds
Started Jun 11 12:25:10 PM PDT 24
Finished Jun 11 12:25:13 PM PDT 24
Peak memory 194996 kb
Host smart-a7202dbf-36b2-4254-9112-7473931740bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519997382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.519997382
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.1532196212
Short name T1117
Test name
Test status
Simulation time 46054253 ps
CPU time 0.56 seconds
Started Jun 11 12:25:08 PM PDT 24
Finished Jun 11 12:25:11 PM PDT 24
Peak memory 194868 kb
Host smart-8cce8d51-5a8b-4a6e-acbe-597de3b33ae1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532196212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.1532196212
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.106241436
Short name T1209
Test name
Test status
Simulation time 26247433 ps
CPU time 0.54 seconds
Started Jun 11 12:25:17 PM PDT 24
Finished Jun 11 12:25:18 PM PDT 24
Peak memory 195128 kb
Host smart-348f3cba-c5fe-48d3-9d3c-fe06e2793980
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106241436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.106241436
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.281706321
Short name T1205
Test name
Test status
Simulation time 31936119 ps
CPU time 0.55 seconds
Started Jun 11 12:25:12 PM PDT 24
Finished Jun 11 12:25:15 PM PDT 24
Peak memory 195124 kb
Host smart-7f1950fa-90fb-41f6-82df-a7345a28597c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281706321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.281706321
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.4156040710
Short name T1180
Test name
Test status
Simulation time 16986681 ps
CPU time 0.58 seconds
Started Jun 11 12:25:08 PM PDT 24
Finished Jun 11 12:25:11 PM PDT 24
Peak memory 195052 kb
Host smart-47bf9d79-bb43-4b32-9e1f-55a39accb590
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156040710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.4156040710
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.682206383
Short name T1108
Test name
Test status
Simulation time 11044938 ps
CPU time 0.53 seconds
Started Jun 11 12:25:12 PM PDT 24
Finished Jun 11 12:25:14 PM PDT 24
Peak memory 194916 kb
Host smart-85c38a74-5a04-40c3-bc48-d4564f481c5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682206383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.682206383
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1207957618
Short name T47
Test name
Test status
Simulation time 47176069 ps
CPU time 0.73 seconds
Started Jun 11 12:24:55 PM PDT 24
Finished Jun 11 12:24:58 PM PDT 24
Peak memory 197100 kb
Host smart-d4e5df4e-9dd0-4aaf-8afe-95e80f239bcc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207957618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.1207957618
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.3976101867
Short name T1212
Test name
Test status
Simulation time 108561492 ps
CPU time 2.12 seconds
Started Jun 11 12:25:02 PM PDT 24
Finished Jun 11 12:25:07 PM PDT 24
Peak memory 197900 kb
Host smart-2729e799-316c-44c3-ba74-eb58f6b989b1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976101867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.3976101867
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.925209176
Short name T1182
Test name
Test status
Simulation time 15855488 ps
CPU time 0.55 seconds
Started Jun 11 12:25:04 PM PDT 24
Finished Jun 11 12:25:08 PM PDT 24
Peak memory 196036 kb
Host smart-ad035f7d-c3b5-492e-aa32-e076ac7667e3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925209176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.925209176
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3888747005
Short name T1103
Test name
Test status
Simulation time 89842864 ps
CPU time 0.65 seconds
Started Jun 11 12:25:02 PM PDT 24
Finished Jun 11 12:25:05 PM PDT 24
Peak memory 198572 kb
Host smart-b0d9fc24-b542-4435-b112-413c49a52d31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888747005 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.3888747005
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.829900501
Short name T57
Test name
Test status
Simulation time 15995824 ps
CPU time 0.56 seconds
Started Jun 11 12:25:03 PM PDT 24
Finished Jun 11 12:25:07 PM PDT 24
Peak memory 196064 kb
Host smart-1934d6aa-d3c4-44dc-88cd-23fc521f55ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829900501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.829900501
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.266971966
Short name T1124
Test name
Test status
Simulation time 12373242 ps
CPU time 0.53 seconds
Started Jun 11 12:25:04 PM PDT 24
Finished Jun 11 12:25:08 PM PDT 24
Peak memory 195036 kb
Host smart-a68cc605-9d1d-47f5-be8e-6ff7223b90f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266971966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.266971966
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2781668654
Short name T54
Test name
Test status
Simulation time 113265651 ps
CPU time 0.71 seconds
Started Jun 11 12:24:55 PM PDT 24
Finished Jun 11 12:24:59 PM PDT 24
Peak memory 197732 kb
Host smart-15683b64-a3ed-44ac-8c23-626e82ad42c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781668654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.2781668654
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.1557276399
Short name T1198
Test name
Test status
Simulation time 38213977 ps
CPU time 1.78 seconds
Started Jun 11 12:25:07 PM PDT 24
Finished Jun 11 12:25:12 PM PDT 24
Peak memory 200740 kb
Host smart-38882b6e-b930-47b2-a517-3f81fa8b3d4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557276399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.1557276399
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.42463833
Short name T1183
Test name
Test status
Simulation time 85033449 ps
CPU time 1.24 seconds
Started Jun 11 12:25:04 PM PDT 24
Finished Jun 11 12:25:09 PM PDT 24
Peak memory 199944 kb
Host smart-45985049-2c18-44ff-a478-81ff462b1cfa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42463833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.42463833
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.3373134622
Short name T1105
Test name
Test status
Simulation time 13916181 ps
CPU time 0.55 seconds
Started Jun 11 12:25:11 PM PDT 24
Finished Jun 11 12:25:13 PM PDT 24
Peak memory 195048 kb
Host smart-7118babf-4b41-403f-83c2-61436432425a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373134622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.3373134622
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.2150042272
Short name T1215
Test name
Test status
Simulation time 37434243 ps
CPU time 0.58 seconds
Started Jun 11 12:25:10 PM PDT 24
Finished Jun 11 12:25:13 PM PDT 24
Peak memory 194848 kb
Host smart-44317611-8907-463e-8903-0ee54aea4fa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150042272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.2150042272
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.906778084
Short name T1191
Test name
Test status
Simulation time 44627377 ps
CPU time 0.58 seconds
Started Jun 11 12:25:24 PM PDT 24
Finished Jun 11 12:25:26 PM PDT 24
Peak memory 195032 kb
Host smart-70b85e71-2d07-40b7-9b8d-8449a7c08900
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906778084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.906778084
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.572453256
Short name T1157
Test name
Test status
Simulation time 17858763 ps
CPU time 0.56 seconds
Started Jun 11 12:25:17 PM PDT 24
Finished Jun 11 12:25:19 PM PDT 24
Peak memory 195136 kb
Host smart-62df462e-b040-4c76-b67a-b4441e3e3c4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572453256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.572453256
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.2664618980
Short name T1231
Test name
Test status
Simulation time 16321299 ps
CPU time 0.59 seconds
Started Jun 11 12:25:09 PM PDT 24
Finished Jun 11 12:25:16 PM PDT 24
Peak memory 195336 kb
Host smart-322d0d98-7ed3-448a-8c41-75bb967e3bfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664618980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.2664618980
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.834452512
Short name T1179
Test name
Test status
Simulation time 21866049 ps
CPU time 0.53 seconds
Started Jun 11 12:25:11 PM PDT 24
Finished Jun 11 12:25:13 PM PDT 24
Peak memory 195120 kb
Host smart-9b04ce86-012d-4e87-ac9b-e623214568ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834452512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.834452512
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.2818234517
Short name T1162
Test name
Test status
Simulation time 14269132 ps
CPU time 0.58 seconds
Started Jun 11 12:25:09 PM PDT 24
Finished Jun 11 12:25:12 PM PDT 24
Peak memory 195272 kb
Host smart-7f54bdb2-6da8-4b90-ba3b-7d4d00e76d5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818234517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.2818234517
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.221729234
Short name T1144
Test name
Test status
Simulation time 28314997 ps
CPU time 0.57 seconds
Started Jun 11 12:25:14 PM PDT 24
Finished Jun 11 12:25:16 PM PDT 24
Peak memory 195276 kb
Host smart-abc6abe8-7817-44f5-8c0f-f74f46be204f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221729234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.221729234
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.61691688
Short name T1143
Test name
Test status
Simulation time 22784707 ps
CPU time 0.57 seconds
Started Jun 11 12:25:24 PM PDT 24
Finished Jun 11 12:25:26 PM PDT 24
Peak memory 194920 kb
Host smart-3d34b401-c183-4455-b298-eadcd58e1cd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61691688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.61691688
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.3426630748
Short name T1119
Test name
Test status
Simulation time 15350102 ps
CPU time 0.56 seconds
Started Jun 11 12:25:16 PM PDT 24
Finished Jun 11 12:25:18 PM PDT 24
Peak memory 195088 kb
Host smart-ff935867-4f09-47b9-91b4-30aab9d4246b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426630748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.3426630748
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1718739561
Short name T44
Test name
Test status
Simulation time 59358351 ps
CPU time 0.73 seconds
Started Jun 11 12:24:52 PM PDT 24
Finished Jun 11 12:24:54 PM PDT 24
Peak memory 196864 kb
Host smart-6517f30a-7c0f-4514-a434-5f9d01d6a558
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718739561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.1718739561
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.673415208
Short name T1136
Test name
Test status
Simulation time 65393263 ps
CPU time 1.36 seconds
Started Jun 11 12:24:54 PM PDT 24
Finished Jun 11 12:24:58 PM PDT 24
Peak memory 198408 kb
Host smart-6e01f07a-da13-4840-8473-51141bff01eb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673415208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.673415208
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1837043518
Short name T1187
Test name
Test status
Simulation time 24324491 ps
CPU time 0.61 seconds
Started Jun 11 12:24:58 PM PDT 24
Finished Jun 11 12:25:01 PM PDT 24
Peak memory 196068 kb
Host smart-f5fb1738-f877-432b-ae5b-a8229678d817
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837043518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.1837043518
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2940984072
Short name T1181
Test name
Test status
Simulation time 17711482 ps
CPU time 0.64 seconds
Started Jun 11 12:24:55 PM PDT 24
Finished Jun 11 12:24:59 PM PDT 24
Peak memory 198264 kb
Host smart-4514f4e4-d83b-451e-82e4-a99a438ef18f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940984072 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.2940984072
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.3324554451
Short name T43
Test name
Test status
Simulation time 12550941 ps
CPU time 0.58 seconds
Started Jun 11 12:24:55 PM PDT 24
Finished Jun 11 12:24:58 PM PDT 24
Peak memory 196056 kb
Host smart-f6a356b0-45a0-41ac-ba70-0aebc663b97d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324554451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.3324554451
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.4166240211
Short name T1222
Test name
Test status
Simulation time 33016532 ps
CPU time 0.59 seconds
Started Jun 11 12:24:53 PM PDT 24
Finished Jun 11 12:24:55 PM PDT 24
Peak memory 194996 kb
Host smart-c7d1bf99-7400-4de4-893f-6fcb0a9f5991
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166240211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.4166240211
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.3743968707
Short name T1213
Test name
Test status
Simulation time 103386616 ps
CPU time 0.7 seconds
Started Jun 11 12:24:51 PM PDT 24
Finished Jun 11 12:24:53 PM PDT 24
Peak memory 197824 kb
Host smart-e578bbbe-7e14-4acd-a317-5ded34587aa3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743968707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.3743968707
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.3869026150
Short name T1204
Test name
Test status
Simulation time 61331736 ps
CPU time 1.43 seconds
Started Jun 11 12:24:57 PM PDT 24
Finished Jun 11 12:25:01 PM PDT 24
Peak memory 200912 kb
Host smart-13caeead-2d47-4224-a11b-4e9b86fac79f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869026150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.3869026150
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.4061796804
Short name T1141
Test name
Test status
Simulation time 166814169 ps
CPU time 0.93 seconds
Started Jun 11 12:24:53 PM PDT 24
Finished Jun 11 12:24:56 PM PDT 24
Peak memory 199372 kb
Host smart-98970145-ff70-498f-84b8-d25de1774369
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061796804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.4061796804
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.2988972860
Short name T1166
Test name
Test status
Simulation time 17895805 ps
CPU time 0.55 seconds
Started Jun 11 12:25:12 PM PDT 24
Finished Jun 11 12:25:14 PM PDT 24
Peak memory 195000 kb
Host smart-b77d23fc-a358-4823-83bc-be7350788ccd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988972860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.2988972860
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.1302324744
Short name T1147
Test name
Test status
Simulation time 36812975 ps
CPU time 0.59 seconds
Started Jun 11 12:25:13 PM PDT 24
Finished Jun 11 12:25:15 PM PDT 24
Peak memory 195348 kb
Host smart-102c9588-8bee-4c01-837d-6caeed0e5c92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302324744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.1302324744
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.4125333979
Short name T1138
Test name
Test status
Simulation time 20688534 ps
CPU time 0.55 seconds
Started Jun 11 12:25:24 PM PDT 24
Finished Jun 11 12:25:26 PM PDT 24
Peak memory 194920 kb
Host smart-47153486-22d6-47f4-b0bb-246a35a10d56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125333979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.4125333979
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.3197614923
Short name T1161
Test name
Test status
Simulation time 32406627 ps
CPU time 0.54 seconds
Started Jun 11 12:25:24 PM PDT 24
Finished Jun 11 12:25:25 PM PDT 24
Peak memory 194696 kb
Host smart-c2311d62-ffd8-4218-adad-bba7611040e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197614923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.3197614923
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.3099052702
Short name T1232
Test name
Test status
Simulation time 12120556 ps
CPU time 0.55 seconds
Started Jun 11 12:25:11 PM PDT 24
Finished Jun 11 12:25:13 PM PDT 24
Peak memory 194896 kb
Host smart-6dee0787-e034-4c6a-980b-cce5473ece19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099052702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.3099052702
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.2077291305
Short name T1225
Test name
Test status
Simulation time 13634276 ps
CPU time 0.58 seconds
Started Jun 11 12:25:24 PM PDT 24
Finished Jun 11 12:25:26 PM PDT 24
Peak memory 194920 kb
Host smart-836bae88-452e-49d4-be1e-b034fa3b4126
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077291305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.2077291305
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.1147277787
Short name T1102
Test name
Test status
Simulation time 73332166 ps
CPU time 0.56 seconds
Started Jun 11 12:25:24 PM PDT 24
Finished Jun 11 12:25:25 PM PDT 24
Peak memory 194832 kb
Host smart-6ab6acc8-921a-4523-80c1-075adc22b922
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147277787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.1147277787
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.959362956
Short name T1163
Test name
Test status
Simulation time 22256807 ps
CPU time 0.56 seconds
Started Jun 11 12:25:32 PM PDT 24
Finished Jun 11 12:25:34 PM PDT 24
Peak memory 195120 kb
Host smart-e3b6505c-01e7-44f0-807a-0f497567d453
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959362956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.959362956
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.3808625311
Short name T1170
Test name
Test status
Simulation time 17835809 ps
CPU time 0.54 seconds
Started Jun 11 12:25:20 PM PDT 24
Finished Jun 11 12:25:22 PM PDT 24
Peak memory 194944 kb
Host smart-85a96b97-0ba4-4b7a-ba77-2f79e863130a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808625311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.3808625311
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.1382906715
Short name T1175
Test name
Test status
Simulation time 18148282 ps
CPU time 0.6 seconds
Started Jun 11 12:25:23 PM PDT 24
Finished Jun 11 12:25:25 PM PDT 24
Peak memory 195080 kb
Host smart-4a745b0f-31ae-4418-a0b3-d20fe87083f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382906715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.1382906715
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3567874296
Short name T1131
Test name
Test status
Simulation time 62855351 ps
CPU time 0.84 seconds
Started Jun 11 12:24:53 PM PDT 24
Finished Jun 11 12:24:56 PM PDT 24
Peak memory 200480 kb
Host smart-dc05347f-c9ce-490f-8753-fb46a5c9b142
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567874296 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.3567874296
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.2468168896
Short name T48
Test name
Test status
Simulation time 11555124 ps
CPU time 0.57 seconds
Started Jun 11 12:24:54 PM PDT 24
Finished Jun 11 12:24:57 PM PDT 24
Peak memory 196076 kb
Host smart-fa222626-1895-45a2-a14d-e2641f1cd1bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468168896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.2468168896
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.4209900332
Short name T1106
Test name
Test status
Simulation time 16003968 ps
CPU time 0.55 seconds
Started Jun 11 12:25:01 PM PDT 24
Finished Jun 11 12:25:04 PM PDT 24
Peak memory 195128 kb
Host smart-16092e19-0b8b-42c2-9cf5-1bf8488a1856
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209900332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.4209900332
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.3360100485
Short name T1168
Test name
Test status
Simulation time 41178173 ps
CPU time 0.61 seconds
Started Jun 11 12:24:56 PM PDT 24
Finished Jun 11 12:25:00 PM PDT 24
Peak memory 195216 kb
Host smart-74f3a4c2-00cd-403d-ab65-605aede4b681
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360100485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.3360100485
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.3039695940
Short name T1210
Test name
Test status
Simulation time 86577384 ps
CPU time 1.83 seconds
Started Jun 11 12:24:55 PM PDT 24
Finished Jun 11 12:25:00 PM PDT 24
Peak memory 200720 kb
Host smart-0de321ea-5fd5-4cf3-bd9d-c7469c41df1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039695940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.3039695940
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1559661881
Short name T65
Test name
Test status
Simulation time 77856247 ps
CPU time 0.91 seconds
Started Jun 11 12:24:51 PM PDT 24
Finished Jun 11 12:24:54 PM PDT 24
Peak memory 199592 kb
Host smart-c6e81eb0-fbc8-4a2c-ac53-ff574bddc577
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559661881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.1559661881
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1782690366
Short name T1113
Test name
Test status
Simulation time 52071115 ps
CPU time 0.72 seconds
Started Jun 11 12:24:55 PM PDT 24
Finished Jun 11 12:24:59 PM PDT 24
Peak memory 199908 kb
Host smart-e064971a-d580-40a3-9790-9e1a404dfa6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782690366 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.1782690366
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.3823984198
Short name T50
Test name
Test status
Simulation time 37559859 ps
CPU time 0.59 seconds
Started Jun 11 12:24:52 PM PDT 24
Finished Jun 11 12:24:55 PM PDT 24
Peak memory 196028 kb
Host smart-3919f8c1-01de-4212-9917-acd1a1c1076f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823984198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.3823984198
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.4293126350
Short name T1190
Test name
Test status
Simulation time 12122076 ps
CPU time 0.55 seconds
Started Jun 11 12:24:54 PM PDT 24
Finished Jun 11 12:24:58 PM PDT 24
Peak memory 195140 kb
Host smart-79764d02-5e0e-488e-9ee4-e3b659b9c72a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293126350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.4293126350
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.2998957879
Short name T1177
Test name
Test status
Simulation time 44890253 ps
CPU time 0.65 seconds
Started Jun 11 12:24:55 PM PDT 24
Finished Jun 11 12:24:59 PM PDT 24
Peak memory 196284 kb
Host smart-7153a442-e767-44b4-9492-9561a8866310
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998957879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.2998957879
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.4146572557
Short name T1123
Test name
Test status
Simulation time 73412068 ps
CPU time 1.42 seconds
Started Jun 11 12:24:52 PM PDT 24
Finished Jun 11 12:24:55 PM PDT 24
Peak memory 200620 kb
Host smart-61a9bb91-325b-4fe8-926e-b3bb07fee622
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146572557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.4146572557
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.637108018
Short name T105
Test name
Test status
Simulation time 106716286 ps
CPU time 0.92 seconds
Started Jun 11 12:24:55 PM PDT 24
Finished Jun 11 12:24:59 PM PDT 24
Peak memory 199524 kb
Host smart-0c12b752-d365-47b2-8cd1-49909543d1e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637108018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.637108018
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.716584368
Short name T1172
Test name
Test status
Simulation time 74283934 ps
CPU time 0.75 seconds
Started Jun 11 12:24:49 PM PDT 24
Finished Jun 11 12:24:52 PM PDT 24
Peak memory 199356 kb
Host smart-95d94b7f-48ca-4213-bb24-0f48ddff0659
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716584368 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.716584368
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.1497989492
Short name T41
Test name
Test status
Simulation time 24786474 ps
CPU time 0.59 seconds
Started Jun 11 12:24:58 PM PDT 24
Finished Jun 11 12:25:01 PM PDT 24
Peak memory 196072 kb
Host smart-deec978b-f3a7-4e66-8c4c-8d43a4e7d4ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497989492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.1497989492
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.2943435632
Short name T1196
Test name
Test status
Simulation time 15315916 ps
CPU time 0.57 seconds
Started Jun 11 12:24:53 PM PDT 24
Finished Jun 11 12:24:56 PM PDT 24
Peak memory 195068 kb
Host smart-4b1c0ce0-81a1-4501-8cce-6ae9a2094396
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943435632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.2943435632
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2132438794
Short name T1217
Test name
Test status
Simulation time 107214577 ps
CPU time 0.76 seconds
Started Jun 11 12:24:51 PM PDT 24
Finished Jun 11 12:24:54 PM PDT 24
Peak memory 197248 kb
Host smart-e5035610-10ff-4ca6-be89-89cbf87ef4c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132438794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.2132438794
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.1748201877
Short name T1160
Test name
Test status
Simulation time 78989509 ps
CPU time 1.23 seconds
Started Jun 11 12:24:51 PM PDT 24
Finished Jun 11 12:24:55 PM PDT 24
Peak memory 200600 kb
Host smart-5be4aab5-76b7-49f5-9b6b-2a3260b566de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748201877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.1748201877
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.4044033021
Short name T1211
Test name
Test status
Simulation time 166393888 ps
CPU time 1.28 seconds
Started Jun 11 12:24:54 PM PDT 24
Finished Jun 11 12:24:58 PM PDT 24
Peak memory 199932 kb
Host smart-2261a036-1517-4bcd-b7e2-657c9ed36f20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044033021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.4044033021
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1957736697
Short name T1186
Test name
Test status
Simulation time 29275742 ps
CPU time 0.62 seconds
Started Jun 11 12:24:57 PM PDT 24
Finished Jun 11 12:25:00 PM PDT 24
Peak memory 197820 kb
Host smart-2487b8e0-dad1-4f7c-a018-48c41f22162c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957736697 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.1957736697
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.3222685277
Short name T1202
Test name
Test status
Simulation time 13560453 ps
CPU time 0.58 seconds
Started Jun 11 12:24:55 PM PDT 24
Finished Jun 11 12:24:59 PM PDT 24
Peak memory 196032 kb
Host smart-83a8122b-607c-4e4b-a700-5900bcbf1620
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222685277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.3222685277
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.586518995
Short name T1226
Test name
Test status
Simulation time 52176900 ps
CPU time 0.55 seconds
Started Jun 11 12:24:51 PM PDT 24
Finished Jun 11 12:24:54 PM PDT 24
Peak memory 194960 kb
Host smart-97e298f7-a40b-4362-be66-ff00e27a29ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586518995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.586518995
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1894016291
Short name T1201
Test name
Test status
Simulation time 26689744 ps
CPU time 0.72 seconds
Started Jun 11 12:24:55 PM PDT 24
Finished Jun 11 12:24:59 PM PDT 24
Peak memory 197784 kb
Host smart-668583f9-0845-403f-9751-57582f38fe72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894016291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.1894016291
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.1278483411
Short name T1112
Test name
Test status
Simulation time 505100397 ps
CPU time 1.83 seconds
Started Jun 11 12:24:56 PM PDT 24
Finished Jun 11 12:25:01 PM PDT 24
Peak memory 200768 kb
Host smart-d2844e01-808a-48b9-b3fd-4a19c3efba27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278483411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.1278483411
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2698671216
Short name T1155
Test name
Test status
Simulation time 95190175 ps
CPU time 1.33 seconds
Started Jun 11 12:24:54 PM PDT 24
Finished Jun 11 12:24:58 PM PDT 24
Peak memory 200264 kb
Host smart-00dc5b67-a434-4fff-a677-d6298bd37b0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698671216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.2698671216
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.4257506127
Short name T1114
Test name
Test status
Simulation time 19991726 ps
CPU time 0.64 seconds
Started Jun 11 12:25:03 PM PDT 24
Finished Jun 11 12:25:07 PM PDT 24
Peak memory 198032 kb
Host smart-6b48a5d2-8abe-476d-9ec6-505201f24389
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257506127 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.4257506127
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.3943585800
Short name T1174
Test name
Test status
Simulation time 24409159 ps
CPU time 0.66 seconds
Started Jun 11 12:24:49 PM PDT 24
Finished Jun 11 12:24:52 PM PDT 24
Peak memory 195948 kb
Host smart-6c7a70a8-a570-4890-808e-bdd691682b4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943585800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.3943585800
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.155077024
Short name T1121
Test name
Test status
Simulation time 38083860 ps
CPU time 0.55 seconds
Started Jun 11 12:24:53 PM PDT 24
Finished Jun 11 12:24:55 PM PDT 24
Peak memory 194908 kb
Host smart-df06bab6-39f1-4112-9562-b35a20d55758
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155077024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.155077024
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1790970738
Short name T1234
Test name
Test status
Simulation time 18894066 ps
CPU time 0.6 seconds
Started Jun 11 12:25:02 PM PDT 24
Finished Jun 11 12:25:06 PM PDT 24
Peak memory 196156 kb
Host smart-dd0b1901-c325-4fc6-a684-b8a03de65b11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790970738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.1790970738
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.2272535795
Short name T1135
Test name
Test status
Simulation time 178463355 ps
CPU time 1.09 seconds
Started Jun 11 12:24:51 PM PDT 24
Finished Jun 11 12:24:54 PM PDT 24
Peak memory 200700 kb
Host smart-38c4d8a4-cf57-4460-bcc4-bf8274e1ee87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272535795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.2272535795
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3324805710
Short name T67
Test name
Test status
Simulation time 69101988 ps
CPU time 1.22 seconds
Started Jun 11 12:24:53 PM PDT 24
Finished Jun 11 12:24:57 PM PDT 24
Peak memory 200216 kb
Host smart-10891b42-3e7e-4005-a7ef-ba1e90802582
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324805710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.3324805710
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.531444095
Short name T364
Test name
Test status
Simulation time 39358137 ps
CPU time 0.57 seconds
Started Jun 11 12:29:01 PM PDT 24
Finished Jun 11 12:29:04 PM PDT 24
Peak memory 195732 kb
Host smart-3acf009f-32a2-4d56-8bce-354ed66d9ec2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531444095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.531444095
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.1454341644
Short name T838
Test name
Test status
Simulation time 71422082060 ps
CPU time 21.7 seconds
Started Jun 11 12:28:52 PM PDT 24
Finished Jun 11 12:29:16 PM PDT 24
Peak memory 200316 kb
Host smart-6a440562-0e84-4829-8a30-5d794097297c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454341644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.1454341644
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.2916548343
Short name T1061
Test name
Test status
Simulation time 14501590583 ps
CPU time 21.57 seconds
Started Jun 11 12:29:02 PM PDT 24
Finished Jun 11 12:29:26 PM PDT 24
Peak memory 200292 kb
Host smart-302d4e27-d94d-4204-a315-83631ec1ed8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916548343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.2916548343
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.3159841316
Short name T500
Test name
Test status
Simulation time 77027854181 ps
CPU time 37.35 seconds
Started Jun 11 12:29:00 PM PDT 24
Finished Jun 11 12:29:39 PM PDT 24
Peak memory 200304 kb
Host smart-75634cea-65d3-487f-a0bf-15600ec88fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159841316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.3159841316
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.3824378854
Short name T344
Test name
Test status
Simulation time 13008391916 ps
CPU time 4.78 seconds
Started Jun 11 12:29:09 PM PDT 24
Finished Jun 11 12:29:15 PM PDT 24
Peak memory 197376 kb
Host smart-9f85f36e-70bc-41d4-824d-ada030bba9e4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824378854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.3824378854
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.211314745
Short name T398
Test name
Test status
Simulation time 145899275086 ps
CPU time 1432.69 seconds
Started Jun 11 12:28:54 PM PDT 24
Finished Jun 11 12:52:49 PM PDT 24
Peak memory 200308 kb
Host smart-88b30fde-eca0-47a7-a8e4-7e544472dfd7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=211314745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.211314745
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.2736882043
Short name T562
Test name
Test status
Simulation time 6555628187 ps
CPU time 9.92 seconds
Started Jun 11 12:28:54 PM PDT 24
Finished Jun 11 12:29:06 PM PDT 24
Peak memory 199420 kb
Host smart-2730cf93-b9ff-4f5e-9c7d-8d0837efbbb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736882043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.2736882043
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_perf.2654107715
Short name T1012
Test name
Test status
Simulation time 10273704999 ps
CPU time 417.19 seconds
Started Jun 11 12:29:05 PM PDT 24
Finished Jun 11 12:36:04 PM PDT 24
Peak memory 200264 kb
Host smart-c1c86d8b-3626-47f6-a2a0-4164f3a8c8b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2654107715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.2654107715
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.1959760882
Short name T373
Test name
Test status
Simulation time 3983051493 ps
CPU time 11.86 seconds
Started Jun 11 12:29:42 PM PDT 24
Finished Jun 11 12:29:57 PM PDT 24
Peak memory 198416 kb
Host smart-72a4f2dd-a161-4d5c-8d3b-57ce760496da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1959760882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.1959760882
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.2188076871
Short name T484
Test name
Test status
Simulation time 20774324411 ps
CPU time 33.11 seconds
Started Jun 11 12:29:00 PM PDT 24
Finished Jun 11 12:29:34 PM PDT 24
Peak memory 200288 kb
Host smart-989b2f66-5b9c-41f4-b2f5-9bea5f56cd2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188076871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.2188076871
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.439935129
Short name T602
Test name
Test status
Simulation time 3137709596 ps
CPU time 5.24 seconds
Started Jun 11 12:28:49 PM PDT 24
Finished Jun 11 12:28:56 PM PDT 24
Peak memory 196192 kb
Host smart-dd78bef0-3b5b-4dae-be89-36a6ee749769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439935129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.439935129
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_sec_cm.1059516206
Short name T70
Test name
Test status
Simulation time 73779491 ps
CPU time 0.83 seconds
Started Jun 11 12:29:02 PM PDT 24
Finished Jun 11 12:29:05 PM PDT 24
Peak memory 218776 kb
Host smart-566e8f91-871c-4575-8861-fce9051b7456
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059516206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.1059516206
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/0.uart_smoke.729618707
Short name T1099
Test name
Test status
Simulation time 524619544 ps
CPU time 1.47 seconds
Started Jun 11 12:29:09 PM PDT 24
Finished Jun 11 12:29:12 PM PDT 24
Peak memory 200248 kb
Host smart-9843b9ab-37c1-4376-b3a2-da15529d145e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729618707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.729618707
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.2773939692
Short name T623
Test name
Test status
Simulation time 35257924615 ps
CPU time 418.86 seconds
Started Jun 11 12:28:48 PM PDT 24
Finished Jun 11 12:35:49 PM PDT 24
Peak memory 216696 kb
Host smart-fdbf49f8-0290-4e18-880d-e0dc2ae41c02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773939692 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.2773939692
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.1733592327
Short name T1072
Test name
Test status
Simulation time 7113164181 ps
CPU time 15.72 seconds
Started Jun 11 12:28:48 PM PDT 24
Finished Jun 11 12:29:06 PM PDT 24
Peak memory 200224 kb
Host smart-99b0c3ce-fda1-476d-b96a-9c1cb373ee1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733592327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.1733592327
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.637812977
Short name T944
Test name
Test status
Simulation time 37225767655 ps
CPU time 58.84 seconds
Started Jun 11 12:29:09 PM PDT 24
Finished Jun 11 12:30:15 PM PDT 24
Peak memory 200208 kb
Host smart-c54d1d4a-33a8-4ffa-a762-91be91686845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637812977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.637812977
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_fifo_full.2680667461
Short name T140
Test name
Test status
Simulation time 70705873603 ps
CPU time 31.15 seconds
Started Jun 11 12:29:01 PM PDT 24
Finished Jun 11 12:29:35 PM PDT 24
Peak memory 200296 kb
Host smart-f41fe127-1d50-422a-8453-4ae3a28d6611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680667461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.2680667461
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.2175105834
Short name T970
Test name
Test status
Simulation time 194510189184 ps
CPU time 30.9 seconds
Started Jun 11 12:28:54 PM PDT 24
Finished Jun 11 12:29:27 PM PDT 24
Peak memory 200316 kb
Host smart-40e28303-f297-4fdc-b9fb-777a5fe4c705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175105834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.2175105834
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.492561754
Short name T711
Test name
Test status
Simulation time 71013754662 ps
CPU time 33.53 seconds
Started Jun 11 12:28:50 PM PDT 24
Finished Jun 11 12:29:26 PM PDT 24
Peak memory 200316 kb
Host smart-8836768c-eb37-4dd2-89e8-fa6306e76d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492561754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.492561754
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.3585614493
Short name T1034
Test name
Test status
Simulation time 32546653276 ps
CPU time 17.64 seconds
Started Jun 11 12:28:47 PM PDT 24
Finished Jun 11 12:29:07 PM PDT 24
Peak memory 200180 kb
Host smart-d84689b4-2bca-4099-90a1-ccf5cb1d7db1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585614493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.3585614493
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_loopback.2912903313
Short name T341
Test name
Test status
Simulation time 2463657806 ps
CPU time 1.81 seconds
Started Jun 11 12:29:05 PM PDT 24
Finished Jun 11 12:29:09 PM PDT 24
Peak memory 197792 kb
Host smart-c5a98504-c044-48e7-ad99-e8be9fc88beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912903313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.2912903313
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_perf.3111787663
Short name T625
Test name
Test status
Simulation time 16068169282 ps
CPU time 828.9 seconds
Started Jun 11 12:28:54 PM PDT 24
Finished Jun 11 12:42:45 PM PDT 24
Peak memory 200192 kb
Host smart-3eaf21d9-897a-4f4a-8bd4-222f0da2fbc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3111787663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.3111787663
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.3803026759
Short name T1010
Test name
Test status
Simulation time 3104927988 ps
CPU time 6.9 seconds
Started Jun 11 12:29:21 PM PDT 24
Finished Jun 11 12:29:29 PM PDT 24
Peak memory 198128 kb
Host smart-4eb8a6ce-e47c-46d3-917f-a225dcd62942
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3803026759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.3803026759
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.2183600785
Short name T126
Test name
Test status
Simulation time 189353136754 ps
CPU time 140.15 seconds
Started Jun 11 12:28:54 PM PDT 24
Finished Jun 11 12:31:16 PM PDT 24
Peak memory 200372 kb
Host smart-e5e8246a-e7c2-43e4-93e9-bb201d2cabd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183600785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.2183600785
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.1111784712
Short name T19
Test name
Test status
Simulation time 795153720 ps
CPU time 2.02 seconds
Started Jun 11 12:28:46 PM PDT 24
Finished Jun 11 12:28:50 PM PDT 24
Peak memory 195728 kb
Host smart-726dfb90-a562-470f-8e9b-884747f0b221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111784712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.1111784712
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_smoke.1519761488
Short name T279
Test name
Test status
Simulation time 689206453 ps
CPU time 1.48 seconds
Started Jun 11 12:29:03 PM PDT 24
Finished Jun 11 12:29:07 PM PDT 24
Peak memory 198896 kb
Host smart-787cf2b0-8a05-40e7-ba3d-2e5e9839d657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519761488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.1519761488
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.773874840
Short name T10
Test name
Test status
Simulation time 6632444129 ps
CPU time 13.24 seconds
Started Jun 11 12:28:46 PM PDT 24
Finished Jun 11 12:29:01 PM PDT 24
Peak memory 200332 kb
Host smart-00867155-c365-4df5-a3e5-324d2cc5c434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773874840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.773874840
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.1695053408
Short name T986
Test name
Test status
Simulation time 37553710217 ps
CPU time 11.99 seconds
Started Jun 11 12:29:16 PM PDT 24
Finished Jun 11 12:29:29 PM PDT 24
Peak memory 200260 kb
Host smart-6c069520-436c-40a4-8d0f-75408e4fe463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695053408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.1695053408
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.3610627368
Short name T493
Test name
Test status
Simulation time 13816088 ps
CPU time 0.56 seconds
Started Jun 11 12:29:31 PM PDT 24
Finished Jun 11 12:29:33 PM PDT 24
Peak memory 194924 kb
Host smart-214a94bc-c54f-417a-b7cf-c42c3aee1a50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610627368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.3610627368
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.497552599
Short name T622
Test name
Test status
Simulation time 39447057610 ps
CPU time 27.51 seconds
Started Jun 11 12:29:37 PM PDT 24
Finished Jun 11 12:30:06 PM PDT 24
Peak memory 200192 kb
Host smart-0337c050-44e3-458f-b644-955c5fad374b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497552599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.497552599
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.2272172657
Short name T108
Test name
Test status
Simulation time 61288696418 ps
CPU time 94.78 seconds
Started Jun 11 12:29:14 PM PDT 24
Finished Jun 11 12:30:50 PM PDT 24
Peak memory 200236 kb
Host smart-30936af5-8066-4e06-a19a-fa3435e0ea74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272172657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.2272172657
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.2484726355
Short name T95
Test name
Test status
Simulation time 19066822772 ps
CPU time 20.06 seconds
Started Jun 11 12:29:30 PM PDT 24
Finished Jun 11 12:29:52 PM PDT 24
Peak memory 200284 kb
Host smart-94ea5f06-8d27-4666-9f73-737724f88e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484726355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.2484726355
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.2353229718
Short name T1092
Test name
Test status
Simulation time 20055781195 ps
CPU time 35.65 seconds
Started Jun 11 12:29:15 PM PDT 24
Finished Jun 11 12:29:52 PM PDT 24
Peak memory 200216 kb
Host smart-a9521b7c-cc12-4def-b6dc-b23c3c1a148d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353229718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.2353229718
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.3175635680
Short name T376
Test name
Test status
Simulation time 102275934481 ps
CPU time 866.29 seconds
Started Jun 11 12:29:24 PM PDT 24
Finished Jun 11 12:43:52 PM PDT 24
Peak memory 200252 kb
Host smart-4c777651-bc52-42a0-a0de-8b7dc14d759b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3175635680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.3175635680
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.2449795033
Short name T90
Test name
Test status
Simulation time 9633052527 ps
CPU time 22.77 seconds
Started Jun 11 12:29:13 PM PDT 24
Finished Jun 11 12:29:37 PM PDT 24
Peak memory 199836 kb
Host smart-ac31877b-ec6d-4db8-a24b-b27788d120dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449795033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.2449795033
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_perf.1077890207
Short name T255
Test name
Test status
Simulation time 12130878701 ps
CPU time 606.44 seconds
Started Jun 11 12:29:20 PM PDT 24
Finished Jun 11 12:39:28 PM PDT 24
Peak memory 200184 kb
Host smart-f792a915-4da8-4724-b7da-5f5ab5085ab4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1077890207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.1077890207
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.872288030
Short name T683
Test name
Test status
Simulation time 6792405683 ps
CPU time 16.89 seconds
Started Jun 11 12:29:19 PM PDT 24
Finished Jun 11 12:29:37 PM PDT 24
Peak memory 199100 kb
Host smart-770b841f-7b91-4722-b71a-386d11ab34b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=872288030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.872288030
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.1231278830
Short name T916
Test name
Test status
Simulation time 41877132326 ps
CPU time 19.09 seconds
Started Jun 11 12:29:23 PM PDT 24
Finished Jun 11 12:29:43 PM PDT 24
Peak memory 196156 kb
Host smart-e29547a2-e8f6-4ee7-ac08-c560f5c6d540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231278830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.1231278830
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.3900815662
Short name T453
Test name
Test status
Simulation time 6241014865 ps
CPU time 12.9 seconds
Started Jun 11 12:29:15 PM PDT 24
Finished Jun 11 12:29:29 PM PDT 24
Peak memory 200044 kb
Host smart-e6391f84-e908-4399-9241-b30b7c8b9c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900815662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.3900815662
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.863418070
Short name T990
Test name
Test status
Simulation time 97510938482 ps
CPU time 46.51 seconds
Started Jun 11 12:29:15 PM PDT 24
Finished Jun 11 12:30:03 PM PDT 24
Peak memory 200168 kb
Host smart-1f2868bc-3e2f-4143-9700-23ae700fdb16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863418070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.863418070
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.1715680223
Short name T307
Test name
Test status
Simulation time 1557674726 ps
CPU time 2.66 seconds
Started Jun 11 12:29:18 PM PDT 24
Finished Jun 11 12:29:21 PM PDT 24
Peak memory 198584 kb
Host smart-3454c2d9-7975-4eba-a2a7-1c81ccb8f44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715680223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.1715680223
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.1313843608
Short name T879
Test name
Test status
Simulation time 118156298076 ps
CPU time 56.98 seconds
Started Jun 11 12:29:42 PM PDT 24
Finished Jun 11 12:30:42 PM PDT 24
Peak memory 200296 kb
Host smart-7b8dad26-0938-4076-97a2-70e290572258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313843608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.1313843608
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.474080301
Short name T192
Test name
Test status
Simulation time 160298994635 ps
CPU time 70.8 seconds
Started Jun 11 12:31:38 PM PDT 24
Finished Jun 11 12:32:50 PM PDT 24
Peak memory 200264 kb
Host smart-906a9288-4274-42bf-9896-0859bd71e68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474080301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.474080301
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.1769942531
Short name T135
Test name
Test status
Simulation time 231156387081 ps
CPU time 24.76 seconds
Started Jun 11 12:31:41 PM PDT 24
Finished Jun 11 12:32:06 PM PDT 24
Peak memory 200332 kb
Host smart-cfecbf3e-19d1-41fd-9186-457237203309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769942531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.1769942531
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.2849612876
Short name T674
Test name
Test status
Simulation time 18286827634 ps
CPU time 15.5 seconds
Started Jun 11 12:31:38 PM PDT 24
Finished Jun 11 12:31:54 PM PDT 24
Peak memory 200284 kb
Host smart-fe90eff9-d126-49f9-870d-9d3a57595109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849612876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.2849612876
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.4009622765
Short name T676
Test name
Test status
Simulation time 73652998402 ps
CPU time 31.7 seconds
Started Jun 11 12:31:44 PM PDT 24
Finished Jun 11 12:32:17 PM PDT 24
Peak memory 200132 kb
Host smart-14d5dae5-0a88-41ac-b16c-a032b7e5d3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009622765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.4009622765
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.1744666178
Short name T661
Test name
Test status
Simulation time 98561590743 ps
CPU time 35.63 seconds
Started Jun 11 12:31:39 PM PDT 24
Finished Jun 11 12:32:16 PM PDT 24
Peak memory 200048 kb
Host smart-808cafc6-98d3-4a6b-b5b9-7da77263b919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744666178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.1744666178
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.539603901
Short name T172
Test name
Test status
Simulation time 167130776659 ps
CPU time 79.52 seconds
Started Jun 11 12:31:38 PM PDT 24
Finished Jun 11 12:32:59 PM PDT 24
Peak memory 200248 kb
Host smart-f57e4115-f6a4-461f-a2f7-9e73bac72a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539603901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.539603901
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.1335385257
Short name T589
Test name
Test status
Simulation time 180288285384 ps
CPU time 339.88 seconds
Started Jun 11 12:31:38 PM PDT 24
Finished Jun 11 12:37:20 PM PDT 24
Peak memory 200116 kb
Host smart-34a80506-6a31-4edc-a63c-1f455e32e753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335385257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.1335385257
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.4218926938
Short name T486
Test name
Test status
Simulation time 13236462 ps
CPU time 0.6 seconds
Started Jun 11 12:29:36 PM PDT 24
Finished Jun 11 12:29:38 PM PDT 24
Peak memory 195664 kb
Host smart-734f1392-113f-43dc-9f26-b5315cfcd0ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218926938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.4218926938
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.2158735547
Short name T830
Test name
Test status
Simulation time 179636530494 ps
CPU time 540.65 seconds
Started Jun 11 12:29:28 PM PDT 24
Finished Jun 11 12:38:31 PM PDT 24
Peak memory 200260 kb
Host smart-eee6ab56-ed82-4514-a3c3-01d5ca43f39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158735547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.2158735547
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.2782014096
Short name T800
Test name
Test status
Simulation time 21335153659 ps
CPU time 39.38 seconds
Started Jun 11 12:29:17 PM PDT 24
Finished Jun 11 12:29:57 PM PDT 24
Peak memory 200332 kb
Host smart-9af089b5-6a26-4c6f-b29b-4ac85b2c8cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782014096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.2782014096
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.3960906547
Short name T672
Test name
Test status
Simulation time 8042410025 ps
CPU time 22.48 seconds
Started Jun 11 12:29:15 PM PDT 24
Finished Jun 11 12:29:39 PM PDT 24
Peak memory 200368 kb
Host smart-537fc93b-100d-423e-aff2-cd6cbc3cd563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960906547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.3960906547
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.2824596654
Short name T924
Test name
Test status
Simulation time 13317713384 ps
CPU time 3.71 seconds
Started Jun 11 12:29:40 PM PDT 24
Finished Jun 11 12:29:47 PM PDT 24
Peak memory 200552 kb
Host smart-298b8bac-1d4a-4f21-a193-afc705cb9d9a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824596654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.2824596654
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.3933611154
Short name T759
Test name
Test status
Simulation time 195328219536 ps
CPU time 273.64 seconds
Started Jun 11 12:29:19 PM PDT 24
Finished Jun 11 12:33:54 PM PDT 24
Peak memory 200360 kb
Host smart-a5a4400a-bc72-4780-93b6-5e9050452aef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3933611154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.3933611154
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.2291546892
Short name T747
Test name
Test status
Simulation time 2691306762 ps
CPU time 2.02 seconds
Started Jun 11 12:29:38 PM PDT 24
Finished Jun 11 12:29:42 PM PDT 24
Peak memory 199364 kb
Host smart-4a5a2636-bf42-4d9d-af8e-268257775f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291546892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.2291546892
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.4270276019
Short name T78
Test name
Test status
Simulation time 51417073388 ps
CPU time 79.21 seconds
Started Jun 11 12:29:41 PM PDT 24
Finished Jun 11 12:31:04 PM PDT 24
Peak memory 200252 kb
Host smart-cbdaede5-791e-4dd0-b86a-d08a2b1b154a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270276019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.4270276019
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.786601604
Short name T463
Test name
Test status
Simulation time 8547348952 ps
CPU time 220.96 seconds
Started Jun 11 12:29:12 PM PDT 24
Finished Jun 11 12:32:54 PM PDT 24
Peak memory 200208 kb
Host smart-c36accf1-495f-4225-a983-e5945c47890d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=786601604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.786601604
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.815047557
Short name T634
Test name
Test status
Simulation time 5705887340 ps
CPU time 52.49 seconds
Started Jun 11 12:29:33 PM PDT 24
Finished Jun 11 12:30:27 PM PDT 24
Peak memory 199440 kb
Host smart-e2d6ac5d-4a04-465d-a3b5-d8dc34074368
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=815047557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.815047557
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.2320317336
Short name T777
Test name
Test status
Simulation time 84931062623 ps
CPU time 41.54 seconds
Started Jun 11 12:29:24 PM PDT 24
Finished Jun 11 12:30:07 PM PDT 24
Peak memory 199500 kb
Host smart-83558bd1-98f5-4ad9-ba68-bc9b80b0b742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320317336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.2320317336
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.220495735
Short name T1059
Test name
Test status
Simulation time 25980371330 ps
CPU time 11.28 seconds
Started Jun 11 12:29:42 PM PDT 24
Finished Jun 11 12:29:56 PM PDT 24
Peak memory 196460 kb
Host smart-1831b088-8ae5-4412-b329-d2bc11a36087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220495735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.220495735
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.3085139298
Short name T524
Test name
Test status
Simulation time 515340033 ps
CPU time 1.59 seconds
Started Jun 11 12:29:12 PM PDT 24
Finished Jun 11 12:29:15 PM PDT 24
Peak memory 200056 kb
Host smart-ea906e70-783f-4ca8-9e7c-b64f9a3121a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085139298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.3085139298
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.1979626449
Short name T958
Test name
Test status
Simulation time 272692513041 ps
CPU time 999.7 seconds
Started Jun 11 12:29:39 PM PDT 24
Finished Jun 11 12:46:22 PM PDT 24
Peak memory 200348 kb
Host smart-933dd877-54f3-42ec-a0d7-71289861a5ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979626449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.1979626449
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.1833665297
Short name T718
Test name
Test status
Simulation time 91386275110 ps
CPU time 433.97 seconds
Started Jun 11 12:29:25 PM PDT 24
Finished Jun 11 12:36:41 PM PDT 24
Peak memory 216672 kb
Host smart-b0407f87-2f0b-4ba6-adcd-9b21cbfef97d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833665297 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.1833665297
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.732891623
Short name T726
Test name
Test status
Simulation time 2014750269 ps
CPU time 2.07 seconds
Started Jun 11 12:29:24 PM PDT 24
Finished Jun 11 12:29:27 PM PDT 24
Peak memory 198972 kb
Host smart-1819aec4-a26c-492d-af93-0741cea41477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732891623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.732891623
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.4057636690
Short name T1021
Test name
Test status
Simulation time 94291888969 ps
CPU time 157.71 seconds
Started Jun 11 12:29:24 PM PDT 24
Finished Jun 11 12:32:03 PM PDT 24
Peak memory 200348 kb
Host smart-cf57ca80-93d4-449d-bf91-4650b02a18e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057636690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.4057636690
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.1036510847
Short name T739
Test name
Test status
Simulation time 98650034074 ps
CPU time 166.81 seconds
Started Jun 11 12:31:44 PM PDT 24
Finished Jun 11 12:34:32 PM PDT 24
Peak memory 200332 kb
Host smart-79919fdb-5009-451e-a0ad-7b236e60eb88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036510847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1036510847
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.1434909222
Short name T523
Test name
Test status
Simulation time 124464879501 ps
CPU time 218.36 seconds
Started Jun 11 12:31:55 PM PDT 24
Finished Jun 11 12:35:34 PM PDT 24
Peak memory 200280 kb
Host smart-b42aeb0c-280b-4303-960d-c57bb440192d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434909222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.1434909222
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.3681894087
Short name T865
Test name
Test status
Simulation time 144670353779 ps
CPU time 120.48 seconds
Started Jun 11 12:31:39 PM PDT 24
Finished Jun 11 12:33:41 PM PDT 24
Peak memory 200520 kb
Host smart-6bada3ba-9c7a-49b7-b79b-3b644bef7fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681894087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.3681894087
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.3718030276
Short name T682
Test name
Test status
Simulation time 22895060639 ps
CPU time 14.55 seconds
Started Jun 11 12:31:37 PM PDT 24
Finished Jun 11 12:31:53 PM PDT 24
Peak memory 200240 kb
Host smart-fc240e2f-8e15-4158-b6d7-5ee0252b0223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718030276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.3718030276
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.3257700214
Short name T215
Test name
Test status
Simulation time 48678988026 ps
CPU time 14.36 seconds
Started Jun 11 12:31:54 PM PDT 24
Finished Jun 11 12:32:10 PM PDT 24
Peak memory 200344 kb
Host smart-64f32e07-6bc0-42c6-b364-54e5fde0a82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257700214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.3257700214
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.592042671
Short name T241
Test name
Test status
Simulation time 14581693244 ps
CPU time 22.2 seconds
Started Jun 11 12:31:42 PM PDT 24
Finished Jun 11 12:32:05 PM PDT 24
Peak memory 200252 kb
Host smart-03d38290-aaea-4b99-b16a-008ea7c9e681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592042671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.592042671
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.280321546
Short name T527
Test name
Test status
Simulation time 263555493937 ps
CPU time 27.09 seconds
Started Jun 11 12:31:55 PM PDT 24
Finished Jun 11 12:32:23 PM PDT 24
Peak memory 200284 kb
Host smart-6605e46b-c92b-4376-a212-d719e73572eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280321546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.280321546
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.331790147
Short name T645
Test name
Test status
Simulation time 104165200877 ps
CPU time 218.64 seconds
Started Jun 11 12:31:39 PM PDT 24
Finished Jun 11 12:35:19 PM PDT 24
Peak memory 200344 kb
Host smart-c177781a-7698-4f15-b00b-6f9143c60f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331790147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.331790147
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.1024602375
Short name T768
Test name
Test status
Simulation time 13318453 ps
CPU time 0.53 seconds
Started Jun 11 12:29:47 PM PDT 24
Finished Jun 11 12:29:49 PM PDT 24
Peak memory 195152 kb
Host smart-58f84754-a8aa-4b38-b56b-5648ac4d0489
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024602375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.1024602375
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.102590217
Short name T604
Test name
Test status
Simulation time 41638048510 ps
CPU time 36.48 seconds
Started Jun 11 12:29:38 PM PDT 24
Finished Jun 11 12:30:17 PM PDT 24
Peak memory 200156 kb
Host smart-51c1417f-2c8d-4696-a2a7-801689ddeaf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102590217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.102590217
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.2821335720
Short name T411
Test name
Test status
Simulation time 40507221861 ps
CPU time 30.64 seconds
Started Jun 11 12:29:15 PM PDT 24
Finished Jun 11 12:29:48 PM PDT 24
Peak memory 200276 kb
Host smart-872f4d41-dc2c-421a-a445-b404e7490b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821335720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.2821335720
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.501578982
Short name T925
Test name
Test status
Simulation time 14859114019 ps
CPU time 14.47 seconds
Started Jun 11 12:29:20 PM PDT 24
Finished Jun 11 12:29:35 PM PDT 24
Peak memory 200176 kb
Host smart-f503c3b2-9b0a-4970-9eb0-9fa6340cf5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501578982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.501578982
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.3392007878
Short name T619
Test name
Test status
Simulation time 26759941577 ps
CPU time 11.26 seconds
Started Jun 11 12:29:41 PM PDT 24
Finished Jun 11 12:29:56 PM PDT 24
Peak memory 197456 kb
Host smart-42381d8c-a420-4b92-9a5f-14496ba6b0fa
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392007878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.3392007878
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.1298126320
Short name T907
Test name
Test status
Simulation time 101336939874 ps
CPU time 303.68 seconds
Started Jun 11 12:29:24 PM PDT 24
Finished Jun 11 12:34:29 PM PDT 24
Peak memory 200300 kb
Host smart-011e7c47-fe25-42ae-8968-78aa2ca3e265
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1298126320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.1298126320
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.3504518945
Short name T744
Test name
Test status
Simulation time 5194011943 ps
CPU time 12.59 seconds
Started Jun 11 12:29:23 PM PDT 24
Finished Jun 11 12:29:37 PM PDT 24
Peak memory 200024 kb
Host smart-8e732f21-4fe8-4189-9efc-157675dbc2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504518945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.3504518945
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.402567602
Short name T334
Test name
Test status
Simulation time 36193940088 ps
CPU time 12 seconds
Started Jun 11 12:29:25 PM PDT 24
Finished Jun 11 12:29:39 PM PDT 24
Peak memory 200044 kb
Host smart-25a43385-0441-4833-be70-87e977eb6914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402567602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.402567602
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.1980502222
Short name T537
Test name
Test status
Simulation time 11926220083 ps
CPU time 668.22 seconds
Started Jun 11 12:29:18 PM PDT 24
Finished Jun 11 12:40:27 PM PDT 24
Peak memory 200304 kb
Host smart-b1c13cdb-d785-4943-9a90-cfd47bd71841
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1980502222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.1980502222
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.112242579
Short name T911
Test name
Test status
Simulation time 6733108725 ps
CPU time 50.44 seconds
Started Jun 11 12:29:32 PM PDT 24
Finished Jun 11 12:30:24 PM PDT 24
Peak memory 199448 kb
Host smart-bd04b455-a574-445f-b891-bae525fb0274
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=112242579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.112242579
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.546604164
Short name T549
Test name
Test status
Simulation time 61008366005 ps
CPU time 25.66 seconds
Started Jun 11 12:29:10 PM PDT 24
Finished Jun 11 12:29:37 PM PDT 24
Peak memory 199972 kb
Host smart-3a1fe142-7ea5-4c66-901b-b642643acdda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546604164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.546604164
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.3110231360
Short name T984
Test name
Test status
Simulation time 1990690745 ps
CPU time 3.48 seconds
Started Jun 11 12:29:22 PM PDT 24
Finished Jun 11 12:29:27 PM PDT 24
Peak memory 195880 kb
Host smart-b3302c24-bd09-40c7-bafb-ba21bcf3efc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110231360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.3110231360
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.474890318
Short name T617
Test name
Test status
Simulation time 5871570233 ps
CPU time 12.08 seconds
Started Jun 11 12:29:33 PM PDT 24
Finished Jun 11 12:29:46 PM PDT 24
Peak memory 200060 kb
Host smart-ec66ded1-e558-4255-9a41-99b902a650f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474890318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.474890318
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.3812496777
Short name T15
Test name
Test status
Simulation time 17151995728 ps
CPU time 201.43 seconds
Started Jun 11 12:29:29 PM PDT 24
Finished Jun 11 12:32:52 PM PDT 24
Peak memory 200312 kb
Host smart-50b11aeb-f234-44a4-90eb-b49080a9100a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812496777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.3812496777
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.3245599533
Short name T416
Test name
Test status
Simulation time 8382094497 ps
CPU time 7.48 seconds
Started Jun 11 12:29:33 PM PDT 24
Finished Jun 11 12:29:42 PM PDT 24
Peak memory 199548 kb
Host smart-c5252faa-7e21-4181-8f1e-77b33ec811ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245599533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.3245599533
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.3624456899
Short name T751
Test name
Test status
Simulation time 74897416334 ps
CPU time 215.03 seconds
Started Jun 11 12:29:15 PM PDT 24
Finished Jun 11 12:32:52 PM PDT 24
Peak memory 200236 kb
Host smart-e3d80304-d92a-4637-add3-715f8db759e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624456899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.3624456899
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.2280639772
Short name T1062
Test name
Test status
Simulation time 28593921190 ps
CPU time 72.22 seconds
Started Jun 11 12:31:39 PM PDT 24
Finished Jun 11 12:32:53 PM PDT 24
Peak memory 200208 kb
Host smart-176ac4fc-163d-491f-a4bc-151d30fa3cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280639772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.2280639772
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.1784364845
Short name T591
Test name
Test status
Simulation time 105699722395 ps
CPU time 113.18 seconds
Started Jun 11 12:31:42 PM PDT 24
Finished Jun 11 12:33:36 PM PDT 24
Peak memory 200276 kb
Host smart-b2d71563-9c99-4843-9c22-e43d27f2527d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784364845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.1784364845
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.3395676117
Short name T807
Test name
Test status
Simulation time 8720399653 ps
CPU time 14.35 seconds
Started Jun 11 12:31:53 PM PDT 24
Finished Jun 11 12:32:09 PM PDT 24
Peak memory 200308 kb
Host smart-b8b3ae15-34e9-4eb7-801d-c066e6be45e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395676117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.3395676117
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.3171472074
Short name T123
Test name
Test status
Simulation time 8079290260 ps
CPU time 5.52 seconds
Started Jun 11 12:31:38 PM PDT 24
Finished Jun 11 12:31:45 PM PDT 24
Peak memory 200048 kb
Host smart-dd70f19c-2d83-49fe-a954-40e6d3f8a963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171472074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.3171472074
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.1191012186
Short name T853
Test name
Test status
Simulation time 21670371954 ps
CPU time 22.09 seconds
Started Jun 11 12:31:38 PM PDT 24
Finished Jun 11 12:32:01 PM PDT 24
Peak memory 200308 kb
Host smart-aab41fb2-a6a2-4a28-b147-1f4236ec45fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191012186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.1191012186
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.799327945
Short name T117
Test name
Test status
Simulation time 42042018180 ps
CPU time 37.44 seconds
Started Jun 11 12:31:43 PM PDT 24
Finished Jun 11 12:32:22 PM PDT 24
Peak memory 200364 kb
Host smart-a4bf8b56-58c8-44bf-a0e8-3b50a797ba12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799327945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.799327945
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.3237009837
Short name T1044
Test name
Test status
Simulation time 41629645072 ps
CPU time 11.83 seconds
Started Jun 11 12:31:44 PM PDT 24
Finished Jun 11 12:31:56 PM PDT 24
Peak memory 199984 kb
Host smart-33ef89ed-1507-49f2-906f-5b997437b629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237009837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.3237009837
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.3578575091
Short name T487
Test name
Test status
Simulation time 208628163239 ps
CPU time 24.45 seconds
Started Jun 11 12:31:39 PM PDT 24
Finished Jun 11 12:32:05 PM PDT 24
Peak memory 200184 kb
Host smart-73aa1c9e-2452-4344-9a11-182bd42da0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578575091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.3578575091
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.643448270
Short name T348
Test name
Test status
Simulation time 40391002 ps
CPU time 0.58 seconds
Started Jun 11 12:29:50 PM PDT 24
Finished Jun 11 12:29:53 PM PDT 24
Peak memory 194924 kb
Host smart-8f726898-12dd-4731-9649-70147cf03b4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643448270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.643448270
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.5200719
Short name T1084
Test name
Test status
Simulation time 53049428333 ps
CPU time 89.9 seconds
Started Jun 11 12:29:37 PM PDT 24
Finished Jun 11 12:31:09 PM PDT 24
Peak memory 200360 kb
Host smart-358c779b-a9ef-4578-b0e4-57e7e2802e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5200719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.5200719
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.3869937436
Short name T262
Test name
Test status
Simulation time 143814024830 ps
CPU time 61.71 seconds
Started Jun 11 12:29:32 PM PDT 24
Finished Jun 11 12:30:35 PM PDT 24
Peak memory 199676 kb
Host smart-60eddb04-f6d9-44c4-aa77-049f017dd6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869937436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.3869937436
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_intr.1332847189
Short name T2
Test name
Test status
Simulation time 48278295799 ps
CPU time 25.05 seconds
Started Jun 11 12:29:20 PM PDT 24
Finished Jun 11 12:29:46 PM PDT 24
Peak memory 200348 kb
Host smart-cdd18a20-8035-4f14-a058-0b4d74d0719c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332847189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.1332847189
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.2399327789
Short name T624
Test name
Test status
Simulation time 201276056160 ps
CPU time 158.98 seconds
Started Jun 11 12:29:25 PM PDT 24
Finished Jun 11 12:32:06 PM PDT 24
Peak memory 200380 kb
Host smart-e62be5a1-3be4-4e8d-9521-8f589228ac52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2399327789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.2399327789
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.643081547
Short name T12
Test name
Test status
Simulation time 6289751364 ps
CPU time 4.23 seconds
Started Jun 11 12:29:28 PM PDT 24
Finished Jun 11 12:29:34 PM PDT 24
Peak memory 198732 kb
Host smart-3ce330c2-fd24-47c6-b0c5-70c672d9b918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643081547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.643081547
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_perf.3027044133
Short name T823
Test name
Test status
Simulation time 17867363985 ps
CPU time 76.53 seconds
Started Jun 11 12:29:27 PM PDT 24
Finished Jun 11 12:30:46 PM PDT 24
Peak memory 200376 kb
Host smart-4f2c4725-0b3e-4859-bf4a-107ecf8ea2a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3027044133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.3027044133
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.2945929445
Short name T480
Test name
Test status
Simulation time 2103450704 ps
CPU time 12.92 seconds
Started Jun 11 12:29:16 PM PDT 24
Finished Jun 11 12:29:30 PM PDT 24
Peak memory 199616 kb
Host smart-1a20a6a0-9349-4fd9-b45e-eed26096508f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2945929445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.2945929445
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.1151789901
Short name T584
Test name
Test status
Simulation time 116704518336 ps
CPU time 275.9 seconds
Started Jun 11 12:29:16 PM PDT 24
Finished Jun 11 12:33:54 PM PDT 24
Peak memory 200292 kb
Host smart-04c57964-7533-4890-a58f-a19ba3b8d171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151789901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.1151789901
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.878554323
Short name T673
Test name
Test status
Simulation time 5212639729 ps
CPU time 2.82 seconds
Started Jun 11 12:29:17 PM PDT 24
Finished Jun 11 12:29:21 PM PDT 24
Peak memory 196448 kb
Host smart-a1f26a02-4617-4f8e-8c58-4f44583e3e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878554323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.878554323
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.1286554057
Short name T420
Test name
Test status
Simulation time 432704618 ps
CPU time 2.03 seconds
Started Jun 11 12:29:35 PM PDT 24
Finished Jun 11 12:29:38 PM PDT 24
Peak memory 200152 kb
Host smart-49149084-823c-4203-a22c-59e27bf63d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286554057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.1286554057
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.782900053
Short name T926
Test name
Test status
Simulation time 137707083071 ps
CPU time 223.56 seconds
Started Jun 11 12:29:26 PM PDT 24
Finished Jun 11 12:33:12 PM PDT 24
Peak memory 199892 kb
Host smart-c0b8e60b-8867-45c4-b1ad-723fe15be916
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782900053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.782900053
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.957778596
Short name T284
Test name
Test status
Simulation time 3950719454 ps
CPU time 1.99 seconds
Started Jun 11 12:29:14 PM PDT 24
Finished Jun 11 12:29:17 PM PDT 24
Peak memory 199192 kb
Host smart-81f30170-1c13-42b5-8d6c-83ce1039e07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957778596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.957778596
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.1230964339
Short name T318
Test name
Test status
Simulation time 68158558110 ps
CPU time 63.65 seconds
Started Jun 11 12:29:26 PM PDT 24
Finished Jun 11 12:30:32 PM PDT 24
Peak memory 200188 kb
Host smart-714d4a57-5544-4272-9c27-163578c06682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230964339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.1230964339
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.23891475
Short name T248
Test name
Test status
Simulation time 175504027748 ps
CPU time 254.1 seconds
Started Jun 11 12:31:49 PM PDT 24
Finished Jun 11 12:36:04 PM PDT 24
Peak memory 200368 kb
Host smart-bad13120-3276-41f1-bc4a-00bbe55912f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23891475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.23891475
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.3530529513
Short name T734
Test name
Test status
Simulation time 94838753438 ps
CPU time 38.3 seconds
Started Jun 11 12:31:40 PM PDT 24
Finished Jun 11 12:32:19 PM PDT 24
Peak memory 200312 kb
Host smart-ab2933af-cf92-41e9-8788-a8f458a68df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530529513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.3530529513
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.3354589508
Short name T335
Test name
Test status
Simulation time 82775112893 ps
CPU time 34.36 seconds
Started Jun 11 12:31:42 PM PDT 24
Finished Jun 11 12:32:17 PM PDT 24
Peak memory 200340 kb
Host smart-e8cfb2d2-47fb-4834-987c-2cbd6d49328f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354589508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.3354589508
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.4237512937
Short name T218
Test name
Test status
Simulation time 49610511619 ps
CPU time 21.33 seconds
Started Jun 11 12:31:41 PM PDT 24
Finished Jun 11 12:32:04 PM PDT 24
Peak memory 200296 kb
Host smart-0ba9a5ab-457a-4685-b2d9-74a2e943bd95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237512937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.4237512937
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.3139324916
Short name T1050
Test name
Test status
Simulation time 11444810684 ps
CPU time 18.45 seconds
Started Jun 11 12:31:53 PM PDT 24
Finished Jun 11 12:32:13 PM PDT 24
Peak memory 200276 kb
Host smart-a5f6b0ea-e318-4766-8750-33fe917b5619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139324916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.3139324916
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.2677181902
Short name T489
Test name
Test status
Simulation time 103426228887 ps
CPU time 17.28 seconds
Started Jun 11 12:31:43 PM PDT 24
Finished Jun 11 12:32:02 PM PDT 24
Peak memory 199920 kb
Host smart-25f818fa-9ca7-4dd6-9998-7273e0ac16e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677181902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.2677181902
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.4128715399
Short name T518
Test name
Test status
Simulation time 178007520982 ps
CPU time 28.59 seconds
Started Jun 11 12:31:53 PM PDT 24
Finished Jun 11 12:32:24 PM PDT 24
Peak memory 200340 kb
Host smart-02e99bf6-2d22-4791-92cc-6324b988f096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128715399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.4128715399
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.331109707
Short name T730
Test name
Test status
Simulation time 78734745787 ps
CPU time 38.66 seconds
Started Jun 11 12:31:54 PM PDT 24
Finished Jun 11 12:32:34 PM PDT 24
Peak memory 200368 kb
Host smart-947c21aa-0c5b-4074-ace2-3059c723d11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331109707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.331109707
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.9440129
Short name T308
Test name
Test status
Simulation time 16856787050 ps
CPU time 30.95 seconds
Started Jun 11 12:31:53 PM PDT 24
Finished Jun 11 12:32:26 PM PDT 24
Peak memory 200284 kb
Host smart-e023a286-98d4-4981-ac82-a5d58269967f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9440129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.9440129
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.763248037
Short name T804
Test name
Test status
Simulation time 104711451038 ps
CPU time 159.8 seconds
Started Jun 11 12:31:38 PM PDT 24
Finished Jun 11 12:34:19 PM PDT 24
Peak memory 200308 kb
Host smart-025d030d-063f-449e-ab06-84dbf9fa2a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763248037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.763248037
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.2468902452
Short name T407
Test name
Test status
Simulation time 35817671 ps
CPU time 0.55 seconds
Started Jun 11 12:29:40 PM PDT 24
Finished Jun 11 12:29:44 PM PDT 24
Peak memory 195076 kb
Host smart-17af823f-33c5-4ab0-8d7a-a6e6f6503e20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468902452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.2468902452
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.737755491
Short name T1003
Test name
Test status
Simulation time 35135832160 ps
CPU time 13.95 seconds
Started Jun 11 12:29:25 PM PDT 24
Finished Jun 11 12:29:40 PM PDT 24
Peak memory 200260 kb
Host smart-2ba483a1-9555-47a5-979a-de86c37e3ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737755491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.737755491
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.3036128243
Short name T250
Test name
Test status
Simulation time 31437818662 ps
CPU time 15.74 seconds
Started Jun 11 12:29:49 PM PDT 24
Finished Jun 11 12:30:07 PM PDT 24
Peak memory 200280 kb
Host smart-fd0893a1-7f87-4cd7-bb3b-528f5c5f8d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036128243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.3036128243
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.441038125
Short name T332
Test name
Test status
Simulation time 7186955693 ps
CPU time 11.14 seconds
Started Jun 11 12:29:46 PM PDT 24
Finished Jun 11 12:30:00 PM PDT 24
Peak memory 200312 kb
Host smart-d4687c25-57ec-48c2-a3a6-fc2a47fdff76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441038125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.441038125
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.2736531402
Short name T380
Test name
Test status
Simulation time 11171733808 ps
CPU time 13.12 seconds
Started Jun 11 12:29:26 PM PDT 24
Finished Jun 11 12:29:41 PM PDT 24
Peak memory 200156 kb
Host smart-7634a09e-335f-4d04-b4e2-ed537eead409
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736531402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.2736531402
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.3408261479
Short name T655
Test name
Test status
Simulation time 63242864723 ps
CPU time 305.91 seconds
Started Jun 11 12:29:36 PM PDT 24
Finished Jun 11 12:34:43 PM PDT 24
Peak memory 200604 kb
Host smart-d040d03a-f0c3-408e-a9c3-5bb7f5172d4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3408261479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.3408261479
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.3288596357
Short name T867
Test name
Test status
Simulation time 7801109984 ps
CPU time 8.62 seconds
Started Jun 11 12:29:35 PM PDT 24
Finished Jun 11 12:29:45 PM PDT 24
Peak memory 199748 kb
Host smart-90a57cc9-da33-42ed-939d-bb0fe7612bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288596357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.3288596357
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_perf.1160856239
Short name T626
Test name
Test status
Simulation time 12257415994 ps
CPU time 278.12 seconds
Started Jun 11 12:29:40 PM PDT 24
Finished Jun 11 12:34:22 PM PDT 24
Peak memory 200288 kb
Host smart-df64872e-f42c-476c-84b5-f17371c7afb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1160856239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.1160856239
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.2703551349
Short name T601
Test name
Test status
Simulation time 7034943207 ps
CPU time 11.64 seconds
Started Jun 11 12:29:26 PM PDT 24
Finished Jun 11 12:29:40 PM PDT 24
Peak memory 199528 kb
Host smart-7006472c-6438-4f34-9279-4c84cb79499f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2703551349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.2703551349
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.2090258923
Short name T137
Test name
Test status
Simulation time 95133271234 ps
CPU time 28.27 seconds
Started Jun 11 12:29:24 PM PDT 24
Finished Jun 11 12:29:54 PM PDT 24
Peak memory 200284 kb
Host smart-b82d86d9-0569-46ea-9400-9f452a4fad83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090258923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.2090258923
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.2566928344
Short name T278
Test name
Test status
Simulation time 556918285 ps
CPU time 1.47 seconds
Started Jun 11 12:29:26 PM PDT 24
Finished Jun 11 12:29:29 PM PDT 24
Peak memory 195928 kb
Host smart-cc74967c-592e-4ba5-b2da-cc3ba5124c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566928344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.2566928344
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.3207396918
Short name T627
Test name
Test status
Simulation time 516181008 ps
CPU time 1.57 seconds
Started Jun 11 12:29:27 PM PDT 24
Finished Jun 11 12:29:30 PM PDT 24
Peak memory 198488 kb
Host smart-79f9c738-2f48-443b-ae41-b126cb93b611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207396918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.3207396918
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.1944468431
Short name T854
Test name
Test status
Simulation time 263287659013 ps
CPU time 1207.03 seconds
Started Jun 11 12:29:42 PM PDT 24
Finished Jun 11 12:49:52 PM PDT 24
Peak memory 200308 kb
Host smart-df7894c8-8719-41bc-a54f-04dec0acc4f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944468431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.1944468431
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.716455513
Short name T874
Test name
Test status
Simulation time 438790136524 ps
CPU time 453.69 seconds
Started Jun 11 12:29:28 PM PDT 24
Finished Jun 11 12:37:04 PM PDT 24
Peak memory 216916 kb
Host smart-97e22223-2b50-4ed1-b12e-47b1e2ee0c6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716455513 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.716455513
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.217474147
Short name T781
Test name
Test status
Simulation time 517635182 ps
CPU time 1.74 seconds
Started Jun 11 12:29:28 PM PDT 24
Finished Jun 11 12:29:32 PM PDT 24
Peak memory 199004 kb
Host smart-88bbb344-8d9a-4d67-8164-6a833a8a797c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217474147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.217474147
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.1065742912
Short name T1029
Test name
Test status
Simulation time 39740353839 ps
CPU time 60.1 seconds
Started Jun 11 12:29:30 PM PDT 24
Finished Jun 11 12:30:32 PM PDT 24
Peak memory 200204 kb
Host smart-df20f2bf-89dd-41a7-8631-d6eb79e03436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065742912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.1065742912
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.2711142569
Short name T177
Test name
Test status
Simulation time 118067437371 ps
CPU time 136.52 seconds
Started Jun 11 12:31:42 PM PDT 24
Finished Jun 11 12:34:00 PM PDT 24
Peak memory 200304 kb
Host smart-5480bff0-54c2-49a8-9b38-afcba814d894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711142569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.2711142569
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.2788992999
Short name T295
Test name
Test status
Simulation time 78959726508 ps
CPU time 57.11 seconds
Started Jun 11 12:31:53 PM PDT 24
Finished Jun 11 12:32:52 PM PDT 24
Peak memory 200244 kb
Host smart-5d7dd75c-52e3-410b-a462-925dd781da78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788992999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.2788992999
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.2393211604
Short name T182
Test name
Test status
Simulation time 35257042946 ps
CPU time 64.24 seconds
Started Jun 11 12:31:52 PM PDT 24
Finished Jun 11 12:32:58 PM PDT 24
Peak memory 200116 kb
Host smart-7df9f000-0c54-4d29-a5ec-c81ce2a7b92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393211604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.2393211604
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.3794137812
Short name T820
Test name
Test status
Simulation time 97351447048 ps
CPU time 43.55 seconds
Started Jun 11 12:31:52 PM PDT 24
Finished Jun 11 12:32:37 PM PDT 24
Peak memory 200276 kb
Host smart-73724d50-0fb1-413d-be6d-f16db33dfe24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794137812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.3794137812
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.371907497
Short name T201
Test name
Test status
Simulation time 38625083405 ps
CPU time 29.92 seconds
Started Jun 11 12:31:52 PM PDT 24
Finished Jun 11 12:32:23 PM PDT 24
Peak memory 200296 kb
Host smart-738fb096-6210-43fe-be06-43e8774d3a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371907497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.371907497
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.1894733830
Short name T969
Test name
Test status
Simulation time 116681960286 ps
CPU time 24.8 seconds
Started Jun 11 12:31:54 PM PDT 24
Finished Jun 11 12:32:20 PM PDT 24
Peak memory 200276 kb
Host smart-c9032a96-4210-4cdd-a47f-885739e62a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894733830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.1894733830
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.1777567462
Short name T199
Test name
Test status
Simulation time 179469773868 ps
CPU time 65.49 seconds
Started Jun 11 12:31:50 PM PDT 24
Finished Jun 11 12:32:56 PM PDT 24
Peak memory 200344 kb
Host smart-b2a5c324-830d-4ed1-a0a3-716d3e455d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777567462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.1777567462
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.3714354026
Short name T446
Test name
Test status
Simulation time 155800189695 ps
CPU time 259.39 seconds
Started Jun 11 12:31:50 PM PDT 24
Finished Jun 11 12:36:10 PM PDT 24
Peak memory 200336 kb
Host smart-0ec897b8-b962-448b-ab6b-08748fc55cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714354026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.3714354026
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.3489276895
Short name T766
Test name
Test status
Simulation time 22624018 ps
CPU time 0.6 seconds
Started Jun 11 12:29:36 PM PDT 24
Finished Jun 11 12:29:37 PM PDT 24
Peak memory 195188 kb
Host smart-ace8b398-7771-4df8-be50-e433f01bd733
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489276895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.3489276895
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.921707575
Short name T259
Test name
Test status
Simulation time 138554694849 ps
CPU time 103.92 seconds
Started Jun 11 12:29:28 PM PDT 24
Finished Jun 11 12:31:14 PM PDT 24
Peak memory 200232 kb
Host smart-f5c17fb6-73eb-47be-8d21-80157aa24a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921707575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.921707575
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.2501516310
Short name T999
Test name
Test status
Simulation time 136908678951 ps
CPU time 151.47 seconds
Started Jun 11 12:29:25 PM PDT 24
Finished Jun 11 12:31:59 PM PDT 24
Peak memory 200288 kb
Host smart-a4e18ca6-6de7-4507-bf71-fedacd702df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501516310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.2501516310
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.1460417502
Short name T451
Test name
Test status
Simulation time 17920406419 ps
CPU time 32.89 seconds
Started Jun 11 12:29:40 PM PDT 24
Finished Jun 11 12:30:16 PM PDT 24
Peak memory 200268 kb
Host smart-27f8b0bf-e303-4ff7-b7c2-8f84df573000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460417502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.1460417502
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.749917487
Short name T1020
Test name
Test status
Simulation time 22229591802 ps
CPU time 10.88 seconds
Started Jun 11 12:29:46 PM PDT 24
Finished Jun 11 12:29:59 PM PDT 24
Peak memory 199344 kb
Host smart-3f0b8752-fa2e-4c21-a6e9-3a0df52acfb0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749917487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.749917487
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.1096566003
Short name T773
Test name
Test status
Simulation time 129040278860 ps
CPU time 563.19 seconds
Started Jun 11 12:29:24 PM PDT 24
Finished Jun 11 12:38:49 PM PDT 24
Peak memory 200276 kb
Host smart-7809f0ce-a2c1-44b8-a762-eb47d6185f59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1096566003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.1096566003
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.1424069649
Short name T1089
Test name
Test status
Simulation time 6807862187 ps
CPU time 14.03 seconds
Started Jun 11 12:29:24 PM PDT 24
Finished Jun 11 12:29:40 PM PDT 24
Peak memory 199924 kb
Host smart-9150bef0-2755-4024-93d5-5e23e050c5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424069649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.1424069649
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_perf.1154228914
Short name T283
Test name
Test status
Simulation time 12187912862 ps
CPU time 146.93 seconds
Started Jun 11 12:29:40 PM PDT 24
Finished Jun 11 12:32:10 PM PDT 24
Peak memory 200316 kb
Host smart-4d9e1615-92f4-4d5f-9166-dbdabf79823e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1154228914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.1154228914
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.4051950537
Short name T629
Test name
Test status
Simulation time 4596815672 ps
CPU time 8.18 seconds
Started Jun 11 12:29:38 PM PDT 24
Finished Jun 11 12:29:48 PM PDT 24
Peak memory 198516 kb
Host smart-22c4eafd-e797-41a5-9e8a-8fc4ef809623
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4051950537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.4051950537
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.213994788
Short name T526
Test name
Test status
Simulation time 114577902465 ps
CPU time 30.16 seconds
Started Jun 11 12:29:27 PM PDT 24
Finished Jun 11 12:30:00 PM PDT 24
Peak memory 200136 kb
Host smart-7dbee25f-f5c4-4470-ba0f-9fd322a1c0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213994788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.213994788
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.1884444337
Short name T395
Test name
Test status
Simulation time 1826705067 ps
CPU time 3.96 seconds
Started Jun 11 12:29:42 PM PDT 24
Finished Jun 11 12:29:49 PM PDT 24
Peak memory 195940 kb
Host smart-521cc71b-e7f7-4958-881b-701fdce22e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884444337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.1884444337
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.1704556889
Short name T434
Test name
Test status
Simulation time 543777130 ps
CPU time 1.79 seconds
Started Jun 11 12:29:28 PM PDT 24
Finished Jun 11 12:29:32 PM PDT 24
Peak memory 198948 kb
Host smart-cfa1d63e-b2a6-41cf-bedf-2eaa4b3d3d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704556889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.1704556889
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.1171488573
Short name T1000
Test name
Test status
Simulation time 285576661108 ps
CPU time 268.69 seconds
Started Jun 11 12:29:37 PM PDT 24
Finished Jun 11 12:34:08 PM PDT 24
Peak memory 200284 kb
Host smart-0725bde4-f767-4f75-ba1b-d8627a238744
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171488573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.1171488573
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.3412681061
Short name T310
Test name
Test status
Simulation time 1819999344 ps
CPU time 2.88 seconds
Started Jun 11 12:29:29 PM PDT 24
Finished Jun 11 12:29:34 PM PDT 24
Peak memory 199164 kb
Host smart-71f0a550-aaf9-47fb-9531-5bda32144a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412681061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.3412681061
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.2346711903
Short name T872
Test name
Test status
Simulation time 5151025523 ps
CPU time 8.53 seconds
Started Jun 11 12:29:46 PM PDT 24
Finished Jun 11 12:29:57 PM PDT 24
Peak memory 200052 kb
Host smart-e9fa8f3c-4860-49d7-9d82-61cd0fc63b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346711903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.2346711903
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.3799800850
Short name T912
Test name
Test status
Simulation time 118693076758 ps
CPU time 100.25 seconds
Started Jun 11 12:31:50 PM PDT 24
Finished Jun 11 12:33:32 PM PDT 24
Peak memory 200356 kb
Host smart-28e69ec4-5e82-4012-9646-7dd00fe3765b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799800850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.3799800850
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.1585313508
Short name T329
Test name
Test status
Simulation time 91064012349 ps
CPU time 19.62 seconds
Started Jun 11 12:31:51 PM PDT 24
Finished Jun 11 12:32:12 PM PDT 24
Peak memory 200272 kb
Host smart-22f00e77-d5d3-487b-a259-cb8d5aa72225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585313508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.1585313508
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.776744345
Short name T600
Test name
Test status
Simulation time 99587645316 ps
CPU time 179.76 seconds
Started Jun 11 12:31:51 PM PDT 24
Finished Jun 11 12:34:52 PM PDT 24
Peak memory 200240 kb
Host smart-6a155080-3bfd-4d1c-a209-7e95cd5904bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776744345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.776744345
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.2189929886
Short name T551
Test name
Test status
Simulation time 157634656444 ps
CPU time 84.92 seconds
Started Jun 11 12:31:51 PM PDT 24
Finished Jun 11 12:33:18 PM PDT 24
Peak memory 200244 kb
Host smart-da9a18d2-06d4-4841-a2e5-8eab3e95f6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189929886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.2189929886
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.4209765764
Short name T1023
Test name
Test status
Simulation time 104192137808 ps
CPU time 216.06 seconds
Started Jun 11 12:31:50 PM PDT 24
Finished Jun 11 12:35:27 PM PDT 24
Peak memory 200308 kb
Host smart-e25e1185-6926-408a-aa14-86568840bae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209765764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.4209765764
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.3312186822
Short name T330
Test name
Test status
Simulation time 65078238426 ps
CPU time 63.05 seconds
Started Jun 11 12:31:50 PM PDT 24
Finished Jun 11 12:32:54 PM PDT 24
Peak memory 200264 kb
Host smart-5d1143f7-4c9d-430d-8b1c-240c5c93c253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312186822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.3312186822
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.1200919515
Short name T864
Test name
Test status
Simulation time 39665852242 ps
CPU time 64.48 seconds
Started Jun 11 12:31:51 PM PDT 24
Finished Jun 11 12:32:57 PM PDT 24
Peak memory 200272 kb
Host smart-ae6264fc-095a-4919-a7b6-6287255f919b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200919515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.1200919515
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.1316840232
Short name T219
Test name
Test status
Simulation time 153241526447 ps
CPU time 65.55 seconds
Started Jun 11 12:31:52 PM PDT 24
Finished Jun 11 12:32:59 PM PDT 24
Peak memory 200336 kb
Host smart-ade34fab-b6df-4040-9158-dd34e1ecfcd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316840232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.1316840232
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.2377671249
Short name T878
Test name
Test status
Simulation time 13729861 ps
CPU time 0.55 seconds
Started Jun 11 12:29:41 PM PDT 24
Finished Jun 11 12:29:45 PM PDT 24
Peak memory 194976 kb
Host smart-174ee4eb-0f67-442c-a9ca-a450f80abff5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377671249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.2377671249
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.3280206563
Short name T1088
Test name
Test status
Simulation time 121374893555 ps
CPU time 336.86 seconds
Started Jun 11 12:29:27 PM PDT 24
Finished Jun 11 12:35:07 PM PDT 24
Peak memory 200252 kb
Host smart-d1c871c8-a2f0-4768-86a2-89d8e9939323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280206563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.3280206563
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.3110523689
Short name T147
Test name
Test status
Simulation time 32777434152 ps
CPU time 51.92 seconds
Started Jun 11 12:29:49 PM PDT 24
Finished Jun 11 12:30:44 PM PDT 24
Peak memory 200284 kb
Host smart-469eaaa8-f00d-459a-943b-f9edcd1372a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110523689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.3110523689
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_loopback.1579171876
Short name T810
Test name
Test status
Simulation time 1626406930 ps
CPU time 1.39 seconds
Started Jun 11 12:29:34 PM PDT 24
Finished Jun 11 12:29:37 PM PDT 24
Peak memory 196320 kb
Host smart-eb566d07-929d-4f16-947e-deb7c13add90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579171876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.1579171876
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_perf.3195654242
Short name T396
Test name
Test status
Simulation time 11520224190 ps
CPU time 232.59 seconds
Started Jun 11 12:29:27 PM PDT 24
Finished Jun 11 12:33:21 PM PDT 24
Peak memory 200596 kb
Host smart-04e7f18c-e6fc-41b8-a7f9-8684c19856b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3195654242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.3195654242
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.256769147
Short name T946
Test name
Test status
Simulation time 1801936055 ps
CPU time 6.58 seconds
Started Jun 11 12:29:45 PM PDT 24
Finished Jun 11 12:29:54 PM PDT 24
Peak memory 199028 kb
Host smart-28361da6-3cce-474d-8378-b9202a154541
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=256769147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.256769147
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.67460385
Short name T883
Test name
Test status
Simulation time 63643677149 ps
CPU time 44.75 seconds
Started Jun 11 12:29:28 PM PDT 24
Finished Jun 11 12:30:15 PM PDT 24
Peak memory 200284 kb
Host smart-66514435-14bd-45ed-8cef-aebefbeb317f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67460385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.67460385
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.2958116418
Short name T277
Test name
Test status
Simulation time 4310465359 ps
CPU time 2.35 seconds
Started Jun 11 12:29:27 PM PDT 24
Finished Jun 11 12:29:32 PM PDT 24
Peak memory 197156 kb
Host smart-65ccb682-34b4-4880-8a8f-e7aca4cf955e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958116418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.2958116418
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.1807910020
Short name T429
Test name
Test status
Simulation time 5883768141 ps
CPU time 10.59 seconds
Started Jun 11 12:29:29 PM PDT 24
Finished Jun 11 12:29:42 PM PDT 24
Peak memory 200076 kb
Host smart-c213aecf-fc07-4f37-a78c-dc653a947c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807910020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.1807910020
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.2950670469
Short name T508
Test name
Test status
Simulation time 82658920676 ps
CPU time 45.1 seconds
Started Jun 11 12:29:39 PM PDT 24
Finished Jun 11 12:30:28 PM PDT 24
Peak memory 200212 kb
Host smart-9cc998a1-fd56-45d7-b4cf-fa8575dfd40a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950670469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.2950670469
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.3882770484
Short name T836
Test name
Test status
Simulation time 42221882928 ps
CPU time 304.31 seconds
Started Jun 11 12:29:27 PM PDT 24
Finished Jun 11 12:34:33 PM PDT 24
Peak memory 216764 kb
Host smart-bc874592-1322-4d79-94eb-4ddb989cb9fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882770484 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.3882770484
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.3490354489
Short name T517
Test name
Test status
Simulation time 6576492781 ps
CPU time 14.95 seconds
Started Jun 11 12:29:42 PM PDT 24
Finished Jun 11 12:30:00 PM PDT 24
Peak memory 199600 kb
Host smart-0f404893-5405-4b75-8582-c83ad9c44454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490354489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.3490354489
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.2076749033
Short name T929
Test name
Test status
Simulation time 62111542617 ps
CPU time 172.9 seconds
Started Jun 11 12:29:29 PM PDT 24
Finished Jun 11 12:32:24 PM PDT 24
Peak memory 200276 kb
Host smart-9d256b43-0489-4018-bb5f-b818660b7b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076749033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.2076749033
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.707220878
Short name T509
Test name
Test status
Simulation time 86246971834 ps
CPU time 37.78 seconds
Started Jun 11 12:31:53 PM PDT 24
Finished Jun 11 12:32:32 PM PDT 24
Peak memory 200196 kb
Host smart-e4fde5b7-4e5b-4593-84b5-620a9e18a9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707220878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.707220878
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.342892253
Short name T991
Test name
Test status
Simulation time 24341226589 ps
CPU time 26.96 seconds
Started Jun 11 12:31:50 PM PDT 24
Finished Jun 11 12:32:18 PM PDT 24
Peak memory 200264 kb
Host smart-4c9fdb87-98ae-45c5-869b-38d157361eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342892253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.342892253
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.2225290190
Short name T632
Test name
Test status
Simulation time 72454505431 ps
CPU time 94.4 seconds
Started Jun 11 12:31:50 PM PDT 24
Finished Jun 11 12:33:26 PM PDT 24
Peak memory 200296 kb
Host smart-4e4ebc96-632e-436d-9c4e-d18f409767c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225290190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.2225290190
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.837453698
Short name T1008
Test name
Test status
Simulation time 15726306820 ps
CPU time 27.8 seconds
Started Jun 11 12:31:52 PM PDT 24
Finished Jun 11 12:32:22 PM PDT 24
Peak memory 200272 kb
Host smart-3158033a-1b8a-4358-865a-e0de609bf262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837453698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.837453698
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.640005926
Short name T267
Test name
Test status
Simulation time 25738421781 ps
CPU time 12.97 seconds
Started Jun 11 12:31:50 PM PDT 24
Finished Jun 11 12:32:04 PM PDT 24
Peak memory 200112 kb
Host smart-c6e6856e-31ad-42a7-a9f5-2b8edd0acb66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640005926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.640005926
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.1197041860
Short name T548
Test name
Test status
Simulation time 166247965853 ps
CPU time 130.64 seconds
Started Jun 11 12:31:51 PM PDT 24
Finished Jun 11 12:34:03 PM PDT 24
Peak memory 200144 kb
Host smart-f7871e32-973e-4539-8cb2-af24a17bb059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197041860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.1197041860
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.743946947
Short name T1082
Test name
Test status
Simulation time 35863901817 ps
CPU time 28.23 seconds
Started Jun 11 12:31:49 PM PDT 24
Finished Jun 11 12:32:18 PM PDT 24
Peak memory 200196 kb
Host smart-a7979fab-3dd7-4746-b2af-937e9c3affe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743946947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.743946947
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.3561013293
Short name T512
Test name
Test status
Simulation time 18866480 ps
CPU time 0.55 seconds
Started Jun 11 12:29:28 PM PDT 24
Finished Jun 11 12:29:31 PM PDT 24
Peak memory 195704 kb
Host smart-767af107-39af-4c36-8a45-4c040fe9fb25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561013293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.3561013293
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.2773362834
Short name T532
Test name
Test status
Simulation time 90900508933 ps
CPU time 144.01 seconds
Started Jun 11 12:29:25 PM PDT 24
Finished Jun 11 12:31:51 PM PDT 24
Peak memory 200196 kb
Host smart-a3df62b1-b556-4bcf-a92a-d080e30fd3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773362834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.2773362834
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.4238227059
Short name T599
Test name
Test status
Simulation time 83953989326 ps
CPU time 38.73 seconds
Started Jun 11 12:29:27 PM PDT 24
Finished Jun 11 12:30:09 PM PDT 24
Peak memory 200180 kb
Host smart-95fbfc37-68b5-48fd-9299-81b92e967b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238227059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.4238227059
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.3507511313
Short name T578
Test name
Test status
Simulation time 95893341926 ps
CPU time 208.16 seconds
Started Jun 11 12:29:26 PM PDT 24
Finished Jun 11 12:32:56 PM PDT 24
Peak memory 199972 kb
Host smart-70182d41-9b41-4160-bf4c-06e3cbcc1107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507511313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.3507511313
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.2867631514
Short name T666
Test name
Test status
Simulation time 124089667213 ps
CPU time 42.23 seconds
Started Jun 11 12:29:29 PM PDT 24
Finished Jun 11 12:30:13 PM PDT 24
Peak memory 197220 kb
Host smart-c7fee694-f5a6-4a81-81b2-951b7f9b6559
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867631514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.2867631514
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.3234331787
Short name T1014
Test name
Test status
Simulation time 181554112749 ps
CPU time 72.49 seconds
Started Jun 11 12:29:47 PM PDT 24
Finished Jun 11 12:31:02 PM PDT 24
Peak memory 200328 kb
Host smart-26fb8d15-76a7-4ab4-a532-d41126652e08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3234331787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.3234331787
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.3445712609
Short name T342
Test name
Test status
Simulation time 4122553913 ps
CPU time 11.6 seconds
Started Jun 11 12:29:41 PM PDT 24
Finished Jun 11 12:29:56 PM PDT 24
Peak memory 199320 kb
Host smart-d298b61f-f963-4e85-8430-2e09eb5144fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445712609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.3445712609
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_perf.3055377111
Short name T423
Test name
Test status
Simulation time 9879641214 ps
CPU time 179.35 seconds
Started Jun 11 12:29:41 PM PDT 24
Finished Jun 11 12:32:44 PM PDT 24
Peak memory 200152 kb
Host smart-f14c2599-e5a6-4321-a306-6d2d2bc656fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3055377111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.3055377111
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.2439450427
Short name T383
Test name
Test status
Simulation time 4319441943 ps
CPU time 29.8 seconds
Started Jun 11 12:29:37 PM PDT 24
Finished Jun 11 12:30:08 PM PDT 24
Peak memory 198540 kb
Host smart-f9abfd60-5c89-43e4-9c65-a4408895e856
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2439450427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.2439450427
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.471779173
Short name T153
Test name
Test status
Simulation time 70859229225 ps
CPU time 109.39 seconds
Started Jun 11 12:29:46 PM PDT 24
Finished Jun 11 12:31:37 PM PDT 24
Peak memory 200248 kb
Host smart-b55f325a-6957-4478-abe3-867ff7283c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471779173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.471779173
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.3689950838
Short name T631
Test name
Test status
Simulation time 562225672 ps
CPU time 1.52 seconds
Started Jun 11 12:29:45 PM PDT 24
Finished Jun 11 12:29:49 PM PDT 24
Peak memory 195580 kb
Host smart-64fb32f8-7b22-443f-89d3-1f73edf9329c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689950838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.3689950838
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.3439419984
Short name T1065
Test name
Test status
Simulation time 669721610 ps
CPU time 2.76 seconds
Started Jun 11 12:29:44 PM PDT 24
Finished Jun 11 12:29:49 PM PDT 24
Peak memory 199904 kb
Host smart-4f4cdb3e-b740-4ffc-8074-46b5e469ef51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439419984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.3439419984
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.147126797
Short name T603
Test name
Test status
Simulation time 227126515936 ps
CPU time 313.06 seconds
Started Jun 11 12:29:40 PM PDT 24
Finished Jun 11 12:34:56 PM PDT 24
Peak memory 200248 kb
Host smart-3b8d3fc3-7f77-47c4-a452-ce06615c4c01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147126797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.147126797
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.2319843966
Short name T653
Test name
Test status
Simulation time 12274688059 ps
CPU time 119.25 seconds
Started Jun 11 12:29:27 PM PDT 24
Finished Jun 11 12:31:28 PM PDT 24
Peak memory 216864 kb
Host smart-0f386e7e-ebff-434d-8d60-b2cfd80c0e5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319843966 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.2319843966
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.784207678
Short name T388
Test name
Test status
Simulation time 3306428529 ps
CPU time 2.2 seconds
Started Jun 11 12:29:46 PM PDT 24
Finished Jun 11 12:29:50 PM PDT 24
Peak memory 199476 kb
Host smart-b56c8097-24b9-4f73-a161-9ab7d4c03a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784207678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.784207678
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.525545291
Short name T445
Test name
Test status
Simulation time 79329793927 ps
CPU time 157.38 seconds
Started Jun 11 12:29:45 PM PDT 24
Finished Jun 11 12:32:25 PM PDT 24
Peak memory 200276 kb
Host smart-8db67a52-41fb-485f-8b7d-5ea0aacac544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525545291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.525545291
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.2848395557
Short name T336
Test name
Test status
Simulation time 125616292401 ps
CPU time 175.39 seconds
Started Jun 11 12:31:53 PM PDT 24
Finished Jun 11 12:34:50 PM PDT 24
Peak memory 200276 kb
Host smart-82ddbf63-909b-41d4-a7ed-174af5550d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848395557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.2848395557
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.3907418963
Short name T235
Test name
Test status
Simulation time 142223172865 ps
CPU time 69.48 seconds
Started Jun 11 12:31:54 PM PDT 24
Finished Jun 11 12:33:05 PM PDT 24
Peak memory 200288 kb
Host smart-540914e4-7048-4826-9b16-ee7845c740ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907418963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.3907418963
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.1875387643
Short name T1032
Test name
Test status
Simulation time 239374556122 ps
CPU time 74.14 seconds
Started Jun 11 12:31:53 PM PDT 24
Finished Jun 11 12:33:08 PM PDT 24
Peak memory 200252 kb
Host smart-424f918b-d9f8-4d92-8834-250c582cbcca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875387643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.1875387643
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.2262677162
Short name T174
Test name
Test status
Simulation time 115598315043 ps
CPU time 155.43 seconds
Started Jun 11 12:31:51 PM PDT 24
Finished Jun 11 12:34:28 PM PDT 24
Peak memory 200240 kb
Host smart-7df33473-18c9-4ef4-9043-3de4077a51e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262677162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.2262677162
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.3702157774
Short name T119
Test name
Test status
Simulation time 222712698367 ps
CPU time 86.09 seconds
Started Jun 11 12:31:51 PM PDT 24
Finished Jun 11 12:33:18 PM PDT 24
Peak memory 200332 kb
Host smart-791b259d-766b-42a8-bcfb-0a0a3548dbd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702157774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.3702157774
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.1444383215
Short name T948
Test name
Test status
Simulation time 16303628701 ps
CPU time 33.93 seconds
Started Jun 11 12:31:54 PM PDT 24
Finished Jun 11 12:32:29 PM PDT 24
Peak memory 200336 kb
Host smart-387d95fb-a2dc-4b75-b011-8b4089a6c5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444383215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.1444383215
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.1761728164
Short name T333
Test name
Test status
Simulation time 107754422303 ps
CPU time 90.68 seconds
Started Jun 11 12:31:51 PM PDT 24
Finished Jun 11 12:33:23 PM PDT 24
Peak memory 200164 kb
Host smart-6d07e8e9-e13a-4783-8e7d-3ab52ca23afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761728164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.1761728164
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.897708607
Short name T569
Test name
Test status
Simulation time 45022600410 ps
CPU time 160.28 seconds
Started Jun 11 12:31:51 PM PDT 24
Finished Jun 11 12:34:33 PM PDT 24
Peak memory 200272 kb
Host smart-1abf7d66-0db8-4223-8f8a-293954a87dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897708607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.897708607
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.3140088859
Short name T708
Test name
Test status
Simulation time 63893625002 ps
CPU time 28.96 seconds
Started Jun 11 12:31:54 PM PDT 24
Finished Jun 11 12:32:25 PM PDT 24
Peak memory 200348 kb
Host smart-f7dc0c9b-54f9-4ab4-857f-187daf6df3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140088859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.3140088859
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.2353932620
Short name T855
Test name
Test status
Simulation time 58628586 ps
CPU time 0.55 seconds
Started Jun 11 12:29:46 PM PDT 24
Finished Jun 11 12:29:48 PM PDT 24
Peak memory 195524 kb
Host smart-e7757979-8c80-40e1-a468-d54e5fed30e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353932620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.2353932620
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.4057859704
Short name T1075
Test name
Test status
Simulation time 281743342646 ps
CPU time 29.12 seconds
Started Jun 11 12:29:46 PM PDT 24
Finished Jun 11 12:30:18 PM PDT 24
Peak memory 200272 kb
Host smart-987b4c98-5f92-4629-9b07-cc834d787829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057859704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.4057859704
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.555887819
Short name T574
Test name
Test status
Simulation time 237723735268 ps
CPU time 232.88 seconds
Started Jun 11 12:29:39 PM PDT 24
Finished Jun 11 12:33:35 PM PDT 24
Peak memory 200352 kb
Host smart-48704269-d515-47dc-91ce-0544c297ce34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555887819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.555887819
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_intr.4218179138
Short name T705
Test name
Test status
Simulation time 4946926914 ps
CPU time 2.31 seconds
Started Jun 11 12:29:36 PM PDT 24
Finished Jun 11 12:29:40 PM PDT 24
Peak memory 200216 kb
Host smart-d2690a4c-d12b-40af-8e15-2aebbb2a0df5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218179138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.4218179138
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.4122638154
Short name T890
Test name
Test status
Simulation time 40822581131 ps
CPU time 372.35 seconds
Started Jun 11 12:29:28 PM PDT 24
Finished Jun 11 12:35:42 PM PDT 24
Peak memory 200160 kb
Host smart-5658b939-f7dc-4ce6-81a5-b71a4c2c3c68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4122638154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.4122638154
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.2188993496
Short name T1068
Test name
Test status
Simulation time 9433003227 ps
CPU time 7.24 seconds
Started Jun 11 12:29:24 PM PDT 24
Finished Jun 11 12:29:33 PM PDT 24
Peak memory 200124 kb
Host smart-d874eb83-972e-4c25-a298-b0bb0dec8a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188993496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.2188993496
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_perf.867918915
Short name T1042
Test name
Test status
Simulation time 24727536931 ps
CPU time 745.04 seconds
Started Jun 11 12:29:47 PM PDT 24
Finished Jun 11 12:42:15 PM PDT 24
Peak memory 200280 kb
Host smart-32e6486d-992f-42af-b2f3-515338227d7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=867918915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.867918915
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.2520099714
Short name T528
Test name
Test status
Simulation time 3142884845 ps
CPU time 10.84 seconds
Started Jun 11 12:29:38 PM PDT 24
Finished Jun 11 12:29:51 PM PDT 24
Peak memory 199268 kb
Host smart-558cdea7-8ad9-43f6-8af6-ce56c1d0d077
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2520099714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.2520099714
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.2170741457
Short name T368
Test name
Test status
Simulation time 39693025198 ps
CPU time 19.34 seconds
Started Jun 11 12:29:49 PM PDT 24
Finished Jun 11 12:30:11 PM PDT 24
Peak memory 196320 kb
Host smart-d81324b3-5f91-4260-9be0-43bb7232040b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170741457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.2170741457
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.1001091390
Short name T597
Test name
Test status
Simulation time 111999740 ps
CPU time 0.83 seconds
Started Jun 11 12:29:29 PM PDT 24
Finished Jun 11 12:29:32 PM PDT 24
Peak memory 197344 kb
Host smart-c4462819-864a-42ff-a6c0-87e834afc235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001091390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.1001091390
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.3060653822
Short name T1077
Test name
Test status
Simulation time 537953990910 ps
CPU time 887.87 seconds
Started Jun 11 12:29:46 PM PDT 24
Finished Jun 11 12:44:36 PM PDT 24
Peak memory 200264 kb
Host smart-6e61b74b-a507-4e54-a095-40ac08e2cfd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060653822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.3060653822
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.4015637390
Short name T915
Test name
Test status
Simulation time 2241245855 ps
CPU time 2.95 seconds
Started Jun 11 12:29:24 PM PDT 24
Finished Jun 11 12:29:28 PM PDT 24
Peak memory 199808 kb
Host smart-57012a41-f192-43de-9ef5-405e1b300d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015637390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.4015637390
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.2514570333
Short name T646
Test name
Test status
Simulation time 84113639899 ps
CPU time 64.95 seconds
Started Jun 11 12:29:29 PM PDT 24
Finished Jun 11 12:30:36 PM PDT 24
Peak memory 200256 kb
Host smart-17f2a15e-8cb8-44e5-ab69-cbdf01490877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514570333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.2514570333
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.1976633173
Short name T928
Test name
Test status
Simulation time 212162427561 ps
CPU time 494.45 seconds
Started Jun 11 12:31:53 PM PDT 24
Finished Jun 11 12:40:09 PM PDT 24
Peak memory 200188 kb
Host smart-6165a08a-ca55-4549-ac26-32e87463b37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976633173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.1976633173
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.695409598
Short name T945
Test name
Test status
Simulation time 42460221851 ps
CPU time 70.43 seconds
Started Jun 11 12:31:50 PM PDT 24
Finished Jun 11 12:33:02 PM PDT 24
Peak memory 200256 kb
Host smart-d18d9e5e-4c38-4a67-8a9d-20f9145a6a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695409598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.695409598
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.256956583
Short name T432
Test name
Test status
Simulation time 36460859313 ps
CPU time 82.96 seconds
Started Jun 11 12:31:52 PM PDT 24
Finished Jun 11 12:33:17 PM PDT 24
Peak memory 200284 kb
Host smart-ca7296d7-4b58-4b5f-a47e-12f5d7f92fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256956583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.256956583
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.1071303809
Short name T223
Test name
Test status
Simulation time 22553060083 ps
CPU time 39.54 seconds
Started Jun 11 12:31:51 PM PDT 24
Finished Jun 11 12:32:32 PM PDT 24
Peak memory 200288 kb
Host smart-6517327a-ad99-4753-9a7f-b8584ecf3d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071303809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.1071303809
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.3089492070
Short name T273
Test name
Test status
Simulation time 297390958812 ps
CPU time 39.12 seconds
Started Jun 11 12:31:52 PM PDT 24
Finished Jun 11 12:32:33 PM PDT 24
Peak memory 200536 kb
Host smart-8023f0b9-6fd4-4cf7-9a97-02a589f0b47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089492070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.3089492070
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.906500652
Short name T1015
Test name
Test status
Simulation time 50224711577 ps
CPU time 22.89 seconds
Started Jun 11 12:31:50 PM PDT 24
Finished Jun 11 12:32:14 PM PDT 24
Peak memory 200260 kb
Host smart-26bf5042-e24c-4a6a-a3c4-0ca98271b170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906500652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.906500652
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.2486877652
Short name T213
Test name
Test status
Simulation time 17507274314 ps
CPU time 29.86 seconds
Started Jun 11 12:31:51 PM PDT 24
Finished Jun 11 12:32:22 PM PDT 24
Peak memory 200204 kb
Host smart-2b7b5f25-ae62-477a-bff7-f62e44fbba53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486877652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.2486877652
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.1106344604
Short name T1094
Test name
Test status
Simulation time 14031766187 ps
CPU time 7.21 seconds
Started Jun 11 12:31:54 PM PDT 24
Finished Jun 11 12:32:03 PM PDT 24
Peak memory 200096 kb
Host smart-a98435d9-0e64-4344-bcde-42db6df98886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106344604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.1106344604
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.1922745517
Short name T198
Test name
Test status
Simulation time 15032828810 ps
CPU time 24.34 seconds
Started Jun 11 12:31:49 PM PDT 24
Finished Jun 11 12:32:14 PM PDT 24
Peak memory 199856 kb
Host smart-227ba377-e08e-4b24-aaef-136691057d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922745517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.1922745517
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.5714505
Short name T370
Test name
Test status
Simulation time 13193931 ps
CPU time 0.53 seconds
Started Jun 11 12:29:37 PM PDT 24
Finished Jun 11 12:29:39 PM PDT 24
Peak memory 194632 kb
Host smart-69e08d6a-1a0c-4a27-b80c-22c9da572a5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5714505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.5714505
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.2802239719
Short name T288
Test name
Test status
Simulation time 54610737314 ps
CPU time 23.88 seconds
Started Jun 11 12:29:28 PM PDT 24
Finished Jun 11 12:29:54 PM PDT 24
Peak memory 200220 kb
Host smart-1dbf9e31-4aba-4d1c-a681-e0f4d642cbb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802239719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.2802239719
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.2265687789
Short name T959
Test name
Test status
Simulation time 66440053106 ps
CPU time 33.14 seconds
Started Jun 11 12:29:50 PM PDT 24
Finished Jun 11 12:30:25 PM PDT 24
Peak memory 200320 kb
Host smart-ec585e5a-ca7b-4a0e-8934-3771e41b2e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265687789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.2265687789
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.2506011078
Short name T216
Test name
Test status
Simulation time 39526756448 ps
CPU time 16.14 seconds
Started Jun 11 12:29:38 PM PDT 24
Finished Jun 11 12:29:55 PM PDT 24
Peak memory 200596 kb
Host smart-06835210-f158-4f7a-9ee4-bdc8a8b13b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506011078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.2506011078
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.651563092
Short name T778
Test name
Test status
Simulation time 2538259391 ps
CPU time 8.53 seconds
Started Jun 11 12:29:47 PM PDT 24
Finished Jun 11 12:29:58 PM PDT 24
Peak memory 200244 kb
Host smart-3b1afc4a-5bd0-4a2a-84bb-a70a98708dbb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651563092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.651563092
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.3253638603
Short name T567
Test name
Test status
Simulation time 78284451129 ps
CPU time 236.97 seconds
Started Jun 11 12:29:37 PM PDT 24
Finished Jun 11 12:33:35 PM PDT 24
Peak memory 200308 kb
Host smart-6d608e32-1214-46af-b017-025631c02af1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3253638603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.3253638603
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.3039471746
Short name T403
Test name
Test status
Simulation time 12001297315 ps
CPU time 5.51 seconds
Started Jun 11 12:29:50 PM PDT 24
Finished Jun 11 12:29:59 PM PDT 24
Peak memory 198416 kb
Host smart-268dc774-5427-4fbd-89e4-6e6f833f3dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039471746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.3039471746
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_perf.1173929489
Short name T261
Test name
Test status
Simulation time 20734051552 ps
CPU time 1112.23 seconds
Started Jun 11 12:29:50 PM PDT 24
Finished Jun 11 12:48:25 PM PDT 24
Peak memory 200316 kb
Host smart-e911c7ca-e0e5-4a77-92c7-61aa1a3ae7bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1173929489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.1173929489
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.2807358715
Short name T343
Test name
Test status
Simulation time 3382267168 ps
CPU time 24.8 seconds
Started Jun 11 12:29:40 PM PDT 24
Finished Jun 11 12:30:08 PM PDT 24
Peak memory 198140 kb
Host smart-88fe72d3-91e8-45f2-89ee-a8a8d8f526fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2807358715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.2807358715
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.803352190
Short name T289
Test name
Test status
Simulation time 159575814670 ps
CPU time 30.03 seconds
Started Jun 11 12:29:48 PM PDT 24
Finished Jun 11 12:30:20 PM PDT 24
Peak memory 200072 kb
Host smart-94b07c8a-82c6-4652-bf25-5897575e1203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803352190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.803352190
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.1110437330
Short name T1037
Test name
Test status
Simulation time 6624031502 ps
CPU time 1.85 seconds
Started Jun 11 12:29:40 PM PDT 24
Finished Jun 11 12:29:45 PM PDT 24
Peak memory 196388 kb
Host smart-a6aaa82f-52f0-4ac1-a8ae-b7ba4957fe68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110437330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.1110437330
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.81549952
Short name T869
Test name
Test status
Simulation time 889545164 ps
CPU time 2.75 seconds
Started Jun 11 12:29:29 PM PDT 24
Finished Jun 11 12:29:34 PM PDT 24
Peak memory 199528 kb
Host smart-82696845-c65a-47de-b102-3ca9d2f932f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81549952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.81549952
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.752986614
Short name T533
Test name
Test status
Simulation time 6111956978 ps
CPU time 19.86 seconds
Started Jun 11 12:29:51 PM PDT 24
Finished Jun 11 12:30:13 PM PDT 24
Peak memory 199784 kb
Host smart-828bb300-dfdb-41e1-bfb3-22e972f230c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752986614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.752986614
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.4039438368
Short name T522
Test name
Test status
Simulation time 131095697109 ps
CPU time 86.73 seconds
Started Jun 11 12:29:42 PM PDT 24
Finished Jun 11 12:31:12 PM PDT 24
Peak memory 200320 kb
Host smart-fd7a0712-fcc1-4fec-81ec-2fbb3db86948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039438368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.4039438368
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.1823888084
Short name T828
Test name
Test status
Simulation time 147002423677 ps
CPU time 80.33 seconds
Started Jun 11 12:31:51 PM PDT 24
Finished Jun 11 12:33:13 PM PDT 24
Peak memory 200292 kb
Host smart-5834392b-f560-42ec-919d-2da9d4095c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823888084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.1823888084
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.1552715259
Short name T107
Test name
Test status
Simulation time 14325051929 ps
CPU time 23.54 seconds
Started Jun 11 12:31:51 PM PDT 24
Finished Jun 11 12:32:16 PM PDT 24
Peak memory 200160 kb
Host smart-6c3364e1-6c61-4fff-afb9-458ddbc8f697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552715259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.1552715259
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.1816151774
Short name T319
Test name
Test status
Simulation time 118887384401 ps
CPU time 34.34 seconds
Started Jun 11 12:31:51 PM PDT 24
Finished Jun 11 12:32:27 PM PDT 24
Peak memory 200288 kb
Host smart-bf228c59-18ed-43b4-955e-5025d2500e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816151774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.1816151774
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.791586842
Short name T668
Test name
Test status
Simulation time 9089889126 ps
CPU time 13.53 seconds
Started Jun 11 12:31:54 PM PDT 24
Finished Jun 11 12:32:09 PM PDT 24
Peak memory 200356 kb
Host smart-3e5220f1-4c7b-4e26-9f72-9c888575c665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791586842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.791586842
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.2705788647
Short name T974
Test name
Test status
Simulation time 10893982487 ps
CPU time 5.12 seconds
Started Jun 11 12:31:54 PM PDT 24
Finished Jun 11 12:32:00 PM PDT 24
Peak memory 200352 kb
Host smart-42731ae3-a660-45d3-8141-4c6cce4aa8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705788647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.2705788647
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.3815533112
Short name T809
Test name
Test status
Simulation time 20614696967 ps
CPU time 22.73 seconds
Started Jun 11 12:31:51 PM PDT 24
Finished Jun 11 12:32:15 PM PDT 24
Peak memory 200236 kb
Host smart-2ddfe28d-bbd1-4c9e-a1e2-6a8fd8241db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815533112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.3815533112
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.2736042549
Short name T221
Test name
Test status
Simulation time 36167734103 ps
CPU time 12.68 seconds
Started Jun 11 12:32:08 PM PDT 24
Finished Jun 11 12:32:22 PM PDT 24
Peak memory 197908 kb
Host smart-ba1a53a0-daa4-472c-8639-1e73d80680e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736042549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.2736042549
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.394931330
Short name T880
Test name
Test status
Simulation time 256721873696 ps
CPU time 55.45 seconds
Started Jun 11 12:32:07 PM PDT 24
Finished Jun 11 12:33:04 PM PDT 24
Peak memory 200600 kb
Host smart-7a5b4d58-9b1b-4e9d-a0d7-87140b11bf43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394931330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.394931330
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.2363374084
Short name T167
Test name
Test status
Simulation time 88527033892 ps
CPU time 33.84 seconds
Started Jun 11 12:32:06 PM PDT 24
Finished Jun 11 12:32:41 PM PDT 24
Peak memory 200144 kb
Host smart-4cc1e1d7-3b8b-464b-9dd1-303c0aa29f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363374084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.2363374084
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.2970671404
Short name T539
Test name
Test status
Simulation time 74775115867 ps
CPU time 34.08 seconds
Started Jun 11 12:32:07 PM PDT 24
Finished Jun 11 12:32:42 PM PDT 24
Peak memory 200264 kb
Host smart-4088d5e1-a1d0-41c0-9211-d18fb275351d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970671404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.2970671404
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.4051263212
Short name T354
Test name
Test status
Simulation time 50914415 ps
CPU time 0.55 seconds
Started Jun 11 12:28:54 PM PDT 24
Finished Jun 11 12:28:57 PM PDT 24
Peak memory 195736 kb
Host smart-a66e437d-642c-46c6-8737-b131932192c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051263212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.4051263212
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.3642360574
Short name T139
Test name
Test status
Simulation time 81028898744 ps
CPU time 36.18 seconds
Started Jun 11 12:29:05 PM PDT 24
Finished Jun 11 12:29:44 PM PDT 24
Peak memory 200244 kb
Host smart-ef8ed279-e69b-4391-bd78-5de01077dc14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642360574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.3642360574
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.958961199
Short name T1026
Test name
Test status
Simulation time 42783757169 ps
CPU time 30.89 seconds
Started Jun 11 12:28:50 PM PDT 24
Finished Jun 11 12:29:23 PM PDT 24
Peak memory 200292 kb
Host smart-3435aae5-5d0b-4850-b0be-abed23087977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958961199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.958961199
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.2974016967
Short name T993
Test name
Test status
Simulation time 21622815103 ps
CPU time 3.65 seconds
Started Jun 11 12:28:52 PM PDT 24
Finished Jun 11 12:28:58 PM PDT 24
Peak memory 197188 kb
Host smart-609a478c-e876-41c6-859c-33c9257d3031
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974016967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.2974016967
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.3098776192
Short name T244
Test name
Test status
Simulation time 70518678048 ps
CPU time 363.66 seconds
Started Jun 11 12:28:48 PM PDT 24
Finished Jun 11 12:34:54 PM PDT 24
Peak memory 200264 kb
Host smart-9916679b-462f-4d13-ba32-15056245f6f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3098776192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.3098776192
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.2946691868
Short name T386
Test name
Test status
Simulation time 7958740734 ps
CPU time 5.68 seconds
Started Jun 11 12:29:17 PM PDT 24
Finished Jun 11 12:29:24 PM PDT 24
Peak memory 200304 kb
Host smart-635d9c8e-340f-4cf4-bd2a-5a81d22e6aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946691868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.2946691868
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_perf.1319749958
Short name T784
Test name
Test status
Simulation time 26083025597 ps
CPU time 234.89 seconds
Started Jun 11 12:28:55 PM PDT 24
Finished Jun 11 12:32:52 PM PDT 24
Peak memory 200360 kb
Host smart-19757bef-6f3e-49df-a771-af7196dda44d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1319749958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.1319749958
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.3477364581
Short name T1018
Test name
Test status
Simulation time 1507982389 ps
CPU time 1.13 seconds
Started Jun 11 12:28:51 PM PDT 24
Finished Jun 11 12:28:54 PM PDT 24
Peak memory 195912 kb
Host smart-0a82ef42-4c2b-435c-9437-9ba193cfea14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3477364581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.3477364581
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.3973258267
Short name T613
Test name
Test status
Simulation time 120491292751 ps
CPU time 100.31 seconds
Started Jun 11 12:28:54 PM PDT 24
Finished Jun 11 12:30:37 PM PDT 24
Peak memory 200368 kb
Host smart-fa85b5e4-869e-4af8-98ec-aa6d61d5f87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973258267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.3973258267
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.3093513614
Short name T998
Test name
Test status
Simulation time 48320209698 ps
CPU time 19.84 seconds
Started Jun 11 12:28:53 PM PDT 24
Finished Jun 11 12:29:14 PM PDT 24
Peak memory 196584 kb
Host smart-f448ffdf-c1b2-4606-a002-382589953fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093513614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.3093513614
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.1490319634
Short name T24
Test name
Test status
Simulation time 32819325 ps
CPU time 0.73 seconds
Started Jun 11 12:29:06 PM PDT 24
Finished Jun 11 12:29:09 PM PDT 24
Peak memory 218804 kb
Host smart-50d897b5-d722-44bc-8d2e-23b2560f32bb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490319634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.1490319634
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.2521545891
Short name T280
Test name
Test status
Simulation time 278171148 ps
CPU time 1.2 seconds
Started Jun 11 12:29:00 PM PDT 24
Finished Jun 11 12:29:03 PM PDT 24
Peak memory 198372 kb
Host smart-3f5a55dc-8761-49ba-ac59-1262747e3575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521545891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.2521545891
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.1456842847
Short name T473
Test name
Test status
Simulation time 6865940912 ps
CPU time 39.51 seconds
Started Jun 11 12:29:00 PM PDT 24
Finished Jun 11 12:29:42 PM PDT 24
Peak memory 200180 kb
Host smart-45900f30-f2f1-4016-9a9b-d0f8ad22a15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456842847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.1456842847
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.4014881172
Short name T792
Test name
Test status
Simulation time 10164611820 ps
CPU time 18.51 seconds
Started Jun 11 12:28:52 PM PDT 24
Finished Jun 11 12:29:13 PM PDT 24
Peak memory 200236 kb
Host smart-c883c50a-a6a9-46fc-9243-901dda475767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014881172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.4014881172
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.970045494
Short name T347
Test name
Test status
Simulation time 11676379 ps
CPU time 0.56 seconds
Started Jun 11 12:29:39 PM PDT 24
Finished Jun 11 12:29:43 PM PDT 24
Peak memory 195696 kb
Host smart-fd2e61fb-b62b-45fb-8d33-479d3f0adcfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970045494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.970045494
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.2793065978
Short name T701
Test name
Test status
Simulation time 86808322154 ps
CPU time 63.36 seconds
Started Jun 11 12:29:41 PM PDT 24
Finished Jun 11 12:30:47 PM PDT 24
Peak memory 200316 kb
Host smart-788b5ab3-ce45-456e-ae39-86eb24de88f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793065978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.2793065978
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.202016836
Short name T791
Test name
Test status
Simulation time 187965722959 ps
CPU time 111.26 seconds
Started Jun 11 12:29:39 PM PDT 24
Finished Jun 11 12:31:33 PM PDT 24
Peak memory 200216 kb
Host smart-90f42bdc-4182-4b3b-8136-cb3453a31601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202016836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.202016836
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.3314796911
Short name T546
Test name
Test status
Simulation time 8879091932 ps
CPU time 13.5 seconds
Started Jun 11 12:29:40 PM PDT 24
Finished Jun 11 12:29:57 PM PDT 24
Peak memory 198208 kb
Host smart-c39cc942-1d98-436f-996e-f5e3f896b48f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314796911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.3314796911
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.2771856065
Short name T992
Test name
Test status
Simulation time 106914159080 ps
CPU time 801.62 seconds
Started Jun 11 12:29:40 PM PDT 24
Finished Jun 11 12:43:05 PM PDT 24
Peak memory 200384 kb
Host smart-183cff39-d69c-4920-ac92-3eae6b06c809
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2771856065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.2771856065
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.1675668106
Short name T816
Test name
Test status
Simulation time 6155120366 ps
CPU time 3.9 seconds
Started Jun 11 12:29:43 PM PDT 24
Finished Jun 11 12:29:49 PM PDT 24
Peak memory 200212 kb
Host smart-1d11fa6e-6377-45c5-af95-582fc158a853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675668106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.1675668106
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.2937047678
Short name T1002
Test name
Test status
Simulation time 1769916739 ps
CPU time 1.12 seconds
Started Jun 11 12:29:50 PM PDT 24
Finished Jun 11 12:29:53 PM PDT 24
Peak memory 198280 kb
Host smart-01fbe73f-d2c7-41c5-8db2-8724daedb032
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2937047678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.2937047678
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.831495458
Short name T637
Test name
Test status
Simulation time 183952008068 ps
CPU time 95.81 seconds
Started Jun 11 12:29:48 PM PDT 24
Finished Jun 11 12:31:26 PM PDT 24
Peak memory 200364 kb
Host smart-1e540821-8d9c-442a-8678-4776bd3b59f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831495458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.831495458
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.1154271867
Short name T1085
Test name
Test status
Simulation time 4527307651 ps
CPU time 8.49 seconds
Started Jun 11 12:29:48 PM PDT 24
Finished Jun 11 12:29:58 PM PDT 24
Peak memory 196392 kb
Host smart-b185a9d7-7cd5-4f41-ad33-696ec38f4dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154271867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.1154271867
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.1380891585
Short name T413
Test name
Test status
Simulation time 275851684 ps
CPU time 1 seconds
Started Jun 11 12:29:48 PM PDT 24
Finished Jun 11 12:29:51 PM PDT 24
Peak memory 198676 kb
Host smart-c1bf3cb5-b7ca-4cb4-b0f2-648d01680d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380891585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.1380891585
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.219821270
Short name T834
Test name
Test status
Simulation time 91716156423 ps
CPU time 68.61 seconds
Started Jun 11 12:29:57 PM PDT 24
Finished Jun 11 12:31:07 PM PDT 24
Peak memory 200284 kb
Host smart-3c132abb-2beb-4f08-8441-2a40be4e298b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219821270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.219821270
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.2261908637
Short name T281
Test name
Test status
Simulation time 6651922399 ps
CPU time 21.3 seconds
Started Jun 11 12:29:39 PM PDT 24
Finished Jun 11 12:30:02 PM PDT 24
Peak memory 200232 kb
Host smart-0940a401-e204-4bf7-afc3-f1624c2789d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261908637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.2261908637
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.3056754668
Short name T75
Test name
Test status
Simulation time 24374696126 ps
CPU time 20.41 seconds
Started Jun 11 12:29:39 PM PDT 24
Finished Jun 11 12:30:01 PM PDT 24
Peak memory 200296 kb
Host smart-11d685b1-0ef9-4310-b0dc-00ca6590f576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056754668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.3056754668
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.3020409598
Short name T772
Test name
Test status
Simulation time 24548494597 ps
CPU time 36.18 seconds
Started Jun 11 12:32:04 PM PDT 24
Finished Jun 11 12:32:41 PM PDT 24
Peak memory 200236 kb
Host smart-2a4ff6ff-2b40-4d18-96df-8437a59ff283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020409598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.3020409598
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.3276868563
Short name T848
Test name
Test status
Simulation time 108894898277 ps
CPU time 40.16 seconds
Started Jun 11 12:32:06 PM PDT 24
Finished Jun 11 12:32:47 PM PDT 24
Peak memory 200256 kb
Host smart-0de27843-fd22-40dc-8736-f89164a335c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276868563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.3276868563
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.223466095
Short name T298
Test name
Test status
Simulation time 14625304930 ps
CPU time 13.8 seconds
Started Jun 11 12:32:11 PM PDT 24
Finished Jun 11 12:32:25 PM PDT 24
Peak memory 200300 kb
Host smart-05be603f-d723-4204-b09c-a51f744a5b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223466095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.223466095
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.3904574339
Short name T767
Test name
Test status
Simulation time 107946295551 ps
CPU time 192.42 seconds
Started Jun 11 12:32:06 PM PDT 24
Finished Jun 11 12:35:20 PM PDT 24
Peak memory 200196 kb
Host smart-ce8dad16-a042-4d04-afca-fbbaaf9cac38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904574339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.3904574339
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.3303401488
Short name T222
Test name
Test status
Simulation time 88049701601 ps
CPU time 327.35 seconds
Started Jun 11 12:32:06 PM PDT 24
Finished Jun 11 12:37:35 PM PDT 24
Peak memory 200176 kb
Host smart-476d1271-d1b1-4bd8-a17c-da613685d615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303401488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.3303401488
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.1863955366
Short name T762
Test name
Test status
Simulation time 84358948277 ps
CPU time 12.8 seconds
Started Jun 11 12:32:14 PM PDT 24
Finished Jun 11 12:32:28 PM PDT 24
Peak memory 198124 kb
Host smart-c6b2aea2-4934-40b5-98b5-0fe5964ce0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863955366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.1863955366
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.1324372759
Short name T326
Test name
Test status
Simulation time 148082681953 ps
CPU time 114.42 seconds
Started Jun 11 12:32:05 PM PDT 24
Finished Jun 11 12:34:00 PM PDT 24
Peak memory 200380 kb
Host smart-602aa74b-bdda-4f28-ace6-e96dc84033ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324372759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.1324372759
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.3563525432
Short name T978
Test name
Test status
Simulation time 166404858004 ps
CPU time 105.61 seconds
Started Jun 11 12:32:09 PM PDT 24
Finished Jun 11 12:33:55 PM PDT 24
Peak memory 200196 kb
Host smart-20b1e4eb-2cad-4854-9ab8-55c6b57bf5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563525432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.3563525432
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.667709466
Short name T481
Test name
Test status
Simulation time 32164651587 ps
CPU time 14 seconds
Started Jun 11 12:32:06 PM PDT 24
Finished Jun 11 12:32:22 PM PDT 24
Peak memory 200348 kb
Host smart-82d4d16e-c167-4ad2-88c2-0ba42771a424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667709466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.667709466
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.4263927499
Short name T424
Test name
Test status
Simulation time 29607997 ps
CPU time 0.56 seconds
Started Jun 11 12:29:37 PM PDT 24
Finished Jun 11 12:29:39 PM PDT 24
Peak memory 195092 kb
Host smart-6e43c8a9-0078-411c-b11c-a9e203207160
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263927499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.4263927499
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.2759096038
Short name T311
Test name
Test status
Simulation time 102954279062 ps
CPU time 39.54 seconds
Started Jun 11 12:29:39 PM PDT 24
Finished Jun 11 12:30:20 PM PDT 24
Peak memory 200288 kb
Host smart-a2034607-5cb4-477c-bc10-cda3f22cc6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759096038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.2759096038
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.3332162609
Short name T294
Test name
Test status
Simulation time 159683157100 ps
CPU time 19.94 seconds
Started Jun 11 12:29:42 PM PDT 24
Finished Jun 11 12:30:04 PM PDT 24
Peak memory 198336 kb
Host smart-525ef316-6039-4d4f-a403-60123aa8735c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332162609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.3332162609
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.2767828031
Short name T110
Test name
Test status
Simulation time 41382865959 ps
CPU time 56.81 seconds
Started Jun 11 12:29:38 PM PDT 24
Finished Jun 11 12:30:36 PM PDT 24
Peak memory 200596 kb
Host smart-8429f3db-f642-4ba6-b1a2-99b663f7916a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767828031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.2767828031
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.923917976
Short name T408
Test name
Test status
Simulation time 25005675316 ps
CPU time 41.64 seconds
Started Jun 11 12:29:40 PM PDT 24
Finished Jun 11 12:30:25 PM PDT 24
Peak memory 200300 kb
Host smart-5cd6764e-0fa6-472f-8f43-a2d9baac1280
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923917976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.923917976
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.614336162
Short name T821
Test name
Test status
Simulation time 111684022605 ps
CPU time 311.62 seconds
Started Jun 11 12:29:41 PM PDT 24
Finished Jun 11 12:34:56 PM PDT 24
Peak memory 200308 kb
Host smart-817c3f00-81e6-4ed9-82fd-9a0237b2b733
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=614336162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.614336162
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.138074347
Short name T466
Test name
Test status
Simulation time 5371163586 ps
CPU time 5.88 seconds
Started Jun 11 12:29:49 PM PDT 24
Finished Jun 11 12:29:57 PM PDT 24
Peak memory 199840 kb
Host smart-bb0fb75f-9897-48f1-a56e-9766820929be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138074347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.138074347
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_perf.1922494984
Short name T421
Test name
Test status
Simulation time 6991402742 ps
CPU time 362.5 seconds
Started Jun 11 12:29:39 PM PDT 24
Finished Jun 11 12:35:44 PM PDT 24
Peak memory 200216 kb
Host smart-0369e659-d4b1-4c01-918e-f8310859974b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1922494984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.1922494984
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.2961903343
Short name T861
Test name
Test status
Simulation time 3694074510 ps
CPU time 7.66 seconds
Started Jun 11 12:29:39 PM PDT 24
Finished Jun 11 12:29:50 PM PDT 24
Peak memory 199228 kb
Host smart-b551d953-c7c9-48ea-841f-8ac85d87c28b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2961903343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.2961903343
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.2475917826
Short name T788
Test name
Test status
Simulation time 175986997430 ps
CPU time 133.6 seconds
Started Jun 11 12:29:37 PM PDT 24
Finished Jun 11 12:31:52 PM PDT 24
Peak memory 200352 kb
Host smart-b9917409-c378-4382-a10a-e23b0e412304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475917826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.2475917826
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.1370034956
Short name T917
Test name
Test status
Simulation time 5751668134 ps
CPU time 2.85 seconds
Started Jun 11 12:30:03 PM PDT 24
Finished Jun 11 12:30:08 PM PDT 24
Peak memory 196600 kb
Host smart-3bc49306-7a7d-44d1-8ab7-ca81347b889f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370034956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.1370034956
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.3280210147
Short name T360
Test name
Test status
Simulation time 674021490 ps
CPU time 1.71 seconds
Started Jun 11 12:29:51 PM PDT 24
Finished Jun 11 12:29:56 PM PDT 24
Peak memory 198612 kb
Host smart-62f7d1a5-3edd-4c95-9c95-7fb916c0c5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280210147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.3280210147
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.2496135608
Short name T729
Test name
Test status
Simulation time 331809740001 ps
CPU time 298.1 seconds
Started Jun 11 12:29:43 PM PDT 24
Finished Jun 11 12:34:44 PM PDT 24
Peak memory 200368 kb
Host smart-48050610-cbc9-41eb-8209-539cec5f4a50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496135608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.2496135608
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.2824075165
Short name T467
Test name
Test status
Simulation time 877473061 ps
CPU time 1.62 seconds
Started Jun 11 12:29:39 PM PDT 24
Finished Jun 11 12:29:44 PM PDT 24
Peak memory 198600 kb
Host smart-41d75d37-b202-42e7-b809-807d6b9dec43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824075165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.2824075165
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.2915400532
Short name T980
Test name
Test status
Simulation time 5809012605 ps
CPU time 8.37 seconds
Started Jun 11 12:29:40 PM PDT 24
Finished Jun 11 12:29:52 PM PDT 24
Peak memory 200168 kb
Host smart-702f0a3e-2f93-48f1-8bf7-d2d09eb82371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915400532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.2915400532
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.3336434249
Short name T650
Test name
Test status
Simulation time 129244844666 ps
CPU time 219.94 seconds
Started Jun 11 12:32:05 PM PDT 24
Finished Jun 11 12:35:45 PM PDT 24
Peak memory 200312 kb
Host smart-ef31ab64-9144-46a2-860d-3de1d52e436b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336434249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.3336434249
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.406457790
Short name T214
Test name
Test status
Simulation time 28006326995 ps
CPU time 49.4 seconds
Started Jun 11 12:32:07 PM PDT 24
Finished Jun 11 12:32:57 PM PDT 24
Peak memory 200268 kb
Host smart-18544e29-35db-4c0e-b290-b7d4fa5c5c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406457790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.406457790
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.912917015
Short name T1027
Test name
Test status
Simulation time 217808892878 ps
CPU time 27.57 seconds
Started Jun 11 12:32:07 PM PDT 24
Finished Jun 11 12:32:36 PM PDT 24
Peak memory 200288 kb
Host smart-525a1aba-9ef7-4121-a32a-8b89234db83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912917015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.912917015
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.4230883299
Short name T897
Test name
Test status
Simulation time 15053402493 ps
CPU time 12.27 seconds
Started Jun 11 12:32:07 PM PDT 24
Finished Jun 11 12:32:21 PM PDT 24
Peak memory 200268 kb
Host smart-bf89660d-b122-4d75-b39f-8d2a74a78c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230883299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.4230883299
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.1789228931
Short name T205
Test name
Test status
Simulation time 86484773314 ps
CPU time 140.15 seconds
Started Jun 11 12:32:05 PM PDT 24
Finished Jun 11 12:34:26 PM PDT 24
Peak memory 200116 kb
Host smart-18db22af-cb36-4603-af20-f497ce21d3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789228931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.1789228931
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.2728610140
Short name T695
Test name
Test status
Simulation time 7346172262 ps
CPU time 13.57 seconds
Started Jun 11 12:32:06 PM PDT 24
Finished Jun 11 12:32:21 PM PDT 24
Peak memory 200332 kb
Host smart-e8424ff6-7652-4acc-ba9e-cf835be41e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728610140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.2728610140
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.2563585670
Short name T91
Test name
Test status
Simulation time 61007407202 ps
CPU time 26.09 seconds
Started Jun 11 12:32:05 PM PDT 24
Finished Jun 11 12:32:33 PM PDT 24
Peak memory 200108 kb
Host smart-6b9a1cff-7cf4-4240-b06e-1de0911d0a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563585670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.2563585670
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.638944441
Short name T202
Test name
Test status
Simulation time 66840566205 ps
CPU time 88.22 seconds
Started Jun 11 12:32:07 PM PDT 24
Finished Jun 11 12:33:36 PM PDT 24
Peak memory 200308 kb
Host smart-6df5771f-1b00-4316-903d-eacf44bfc8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638944441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.638944441
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.41863002
Short name T183
Test name
Test status
Simulation time 143963359297 ps
CPU time 17.08 seconds
Started Jun 11 12:32:07 PM PDT 24
Finished Jun 11 12:32:26 PM PDT 24
Peak memory 200296 kb
Host smart-dd20d71a-a780-4411-bae3-e2e11d01c9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41863002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.41863002
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.309918936
Short name T710
Test name
Test status
Simulation time 24546583612 ps
CPU time 39.97 seconds
Started Jun 11 12:32:05 PM PDT 24
Finished Jun 11 12:32:46 PM PDT 24
Peak memory 200336 kb
Host smart-a33934ef-6fa1-4bfb-a5b9-eaf21828b5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309918936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.309918936
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.320627258
Short name T475
Test name
Test status
Simulation time 14283913 ps
CPU time 0.55 seconds
Started Jun 11 12:29:42 PM PDT 24
Finished Jun 11 12:29:46 PM PDT 24
Peak memory 195044 kb
Host smart-cb9ed7ab-793c-46bd-a58c-40eee013e6c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320627258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.320627258
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.1262632727
Short name T315
Test name
Test status
Simulation time 53158771229 ps
CPU time 24.51 seconds
Started Jun 11 12:29:50 PM PDT 24
Finished Jun 11 12:30:17 PM PDT 24
Peak memory 200272 kb
Host smart-00b0c2ed-0cc0-4e23-95fa-4b5af5d0ed0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262632727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.1262632727
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.2013797980
Short name T786
Test name
Test status
Simulation time 125642342150 ps
CPU time 183.82 seconds
Started Jun 11 12:30:01 PM PDT 24
Finished Jun 11 12:33:07 PM PDT 24
Peak memory 200336 kb
Host smart-420d8f26-ada0-4164-b210-b91fa7e7ccb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013797980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.2013797980
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.942968464
Short name T503
Test name
Test status
Simulation time 23072184718 ps
CPU time 32.68 seconds
Started Jun 11 12:29:49 PM PDT 24
Finished Jun 11 12:30:24 PM PDT 24
Peak memory 200256 kb
Host smart-8167a54d-c751-4a7f-bf31-6179131981ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942968464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.942968464
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.633834652
Short name T8
Test name
Test status
Simulation time 52622547087 ps
CPU time 78.1 seconds
Started Jun 11 12:29:38 PM PDT 24
Finished Jun 11 12:30:59 PM PDT 24
Peak memory 200372 kb
Host smart-fadae055-ecc1-4101-9545-e2f38b587852
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633834652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.633834652
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.3973191298
Short name T724
Test name
Test status
Simulation time 127822832753 ps
CPU time 708.84 seconds
Started Jun 11 12:29:40 PM PDT 24
Finished Jun 11 12:41:32 PM PDT 24
Peak memory 200204 kb
Host smart-a5aa4c82-a258-4093-a186-09d476d1ed12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3973191298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.3973191298
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.2033363998
Short name T392
Test name
Test status
Simulation time 7571428881 ps
CPU time 12.2 seconds
Started Jun 11 12:29:57 PM PDT 24
Finished Jun 11 12:30:11 PM PDT 24
Peak memory 200156 kb
Host smart-1581416d-2126-4981-8c1f-ea473b5962a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033363998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.2033363998
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_perf.3756509803
Short name T817
Test name
Test status
Simulation time 11980730440 ps
CPU time 675.19 seconds
Started Jun 11 12:29:57 PM PDT 24
Finished Jun 11 12:41:14 PM PDT 24
Peak memory 200276 kb
Host smart-7445bd94-1434-4414-b9a2-0651060e43b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3756509803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.3756509803
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.2014732679
Short name T707
Test name
Test status
Simulation time 7167754061 ps
CPU time 8.62 seconds
Started Jun 11 12:29:50 PM PDT 24
Finished Jun 11 12:30:01 PM PDT 24
Peak memory 198532 kb
Host smart-5b4b4b5f-0f14-468d-84ae-09418fc09615
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2014732679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.2014732679
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.2641184353
Short name T305
Test name
Test status
Simulation time 19781473543 ps
CPU time 35.76 seconds
Started Jun 11 12:29:43 PM PDT 24
Finished Jun 11 12:30:21 PM PDT 24
Peak memory 200228 kb
Host smart-f3a89297-b89e-4863-b840-b191e89d8a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641184353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.2641184353
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.4237352854
Short name T462
Test name
Test status
Simulation time 40877147096 ps
CPU time 62.67 seconds
Started Jun 11 12:29:38 PM PDT 24
Finished Jun 11 12:30:43 PM PDT 24
Peak memory 196320 kb
Host smart-3f5824e5-606a-4400-a054-2c7376ea0cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237352854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.4237352854
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.2218475153
Short name T80
Test name
Test status
Simulation time 485645831 ps
CPU time 1.3 seconds
Started Jun 11 12:29:37 PM PDT 24
Finished Jun 11 12:29:40 PM PDT 24
Peak memory 200128 kb
Host smart-35bef664-dfb8-4cd9-a853-0178490222d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218475153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.2218475153
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.4008764457
Short name T934
Test name
Test status
Simulation time 543568801089 ps
CPU time 1104.56 seconds
Started Jun 11 12:29:40 PM PDT 24
Finished Jun 11 12:48:09 PM PDT 24
Peak memory 225124 kb
Host smart-5e3e6fef-1fa5-47ab-813e-3e6430b446ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008764457 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.4008764457
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.3814846645
Short name T547
Test name
Test status
Simulation time 6291942113 ps
CPU time 1.58 seconds
Started Jun 11 12:29:37 PM PDT 24
Finished Jun 11 12:29:40 PM PDT 24
Peak memory 199352 kb
Host smart-4e1cb0d6-1cc0-43ca-878d-ccf280f145f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814846645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.3814846645
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.3831297503
Short name T456
Test name
Test status
Simulation time 69563070703 ps
CPU time 16.96 seconds
Started Jun 11 12:29:51 PM PDT 24
Finished Jun 11 12:30:11 PM PDT 24
Peak memory 200348 kb
Host smart-420910fc-a763-45c9-a032-e83245a31c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831297503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.3831297503
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.1659879909
Short name T232
Test name
Test status
Simulation time 5585891163 ps
CPU time 29.6 seconds
Started Jun 11 12:32:10 PM PDT 24
Finished Jun 11 12:32:40 PM PDT 24
Peak memory 200192 kb
Host smart-c52dea7a-22c7-4872-9515-32049821909e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659879909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.1659879909
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.2121223127
Short name T514
Test name
Test status
Simulation time 136617866055 ps
CPU time 52.89 seconds
Started Jun 11 12:32:10 PM PDT 24
Finished Jun 11 12:33:04 PM PDT 24
Peak memory 199972 kb
Host smart-fa430980-db7f-4641-8431-1b5899e75645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121223127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.2121223127
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.1160369878
Short name T155
Test name
Test status
Simulation time 44415475091 ps
CPU time 37.3 seconds
Started Jun 11 12:32:06 PM PDT 24
Finished Jun 11 12:32:45 PM PDT 24
Peak memory 200132 kb
Host smart-88937aeb-29b2-4a08-a4f9-4b9f02505bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160369878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.1160369878
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.1095787245
Short name T937
Test name
Test status
Simulation time 21565421630 ps
CPU time 37.4 seconds
Started Jun 11 12:32:06 PM PDT 24
Finished Jun 11 12:32:44 PM PDT 24
Peak memory 200368 kb
Host smart-81bf3ef5-e407-4ba8-accf-004829546e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095787245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.1095787245
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.2128112021
Short name T304
Test name
Test status
Simulation time 27725456966 ps
CPU time 24.29 seconds
Started Jun 11 12:32:07 PM PDT 24
Finished Jun 11 12:32:33 PM PDT 24
Peak memory 200344 kb
Host smart-c77174cf-0a7e-46b8-b704-e7bf4ee3aa56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128112021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.2128112021
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.1095559033
Short name T14
Test name
Test status
Simulation time 137746933642 ps
CPU time 44.8 seconds
Started Jun 11 12:32:09 PM PDT 24
Finished Jun 11 12:32:54 PM PDT 24
Peak memory 200276 kb
Host smart-1c1b792d-75d6-46d1-96ba-a92ed48f27dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095559033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.1095559033
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.3864197993
Short name T264
Test name
Test status
Simulation time 116118953283 ps
CPU time 36.36 seconds
Started Jun 11 12:32:08 PM PDT 24
Finished Jun 11 12:32:45 PM PDT 24
Peak memory 200192 kb
Host smart-21ff2678-b7ae-4648-9484-346ee33f350d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864197993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.3864197993
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.2107735301
Short name T21
Test name
Test status
Simulation time 11124191 ps
CPU time 0.56 seconds
Started Jun 11 12:29:50 PM PDT 24
Finished Jun 11 12:29:53 PM PDT 24
Peak memory 195676 kb
Host smart-5c9c6f59-8c2f-4273-af68-eab59f806ad1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107735301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.2107735301
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.2134188159
Short name T862
Test name
Test status
Simulation time 88512990489 ps
CPU time 146.02 seconds
Started Jun 11 12:29:43 PM PDT 24
Finished Jun 11 12:32:12 PM PDT 24
Peak memory 200220 kb
Host smart-46e09923-cab8-4314-a10e-14deb6591035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134188159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.2134188159
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.3910518521
Short name T130
Test name
Test status
Simulation time 45427254763 ps
CPU time 31.34 seconds
Started Jun 11 12:29:52 PM PDT 24
Finished Jun 11 12:30:26 PM PDT 24
Peak memory 200228 kb
Host smart-282faa00-28f6-4de8-94d6-d2c0b0b9bf7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910518521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.3910518521
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_intr.3575742467
Short name T93
Test name
Test status
Simulation time 118401593468 ps
CPU time 51.83 seconds
Started Jun 11 12:29:41 PM PDT 24
Finished Jun 11 12:30:36 PM PDT 24
Peak memory 198020 kb
Host smart-e78faff7-c16e-4de5-8c0e-120b4a7f1c9e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575742467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.3575742467
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.222266920
Short name T648
Test name
Test status
Simulation time 83590092287 ps
CPU time 141.12 seconds
Started Jun 11 12:29:39 PM PDT 24
Finished Jun 11 12:32:04 PM PDT 24
Peak memory 200032 kb
Host smart-9fc78f44-f537-4ac2-af57-b96fd3ca8413
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=222266920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.222266920
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.2960049531
Short name T787
Test name
Test status
Simulation time 7198110378 ps
CPU time 5.55 seconds
Started Jun 11 12:29:42 PM PDT 24
Finished Jun 11 12:29:50 PM PDT 24
Peak memory 199944 kb
Host smart-0f50f5af-e072-4c56-ab34-f859c0eda49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960049531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.2960049531
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_perf.4234131680
Short name T656
Test name
Test status
Simulation time 23576858149 ps
CPU time 387.08 seconds
Started Jun 11 12:29:37 PM PDT 24
Finished Jun 11 12:36:06 PM PDT 24
Peak memory 200340 kb
Host smart-c9f45e30-77ed-4cf0-af51-5d9a5e23a33d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4234131680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.4234131680
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.1787748172
Short name T966
Test name
Test status
Simulation time 4526289310 ps
CPU time 18.39 seconds
Started Jun 11 12:30:16 PM PDT 24
Finished Jun 11 12:30:38 PM PDT 24
Peak memory 198824 kb
Host smart-8b8ff712-bf1c-4f8a-9974-53cca48e86fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1787748172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.1787748172
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.2597497575
Short name T901
Test name
Test status
Simulation time 18831615102 ps
CPU time 15.61 seconds
Started Jun 11 12:29:44 PM PDT 24
Finished Jun 11 12:30:02 PM PDT 24
Peak memory 200348 kb
Host smart-5c811636-4583-4102-a005-fcd06212e924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597497575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.2597497575
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.3624960357
Short name T585
Test name
Test status
Simulation time 4305973287 ps
CPU time 2.27 seconds
Started Jun 11 12:30:07 PM PDT 24
Finished Jun 11 12:30:12 PM PDT 24
Peak memory 196332 kb
Host smart-af3c2e92-0a7b-439c-85a1-7b75b023ee75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624960357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.3624960357
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.27688393
Short name T442
Test name
Test status
Simulation time 428989309 ps
CPU time 1.88 seconds
Started Jun 11 12:29:57 PM PDT 24
Finished Jun 11 12:30:00 PM PDT 24
Peak memory 199068 kb
Host smart-f7fa7ae4-8e17-45bc-9c1b-788ece984b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27688393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.27688393
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.2081691934
Short name T1064
Test name
Test status
Simulation time 272241076042 ps
CPU time 111.56 seconds
Started Jun 11 12:29:48 PM PDT 24
Finished Jun 11 12:31:42 PM PDT 24
Peak memory 200280 kb
Host smart-265d1988-6ad6-43a8-bf04-e3fe92c4ce4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081691934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.2081691934
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.787444541
Short name T101
Test name
Test status
Simulation time 49154943034 ps
CPU time 345.47 seconds
Started Jun 11 12:29:49 PM PDT 24
Finished Jun 11 12:35:37 PM PDT 24
Peak memory 216912 kb
Host smart-a8b5a269-4748-4f73-8cd2-44fb39599275
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787444541 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.787444541
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.2321583927
Short name T390
Test name
Test status
Simulation time 1741957722 ps
CPU time 1.55 seconds
Started Jun 11 12:30:11 PM PDT 24
Finished Jun 11 12:30:15 PM PDT 24
Peak memory 198788 kb
Host smart-72f8f2ec-1005-409d-ad36-623827c1e668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321583927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.2321583927
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.2307157841
Short name T586
Test name
Test status
Simulation time 86997387529 ps
CPU time 230.38 seconds
Started Jun 11 12:29:51 PM PDT 24
Finished Jun 11 12:33:44 PM PDT 24
Peak memory 200248 kb
Host smart-f734c8ad-2475-4cd1-acad-e439cf2a6813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307157841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.2307157841
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.242415427
Short name T128
Test name
Test status
Simulation time 20418036824 ps
CPU time 37.02 seconds
Started Jun 11 12:32:06 PM PDT 24
Finished Jun 11 12:32:44 PM PDT 24
Peak memory 200224 kb
Host smart-c860f062-46d5-4e70-bed4-ead42a62473d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242415427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.242415427
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.3428012603
Short name T825
Test name
Test status
Simulation time 19459604673 ps
CPU time 23.14 seconds
Started Jun 11 12:32:05 PM PDT 24
Finished Jun 11 12:32:29 PM PDT 24
Peak memory 200264 kb
Host smart-a810b6f2-283e-478b-9d3d-3222336decea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428012603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.3428012603
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.149504776
Short name T118
Test name
Test status
Simulation time 63810247504 ps
CPU time 23.44 seconds
Started Jun 11 12:32:09 PM PDT 24
Finished Jun 11 12:32:33 PM PDT 24
Peak memory 200192 kb
Host smart-a0ff094c-fb7b-4a57-9132-e709fe6d155f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149504776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.149504776
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.118617758
Short name T203
Test name
Test status
Simulation time 140952519839 ps
CPU time 204.43 seconds
Started Jun 11 12:32:07 PM PDT 24
Finished Jun 11 12:35:33 PM PDT 24
Peak memory 200212 kb
Host smart-6b3225c8-62e9-496a-9f01-de8ca288b7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118617758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.118617758
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.1272854696
Short name T208
Test name
Test status
Simulation time 56935378166 ps
CPU time 104.18 seconds
Started Jun 11 12:32:07 PM PDT 24
Finished Jun 11 12:33:52 PM PDT 24
Peak memory 200264 kb
Host smart-d1a9e9c7-d918-401f-aa37-fff9fe2f333a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272854696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.1272854696
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.2620868939
Short name T612
Test name
Test status
Simulation time 138581934995 ps
CPU time 191.33 seconds
Started Jun 11 12:32:14 PM PDT 24
Finished Jun 11 12:35:26 PM PDT 24
Peak memory 200104 kb
Host smart-f3a3b1fa-c805-4f60-964a-36673c57695c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620868939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.2620868939
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.3928378179
Short name T995
Test name
Test status
Simulation time 77626930098 ps
CPU time 34.69 seconds
Started Jun 11 12:32:14 PM PDT 24
Finished Jun 11 12:32:49 PM PDT 24
Peak memory 200332 kb
Host smart-f9588f40-b366-4bbe-a596-fc3eaf685d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928378179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.3928378179
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.2967981821
Short name T687
Test name
Test status
Simulation time 90299906168 ps
CPU time 122.52 seconds
Started Jun 11 12:32:05 PM PDT 24
Finished Jun 11 12:34:09 PM PDT 24
Peak memory 200208 kb
Host smart-8c1a27e4-03c1-4715-b7db-384db3ee946f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967981821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.2967981821
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.2293724290
Short name T667
Test name
Test status
Simulation time 176378800709 ps
CPU time 87.48 seconds
Started Jun 11 12:32:06 PM PDT 24
Finished Jun 11 12:33:34 PM PDT 24
Peak memory 200292 kb
Host smart-e4dc2d85-759f-46b6-af08-51f807dd1afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293724290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.2293724290
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.2993039391
Short name T863
Test name
Test status
Simulation time 20396498 ps
CPU time 0.62 seconds
Started Jun 11 12:30:02 PM PDT 24
Finished Jun 11 12:30:05 PM PDT 24
Peak memory 195604 kb
Host smart-66fa0617-cd79-41ae-b3db-ddd33808b2b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993039391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.2993039391
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.3088919292
Short name T495
Test name
Test status
Simulation time 65304539480 ps
CPU time 46.06 seconds
Started Jun 11 12:29:43 PM PDT 24
Finished Jun 11 12:30:32 PM PDT 24
Peak memory 200316 kb
Host smart-cef2fa7a-bc26-43a7-92ab-3e74451f7e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088919292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.3088919292
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.3631378519
Short name T688
Test name
Test status
Simulation time 22619359093 ps
CPU time 11.75 seconds
Started Jun 11 12:29:39 PM PDT 24
Finished Jun 11 12:29:54 PM PDT 24
Peak memory 200156 kb
Host smart-ab9ec6f1-90bc-45a4-ac0e-088cb3eb7e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631378519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.3631378519
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.738262448
Short name T165
Test name
Test status
Simulation time 13001075059 ps
CPU time 22.76 seconds
Started Jun 11 12:29:51 PM PDT 24
Finished Jun 11 12:30:17 PM PDT 24
Peak memory 200116 kb
Host smart-7add46a8-e462-460d-a916-4b0001119468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738262448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.738262448
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.3877033600
Short name T870
Test name
Test status
Simulation time 22358788517 ps
CPU time 11.2 seconds
Started Jun 11 12:29:47 PM PDT 24
Finished Jun 11 12:30:01 PM PDT 24
Peak memory 200064 kb
Host smart-e553aaa4-5f58-4070-9dc9-81a568659e60
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877033600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.3877033600
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.4206195605
Short name T837
Test name
Test status
Simulation time 60679602903 ps
CPU time 512.31 seconds
Started Jun 11 12:30:09 PM PDT 24
Finished Jun 11 12:38:44 PM PDT 24
Peak memory 200324 kb
Host smart-80de18d2-8798-4591-8b61-5b60a9695d9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4206195605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.4206195605
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.3869659864
Short name T504
Test name
Test status
Simulation time 2600606962 ps
CPU time 1.51 seconds
Started Jun 11 12:30:00 PM PDT 24
Finished Jun 11 12:30:03 PM PDT 24
Peak memory 198328 kb
Host smart-70b67929-791c-466f-b0f4-08d101bd9863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869659864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.3869659864
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_perf.2029300996
Short name T356
Test name
Test status
Simulation time 4163992486 ps
CPU time 235.19 seconds
Started Jun 11 12:29:53 PM PDT 24
Finished Jun 11 12:33:50 PM PDT 24
Peak memory 200208 kb
Host smart-25940006-c601-4183-890c-0be1377dec89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2029300996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.2029300996
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.1565403280
Short name T987
Test name
Test status
Simulation time 1899488636 ps
CPU time 8.83 seconds
Started Jun 11 12:29:41 PM PDT 24
Finished Jun 11 12:29:53 PM PDT 24
Peak memory 198228 kb
Host smart-833575cd-ecaf-410d-b36d-8e43b75efe52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1565403280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.1565403280
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.954281866
Short name T621
Test name
Test status
Simulation time 116524697345 ps
CPU time 46.59 seconds
Started Jun 11 12:29:57 PM PDT 24
Finished Jun 11 12:30:45 PM PDT 24
Peak memory 200272 kb
Host smart-83b8930b-4b5b-413d-a39f-5a907251c40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954281866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.954281866
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.4294726008
Short name T276
Test name
Test status
Simulation time 50140955811 ps
CPU time 36.75 seconds
Started Jun 11 12:30:11 PM PDT 24
Finished Jun 11 12:30:51 PM PDT 24
Peak memory 195964 kb
Host smart-07733178-19ce-47d0-a06a-0145ff8b179b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294726008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.4294726008
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.3994894668
Short name T851
Test name
Test status
Simulation time 141787484 ps
CPU time 0.81 seconds
Started Jun 11 12:29:50 PM PDT 24
Finished Jun 11 12:29:54 PM PDT 24
Peak memory 198332 kb
Host smart-ef3be392-9c8a-4100-ad86-618d4fb5d079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994894668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.3994894668
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.3360793555
Short name T560
Test name
Test status
Simulation time 547492259 ps
CPU time 1.84 seconds
Started Jun 11 12:29:52 PM PDT 24
Finished Jun 11 12:29:56 PM PDT 24
Peak memory 198992 kb
Host smart-03a9d64e-d9e8-40a6-86b2-eb895f9d2451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360793555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.3360793555
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.3627244434
Short name T941
Test name
Test status
Simulation time 93948140505 ps
CPU time 38.54 seconds
Started Jun 11 12:29:38 PM PDT 24
Finished Jun 11 12:30:19 PM PDT 24
Peak memory 200260 kb
Host smart-bd48f909-72b7-4f72-9007-9ebf15b2780b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627244434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.3627244434
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.1126268577
Short name T338
Test name
Test status
Simulation time 69740739725 ps
CPU time 146.18 seconds
Started Jun 11 12:32:13 PM PDT 24
Finished Jun 11 12:34:40 PM PDT 24
Peak memory 200332 kb
Host smart-4c89e234-ecb7-4bcf-8e1c-f868b68f2d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126268577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.1126268577
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.143485472
Short name T188
Test name
Test status
Simulation time 99094267156 ps
CPU time 35.54 seconds
Started Jun 11 12:32:05 PM PDT 24
Finished Jun 11 12:32:42 PM PDT 24
Peak memory 199992 kb
Host smart-08d3b01b-7610-4fc1-b94d-8501b460b6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143485472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.143485472
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.3634830240
Short name T256
Test name
Test status
Simulation time 41966706577 ps
CPU time 411.76 seconds
Started Jun 11 12:32:06 PM PDT 24
Finished Jun 11 12:39:00 PM PDT 24
Peak memory 200280 kb
Host smart-612d57c2-11c1-46cf-b722-01c1dd66d4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634830240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.3634830240
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.3764105241
Short name T670
Test name
Test status
Simulation time 25954822623 ps
CPU time 43.88 seconds
Started Jun 11 12:32:05 PM PDT 24
Finished Jun 11 12:32:50 PM PDT 24
Peak memory 200180 kb
Host smart-65770530-f2f4-4da2-a4d6-22be4e62710b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764105241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.3764105241
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.2951543962
Short name T859
Test name
Test status
Simulation time 19621607736 ps
CPU time 44.48 seconds
Started Jun 11 12:32:10 PM PDT 24
Finished Jun 11 12:32:55 PM PDT 24
Peak memory 200256 kb
Host smart-f53675c5-ff5a-4f01-9742-500cbe08f996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951543962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.2951543962
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.1601233778
Short name T246
Test name
Test status
Simulation time 26495313653 ps
CPU time 12.54 seconds
Started Jun 11 12:32:10 PM PDT 24
Finished Jun 11 12:32:24 PM PDT 24
Peak memory 200360 kb
Host smart-720772b0-33ba-4883-8133-a8c910bef99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601233778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.1601233778
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.2318744981
Short name T271
Test name
Test status
Simulation time 157313780400 ps
CPU time 515.91 seconds
Started Jun 11 12:32:07 PM PDT 24
Finished Jun 11 12:40:44 PM PDT 24
Peak memory 200212 kb
Host smart-59a2617f-87c9-43d0-9f27-4eae51fc4dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318744981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.2318744981
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.268560019
Short name T1033
Test name
Test status
Simulation time 78076369604 ps
CPU time 9.14 seconds
Started Jun 11 12:32:06 PM PDT 24
Finished Jun 11 12:32:16 PM PDT 24
Peak memory 199956 kb
Host smart-efa96ded-edf1-486f-9588-6bb28df5c55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268560019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.268560019
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.1040998195
Short name T204
Test name
Test status
Simulation time 133819212305 ps
CPU time 58.3 seconds
Started Jun 11 12:32:07 PM PDT 24
Finished Jun 11 12:33:07 PM PDT 24
Peak memory 200152 kb
Host smart-5f60d9f9-ad0f-4d63-a5d0-919548ba42fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040998195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.1040998195
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.4055424475
Short name T575
Test name
Test status
Simulation time 148400959 ps
CPU time 0.56 seconds
Started Jun 11 12:29:52 PM PDT 24
Finished Jun 11 12:29:55 PM PDT 24
Peak memory 195032 kb
Host smart-1f011f2f-6e0a-4ee5-8820-856fa5889c4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055424475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.4055424475
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.2852012730
Short name T1011
Test name
Test status
Simulation time 35233755953 ps
CPU time 15.06 seconds
Started Jun 11 12:30:12 PM PDT 24
Finished Jun 11 12:30:29 PM PDT 24
Peak memory 200212 kb
Host smart-c1eece1d-0266-4c7d-bf40-7fc924f943c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852012730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.2852012730
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.1241045632
Short name T951
Test name
Test status
Simulation time 117160249528 ps
CPU time 49 seconds
Started Jun 11 12:29:49 PM PDT 24
Finished Jun 11 12:30:40 PM PDT 24
Peak memory 200252 kb
Host smart-186b60cc-dd49-46a0-8c4f-517a46c99a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241045632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.1241045632
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.2500935434
Short name T184
Test name
Test status
Simulation time 19738159291 ps
CPU time 19.64 seconds
Started Jun 11 12:30:10 PM PDT 24
Finished Jun 11 12:30:32 PM PDT 24
Peak memory 200204 kb
Host smart-a27b57f5-1be6-4941-af4c-e5ae03447e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500935434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.2500935434
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.1717501895
Short name T737
Test name
Test status
Simulation time 50674201445 ps
CPU time 51.04 seconds
Started Jun 11 12:29:49 PM PDT 24
Finished Jun 11 12:30:43 PM PDT 24
Peak memory 200312 kb
Host smart-da41713f-24d0-4243-8356-18ad6ee2ee9f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717501895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.1717501895
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.2950390954
Short name T1039
Test name
Test status
Simulation time 320649233870 ps
CPU time 186.56 seconds
Started Jun 11 12:30:10 PM PDT 24
Finished Jun 11 12:33:19 PM PDT 24
Peak memory 200052 kb
Host smart-78d48179-f79a-45db-b37c-74edf7c0ba63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2950390954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.2950390954
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.3684450959
Short name T492
Test name
Test status
Simulation time 4757506323 ps
CPU time 4.84 seconds
Started Jun 11 12:29:50 PM PDT 24
Finished Jun 11 12:29:58 PM PDT 24
Peak memory 198940 kb
Host smart-741cc195-0859-4d2b-ac53-a37c41cd5749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684450959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.3684450959
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_perf.3320855330
Short name T793
Test name
Test status
Simulation time 10671144854 ps
CPU time 283.79 seconds
Started Jun 11 12:30:05 PM PDT 24
Finished Jun 11 12:34:51 PM PDT 24
Peak memory 200220 kb
Host smart-38ad0f28-afd9-4dac-87a1-a2a28ddc9887
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3320855330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.3320855330
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.2404336918
Short name T796
Test name
Test status
Simulation time 4406786324 ps
CPU time 2.93 seconds
Started Jun 11 12:30:02 PM PDT 24
Finished Jun 11 12:30:07 PM PDT 24
Peak memory 198676 kb
Host smart-d02173a5-748f-40e9-9d7e-c31019e0bcf3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2404336918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.2404336918
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.2233543596
Short name T160
Test name
Test status
Simulation time 78049635311 ps
CPU time 34.02 seconds
Started Jun 11 12:30:10 PM PDT 24
Finished Jun 11 12:30:47 PM PDT 24
Peak memory 200224 kb
Host smart-79d0e014-4361-4d62-a4c6-60a83d810f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233543596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.2233543596
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.3463299077
Short name T478
Test name
Test status
Simulation time 40891134430 ps
CPU time 27.17 seconds
Started Jun 11 12:29:51 PM PDT 24
Finished Jun 11 12:30:21 PM PDT 24
Peak memory 196008 kb
Host smart-cc025be1-4cff-4e69-b767-c5cc2fe4f7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463299077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.3463299077
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.2880128221
Short name T745
Test name
Test status
Simulation time 5904393036 ps
CPU time 11.25 seconds
Started Jun 11 12:30:09 PM PDT 24
Finished Jun 11 12:30:23 PM PDT 24
Peak memory 200332 kb
Host smart-22fc1de9-ecc3-4ddc-b3e2-a0266690b63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880128221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.2880128221
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.2075680915
Short name T154
Test name
Test status
Simulation time 227577983901 ps
CPU time 101.55 seconds
Started Jun 11 12:29:53 PM PDT 24
Finished Jun 11 12:31:37 PM PDT 24
Peak memory 200260 kb
Host smart-5e5cebe8-5b9d-47a5-a64d-6ffdf76db635
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075680915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.2075680915
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.4033899232
Short name T651
Test name
Test status
Simulation time 19334946616 ps
CPU time 233.23 seconds
Started Jun 11 12:29:50 PM PDT 24
Finished Jun 11 12:33:45 PM PDT 24
Peak memory 216788 kb
Host smart-c79cf5f9-c40b-43fe-b4c2-586dbad01606
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033899232 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.4033899232
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.641131211
Short name T565
Test name
Test status
Simulation time 1970548909 ps
CPU time 2.19 seconds
Started Jun 11 12:29:50 PM PDT 24
Finished Jun 11 12:29:55 PM PDT 24
Peak memory 199120 kb
Host smart-44e08b9e-30e0-42dc-b44c-dca28eaa1de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641131211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.641131211
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.2388982744
Short name T377
Test name
Test status
Simulation time 9706752947 ps
CPU time 14.78 seconds
Started Jun 11 12:30:05 PM PDT 24
Finished Jun 11 12:30:21 PM PDT 24
Peak memory 200220 kb
Host smart-20567443-562e-4ed9-8cbb-7031c2f45046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388982744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.2388982744
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.1455965946
Short name T552
Test name
Test status
Simulation time 9258817288 ps
CPU time 17.07 seconds
Started Jun 11 12:32:16 PM PDT 24
Finished Jun 11 12:32:36 PM PDT 24
Peak memory 200260 kb
Host smart-012eb3e1-8693-44e3-bf23-4d1b49f92f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455965946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.1455965946
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.2079226128
Short name T1055
Test name
Test status
Simulation time 57730206129 ps
CPU time 45.83 seconds
Started Jun 11 12:32:16 PM PDT 24
Finished Jun 11 12:33:04 PM PDT 24
Peak memory 200324 kb
Host smart-a0c3371e-0592-492d-be50-2b6e987cde31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079226128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.2079226128
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.4068970385
Short name T953
Test name
Test status
Simulation time 138924232480 ps
CPU time 78.68 seconds
Started Jun 11 12:32:18 PM PDT 24
Finished Jun 11 12:33:40 PM PDT 24
Peak memory 200252 kb
Host smart-340bfc98-a916-4e7d-b264-fd185220c83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068970385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.4068970385
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.283268029
Short name T935
Test name
Test status
Simulation time 142007789961 ps
CPU time 27.87 seconds
Started Jun 11 12:32:17 PM PDT 24
Finished Jun 11 12:32:47 PM PDT 24
Peak memory 200204 kb
Host smart-d35dafb9-4163-46e2-8a4b-e84d2d4f6a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283268029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.283268029
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.318769246
Short name T919
Test name
Test status
Simulation time 39349249726 ps
CPU time 20.25 seconds
Started Jun 11 12:32:28 PM PDT 24
Finished Jun 11 12:32:50 PM PDT 24
Peak memory 200236 kb
Host smart-d8a8a2c2-94e8-4737-b9b7-2c135fde9160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318769246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.318769246
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.2018818559
Short name T677
Test name
Test status
Simulation time 31588999827 ps
CPU time 45.11 seconds
Started Jun 11 12:32:19 PM PDT 24
Finished Jun 11 12:33:06 PM PDT 24
Peak memory 200272 kb
Host smart-e2f40539-2120-41a2-b9d2-1495e0ac2a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018818559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.2018818559
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.3742500474
Short name T662
Test name
Test status
Simulation time 92821132897 ps
CPU time 25.94 seconds
Started Jun 11 12:32:17 PM PDT 24
Finished Jun 11 12:32:45 PM PDT 24
Peak memory 200312 kb
Host smart-34f5f2c1-a280-47e4-ac63-767cf407d1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742500474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.3742500474
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.1781270129
Short name T296
Test name
Test status
Simulation time 143552505980 ps
CPU time 100.91 seconds
Started Jun 11 12:32:16 PM PDT 24
Finished Jun 11 12:33:59 PM PDT 24
Peak memory 200228 kb
Host smart-e03c9d5e-3893-4fe3-9584-9e983da92bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781270129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.1781270129
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.2979987056
Short name T164
Test name
Test status
Simulation time 170444129151 ps
CPU time 299.57 seconds
Started Jun 11 12:32:18 PM PDT 24
Finished Jun 11 12:37:20 PM PDT 24
Peak memory 200176 kb
Host smart-aed0c802-8e00-4d88-8d30-5b0e8a0d529d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979987056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.2979987056
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.1835177449
Short name T515
Test name
Test status
Simulation time 281754050825 ps
CPU time 149.72 seconds
Started Jun 11 12:32:16 PM PDT 24
Finished Jun 11 12:34:48 PM PDT 24
Peak memory 200296 kb
Host smart-4a6404ec-9325-4eb0-a66d-8c975bd97ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835177449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.1835177449
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.745398881
Short name T1100
Test name
Test status
Simulation time 40298743 ps
CPU time 0.53 seconds
Started Jun 11 12:29:51 PM PDT 24
Finished Jun 11 12:29:54 PM PDT 24
Peak memory 195736 kb
Host smart-093db49c-5b67-4a32-872f-53a43abaa016
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745398881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.745398881
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.812156244
Short name T530
Test name
Test status
Simulation time 73489597331 ps
CPU time 110.81 seconds
Started Jun 11 12:29:49 PM PDT 24
Finished Jun 11 12:31:42 PM PDT 24
Peak memory 200296 kb
Host smart-fdc0d1f0-eff6-417d-9633-adb1491bc980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812156244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.812156244
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.3989444797
Short name T731
Test name
Test status
Simulation time 84167612743 ps
CPU time 41.07 seconds
Started Jun 11 12:29:53 PM PDT 24
Finished Jun 11 12:30:36 PM PDT 24
Peak memory 200324 kb
Host smart-ef36ba86-d6c3-4cf4-82ec-ad310468644e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989444797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.3989444797
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.1235632846
Short name T497
Test name
Test status
Simulation time 74514617034 ps
CPU time 9.13 seconds
Started Jun 11 12:30:14 PM PDT 24
Finished Jun 11 12:30:26 PM PDT 24
Peak memory 200296 kb
Host smart-dab39e8f-2a6c-4a1d-9975-e6b1fe205fce
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235632846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.1235632846
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.77396729
Short name T400
Test name
Test status
Simulation time 119430308046 ps
CPU time 461.52 seconds
Started Jun 11 12:30:02 PM PDT 24
Finished Jun 11 12:37:46 PM PDT 24
Peak memory 200308 kb
Host smart-a989c03a-1837-4184-bcb7-b6ed6a33efce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=77396729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.77396729
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.3090892141
Short name T439
Test name
Test status
Simulation time 3794644525 ps
CPU time 2.46 seconds
Started Jun 11 12:29:52 PM PDT 24
Finished Jun 11 12:29:57 PM PDT 24
Peak memory 196784 kb
Host smart-1aaf0cfa-3bae-4547-ad03-28cd23a8c641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090892141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.3090892141
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_perf.1346549189
Short name T1001
Test name
Test status
Simulation time 10810598022 ps
CPU time 485.93 seconds
Started Jun 11 12:29:51 PM PDT 24
Finished Jun 11 12:37:59 PM PDT 24
Peak memory 200228 kb
Host smart-4b2626cd-5c0f-4973-937c-fbe4cc0528c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1346549189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.1346549189
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.1885690953
Short name T703
Test name
Test status
Simulation time 2825714139 ps
CPU time 4.17 seconds
Started Jun 11 12:29:53 PM PDT 24
Finished Jun 11 12:29:59 PM PDT 24
Peak memory 200148 kb
Host smart-e45c4155-60d3-4cfa-af9a-3fda6dd156fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1885690953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.1885690953
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.3040198509
Short name T115
Test name
Test status
Simulation time 151692917507 ps
CPU time 126 seconds
Started Jun 11 12:30:01 PM PDT 24
Finished Jun 11 12:32:09 PM PDT 24
Peak memory 200308 kb
Host smart-7d9922b3-228d-4dba-ad59-74ae2fe78bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040198509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.3040198509
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.1209966575
Short name T437
Test name
Test status
Simulation time 3564713629 ps
CPU time 1.74 seconds
Started Jun 11 12:29:49 PM PDT 24
Finished Jun 11 12:29:53 PM PDT 24
Peak memory 196544 kb
Host smart-c396f5a7-d778-42e1-902a-5d26dd8b8111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209966575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.1209966575
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.4102531356
Short name T491
Test name
Test status
Simulation time 851721258 ps
CPU time 2 seconds
Started Jun 11 12:29:53 PM PDT 24
Finished Jun 11 12:29:57 PM PDT 24
Peak memory 199872 kb
Host smart-9b2d8703-affa-4029-a0a1-6b18cfcc1ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102531356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.4102531356
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.3773187148
Short name T813
Test name
Test status
Simulation time 306303046065 ps
CPU time 554.42 seconds
Started Jun 11 12:30:04 PM PDT 24
Finished Jun 11 12:39:20 PM PDT 24
Peak memory 200324 kb
Host smart-f57adbb5-0110-4eb1-9e56-d47245d9c8a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773187148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.3773187148
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.4060145837
Short name T702
Test name
Test status
Simulation time 2019794763 ps
CPU time 2.11 seconds
Started Jun 11 12:30:04 PM PDT 24
Finished Jun 11 12:30:07 PM PDT 24
Peak memory 199040 kb
Host smart-70359f0b-af70-4a0c-ac43-f3046e603a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060145837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.4060145837
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.400576258
Short name T595
Test name
Test status
Simulation time 304614869267 ps
CPU time 49.94 seconds
Started Jun 11 12:29:51 PM PDT 24
Finished Jun 11 12:30:43 PM PDT 24
Peak memory 200292 kb
Host smart-d336b96b-b8cf-4c3e-9de9-25a34a96839d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400576258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.400576258
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.839253365
Short name T1031
Test name
Test status
Simulation time 73375086391 ps
CPU time 30.44 seconds
Started Jun 11 12:32:29 PM PDT 24
Finished Jun 11 12:33:01 PM PDT 24
Peak memory 200300 kb
Host smart-27a354db-9949-4201-b2eb-8283d3883024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839253365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.839253365
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.912148237
Short name T133
Test name
Test status
Simulation time 46470315365 ps
CPU time 19.09 seconds
Started Jun 11 12:32:18 PM PDT 24
Finished Jun 11 12:32:39 PM PDT 24
Peak memory 200308 kb
Host smart-357ba1d2-9946-4744-b87d-380a9b925673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912148237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.912148237
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.3193559044
Short name T322
Test name
Test status
Simulation time 57749735748 ps
CPU time 92.68 seconds
Started Jun 11 12:32:29 PM PDT 24
Finished Jun 11 12:34:03 PM PDT 24
Peak memory 199960 kb
Host smart-61361d4f-bb1d-4487-8ed2-1cfe138f186a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193559044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.3193559044
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.3846074915
Short name T207
Test name
Test status
Simulation time 58152810721 ps
CPU time 95.97 seconds
Started Jun 11 12:32:19 PM PDT 24
Finished Jun 11 12:33:57 PM PDT 24
Peak memory 200284 kb
Host smart-e8d0c9ec-f298-440c-9028-d2a4e66bbef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846074915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.3846074915
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.2397409024
Short name T162
Test name
Test status
Simulation time 195759427883 ps
CPU time 52.59 seconds
Started Jun 11 12:32:29 PM PDT 24
Finished Jun 11 12:33:23 PM PDT 24
Peak memory 200336 kb
Host smart-0a54ed25-d428-4ce8-b861-56c677751c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397409024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.2397409024
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.3417609329
Short name T678
Test name
Test status
Simulation time 42627628636 ps
CPU time 24.64 seconds
Started Jun 11 12:32:17 PM PDT 24
Finished Jun 11 12:32:43 PM PDT 24
Peak memory 200208 kb
Host smart-4e060a51-ed88-41e6-917c-9974245957aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417609329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.3417609329
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.1196887211
Short name T415
Test name
Test status
Simulation time 102765277275 ps
CPU time 19.32 seconds
Started Jun 11 12:32:17 PM PDT 24
Finished Jun 11 12:32:39 PM PDT 24
Peak memory 200296 kb
Host smart-8a90b3ae-ba58-4ee3-8cf7-58b87909d9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196887211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.1196887211
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.464447285
Short name T733
Test name
Test status
Simulation time 16775772908 ps
CPU time 34.17 seconds
Started Jun 11 12:32:21 PM PDT 24
Finished Jun 11 12:32:57 PM PDT 24
Peak memory 200316 kb
Host smart-f49640af-4fa9-497b-abbd-dd2e22de8c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464447285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.464447285
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.378125930
Short name T641
Test name
Test status
Simulation time 99800907900 ps
CPU time 40.62 seconds
Started Jun 11 12:32:18 PM PDT 24
Finished Jun 11 12:33:01 PM PDT 24
Peak memory 200248 kb
Host smart-db23a6dc-09b4-42e9-9a1e-97ec3f86bdca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378125930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.378125930
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.3238656698
Short name T748
Test name
Test status
Simulation time 13496354 ps
CPU time 0.55 seconds
Started Jun 11 12:30:08 PM PDT 24
Finished Jun 11 12:30:11 PM PDT 24
Peak memory 195688 kb
Host smart-da421083-a2d5-404b-b890-580c76a6840f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238656698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.3238656698
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.3177584796
Short name T157
Test name
Test status
Simulation time 56653146430 ps
CPU time 42.26 seconds
Started Jun 11 12:30:08 PM PDT 24
Finished Jun 11 12:30:53 PM PDT 24
Peak memory 200348 kb
Host smart-45da580a-0bac-4f19-9180-85d9651d48c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177584796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.3177584796
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.2542456165
Short name T976
Test name
Test status
Simulation time 35177645048 ps
CPU time 17.15 seconds
Started Jun 11 12:29:56 PM PDT 24
Finished Jun 11 12:30:14 PM PDT 24
Peak memory 200324 kb
Host smart-b22fc1bb-5749-4e09-8874-dcd38cec3707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542456165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.2542456165
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.1473835867
Short name T220
Test name
Test status
Simulation time 67801755284 ps
CPU time 30.63 seconds
Started Jun 11 12:29:50 PM PDT 24
Finished Jun 11 12:30:24 PM PDT 24
Peak memory 200096 kb
Host smart-422be46b-e1d2-4017-896c-63c8a946ee35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473835867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.1473835867
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.985755682
Short name T260
Test name
Test status
Simulation time 226815982964 ps
CPU time 208.5 seconds
Started Jun 11 12:30:11 PM PDT 24
Finished Jun 11 12:33:42 PM PDT 24
Peak memory 200316 kb
Host smart-77138260-aa51-4250-90e0-c1b4a7da2a79
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985755682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.985755682
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.4113203023
Short name T644
Test name
Test status
Simulation time 295603972528 ps
CPU time 96.57 seconds
Started Jun 11 12:30:17 PM PDT 24
Finished Jun 11 12:31:57 PM PDT 24
Peak memory 200240 kb
Host smart-d334ecdf-fefc-4c12-8959-400d078d95fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4113203023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.4113203023
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.689257804
Short name T355
Test name
Test status
Simulation time 1606219614 ps
CPU time 1.86 seconds
Started Jun 11 12:30:17 PM PDT 24
Finished Jun 11 12:30:22 PM PDT 24
Peak memory 196464 kb
Host smart-f3150e87-011e-4d32-b4d7-835de4ddf44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689257804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.689257804
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_perf.4255533500
Short name T690
Test name
Test status
Simulation time 11425375043 ps
CPU time 156.33 seconds
Started Jun 11 12:29:51 PM PDT 24
Finished Jun 11 12:32:30 PM PDT 24
Peak memory 200548 kb
Host smart-b29b26c2-f8bc-4787-9969-7838d8049319
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4255533500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.4255533500
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.1862254421
Short name T1035
Test name
Test status
Simulation time 6080804405 ps
CPU time 33.36 seconds
Started Jun 11 12:30:10 PM PDT 24
Finished Jun 11 12:30:46 PM PDT 24
Peak memory 199276 kb
Host smart-7574ff9d-b17c-4237-a71d-e3ab87dde4f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1862254421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.1862254421
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.159520415
Short name T249
Test name
Test status
Simulation time 60807118919 ps
CPU time 30.3 seconds
Started Jun 11 12:30:06 PM PDT 24
Finished Jun 11 12:30:38 PM PDT 24
Peak memory 200320 kb
Host smart-51bbcfa5-c4cb-471c-972c-a4a9aee76d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159520415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.159520415
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.1990227566
Short name T620
Test name
Test status
Simulation time 4117390251 ps
CPU time 2.37 seconds
Started Jun 11 12:30:05 PM PDT 24
Finished Jun 11 12:30:10 PM PDT 24
Peak memory 196340 kb
Host smart-82cfeeb0-62d1-4d37-b8b1-d825c68d58ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990227566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.1990227566
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.2706486954
Short name T1040
Test name
Test status
Simulation time 6033134900 ps
CPU time 10.61 seconds
Started Jun 11 12:29:52 PM PDT 24
Finished Jun 11 12:30:05 PM PDT 24
Peak memory 199652 kb
Host smart-64a9da12-fe79-4030-bc3d-6c5beb4a727a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706486954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.2706486954
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.234403469
Short name T594
Test name
Test status
Simulation time 71203665265 ps
CPU time 164.77 seconds
Started Jun 11 12:29:52 PM PDT 24
Finished Jun 11 12:32:39 PM PDT 24
Peak memory 200300 kb
Host smart-08f296f2-29fd-4fcc-8a6c-b92b284d6c25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234403469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.234403469
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.2353706310
Short name T553
Test name
Test status
Simulation time 3722114997 ps
CPU time 2.51 seconds
Started Jun 11 12:30:02 PM PDT 24
Finished Jun 11 12:30:07 PM PDT 24
Peak memory 199060 kb
Host smart-9d2a934c-8f28-4dd3-97a4-69ac37b55953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353706310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.2353706310
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.4098065603
Short name T538
Test name
Test status
Simulation time 25749561045 ps
CPU time 41.62 seconds
Started Jun 11 12:29:51 PM PDT 24
Finished Jun 11 12:30:36 PM PDT 24
Peak memory 200092 kb
Host smart-a2e1605e-0c1c-43d3-8860-f3cef4cda2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098065603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.4098065603
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.3905822100
Short name T961
Test name
Test status
Simulation time 51050079057 ps
CPU time 15.42 seconds
Started Jun 11 12:32:19 PM PDT 24
Finished Jun 11 12:32:37 PM PDT 24
Peak memory 200356 kb
Host smart-245ef09b-3bc0-4716-9bde-48a9478b92be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905822100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.3905822100
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.1133803804
Short name T616
Test name
Test status
Simulation time 103603724175 ps
CPU time 109.14 seconds
Started Jun 11 12:32:18 PM PDT 24
Finished Jun 11 12:34:10 PM PDT 24
Peak memory 200308 kb
Host smart-37228782-8f2e-4fab-9c37-519117ce60e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133803804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.1133803804
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.4267854945
Short name T1056
Test name
Test status
Simulation time 64969345356 ps
CPU time 103.9 seconds
Started Jun 11 12:32:16 PM PDT 24
Finished Jun 11 12:34:01 PM PDT 24
Peak memory 200256 kb
Host smart-86835264-318f-4986-935e-248f492f8bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267854945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.4267854945
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.1110462990
Short name T728
Test name
Test status
Simulation time 175661229681 ps
CPU time 19.62 seconds
Started Jun 11 12:32:18 PM PDT 24
Finished Jun 11 12:32:40 PM PDT 24
Peak memory 200144 kb
Host smart-8ba3cf70-57fa-4f04-94b3-bf2af812785b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110462990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.1110462990
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.18014010
Short name T502
Test name
Test status
Simulation time 24202497081 ps
CPU time 42.33 seconds
Started Jun 11 12:32:18 PM PDT 24
Finished Jun 11 12:33:02 PM PDT 24
Peak memory 200264 kb
Host smart-f49a4b37-d3a0-4f0f-8fa1-c32c88230a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18014010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.18014010
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.3852234521
Short name T18
Test name
Test status
Simulation time 52472690452 ps
CPU time 183.55 seconds
Started Jun 11 12:32:18 PM PDT 24
Finished Jun 11 12:35:24 PM PDT 24
Peak memory 200196 kb
Host smart-e9eded2e-0cb7-49db-a6dd-d196a06896df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852234521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.3852234521
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.945199312
Short name T520
Test name
Test status
Simulation time 105153913169 ps
CPU time 105.13 seconds
Started Jun 11 12:32:29 PM PDT 24
Finished Jun 11 12:34:16 PM PDT 24
Peak memory 200288 kb
Host smart-4cdc25e1-6623-43e7-b37a-b1a95a585f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945199312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.945199312
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.3349660318
Short name T927
Test name
Test status
Simulation time 39773732175 ps
CPU time 11.01 seconds
Started Jun 11 12:32:16 PM PDT 24
Finished Jun 11 12:32:29 PM PDT 24
Peak memory 200352 kb
Host smart-075c96b2-1121-4ef0-baa9-11e9409b4dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349660318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.3349660318
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.2803482092
Short name T1054
Test name
Test status
Simulation time 32205025822 ps
CPU time 59.37 seconds
Started Jun 11 12:32:18 PM PDT 24
Finished Jun 11 12:33:20 PM PDT 24
Peak memory 200320 kb
Host smart-0d710bad-28d9-4ed6-8c74-3a641dc38fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803482092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.2803482092
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.1028843327
Short name T414
Test name
Test status
Simulation time 111632656016 ps
CPU time 237.66 seconds
Started Jun 11 12:32:18 PM PDT 24
Finished Jun 11 12:36:18 PM PDT 24
Peak memory 200164 kb
Host smart-69cc45d5-3d92-46e2-b701-cdf13059a371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028843327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.1028843327
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.1940575195
Short name T1048
Test name
Test status
Simulation time 32789277 ps
CPU time 0.52 seconds
Started Jun 11 12:30:14 PM PDT 24
Finished Jun 11 12:30:17 PM PDT 24
Peak memory 195676 kb
Host smart-bf59e2db-afca-4958-96a2-4fb3067f3b9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940575195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.1940575195
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.868200503
Short name T1013
Test name
Test status
Simulation time 82943655625 ps
CPU time 22.5 seconds
Started Jun 11 12:29:53 PM PDT 24
Finished Jun 11 12:30:17 PM PDT 24
Peak memory 200156 kb
Host smart-5abf97eb-4528-41de-93fa-6605e34033f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868200503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.868200503
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.2729742764
Short name T1028
Test name
Test status
Simulation time 163152743688 ps
CPU time 274.44 seconds
Started Jun 11 12:30:02 PM PDT 24
Finished Jun 11 12:34:39 PM PDT 24
Peak memory 199992 kb
Host smart-e23fc51e-e600-4a57-aea8-13e720da521c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729742764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.2729742764
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.3886693443
Short name T485
Test name
Test status
Simulation time 60335549009 ps
CPU time 29.35 seconds
Started Jun 11 12:30:10 PM PDT 24
Finished Jun 11 12:30:42 PM PDT 24
Peak memory 200304 kb
Host smart-160668b5-8ea5-4aca-a39d-03662f64f0e4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886693443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.3886693443
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.3438152988
Short name T611
Test name
Test status
Simulation time 98803322946 ps
CPU time 358.35 seconds
Started Jun 11 12:30:14 PM PDT 24
Finished Jun 11 12:36:15 PM PDT 24
Peak memory 200256 kb
Host smart-adabc242-6494-4eb6-9dd9-ea70210b8ae3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3438152988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.3438152988
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.861707442
Short name T1071
Test name
Test status
Simulation time 6138725792 ps
CPU time 4.44 seconds
Started Jun 11 12:30:11 PM PDT 24
Finished Jun 11 12:30:18 PM PDT 24
Peak memory 199612 kb
Host smart-6b182935-94c0-4671-ba1e-158cb0054c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861707442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.861707442
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_perf.2297404361
Short name T942
Test name
Test status
Simulation time 8212262171 ps
CPU time 518.18 seconds
Started Jun 11 12:30:13 PM PDT 24
Finished Jun 11 12:38:53 PM PDT 24
Peak memory 200328 kb
Host smart-aae0c0af-136f-4bd7-84d6-041d9ed3658b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2297404361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.2297404361
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.4107466083
Short name T566
Test name
Test status
Simulation time 1178931626 ps
CPU time 1.32 seconds
Started Jun 11 12:30:10 PM PDT 24
Finished Jun 11 12:30:13 PM PDT 24
Peak memory 195708 kb
Host smart-8e0b9547-f6e6-4995-98c1-2f627de4f818
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4107466083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.4107466083
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.1575258877
Short name T1069
Test name
Test status
Simulation time 72560267196 ps
CPU time 137.22 seconds
Started Jun 11 12:30:04 PM PDT 24
Finished Jun 11 12:32:23 PM PDT 24
Peak memory 200080 kb
Host smart-64d40f92-b525-44fb-912b-a343c2b4e7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575258877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.1575258877
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.2526757516
Short name T501
Test name
Test status
Simulation time 1514247693 ps
CPU time 1.29 seconds
Started Jun 11 12:29:56 PM PDT 24
Finished Jun 11 12:29:59 PM PDT 24
Peak memory 195708 kb
Host smart-45322084-3dae-4fde-83fd-8f8c67e7d37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526757516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.2526757516
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.3416210644
Short name T286
Test name
Test status
Simulation time 6041397944 ps
CPU time 6.34 seconds
Started Jun 11 12:30:02 PM PDT 24
Finished Jun 11 12:30:10 PM PDT 24
Peak memory 200092 kb
Host smart-c017ebcd-7e72-4e19-9b24-ff35809fdd71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416210644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.3416210644
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.2200171415
Short name T1005
Test name
Test status
Simulation time 119163081850 ps
CPU time 377.81 seconds
Started Jun 11 12:30:01 PM PDT 24
Finished Jun 11 12:36:21 PM PDT 24
Peak memory 216648 kb
Host smart-4b6f8f3d-743e-4573-afb1-58de3b9743d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200171415 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.2200171415
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.4230758734
Short name T790
Test name
Test status
Simulation time 982550232 ps
CPU time 2.6 seconds
Started Jun 11 12:30:15 PM PDT 24
Finished Jun 11 12:30:20 PM PDT 24
Peak memory 199096 kb
Host smart-89f4428d-d705-4193-ac2e-cdffc42838e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230758734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.4230758734
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.3972962524
Short name T313
Test name
Test status
Simulation time 93229734262 ps
CPU time 23.54 seconds
Started Jun 11 12:30:08 PM PDT 24
Finished Jun 11 12:30:34 PM PDT 24
Peak memory 200260 kb
Host smart-e2603875-4b7d-44ef-bd02-fc813b6a1e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972962524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.3972962524
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.848902443
Short name T536
Test name
Test status
Simulation time 37317701234 ps
CPU time 101.55 seconds
Started Jun 11 12:32:29 PM PDT 24
Finished Jun 11 12:34:12 PM PDT 24
Peak memory 199872 kb
Host smart-78526289-27f8-4311-ab3c-8ebb4b729545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848902443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.848902443
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.3858450075
Short name T482
Test name
Test status
Simulation time 10165349300 ps
CPU time 14.32 seconds
Started Jun 11 12:32:18 PM PDT 24
Finished Jun 11 12:32:35 PM PDT 24
Peak memory 199128 kb
Host smart-1a754d0b-02a1-4ed9-b031-573f3686bb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858450075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.3858450075
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.1730681769
Short name T112
Test name
Test status
Simulation time 116118817292 ps
CPU time 180.85 seconds
Started Jun 11 12:32:18 PM PDT 24
Finished Jun 11 12:35:22 PM PDT 24
Peak memory 200244 kb
Host smart-12cd83d1-c827-4596-93b8-723fe322c4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730681769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.1730681769
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.548768765
Short name T819
Test name
Test status
Simulation time 18013967158 ps
CPU time 25.84 seconds
Started Jun 11 12:32:18 PM PDT 24
Finished Jun 11 12:32:46 PM PDT 24
Peak memory 200328 kb
Host smart-9fac540c-83d8-4f1e-9bc6-2218cb509bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548768765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.548768765
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.2129119391
Short name T876
Test name
Test status
Simulation time 80155935934 ps
CPU time 119.02 seconds
Started Jun 11 12:32:18 PM PDT 24
Finished Jun 11 12:34:19 PM PDT 24
Peak memory 200092 kb
Host smart-1f6bcf1a-5a34-44dc-ad80-85eb78bbe41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129119391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.2129119391
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.2468462766
Short name T1052
Test name
Test status
Simulation time 38500063100 ps
CPU time 17.14 seconds
Started Jun 11 12:32:18 PM PDT 24
Finished Jun 11 12:32:38 PM PDT 24
Peak memory 200260 kb
Host smart-6446d5e2-2053-45c1-8a18-c89201b30ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468462766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.2468462766
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.1344090325
Short name T910
Test name
Test status
Simulation time 39963839290 ps
CPU time 56.89 seconds
Started Jun 11 12:32:19 PM PDT 24
Finished Jun 11 12:33:18 PM PDT 24
Peak memory 200088 kb
Host smart-6eb751c8-0a87-41cc-a674-04ad68067284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344090325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.1344090325
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.3919467815
Short name T697
Test name
Test status
Simulation time 56428087418 ps
CPU time 94.5 seconds
Started Jun 11 12:32:18 PM PDT 24
Finished Jun 11 12:33:55 PM PDT 24
Peak memory 200276 kb
Host smart-fe911a35-ad6a-4eb0-8545-ae9b61d307ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919467815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.3919467815
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.1395241223
Short name T477
Test name
Test status
Simulation time 42670678847 ps
CPU time 53.38 seconds
Started Jun 11 12:32:16 PM PDT 24
Finished Jun 11 12:33:12 PM PDT 24
Peak memory 200092 kb
Host smart-19a1b949-a018-4987-b038-30a7c226e411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395241223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.1395241223
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.3120654478
Short name T349
Test name
Test status
Simulation time 11681266 ps
CPU time 0.55 seconds
Started Jun 11 12:30:01 PM PDT 24
Finished Jun 11 12:30:03 PM PDT 24
Peak memory 195628 kb
Host smart-5e9ec36e-c621-4012-b320-008d610c5a7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120654478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.3120654478
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.999843516
Short name T844
Test name
Test status
Simulation time 122982487322 ps
CPU time 46.96 seconds
Started Jun 11 12:30:01 PM PDT 24
Finished Jun 11 12:30:49 PM PDT 24
Peak memory 200264 kb
Host smart-a40f8d05-4372-431b-86a7-a36fa7afa8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999843516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.999843516
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.2939487233
Short name T1081
Test name
Test status
Simulation time 26892731072 ps
CPU time 49.08 seconds
Started Jun 11 12:30:16 PM PDT 24
Finished Jun 11 12:31:08 PM PDT 24
Peak memory 200256 kb
Host smart-8aff5554-fe3a-4aea-a43a-4d55e65f9135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939487233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.2939487233
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.1411386076
Short name T175
Test name
Test status
Simulation time 20376404022 ps
CPU time 30.46 seconds
Started Jun 11 12:30:13 PM PDT 24
Finished Jun 11 12:30:46 PM PDT 24
Peak memory 200320 kb
Host smart-35a44a37-8388-435d-94fd-5b046fccac7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411386076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.1411386076
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.3615582910
Short name T671
Test name
Test status
Simulation time 31999719267 ps
CPU time 56.5 seconds
Started Jun 11 12:30:11 PM PDT 24
Finished Jun 11 12:31:10 PM PDT 24
Peak memory 199912 kb
Host smart-ec151af7-6a18-4707-bf28-47c1b9e0607b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615582910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.3615582910
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.3432428269
Short name T568
Test name
Test status
Simulation time 111582187171 ps
CPU time 446.25 seconds
Started Jun 11 12:30:01 PM PDT 24
Finished Jun 11 12:37:29 PM PDT 24
Peak memory 200316 kb
Host smart-ae2161a3-b383-4ee2-96ad-3e3fc2a0ba0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3432428269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.3432428269
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.3625334093
Short name T909
Test name
Test status
Simulation time 3838519960 ps
CPU time 7.37 seconds
Started Jun 11 12:30:10 PM PDT 24
Finished Jun 11 12:30:20 PM PDT 24
Peak memory 198984 kb
Host smart-d14230c0-eb5f-445c-b32b-1ea5a00e2da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625334093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.3625334093
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_perf.1540939290
Short name T1016
Test name
Test status
Simulation time 27694360173 ps
CPU time 451.54 seconds
Started Jun 11 12:30:01 PM PDT 24
Finished Jun 11 12:37:34 PM PDT 24
Peak memory 200332 kb
Host smart-6914fe11-ddfc-4202-8316-bca4e6b140d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1540939290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.1540939290
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.2864268345
Short name T755
Test name
Test status
Simulation time 7351536300 ps
CPU time 35.57 seconds
Started Jun 11 12:30:15 PM PDT 24
Finished Jun 11 12:30:54 PM PDT 24
Peak memory 199400 kb
Host smart-e0174342-694e-4d13-8a15-101cbb1134bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2864268345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.2864268345
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.2421588547
Short name T124
Test name
Test status
Simulation time 72149426993 ps
CPU time 28.62 seconds
Started Jun 11 12:30:12 PM PDT 24
Finished Jun 11 12:30:43 PM PDT 24
Peak memory 200368 kb
Host smart-5e0e47b9-17c3-4491-bc67-0ea52ce6c364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421588547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.2421588547
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.1214849481
Short name T593
Test name
Test status
Simulation time 1815688617 ps
CPU time 1.42 seconds
Started Jun 11 12:30:04 PM PDT 24
Finished Jun 11 12:30:07 PM PDT 24
Peak memory 195896 kb
Host smart-52089bed-d664-406a-8d3b-919b8df8683a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214849481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.1214849481
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.3806040059
Short name T419
Test name
Test status
Simulation time 670982791 ps
CPU time 3.07 seconds
Started Jun 11 12:30:04 PM PDT 24
Finished Jun 11 12:30:08 PM PDT 24
Peak memory 199260 kb
Host smart-aa5e9e49-c8df-4ae4-92fe-b5db52c7af61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806040059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.3806040059
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.3623629891
Short name T169
Test name
Test status
Simulation time 227309864244 ps
CPU time 206.37 seconds
Started Jun 11 12:30:06 PM PDT 24
Finished Jun 11 12:33:34 PM PDT 24
Peak memory 200400 kb
Host smart-2b23729e-c484-427d-83fe-9204828fe6af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623629891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.3623629891
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.920799650
Short name T866
Test name
Test status
Simulation time 189047297742 ps
CPU time 539.33 seconds
Started Jun 11 12:30:04 PM PDT 24
Finished Jun 11 12:39:05 PM PDT 24
Peak memory 216120 kb
Host smart-1e4e3f74-d9f3-4fda-92a5-4e28bbd9481a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920799650 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.920799650
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.2695108087
Short name T471
Test name
Test status
Simulation time 7555570111 ps
CPU time 40.46 seconds
Started Jun 11 12:30:16 PM PDT 24
Finished Jun 11 12:31:00 PM PDT 24
Peak memory 200372 kb
Host smart-e2b3b0c3-f58e-4dfb-b0d7-fae70f2fc576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695108087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.2695108087
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.3289065334
Short name T983
Test name
Test status
Simulation time 27868351967 ps
CPU time 53.05 seconds
Started Jun 11 12:30:10 PM PDT 24
Finished Jun 11 12:31:06 PM PDT 24
Peak memory 200316 kb
Host smart-c5340c42-f6ed-442d-bed7-83b787dec0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289065334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.3289065334
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.3215798135
Short name T900
Test name
Test status
Simulation time 159833784227 ps
CPU time 47.7 seconds
Started Jun 11 12:32:17 PM PDT 24
Finished Jun 11 12:33:07 PM PDT 24
Peak memory 200120 kb
Host smart-3535b778-52df-4080-83b9-ac5670fc4b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215798135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.3215798135
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.1770817811
Short name T314
Test name
Test status
Simulation time 29643629776 ps
CPU time 46.28 seconds
Started Jun 11 12:32:18 PM PDT 24
Finished Jun 11 12:33:07 PM PDT 24
Peak memory 200312 kb
Host smart-82f4c988-b795-45b8-8a79-d91bc1b06f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770817811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.1770817811
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.2291063236
Short name T30
Test name
Test status
Simulation time 110277851572 ps
CPU time 154.16 seconds
Started Jun 11 12:32:17 PM PDT 24
Finished Jun 11 12:34:54 PM PDT 24
Peak memory 200340 kb
Host smart-9f8fce5c-8141-4b48-8a33-b95bbe1d24cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291063236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.2291063236
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.4026713752
Short name T1093
Test name
Test status
Simulation time 33002879712 ps
CPU time 13.4 seconds
Started Jun 11 12:32:20 PM PDT 24
Finished Jun 11 12:32:35 PM PDT 24
Peak memory 200336 kb
Host smart-3b69d0ea-eb06-48ab-815c-673be9c89411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026713752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.4026713752
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.2922010370
Short name T973
Test name
Test status
Simulation time 66930881769 ps
CPU time 112.34 seconds
Started Jun 11 12:32:16 PM PDT 24
Finished Jun 11 12:34:10 PM PDT 24
Peak memory 200212 kb
Host smart-3b5d697b-3d04-40bd-be8e-8582ac35a5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922010370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.2922010370
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.2741975496
Short name T418
Test name
Test status
Simulation time 63711264258 ps
CPU time 174.65 seconds
Started Jun 11 12:32:28 PM PDT 24
Finished Jun 11 12:35:24 PM PDT 24
Peak memory 200272 kb
Host smart-41bd0cde-58e8-4f6a-b1a2-d5d8032fc84e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741975496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.2741975496
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.746589308
Short name T789
Test name
Test status
Simulation time 80089088984 ps
CPU time 126.38 seconds
Started Jun 11 12:32:18 PM PDT 24
Finished Jun 11 12:34:27 PM PDT 24
Peak memory 200268 kb
Host smart-667c0295-0824-4662-8ffe-199b1fd18127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746589308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.746589308
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.191743226
Short name T1038
Test name
Test status
Simulation time 8983426303 ps
CPU time 14.96 seconds
Started Jun 11 12:32:28 PM PDT 24
Finished Jun 11 12:32:45 PM PDT 24
Peak memory 199992 kb
Host smart-0bc3dbe5-c285-4e30-8a3e-c1fc6c88d6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191743226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.191743226
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.3585853402
Short name T113
Test name
Test status
Simulation time 98927379584 ps
CPU time 152.02 seconds
Started Jun 11 12:32:27 PM PDT 24
Finished Jun 11 12:35:01 PM PDT 24
Peak memory 200368 kb
Host smart-86d822c0-d692-40b9-8104-a919d607d245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585853402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.3585853402
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.2414323129
Short name T886
Test name
Test status
Simulation time 238488374680 ps
CPU time 126.77 seconds
Started Jun 11 12:32:30 PM PDT 24
Finished Jun 11 12:34:38 PM PDT 24
Peak memory 200240 kb
Host smart-6730a7a6-692c-47b8-851c-37a0e1477db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414323129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.2414323129
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.1907332134
Short name T385
Test name
Test status
Simulation time 16327671 ps
CPU time 0.52 seconds
Started Jun 11 12:29:02 PM PDT 24
Finished Jun 11 12:29:05 PM PDT 24
Peak memory 195676 kb
Host smart-997e50c3-66ec-41d0-b728-45d97ae358e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907332134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.1907332134
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.259763723
Short name T964
Test name
Test status
Simulation time 42917803802 ps
CPU time 67.99 seconds
Started Jun 11 12:28:52 PM PDT 24
Finished Jun 11 12:30:02 PM PDT 24
Peak memory 200292 kb
Host smart-f623909b-eb72-4a1d-8391-b41bdbc62047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259763723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.259763723
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.2291620292
Short name T163
Test name
Test status
Simulation time 29297061825 ps
CPU time 13.31 seconds
Started Jun 11 12:29:16 PM PDT 24
Finished Jun 11 12:29:31 PM PDT 24
Peak memory 200328 kb
Host smart-c3c3623b-f502-4fef-98ae-e4a66e191bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291620292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.2291620292
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.3801547174
Short name T769
Test name
Test status
Simulation time 247173716904 ps
CPU time 105.41 seconds
Started Jun 11 12:28:50 PM PDT 24
Finished Jun 11 12:30:37 PM PDT 24
Peak memory 199788 kb
Host smart-78de4b7d-d6f2-4ca4-a568-3554b34badf2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801547174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.3801547174
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.39822123
Short name T906
Test name
Test status
Simulation time 78097101515 ps
CPU time 586.54 seconds
Started Jun 11 12:28:46 PM PDT 24
Finished Jun 11 12:38:35 PM PDT 24
Peak memory 200080 kb
Host smart-502a1ef0-de66-4cfc-a365-50ff8fc9a2ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=39822123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.39822123
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.3784375374
Short name T340
Test name
Test status
Simulation time 12549313695 ps
CPU time 10.72 seconds
Started Jun 11 12:29:06 PM PDT 24
Finished Jun 11 12:29:18 PM PDT 24
Peak memory 200032 kb
Host smart-1adfe7ce-4f7f-48f9-8340-98ca80e3e7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784375374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.3784375374
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.1549539662
Short name T614
Test name
Test status
Simulation time 3990718448 ps
CPU time 8.57 seconds
Started Jun 11 12:28:57 PM PDT 24
Finished Jun 11 12:29:08 PM PDT 24
Peak memory 199396 kb
Host smart-2a1b4924-8e77-4d19-9f0a-d2d98cc952af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1549539662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.1549539662
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.164943765
Short name T127
Test name
Test status
Simulation time 46538964486 ps
CPU time 86.09 seconds
Started Jun 11 12:28:49 PM PDT 24
Finished Jun 11 12:30:17 PM PDT 24
Peak memory 200304 kb
Host smart-72dc84b9-5ae5-4866-bbad-afea74fb4c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164943765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.164943765
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.2502239558
Short name T529
Test name
Test status
Simulation time 1706133137 ps
CPU time 1.3 seconds
Started Jun 11 12:28:54 PM PDT 24
Finished Jun 11 12:28:58 PM PDT 24
Peak memory 195712 kb
Host smart-0f4480ba-e042-403f-a9c6-b179c62efc5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502239558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.2502239558
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.1028343957
Short name T23
Test name
Test status
Simulation time 428721470 ps
CPU time 0.88 seconds
Started Jun 11 12:29:04 PM PDT 24
Finished Jun 11 12:29:07 PM PDT 24
Peak memory 218700 kb
Host smart-fe4b73ec-0ce0-4f16-8a9f-5c1439432412
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028343957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.1028343957
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.1326340346
Short name T433
Test name
Test status
Simulation time 889205421 ps
CPU time 2.82 seconds
Started Jun 11 12:28:56 PM PDT 24
Finished Jun 11 12:29:01 PM PDT 24
Peak memory 198604 kb
Host smart-321e0ca8-2920-448f-835f-a2d9a6729dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326340346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.1326340346
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.3878778084
Short name T122
Test name
Test status
Simulation time 285392040469 ps
CPU time 531.89 seconds
Started Jun 11 12:29:19 PM PDT 24
Finished Jun 11 12:38:12 PM PDT 24
Peak memory 211760 kb
Host smart-b85a817d-a3e2-460e-b7b6-83fbc3c4b375
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878778084 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.3878778084
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.1230325398
Short name T977
Test name
Test status
Simulation time 809099189 ps
CPU time 2.54 seconds
Started Jun 11 12:28:47 PM PDT 24
Finished Jun 11 12:28:52 PM PDT 24
Peak memory 200060 kb
Host smart-b140e84a-a8aa-4c3f-97b8-4347eff58c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230325398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.1230325398
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.1010294220
Short name T658
Test name
Test status
Simulation time 16671589828 ps
CPU time 24.56 seconds
Started Jun 11 12:29:10 PM PDT 24
Finished Jun 11 12:29:36 PM PDT 24
Peak memory 198532 kb
Host smart-ab3fd58d-5dd3-43b8-a1f7-fffb22cd0423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010294220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.1010294220
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.1330777306
Short name T776
Test name
Test status
Simulation time 18385228 ps
CPU time 0.56 seconds
Started Jun 11 12:30:01 PM PDT 24
Finished Jun 11 12:30:03 PM PDT 24
Peak memory 195736 kb
Host smart-7dbf5aab-04be-46c6-bed7-d326f20bb92e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330777306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.1330777306
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.1690807591
Short name T417
Test name
Test status
Simulation time 35535380197 ps
CPU time 48.26 seconds
Started Jun 11 12:30:03 PM PDT 24
Finished Jun 11 12:30:53 PM PDT 24
Peak memory 200332 kb
Host smart-f6488bec-a7c2-42a4-aeac-d10a4eb0e9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690807591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.1690807591
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.677876736
Short name T803
Test name
Test status
Simulation time 22434049861 ps
CPU time 39.2 seconds
Started Jun 11 12:30:18 PM PDT 24
Finished Jun 11 12:31:00 PM PDT 24
Peak memory 200332 kb
Host smart-33762579-1d5f-49f4-a808-ade8915b98a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677876736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.677876736
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.1483463702
Short name T882
Test name
Test status
Simulation time 67930351945 ps
CPU time 28.23 seconds
Started Jun 11 12:30:10 PM PDT 24
Finished Jun 11 12:30:41 PM PDT 24
Peak memory 200312 kb
Host smart-2bf21f4e-7262-462b-8195-27aa85f1bc34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483463702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.1483463702
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.137325497
Short name T399
Test name
Test status
Simulation time 22780260389 ps
CPU time 17.82 seconds
Started Jun 11 12:30:12 PM PDT 24
Finished Jun 11 12:30:32 PM PDT 24
Peak memory 199536 kb
Host smart-6edf9221-31d4-44e1-84af-4109b9df8ea9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137325497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.137325497
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.1375245280
Short name T32
Test name
Test status
Simulation time 118082408359 ps
CPU time 206.63 seconds
Started Jun 11 12:30:12 PM PDT 24
Finished Jun 11 12:33:41 PM PDT 24
Peak memory 200336 kb
Host smart-9482f595-10f6-428c-81d9-670d24fbf389
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1375245280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.1375245280
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.1941257433
Short name T362
Test name
Test status
Simulation time 5784392588 ps
CPU time 8.77 seconds
Started Jun 11 12:30:14 PM PDT 24
Finished Jun 11 12:30:26 PM PDT 24
Peak memory 200312 kb
Host smart-eddd05c5-0948-4520-a689-6828c358dedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941257433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.1941257433
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_perf.3094155207
Short name T1019
Test name
Test status
Simulation time 25054212466 ps
CPU time 490.68 seconds
Started Jun 11 12:30:12 PM PDT 24
Finished Jun 11 12:38:26 PM PDT 24
Peak memory 200332 kb
Host smart-8dbe5d9d-622b-48f2-bacb-baf6cccc9ad5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3094155207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.3094155207
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.1992081250
Short name T531
Test name
Test status
Simulation time 2318550638 ps
CPU time 8.25 seconds
Started Jun 11 12:30:32 PM PDT 24
Finished Jun 11 12:30:41 PM PDT 24
Peak memory 198196 kb
Host smart-136778bb-d393-49db-8b70-96d61f777221
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1992081250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.1992081250
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.1362751448
Short name T161
Test name
Test status
Simulation time 9514863200 ps
CPU time 17.78 seconds
Started Jun 11 12:30:02 PM PDT 24
Finished Jun 11 12:30:22 PM PDT 24
Peak memory 200316 kb
Host smart-66835df5-48db-46c0-94a4-a09d90649478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362751448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.1362751448
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.1687844881
Short name T542
Test name
Test status
Simulation time 571402082 ps
CPU time 0.83 seconds
Started Jun 11 12:30:09 PM PDT 24
Finished Jun 11 12:30:13 PM PDT 24
Peak memory 195888 kb
Host smart-8f99422c-fecd-4769-bd44-eb84baf3900e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687844881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.1687844881
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.3586797805
Short name T378
Test name
Test status
Simulation time 535008258 ps
CPU time 2.16 seconds
Started Jun 11 12:30:18 PM PDT 24
Finished Jun 11 12:30:23 PM PDT 24
Peak memory 198536 kb
Host smart-525ed873-9de2-487c-894a-2c87988b23d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586797805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.3586797805
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.3561330505
Short name T1097
Test name
Test status
Simulation time 112166327471 ps
CPU time 183.85 seconds
Started Jun 11 12:30:13 PM PDT 24
Finished Jun 11 12:33:19 PM PDT 24
Peak memory 200272 kb
Host smart-e6391212-679e-420d-9687-3ce30b85b301
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561330505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.3561330505
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.4228594756
Short name T28
Test name
Test status
Simulation time 49869591575 ps
CPU time 214.24 seconds
Started Jun 11 12:30:00 PM PDT 24
Finished Jun 11 12:33:36 PM PDT 24
Peak memory 216144 kb
Host smart-114a2b4b-beed-4ed3-8363-1024fdb7f437
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228594756 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.4228594756
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.2662018492
Short name T981
Test name
Test status
Simulation time 1292058128 ps
CPU time 2.4 seconds
Started Jun 11 12:30:13 PM PDT 24
Finished Jun 11 12:30:18 PM PDT 24
Peak memory 199208 kb
Host smart-c93a1fe7-4f10-45a0-882b-54243eda00ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662018492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.2662018492
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.2360422598
Short name T472
Test name
Test status
Simulation time 30892494435 ps
CPU time 22.16 seconds
Started Jun 11 12:30:12 PM PDT 24
Finished Jun 11 12:30:36 PM PDT 24
Peak memory 200324 kb
Host smart-4d8c841c-2253-4133-9046-fd9c967ee5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360422598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.2360422598
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.1297779613
Short name T564
Test name
Test status
Simulation time 17694775 ps
CPU time 0.53 seconds
Started Jun 11 12:30:14 PM PDT 24
Finished Jun 11 12:30:18 PM PDT 24
Peak memory 195116 kb
Host smart-0de8465e-f035-4b45-b293-58232dd0b83c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297779613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.1297779613
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.17298130
Short name T92
Test name
Test status
Simulation time 305861903484 ps
CPU time 127.25 seconds
Started Jun 11 12:30:14 PM PDT 24
Finished Jun 11 12:32:24 PM PDT 24
Peak memory 200248 kb
Host smart-c4f33a27-d8cc-48c0-a3b8-127372336ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17298130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.17298130
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.1141709319
Short name T868
Test name
Test status
Simulation time 76730335841 ps
CPU time 123.55 seconds
Started Jun 11 12:30:12 PM PDT 24
Finished Jun 11 12:32:18 PM PDT 24
Peak memory 200320 kb
Host smart-39f88ba5-68e3-4568-b8e9-9842985e74e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141709319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.1141709319
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.4181771805
Short name T210
Test name
Test status
Simulation time 86317932479 ps
CPU time 578.56 seconds
Started Jun 11 12:30:01 PM PDT 24
Finished Jun 11 12:39:40 PM PDT 24
Peak memory 200256 kb
Host smart-f41cb0b9-71d4-4287-82b9-35e51d06d51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181771805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.4181771805
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.1048278570
Short name T292
Test name
Test status
Simulation time 409704439747 ps
CPU time 103.3 seconds
Started Jun 11 12:30:03 PM PDT 24
Finished Jun 11 12:31:48 PM PDT 24
Peak memory 200304 kb
Host smart-c43bb44d-1e68-4327-ac26-743fc1ec4625
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048278570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.1048278570
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.1026420140
Short name T783
Test name
Test status
Simulation time 129082046562 ps
CPU time 823.57 seconds
Started Jun 11 12:30:23 PM PDT 24
Finished Jun 11 12:44:08 PM PDT 24
Peak memory 200332 kb
Host smart-101cb8f2-79e8-4093-acd3-0cc55c0145bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1026420140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.1026420140
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.561361857
Short name T716
Test name
Test status
Simulation time 1600485845 ps
CPU time 1.38 seconds
Started Jun 11 12:30:30 PM PDT 24
Finished Jun 11 12:30:33 PM PDT 24
Peak memory 196340 kb
Host smart-37da681f-8ac0-4bc8-b392-3948eae5581d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561361857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.561361857
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_perf.2002265786
Short name T782
Test name
Test status
Simulation time 6561831426 ps
CPU time 76.8 seconds
Started Jun 11 12:30:19 PM PDT 24
Finished Jun 11 12:31:38 PM PDT 24
Peak memory 200256 kb
Host smart-c1b59057-6270-4935-b176-13ce359dc5cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2002265786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.2002265786
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.1679931512
Short name T465
Test name
Test status
Simulation time 6132532524 ps
CPU time 44.46 seconds
Started Jun 11 12:30:04 PM PDT 24
Finished Jun 11 12:30:49 PM PDT 24
Peak memory 199460 kb
Host smart-bd500c37-d45a-47d8-b889-9ed524d454af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1679931512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.1679931512
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.3259099843
Short name T144
Test name
Test status
Simulation time 81300928526 ps
CPU time 29.62 seconds
Started Jun 11 12:30:14 PM PDT 24
Finished Jun 11 12:30:46 PM PDT 24
Peak memory 200316 kb
Host smart-bc544cf4-62ec-4408-9565-9d6e3bcf7179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259099843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.3259099843
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.1066151378
Short name T269
Test name
Test status
Simulation time 5796329399 ps
CPU time 10.72 seconds
Started Jun 11 12:30:17 PM PDT 24
Finished Jun 11 12:30:31 PM PDT 24
Peak memory 196416 kb
Host smart-9034aeba-3eb8-430d-98a7-117fcdc02bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066151378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.1066151378
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.3157331867
Short name T381
Test name
Test status
Simulation time 275096817 ps
CPU time 1.05 seconds
Started Jun 11 12:30:11 PM PDT 24
Finished Jun 11 12:30:15 PM PDT 24
Peak memory 198784 kb
Host smart-31a1817c-eb12-4863-92c3-ea6778c8b009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157331867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.3157331867
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.1588600959
Short name T858
Test name
Test status
Simulation time 157002212116 ps
CPU time 122.45 seconds
Started Jun 11 12:30:23 PM PDT 24
Finished Jun 11 12:32:26 PM PDT 24
Peak memory 200616 kb
Host smart-c26f6239-c437-445f-b1e4-4904d3aa5c4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588600959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.1588600959
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.1899694081
Short name T657
Test name
Test status
Simulation time 379876422474 ps
CPU time 477.7 seconds
Started Jun 11 12:30:20 PM PDT 24
Finished Jun 11 12:38:19 PM PDT 24
Peak memory 217156 kb
Host smart-fd8dd94c-eb3b-4eb8-96c3-8e66bb2b0dcb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899694081 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.1899694081
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.2002878717
Short name T474
Test name
Test status
Simulation time 969189854 ps
CPU time 1.9 seconds
Started Jun 11 12:30:19 PM PDT 24
Finished Jun 11 12:30:23 PM PDT 24
Peak memory 198916 kb
Host smart-f69cb8f7-b510-4849-bfb2-93463216a409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002878717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.2002878717
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.4111390852
Short name T479
Test name
Test status
Simulation time 34672704896 ps
CPU time 11.49 seconds
Started Jun 11 12:30:17 PM PDT 24
Finished Jun 11 12:30:32 PM PDT 24
Peak memory 197096 kb
Host smart-3836a045-4c50-440a-804c-1483a2cf25b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111390852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.4111390852
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.855439817
Short name T647
Test name
Test status
Simulation time 37612972 ps
CPU time 0.55 seconds
Started Jun 11 12:30:27 PM PDT 24
Finished Jun 11 12:30:29 PM PDT 24
Peak memory 196004 kb
Host smart-cee8824b-b059-497d-aff5-939cfac1acd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855439817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.855439817
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.4125283521
Short name T561
Test name
Test status
Simulation time 92665630321 ps
CPU time 46.25 seconds
Started Jun 11 12:30:14 PM PDT 24
Finished Jun 11 12:31:02 PM PDT 24
Peak memory 200088 kb
Host smart-eafb76f9-e799-4457-bdb3-02657f3cf3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125283521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.4125283521
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.643858048
Short name T1080
Test name
Test status
Simulation time 30089927650 ps
CPU time 53.81 seconds
Started Jun 11 12:30:18 PM PDT 24
Finished Jun 11 12:31:15 PM PDT 24
Peak memory 200300 kb
Host smart-5526e82a-635c-4e97-b85b-a1495e023c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643858048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.643858048
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.1892178609
Short name T649
Test name
Test status
Simulation time 74105630710 ps
CPU time 26.98 seconds
Started Jun 11 12:30:14 PM PDT 24
Finished Jun 11 12:30:43 PM PDT 24
Peak memory 200288 kb
Host smart-2d0d2d66-e91a-472e-92f2-ed833bdfaf58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892178609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.1892178609
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.2910982448
Short name T896
Test name
Test status
Simulation time 36222399653 ps
CPU time 21.86 seconds
Started Jun 11 12:30:15 PM PDT 24
Finished Jun 11 12:30:40 PM PDT 24
Peak memory 199224 kb
Host smart-413c0d2d-1990-4fde-a24c-33978cfe7f2b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910982448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.2910982448
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.1478545076
Short name T956
Test name
Test status
Simulation time 63563902509 ps
CPU time 607.37 seconds
Started Jun 11 12:30:14 PM PDT 24
Finished Jun 11 12:40:24 PM PDT 24
Peak memory 200172 kb
Host smart-e225843e-6e57-467c-9040-8e2025e7f816
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1478545076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.1478545076
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.1691631301
Short name T521
Test name
Test status
Simulation time 6319115488 ps
CPU time 7.33 seconds
Started Jun 11 12:30:13 PM PDT 24
Finished Jun 11 12:30:23 PM PDT 24
Peak memory 199848 kb
Host smart-ba352d86-43e9-4786-ae7a-c15df5759c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691631301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.1691631301
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_perf.4267733211
Short name T639
Test name
Test status
Simulation time 18768743338 ps
CPU time 1014.29 seconds
Started Jun 11 12:30:15 PM PDT 24
Finished Jun 11 12:47:12 PM PDT 24
Peak memory 200304 kb
Host smart-cc9366ca-b30e-4756-bcfa-2d4e88ffe6f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4267733211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.4267733211
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.1174814422
Short name T545
Test name
Test status
Simulation time 1499229351 ps
CPU time 1.3 seconds
Started Jun 11 12:30:18 PM PDT 24
Finished Jun 11 12:30:22 PM PDT 24
Peak memory 195848 kb
Host smart-dd127841-dc26-4e58-ad17-1eb89569c66c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1174814422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.1174814422
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.2858543147
Short name T510
Test name
Test status
Simulation time 13984778882 ps
CPU time 23.13 seconds
Started Jun 11 12:30:32 PM PDT 24
Finished Jun 11 12:30:56 PM PDT 24
Peak memory 200336 kb
Host smart-0cd34810-fbd8-41c5-bc78-ff66cc9f219f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858543147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.2858543147
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.368586246
Short name T797
Test name
Test status
Simulation time 39744809819 ps
CPU time 66.98 seconds
Started Jun 11 12:30:14 PM PDT 24
Finished Jun 11 12:31:23 PM PDT 24
Peak memory 196308 kb
Host smart-f0b91bd2-07a9-41d7-b6f6-2fb0e760ea81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368586246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.368586246
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.687212825
Short name T375
Test name
Test status
Simulation time 551502774 ps
CPU time 3.09 seconds
Started Jun 11 12:30:18 PM PDT 24
Finished Jun 11 12:30:24 PM PDT 24
Peak memory 199264 kb
Host smart-1a33ca1b-a901-41e2-a5bd-702a39763fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687212825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.687212825
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.2316836824
Short name T950
Test name
Test status
Simulation time 1616049503 ps
CPU time 1.47 seconds
Started Jun 11 12:30:25 PM PDT 24
Finished Jun 11 12:30:28 PM PDT 24
Peak memory 199468 kb
Host smart-3333d63d-bb49-4641-ab6d-9d6b2a758596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316836824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.2316836824
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.1430529268
Short name T795
Test name
Test status
Simulation time 62121350439 ps
CPU time 110.59 seconds
Started Jun 11 12:30:16 PM PDT 24
Finished Jun 11 12:32:09 PM PDT 24
Peak memory 200248 kb
Host smart-66ba2453-0925-4436-8b3c-fce6957ac12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430529268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.1430529268
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.2582899756
Short name T346
Test name
Test status
Simulation time 151093938 ps
CPU time 0.54 seconds
Started Jun 11 12:30:15 PM PDT 24
Finished Jun 11 12:30:19 PM PDT 24
Peak memory 195720 kb
Host smart-f8553858-717a-4a6e-9f01-6e1e86d54167
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582899756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.2582899756
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.403583592
Short name T722
Test name
Test status
Simulation time 45566577341 ps
CPU time 70.17 seconds
Started Jun 11 12:30:16 PM PDT 24
Finished Jun 11 12:31:29 PM PDT 24
Peak memory 200232 kb
Host smart-86a4bf38-f388-4206-b058-3d061120d6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403583592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.403583592
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.514065070
Short name T535
Test name
Test status
Simulation time 110729164080 ps
CPU time 177.46 seconds
Started Jun 11 12:30:27 PM PDT 24
Finished Jun 11 12:33:26 PM PDT 24
Peak memory 200308 kb
Host smart-8d381f4c-f9f5-4576-84c3-dbb0ca4a67b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514065070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.514065070
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.3980805325
Short name T598
Test name
Test status
Simulation time 121009470863 ps
CPU time 51.67 seconds
Started Jun 11 12:30:25 PM PDT 24
Finished Jun 11 12:31:17 PM PDT 24
Peak memory 200268 kb
Host smart-0b0ad431-6fe5-4ab8-a5e6-6461c758c597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980805325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.3980805325
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.96798593
Short name T706
Test name
Test status
Simulation time 15949859542 ps
CPU time 30.28 seconds
Started Jun 11 12:30:18 PM PDT 24
Finished Jun 11 12:30:51 PM PDT 24
Peak memory 200364 kb
Host smart-040c9769-4a48-4bd9-bee8-f27a1399ec07
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96798593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.96798593
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.1156042465
Short name T849
Test name
Test status
Simulation time 83883903813 ps
CPU time 808.48 seconds
Started Jun 11 12:30:20 PM PDT 24
Finished Jun 11 12:43:51 PM PDT 24
Peak memory 200368 kb
Host smart-0987940b-743b-40d7-a718-9d3ce4172c6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1156042465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.1156042465
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.4263876504
Short name T715
Test name
Test status
Simulation time 1362620854 ps
CPU time 3.37 seconds
Started Jun 11 12:30:16 PM PDT 24
Finished Jun 11 12:30:23 PM PDT 24
Peak memory 196968 kb
Host smart-78ccaf3a-3fb4-41a9-9e0a-c07d1e2202e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263876504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.4263876504
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_perf.4161601751
Short name T270
Test name
Test status
Simulation time 10043543433 ps
CPU time 188.94 seconds
Started Jun 11 12:30:16 PM PDT 24
Finished Jun 11 12:33:28 PM PDT 24
Peak memory 200176 kb
Host smart-4e4808e1-9025-44b3-8e6c-77e0c7dcd1aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4161601751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.4161601751
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.3770081229
Short name T389
Test name
Test status
Simulation time 5005802476 ps
CPU time 14.61 seconds
Started Jun 11 12:30:16 PM PDT 24
Finished Jun 11 12:30:34 PM PDT 24
Peak memory 198628 kb
Host smart-6bac1341-7992-4803-a3c2-0acf047e7eb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3770081229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.3770081229
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.3622491842
Short name T440
Test name
Test status
Simulation time 70206804683 ps
CPU time 103.97 seconds
Started Jun 11 12:30:17 PM PDT 24
Finished Jun 11 12:32:04 PM PDT 24
Peak memory 200328 kb
Host smart-03d7135e-b39b-48bc-8add-daaaa29afc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622491842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.3622491842
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.2511881412
Short name T845
Test name
Test status
Simulation time 34966272468 ps
CPU time 14.51 seconds
Started Jun 11 12:30:14 PM PDT 24
Finished Jun 11 12:30:31 PM PDT 24
Peak memory 196328 kb
Host smart-a22a7857-d9b9-423d-8f62-eaa1e95bd5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511881412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.2511881412
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.372937247
Short name T936
Test name
Test status
Simulation time 624074247 ps
CPU time 2.7 seconds
Started Jun 11 12:30:15 PM PDT 24
Finished Jun 11 12:30:21 PM PDT 24
Peak memory 199208 kb
Host smart-108609b8-b2e0-4ebe-b807-15571b7e61b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372937247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.372937247
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.2611836335
Short name T699
Test name
Test status
Simulation time 70355978915 ps
CPU time 36.29 seconds
Started Jun 11 12:30:14 PM PDT 24
Finished Jun 11 12:30:52 PM PDT 24
Peak memory 200168 kb
Host smart-f3f6ed0a-82c7-4d71-b513-49dafea2b813
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611836335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.2611836335
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.3579038589
Short name T37
Test name
Test status
Simulation time 68106762223 ps
CPU time 683.45 seconds
Started Jun 11 12:30:15 PM PDT 24
Finished Jun 11 12:41:41 PM PDT 24
Peak memory 214580 kb
Host smart-9c9bbcdd-2be2-40b2-a136-ce233f3800a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579038589 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.3579038589
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.1434729844
Short name T519
Test name
Test status
Simulation time 1245137138 ps
CPU time 1.67 seconds
Started Jun 11 12:30:21 PM PDT 24
Finished Jun 11 12:30:25 PM PDT 24
Peak memory 200160 kb
Host smart-cdf12e6e-7426-4c5f-bc60-1b2005c3e6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434729844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.1434729844
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.3871902407
Short name T798
Test name
Test status
Simulation time 37515775265 ps
CPU time 71.03 seconds
Started Jun 11 12:30:35 PM PDT 24
Finished Jun 11 12:31:47 PM PDT 24
Peak memory 200308 kb
Host smart-1a608934-d5ab-4f17-ae5c-072ce8e06d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871902407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.3871902407
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.2836716520
Short name T438
Test name
Test status
Simulation time 14257154 ps
CPU time 0.59 seconds
Started Jun 11 12:30:33 PM PDT 24
Finished Jun 11 12:30:35 PM PDT 24
Peak memory 195716 kb
Host smart-5677e99a-6e64-49fe-a50e-ad4826688181
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836716520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.2836716520
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.928676877
Short name T31
Test name
Test status
Simulation time 58092300388 ps
CPU time 26.74 seconds
Started Jun 11 12:30:14 PM PDT 24
Finished Jun 11 12:30:43 PM PDT 24
Peak memory 200192 kb
Host smart-70ee272f-0377-4edb-8575-755c9625c5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928676877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.928676877
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.2261822371
Short name T698
Test name
Test status
Simulation time 42072395048 ps
CPU time 8.16 seconds
Started Jun 11 12:30:16 PM PDT 24
Finished Jun 11 12:30:27 PM PDT 24
Peak memory 200048 kb
Host smart-1aa24a31-d1a8-4fcb-bec9-0ac42de6a2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261822371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.2261822371
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.126440873
Short name T382
Test name
Test status
Simulation time 17724148607 ps
CPU time 13.66 seconds
Started Jun 11 12:30:16 PM PDT 24
Finished Jun 11 12:30:33 PM PDT 24
Peak memory 200336 kb
Host smart-866d7205-e153-4bbc-9351-19dd293b59ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126440873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.126440873
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.4105719172
Short name T1045
Test name
Test status
Simulation time 161378963061 ps
CPU time 355.06 seconds
Started Jun 11 12:30:29 PM PDT 24
Finished Jun 11 12:36:25 PM PDT 24
Peak memory 200356 kb
Host smart-15189838-b2bc-4b0b-9df7-a7bea2f64563
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105719172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.4105719172
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.1829408100
Short name T760
Test name
Test status
Simulation time 123399945810 ps
CPU time 181.41 seconds
Started Jun 11 12:30:34 PM PDT 24
Finished Jun 11 12:33:37 PM PDT 24
Peak memory 200364 kb
Host smart-c24ce317-703f-4b08-92f5-eba2a1a4ec26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1829408100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.1829408100
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.437229807
Short name T4
Test name
Test status
Simulation time 4959047500 ps
CPU time 2.64 seconds
Started Jun 11 12:30:28 PM PDT 24
Finished Jun 11 12:30:31 PM PDT 24
Peak memory 197624 kb
Host smart-d2d79086-2686-4a8d-a657-48332a02a824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437229807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.437229807
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.2662548597
Short name T609
Test name
Test status
Simulation time 6547387632 ps
CPU time 11.92 seconds
Started Jun 11 12:30:32 PM PDT 24
Finished Jun 11 12:30:45 PM PDT 24
Peak memory 200108 kb
Host smart-7a2f2c80-d70a-43f8-bd00-8a7bff578335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662548597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.2662548597
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.1549743377
Short name T426
Test name
Test status
Simulation time 13143598668 ps
CPU time 673.4 seconds
Started Jun 11 12:30:27 PM PDT 24
Finished Jun 11 12:41:41 PM PDT 24
Peak memory 200256 kb
Host smart-c4ae0cae-6e37-407e-89b4-e851824e9d88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1549743377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.1549743377
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.2138617192
Short name T720
Test name
Test status
Simulation time 3481973905 ps
CPU time 7.19 seconds
Started Jun 11 12:30:15 PM PDT 24
Finished Jun 11 12:30:25 PM PDT 24
Peak memory 199164 kb
Host smart-c0b9f80b-f741-4433-a308-05fc4ad23f19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2138617192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.2138617192
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.1859921051
Short name T287
Test name
Test status
Simulation time 198216983715 ps
CPU time 268.87 seconds
Started Jun 11 12:30:37 PM PDT 24
Finished Jun 11 12:35:07 PM PDT 24
Peak memory 200284 kb
Host smart-6f3553e6-f9f8-47d9-9be6-753d22f37dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859921051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.1859921051
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.4118199097
Short name T367
Test name
Test status
Simulation time 447873724 ps
CPU time 1.32 seconds
Started Jun 11 12:30:36 PM PDT 24
Finished Jun 11 12:30:39 PM PDT 24
Peak memory 195612 kb
Host smart-5ff0c68e-2ff0-4005-8c7e-cf900100cc3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118199097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.4118199097
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.1462545764
Short name T498
Test name
Test status
Simulation time 888589985 ps
CPU time 2.87 seconds
Started Jun 11 12:30:17 PM PDT 24
Finished Jun 11 12:30:23 PM PDT 24
Peak memory 198680 kb
Host smart-3d87992d-856a-432a-a393-1af795fd3c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462545764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.1462545764
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.394338905
Short name T1098
Test name
Test status
Simulation time 10743802221 ps
CPU time 37.39 seconds
Started Jun 11 12:30:42 PM PDT 24
Finished Jun 11 12:31:20 PM PDT 24
Peak memory 200364 kb
Host smart-857f9e87-2b6c-4ad5-9634-e6e98c173da2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394338905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.394338905
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.551208077
Short name T268
Test name
Test status
Simulation time 318115474 ps
CPU time 1.25 seconds
Started Jun 11 12:30:30 PM PDT 24
Finished Jun 11 12:30:32 PM PDT 24
Peak memory 197108 kb
Host smart-475c8dbf-bf9f-41fc-856d-357e1306e12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551208077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.551208077
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.3551680724
Short name T801
Test name
Test status
Simulation time 126366913077 ps
CPU time 153.17 seconds
Started Jun 11 12:30:19 PM PDT 24
Finished Jun 11 12:32:55 PM PDT 24
Peak memory 200300 kb
Host smart-1cd4c61b-b762-4a52-9160-e0ca8a9bcf3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551680724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.3551680724
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.3824349202
Short name T550
Test name
Test status
Simulation time 11417619 ps
CPU time 0.54 seconds
Started Jun 11 12:30:32 PM PDT 24
Finished Jun 11 12:30:34 PM PDT 24
Peak memory 195700 kb
Host smart-fb98b5ba-37d0-4192-bca2-d4bae175eb91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824349202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.3824349202
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.2055061460
Short name T1079
Test name
Test status
Simulation time 232531609057 ps
CPU time 80.76 seconds
Started Jun 11 12:30:30 PM PDT 24
Finished Jun 11 12:31:52 PM PDT 24
Peak memory 200356 kb
Host smart-0ffe21db-436e-401b-b6bc-893e4a26a64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055061460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.2055061460
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.2821432182
Short name T902
Test name
Test status
Simulation time 54208079772 ps
CPU time 10.3 seconds
Started Jun 11 12:30:34 PM PDT 24
Finished Jun 11 12:30:46 PM PDT 24
Peak memory 200200 kb
Host smart-e04b4b42-8a3b-4f15-8105-20803fe53b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821432182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.2821432182
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.3246888099
Short name T628
Test name
Test status
Simulation time 275590179549 ps
CPU time 257.03 seconds
Started Jun 11 12:30:40 PM PDT 24
Finished Jun 11 12:34:58 PM PDT 24
Peak memory 200284 kb
Host smart-0808ff15-1c87-4581-bb80-659a67201601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246888099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.3246888099
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.4015649234
Short name T771
Test name
Test status
Simulation time 39395167804 ps
CPU time 21 seconds
Started Jun 11 12:30:28 PM PDT 24
Finished Jun 11 12:30:49 PM PDT 24
Peak memory 200160 kb
Host smart-1c282af2-e8a8-496c-8dd3-adcb4074df7c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015649234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.4015649234
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.3673850071
Short name T559
Test name
Test status
Simulation time 140263956631 ps
CPU time 320.76 seconds
Started Jun 11 12:30:34 PM PDT 24
Finished Jun 11 12:35:57 PM PDT 24
Peak memory 200168 kb
Host smart-14335b35-49bf-4f20-bfd2-0732c2599946
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3673850071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.3673850071
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.3973829962
Short name T749
Test name
Test status
Simulation time 7435873673 ps
CPU time 4.16 seconds
Started Jun 11 12:30:28 PM PDT 24
Finished Jun 11 12:30:33 PM PDT 24
Peak memory 199156 kb
Host smart-7e81e36d-51aa-4edd-b3b5-2e4398d2cb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973829962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.3973829962
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.872962815
Short name T835
Test name
Test status
Simulation time 85885154829 ps
CPU time 6.76 seconds
Started Jun 11 12:30:30 PM PDT 24
Finished Jun 11 12:30:38 PM PDT 24
Peak memory 196772 kb
Host smart-73b8f509-9110-463a-a2a6-f9b0d18a8222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872962815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.872962815
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.3209099793
Short name T846
Test name
Test status
Simulation time 12549014339 ps
CPU time 76.47 seconds
Started Jun 11 12:30:34 PM PDT 24
Finished Jun 11 12:31:52 PM PDT 24
Peak memory 200280 kb
Host smart-588e8c77-80e3-40bf-a690-7affb447d604
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3209099793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.3209099793
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.2877963710
Short name T962
Test name
Test status
Simulation time 3699913613 ps
CPU time 9.08 seconds
Started Jun 11 12:30:30 PM PDT 24
Finished Jun 11 12:30:41 PM PDT 24
Peak memory 199456 kb
Host smart-b2c914e0-98e2-47b0-9a38-282d5c3b8bba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2877963710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.2877963710
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.3506486360
Short name T132
Test name
Test status
Simulation time 54691138824 ps
CPU time 33.15 seconds
Started Jun 11 12:30:29 PM PDT 24
Finished Jun 11 12:31:04 PM PDT 24
Peak memory 200120 kb
Host smart-41da7787-d4ff-4e12-9d31-c50c45b952ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506486360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.3506486360
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.270724379
Short name T605
Test name
Test status
Simulation time 33676703151 ps
CPU time 54.49 seconds
Started Jun 11 12:30:31 PM PDT 24
Finished Jun 11 12:31:27 PM PDT 24
Peak memory 196496 kb
Host smart-09ff13c1-f9c2-488c-a0ce-1d13bb0b35ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270724379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.270724379
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.3120894274
Short name T1043
Test name
Test status
Simulation time 935723805 ps
CPU time 2.95 seconds
Started Jun 11 12:30:29 PM PDT 24
Finished Jun 11 12:30:33 PM PDT 24
Peak memory 199644 kb
Host smart-b625be02-e48f-4c5a-8ae5-d61550e2d1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120894274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.3120894274
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.1803381693
Short name T9
Test name
Test status
Simulation time 39987850597 ps
CPU time 787.85 seconds
Started Jun 11 12:30:33 PM PDT 24
Finished Jun 11 12:43:43 PM PDT 24
Peak memory 216864 kb
Host smart-f5806179-c11c-44b1-93f9-36b58d489620
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803381693 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.1803381693
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.2496271089
Short name T540
Test name
Test status
Simulation time 6588269096 ps
CPU time 2.33 seconds
Started Jun 11 12:30:35 PM PDT 24
Finished Jun 11 12:30:39 PM PDT 24
Peak memory 200260 kb
Host smart-bfe0706e-5c80-431e-b7de-07f5db3e333c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496271089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.2496271089
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.3681872004
Short name T337
Test name
Test status
Simulation time 35428115252 ps
CPU time 59.73 seconds
Started Jun 11 12:30:33 PM PDT 24
Finished Jun 11 12:31:34 PM PDT 24
Peak memory 200256 kb
Host smart-848c3e70-3fd2-463f-813b-d5f5c530ee4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681872004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.3681872004
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.2217263138
Short name T725
Test name
Test status
Simulation time 31012403 ps
CPU time 0.56 seconds
Started Jun 11 12:30:35 PM PDT 24
Finished Jun 11 12:30:37 PM PDT 24
Peak memory 195688 kb
Host smart-cf273671-fdf2-41cb-8102-18cf1f1568a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217263138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.2217263138
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.3388783358
Short name T618
Test name
Test status
Simulation time 14986467004 ps
CPU time 24.9 seconds
Started Jun 11 12:30:37 PM PDT 24
Finished Jun 11 12:31:03 PM PDT 24
Peak memory 200360 kb
Host smart-89fa671c-a183-400c-bd4f-e81061d5def1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388783358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.3388783358
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.3222195047
Short name T409
Test name
Test status
Simulation time 261203358486 ps
CPU time 42.19 seconds
Started Jun 11 12:30:34 PM PDT 24
Finished Jun 11 12:31:18 PM PDT 24
Peak memory 199708 kb
Host smart-10e39583-6b54-408a-814a-9142759fd2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222195047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.3222195047
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.2170100216
Short name T150
Test name
Test status
Simulation time 106921359247 ps
CPU time 20.95 seconds
Started Jun 11 12:30:29 PM PDT 24
Finished Jun 11 12:30:51 PM PDT 24
Peak memory 200172 kb
Host smart-2cb126ea-3e25-4943-9670-830d1cddc03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170100216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.2170100216
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.980102340
Short name T704
Test name
Test status
Simulation time 82336747503 ps
CPU time 33.75 seconds
Started Jun 11 12:30:31 PM PDT 24
Finished Jun 11 12:31:06 PM PDT 24
Peak memory 200236 kb
Host smart-cdf0c580-c057-4409-9cbd-9ac545543253
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980102340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.980102340
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.1528518445
Short name T541
Test name
Test status
Simulation time 78962284126 ps
CPU time 110.92 seconds
Started Jun 11 12:30:34 PM PDT 24
Finished Jun 11 12:32:27 PM PDT 24
Peak memory 200284 kb
Host smart-84fee45d-90fe-485f-a81f-fca3a2ff2e79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1528518445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.1528518445
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.1906392730
Short name T918
Test name
Test status
Simulation time 3941535740 ps
CPU time 2.03 seconds
Started Jun 11 12:30:34 PM PDT 24
Finished Jun 11 12:30:37 PM PDT 24
Peak memory 198824 kb
Host smart-81b8d72e-402c-4319-a952-c87f2e7f85da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906392730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.1906392730
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_perf.3890394140
Short name T401
Test name
Test status
Simulation time 24060244574 ps
CPU time 1074.21 seconds
Started Jun 11 12:30:31 PM PDT 24
Finished Jun 11 12:48:27 PM PDT 24
Peak memory 200232 kb
Host smart-400290d5-e910-4e93-b515-6300948b9e4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3890394140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.3890394140
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.1266429618
Short name T358
Test name
Test status
Simulation time 1703487444 ps
CPU time 5.52 seconds
Started Jun 11 12:30:34 PM PDT 24
Finished Jun 11 12:30:40 PM PDT 24
Peak memory 199436 kb
Host smart-304eedb8-c087-4c8d-9fba-a09415248960
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1266429618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.1266429618
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.295812412
Short name T754
Test name
Test status
Simulation time 104645811260 ps
CPU time 119.33 seconds
Started Jun 11 12:30:37 PM PDT 24
Finished Jun 11 12:32:37 PM PDT 24
Peak memory 200296 kb
Host smart-442ae1ed-c3a8-491d-a0f1-46b109fa42ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295812412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.295812412
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.3178426330
Short name T826
Test name
Test status
Simulation time 2277847191 ps
CPU time 4.03 seconds
Started Jun 11 12:30:30 PM PDT 24
Finished Jun 11 12:30:35 PM PDT 24
Peak memory 195672 kb
Host smart-3db10f10-b331-4ecf-b17e-11a8a4e8089d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178426330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.3178426330
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.4272409507
Short name T406
Test name
Test status
Simulation time 88431534 ps
CPU time 0.76 seconds
Started Jun 11 12:30:29 PM PDT 24
Finished Jun 11 12:30:31 PM PDT 24
Peak memory 198264 kb
Host smart-974efb69-b573-4135-9b89-191d96ba061e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272409507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.4272409507
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.3409365206
Short name T587
Test name
Test status
Simulation time 110667036695 ps
CPU time 138.21 seconds
Started Jun 11 12:30:30 PM PDT 24
Finished Jun 11 12:32:49 PM PDT 24
Peak memory 200440 kb
Host smart-8836c57c-06d0-4462-80d8-6cf406dc556a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409365206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.3409365206
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.364256763
Short name T1025
Test name
Test status
Simulation time 47075618217 ps
CPU time 147.85 seconds
Started Jun 11 12:30:31 PM PDT 24
Finished Jun 11 12:33:00 PM PDT 24
Peak memory 209096 kb
Host smart-4c838160-06ba-456a-b705-4f43f611b078
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364256763 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.364256763
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.2893486518
Short name T5
Test name
Test status
Simulation time 6606958432 ps
CPU time 20.99 seconds
Started Jun 11 12:30:36 PM PDT 24
Finished Jun 11 12:30:59 PM PDT 24
Peak memory 200452 kb
Host smart-2c23d888-7857-450f-b898-decccea3bd9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893486518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.2893486518
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.1543103409
Short name T660
Test name
Test status
Simulation time 35092613222 ps
CPU time 14.6 seconds
Started Jun 11 12:30:43 PM PDT 24
Finished Jun 11 12:30:58 PM PDT 24
Peak memory 198596 kb
Host smart-e6b74733-3457-4bcf-a2e3-a239eec17c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543103409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.1543103409
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.1376586862
Short name T607
Test name
Test status
Simulation time 18741926 ps
CPU time 0.55 seconds
Started Jun 11 12:30:46 PM PDT 24
Finished Jun 11 12:30:47 PM PDT 24
Peak memory 195592 kb
Host smart-954477c3-0e37-4955-bcce-470bce967b5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376586862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.1376586862
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.1880027306
Short name T638
Test name
Test status
Simulation time 111617973833 ps
CPU time 78.67 seconds
Started Jun 11 12:30:31 PM PDT 24
Finished Jun 11 12:31:51 PM PDT 24
Peak memory 200204 kb
Host smart-a9194335-9f83-480f-8b8e-76afcbde2845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880027306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.1880027306
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.3338325901
Short name T806
Test name
Test status
Simulation time 98987677951 ps
CPU time 36.2 seconds
Started Jun 11 12:30:36 PM PDT 24
Finished Jun 11 12:31:14 PM PDT 24
Peak memory 198932 kb
Host smart-87420b8b-a452-413b-8768-99f9fca15719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338325901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.3338325901
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.3896516816
Short name T263
Test name
Test status
Simulation time 20393475058 ps
CPU time 20.51 seconds
Started Jun 11 12:30:30 PM PDT 24
Finished Jun 11 12:30:51 PM PDT 24
Peak memory 200288 kb
Host smart-60aca305-3117-45ff-bef0-dce887f95758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896516816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.3896516816
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.522779899
Short name T293
Test name
Test status
Simulation time 174085822437 ps
CPU time 66.87 seconds
Started Jun 11 12:30:29 PM PDT 24
Finished Jun 11 12:31:37 PM PDT 24
Peak memory 200184 kb
Host smart-2d3cdb69-0276-4b42-91c7-ff904cbe5f02
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522779899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.522779899
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.3795943808
Short name T374
Test name
Test status
Simulation time 109354970976 ps
CPU time 938.86 seconds
Started Jun 11 12:30:30 PM PDT 24
Finished Jun 11 12:46:11 PM PDT 24
Peak memory 200368 kb
Host smart-53676a80-850d-4628-8a05-07c6deb807c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3795943808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.3795943808
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.3721722105
Short name T913
Test name
Test status
Simulation time 7614883643 ps
CPU time 8.2 seconds
Started Jun 11 12:30:34 PM PDT 24
Finished Jun 11 12:30:44 PM PDT 24
Peak memory 198480 kb
Host smart-d80e3a2d-8cb3-4d10-a0e8-e8f369318e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721722105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.3721722105
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_perf.279420660
Short name T387
Test name
Test status
Simulation time 15047536278 ps
CPU time 178.67 seconds
Started Jun 11 12:30:39 PM PDT 24
Finished Jun 11 12:33:38 PM PDT 24
Peak memory 200268 kb
Host smart-9555cb0a-70e6-4075-930c-fa642fb32edb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=279420660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.279420660
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.2369680747
Short name T324
Test name
Test status
Simulation time 2444215367 ps
CPU time 7.2 seconds
Started Jun 11 12:30:34 PM PDT 24
Finished Jun 11 12:30:42 PM PDT 24
Peak memory 199280 kb
Host smart-c08b921c-41e8-43ba-8278-dc81b8d45300
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2369680747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.2369680747
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.2384365566
Short name T452
Test name
Test status
Simulation time 46996995280 ps
CPU time 38.24 seconds
Started Jun 11 12:30:29 PM PDT 24
Finished Jun 11 12:31:09 PM PDT 24
Peak memory 200156 kb
Host smart-380d68cc-f77f-475e-9546-2ba7011af06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384365566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.2384365566
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.3148681884
Short name T686
Test name
Test status
Simulation time 593058700 ps
CPU time 0.9 seconds
Started Jun 11 12:30:29 PM PDT 24
Finished Jun 11 12:30:32 PM PDT 24
Peak memory 195856 kb
Host smart-023d94ea-95de-4b45-bf56-0b0c4a89f0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148681884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.3148681884
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.3406641465
Short name T425
Test name
Test status
Simulation time 5567874083 ps
CPU time 9.27 seconds
Started Jun 11 12:30:30 PM PDT 24
Finished Jun 11 12:30:40 PM PDT 24
Peak memory 200308 kb
Host smart-677a84da-d2e6-4b02-86f1-d2c74f994bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406641465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.3406641465
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.419407492
Short name T328
Test name
Test status
Simulation time 204418401695 ps
CPU time 78.09 seconds
Started Jun 11 12:30:46 PM PDT 24
Finished Jun 11 12:32:06 PM PDT 24
Peak memory 200276 kb
Host smart-c0d9c744-bfb5-40e1-82ef-426a57174de5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419407492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.419407492
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.167094651
Short name T580
Test name
Test status
Simulation time 99406557095 ps
CPU time 1378.86 seconds
Started Jun 11 12:30:41 PM PDT 24
Finished Jun 11 12:53:41 PM PDT 24
Peak memory 225016 kb
Host smart-a92c0f69-cd41-4fcf-bf74-5031a97e9c3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167094651 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.167094651
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.3280486923
Short name T736
Test name
Test status
Simulation time 1126159197 ps
CPU time 1.92 seconds
Started Jun 11 12:30:29 PM PDT 24
Finished Jun 11 12:30:33 PM PDT 24
Peak memory 199080 kb
Host smart-957d6de3-f384-48d0-8877-6c5bebc8829d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280486923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.3280486923
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.1311029431
Short name T243
Test name
Test status
Simulation time 54866150105 ps
CPU time 86.94 seconds
Started Jun 11 12:30:31 PM PDT 24
Finished Jun 11 12:32:00 PM PDT 24
Peak memory 200224 kb
Host smart-bd517f62-1f43-4c3a-9635-dd97107044ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311029431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.1311029431
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.2701426903
Short name T640
Test name
Test status
Simulation time 22506625 ps
CPU time 0.54 seconds
Started Jun 11 12:30:44 PM PDT 24
Finished Jun 11 12:30:46 PM PDT 24
Peak memory 195720 kb
Host smart-8764eed4-285a-4314-8021-0a67c4b3746b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701426903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.2701426903
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.1617772935
Short name T464
Test name
Test status
Simulation time 32976261402 ps
CPU time 52.14 seconds
Started Jun 11 12:30:48 PM PDT 24
Finished Jun 11 12:31:42 PM PDT 24
Peak memory 200216 kb
Host smart-4ab7492b-39b1-4657-98a4-f94a773cfb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617772935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.1617772935
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.1446730389
Short name T914
Test name
Test status
Simulation time 40578548481 ps
CPU time 42.09 seconds
Started Jun 11 12:30:49 PM PDT 24
Finished Jun 11 12:31:33 PM PDT 24
Peak memory 200312 kb
Host smart-be35bce9-df12-4f48-babe-4ae42cc3facf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446730389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.1446730389
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_intr.1599537808
Short name T899
Test name
Test status
Simulation time 47225750767 ps
CPU time 41.04 seconds
Started Jun 11 12:30:48 PM PDT 24
Finished Jun 11 12:31:31 PM PDT 24
Peak memory 200360 kb
Host smart-523c8674-c89c-47fa-bae6-c55b27ecb9c9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599537808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.1599537808
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.1514169459
Short name T499
Test name
Test status
Simulation time 143053448737 ps
CPU time 1118.46 seconds
Started Jun 11 12:30:47 PM PDT 24
Finished Jun 11 12:49:27 PM PDT 24
Peak memory 200300 kb
Host smart-b2997e3c-1989-4d65-b7aa-42c1deaadcdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1514169459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.1514169459
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.4289391525
Short name T339
Test name
Test status
Simulation time 8232257321 ps
CPU time 16.66 seconds
Started Jun 11 12:30:49 PM PDT 24
Finished Jun 11 12:31:08 PM PDT 24
Peak memory 200164 kb
Host smart-1e5078e9-9c55-4e97-bcff-2f33ed3ac7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289391525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.4289391525
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_perf.2143742969
Short name T1030
Test name
Test status
Simulation time 22866237386 ps
CPU time 312.88 seconds
Started Jun 11 12:30:45 PM PDT 24
Finished Jun 11 12:36:00 PM PDT 24
Peak memory 200096 kb
Host smart-d275efc5-a912-44ab-8626-dae1a45d28aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2143742969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.2143742969
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.404107205
Short name T507
Test name
Test status
Simulation time 3575211955 ps
CPU time 7.23 seconds
Started Jun 11 12:30:49 PM PDT 24
Finished Jun 11 12:30:58 PM PDT 24
Peak memory 198772 kb
Host smart-fd111896-4507-482d-a5aa-a03cf4437cee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=404107205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.404107205
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.74356059
Short name T455
Test name
Test status
Simulation time 22478920762 ps
CPU time 32.26 seconds
Started Jun 11 12:30:47 PM PDT 24
Finished Jun 11 12:31:22 PM PDT 24
Peak memory 199720 kb
Host smart-f47890c7-3790-4bea-880e-e9516efe9ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74356059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.74356059
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.1129268349
Short name T1074
Test name
Test status
Simulation time 1609616687 ps
CPU time 1.67 seconds
Started Jun 11 12:30:47 PM PDT 24
Finished Jun 11 12:30:50 PM PDT 24
Peak memory 195692 kb
Host smart-f9480f2c-daa6-4d4a-89a4-a36372e34504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129268349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.1129268349
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.1974335320
Short name T694
Test name
Test status
Simulation time 288116818 ps
CPU time 1.35 seconds
Started Jun 11 12:30:47 PM PDT 24
Finished Jun 11 12:30:50 PM PDT 24
Peak memory 198624 kb
Host smart-c42af9e6-d208-4812-a5d2-2dd8414ecb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974335320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.1974335320
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.1581612973
Short name T87
Test name
Test status
Simulation time 6956218661 ps
CPU time 20.77 seconds
Started Jun 11 12:30:44 PM PDT 24
Finished Jun 11 12:31:06 PM PDT 24
Peak memory 200188 kb
Host smart-c864f1b4-d23f-4805-ba41-1d77d6dd439e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581612973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.1581612973
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.1284511530
Short name T721
Test name
Test status
Simulation time 28375559482 ps
CPU time 40.82 seconds
Started Jun 11 12:30:49 PM PDT 24
Finished Jun 11 12:31:32 PM PDT 24
Peak memory 200276 kb
Host smart-c6e87c31-c102-4f9f-86a2-04067a1cd302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284511530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.1284511530
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.2878409224
Short name T955
Test name
Test status
Simulation time 14271195 ps
CPU time 0.57 seconds
Started Jun 11 12:30:45 PM PDT 24
Finished Jun 11 12:30:47 PM PDT 24
Peak memory 195640 kb
Host smart-b03e9165-aa62-4928-af6a-1a999437900b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878409224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.2878409224
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.1979485435
Short name T576
Test name
Test status
Simulation time 41762784246 ps
CPU time 85.49 seconds
Started Jun 11 12:30:50 PM PDT 24
Finished Jun 11 12:32:17 PM PDT 24
Peak memory 200284 kb
Host smart-19357048-1a1f-4cd4-b53a-649d33b5841e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979485435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.1979485435
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.2711619407
Short name T1066
Test name
Test status
Simulation time 159948502907 ps
CPU time 136.49 seconds
Started Jun 11 12:30:46 PM PDT 24
Finished Jun 11 12:33:04 PM PDT 24
Peak memory 200320 kb
Host smart-9d770139-f88e-483e-893b-bec7c931dfe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711619407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.2711619407
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_intr.787878696
Short name T903
Test name
Test status
Simulation time 33454682352 ps
CPU time 26.41 seconds
Started Jun 11 12:30:47 PM PDT 24
Finished Jun 11 12:31:16 PM PDT 24
Peak memory 199700 kb
Host smart-3617e803-d104-4322-b691-ebee4e977976
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787878696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.787878696
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.1269656270
Short name T960
Test name
Test status
Simulation time 192758534953 ps
CPU time 573.95 seconds
Started Jun 11 12:30:49 PM PDT 24
Finished Jun 11 12:40:26 PM PDT 24
Peak memory 200264 kb
Host smart-3327a5d3-54de-4ec4-81e8-b69c2216b300
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1269656270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.1269656270
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.2078689329
Short name T832
Test name
Test status
Simulation time 8951565808 ps
CPU time 13.95 seconds
Started Jun 11 12:30:46 PM PDT 24
Finished Jun 11 12:31:01 PM PDT 24
Peak memory 197768 kb
Host smart-d75c1a8e-bbf7-4606-b22b-e3dbaf3fa346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078689329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.2078689329
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_perf.1596234144
Short name T430
Test name
Test status
Simulation time 563796713 ps
CPU time 6.8 seconds
Started Jun 11 12:30:48 PM PDT 24
Finished Jun 11 12:30:56 PM PDT 24
Peak memory 199892 kb
Host smart-85483591-d4f7-44f9-a1b4-bd7e58eb685c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1596234144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.1596234144
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.1456869197
Short name T366
Test name
Test status
Simulation time 3928101657 ps
CPU time 6.63 seconds
Started Jun 11 12:30:49 PM PDT 24
Finished Jun 11 12:30:58 PM PDT 24
Peak memory 199308 kb
Host smart-e413c49d-16a3-46e7-869d-c96c4710f1a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1456869197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.1456869197
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.2104605356
Short name T511
Test name
Test status
Simulation time 29200815768 ps
CPU time 42.22 seconds
Started Jun 11 12:30:48 PM PDT 24
Finished Jun 11 12:31:32 PM PDT 24
Peak memory 200248 kb
Host smart-f51ee294-08a9-4712-b880-02695bb5ac55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104605356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.2104605356
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.2281118439
Short name T588
Test name
Test status
Simulation time 1924334087 ps
CPU time 3.17 seconds
Started Jun 11 12:30:49 PM PDT 24
Finished Jun 11 12:30:54 PM PDT 24
Peak memory 195684 kb
Host smart-36c7ea39-2314-44be-b1a9-09d87f95186a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281118439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.2281118439
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.2289836599
Short name T436
Test name
Test status
Simulation time 11592796380 ps
CPU time 17.05 seconds
Started Jun 11 12:30:45 PM PDT 24
Finished Jun 11 12:31:03 PM PDT 24
Peak memory 200148 kb
Host smart-f28b42da-5d7d-4aa0-8d36-569efe3a6811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289836599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.2289836599
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.899911722
Short name T888
Test name
Test status
Simulation time 7564480921 ps
CPU time 23.37 seconds
Started Jun 11 12:30:50 PM PDT 24
Finished Jun 11 12:31:15 PM PDT 24
Peak memory 200168 kb
Host smart-c77b4f37-acd8-4604-940a-4fb4da356166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899911722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.899911722
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.937922477
Short name T1004
Test name
Test status
Simulation time 74023541332 ps
CPU time 153.59 seconds
Started Jun 11 12:30:46 PM PDT 24
Finished Jun 11 12:33:21 PM PDT 24
Peak memory 200264 kb
Host smart-8d726c53-431b-48f3-a7b8-2c7fe56ebe98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937922477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.937922477
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.3890951454
Short name T351
Test name
Test status
Simulation time 16653687 ps
CPU time 0.56 seconds
Started Jun 11 12:29:08 PM PDT 24
Finished Jun 11 12:29:10 PM PDT 24
Peak memory 195676 kb
Host smart-68681e86-e607-41ed-8bc0-54d6bb2fba84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890951454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.3890951454
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.913787256
Short name T412
Test name
Test status
Simulation time 30723706220 ps
CPU time 47.5 seconds
Started Jun 11 12:29:16 PM PDT 24
Finished Jun 11 12:30:05 PM PDT 24
Peak memory 200272 kb
Host smart-e6e301f5-d176-4b39-92d1-c2ae26741de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913787256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.913787256
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.1497588878
Short name T642
Test name
Test status
Simulation time 16851862839 ps
CPU time 29.65 seconds
Started Jun 11 12:29:08 PM PDT 24
Finished Jun 11 12:29:39 PM PDT 24
Peak memory 200300 kb
Host smart-71eb5dcc-725d-428a-a097-a8205743b753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497588878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.1497588878
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_intr.3869129692
Short name T743
Test name
Test status
Simulation time 11041423712 ps
CPU time 4.86 seconds
Started Jun 11 12:29:21 PM PDT 24
Finished Jun 11 12:29:28 PM PDT 24
Peak memory 196908 kb
Host smart-58b6ce06-e4eb-4eeb-8744-b5ec2d732e38
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869129692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.3869129692
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.546212003
Short name T741
Test name
Test status
Simulation time 135092362080 ps
CPU time 360.93 seconds
Started Jun 11 12:29:06 PM PDT 24
Finished Jun 11 12:35:09 PM PDT 24
Peak memory 200192 kb
Host smart-4bea0c0b-722c-4518-9b3d-ccdbf719f215
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=546212003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.546212003
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.2804468787
Short name T447
Test name
Test status
Simulation time 4002051814 ps
CPU time 7.15 seconds
Started Jun 11 12:29:17 PM PDT 24
Finished Jun 11 12:29:25 PM PDT 24
Peak memory 199188 kb
Host smart-8794d1d8-aa20-4220-bc4e-5c3ef60edf09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804468787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.2804468787
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_perf.1516387684
Short name T257
Test name
Test status
Simulation time 13711929544 ps
CPU time 185.74 seconds
Started Jun 11 12:29:21 PM PDT 24
Finished Jun 11 12:32:29 PM PDT 24
Peak memory 200236 kb
Host smart-45d9610c-e1ee-45cc-b4bf-44355a4f2770
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1516387684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.1516387684
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.1259044196
Short name T72
Test name
Test status
Simulation time 2236057818 ps
CPU time 4.15 seconds
Started Jun 11 12:29:05 PM PDT 24
Finished Jun 11 12:29:11 PM PDT 24
Peak memory 199268 kb
Host smart-d8add7e6-caee-4c41-a9d4-ffbfb78f45f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1259044196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.1259044196
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.1238414041
Short name T940
Test name
Test status
Simulation time 156653258002 ps
CPU time 22.36 seconds
Started Jun 11 12:29:12 PM PDT 24
Finished Jun 11 12:29:35 PM PDT 24
Peak memory 199652 kb
Host smart-0e97d991-e1d8-4161-90f3-0a1eae76433a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238414041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.1238414041
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.1070338186
Short name T1047
Test name
Test status
Simulation time 6434856201 ps
CPU time 1.96 seconds
Started Jun 11 12:29:02 PM PDT 24
Finished Jun 11 12:29:06 PM PDT 24
Peak memory 196436 kb
Host smart-97494c55-e74c-4a6d-a760-8124ebb3cae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070338186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.1070338186
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.2112178798
Short name T71
Test name
Test status
Simulation time 112004493 ps
CPU time 0.83 seconds
Started Jun 11 12:29:21 PM PDT 24
Finished Jun 11 12:29:23 PM PDT 24
Peak memory 218668 kb
Host smart-1b60fabf-ea5e-4ac5-aa98-5c4ced7800c2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112178798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.2112178798
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.1729345676
Short name T954
Test name
Test status
Simulation time 5603859438 ps
CPU time 4.16 seconds
Started Jun 11 12:29:05 PM PDT 24
Finished Jun 11 12:29:11 PM PDT 24
Peak memory 200112 kb
Host smart-17e96a45-5305-49cf-86ce-e620598af422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729345676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.1729345676
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.3253196587
Short name T1041
Test name
Test status
Simulation time 150426712993 ps
CPU time 905.53 seconds
Started Jun 11 12:29:16 PM PDT 24
Finished Jun 11 12:44:22 PM PDT 24
Peak memory 200188 kb
Host smart-48eadd3a-56e6-48d6-8ccf-12a17a282406
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253196587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.3253196587
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.466768108
Short name T85
Test name
Test status
Simulation time 255116957652 ps
CPU time 253.88 seconds
Started Jun 11 12:29:10 PM PDT 24
Finished Jun 11 12:33:25 PM PDT 24
Peak memory 216856 kb
Host smart-7abbb580-a021-4828-8ac7-9673c273d487
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466768108 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.466768108
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.809376889
Short name T431
Test name
Test status
Simulation time 569100468 ps
CPU time 2.11 seconds
Started Jun 11 12:30:17 PM PDT 24
Finished Jun 11 12:30:22 PM PDT 24
Peak memory 199676 kb
Host smart-c2803d05-7bcf-41a6-beb3-2b79c27ae6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809376889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.809376889
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.3283838064
Short name T345
Test name
Test status
Simulation time 24431482135 ps
CPU time 7.63 seconds
Started Jun 11 12:29:02 PM PDT 24
Finished Jun 11 12:29:12 PM PDT 24
Peak memory 197420 kb
Host smart-1f574e4a-07a1-45d7-bb58-95b9bd384745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283838064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.3283838064
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.2396589709
Short name T664
Test name
Test status
Simulation time 13037930 ps
CPU time 0.55 seconds
Started Jun 11 12:30:46 PM PDT 24
Finished Jun 11 12:30:48 PM PDT 24
Peak memory 194672 kb
Host smart-2193c339-6f41-41dc-9143-468750e7e3a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396589709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.2396589709
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.1281104753
Short name T633
Test name
Test status
Simulation time 44448501422 ps
CPU time 20.52 seconds
Started Jun 11 12:30:47 PM PDT 24
Finished Jun 11 12:31:09 PM PDT 24
Peak memory 200232 kb
Host smart-e202fbed-46cc-46e0-a002-363923333449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281104753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.1281104753
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.1866021279
Short name T873
Test name
Test status
Simulation time 11664541402 ps
CPU time 16.32 seconds
Started Jun 11 12:30:47 PM PDT 24
Finished Jun 11 12:31:04 PM PDT 24
Peak memory 200256 kb
Host smart-cd0c531c-0329-4fb1-a8e7-d86b7c492e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866021279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.1866021279
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.431756110
Short name T808
Test name
Test status
Simulation time 29326686655 ps
CPU time 36.06 seconds
Started Jun 11 12:30:48 PM PDT 24
Finished Jun 11 12:31:27 PM PDT 24
Peak memory 200264 kb
Host smart-60252bc4-7a6b-44d4-b014-568b22eb166b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431756110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.431756110
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.3384443138
Short name T700
Test name
Test status
Simulation time 21216545237 ps
CPU time 4.62 seconds
Started Jun 11 12:30:48 PM PDT 24
Finished Jun 11 12:30:55 PM PDT 24
Peak memory 200252 kb
Host smart-634e9309-92d0-41ea-b0e2-d2179b2f28e1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384443138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.3384443138
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.4204836117
Short name T544
Test name
Test status
Simulation time 134304904782 ps
CPU time 299.26 seconds
Started Jun 11 12:30:49 PM PDT 24
Finished Jun 11 12:35:51 PM PDT 24
Peak memory 200168 kb
Host smart-00864d2f-d14b-4d6d-aa6d-c67ce36b557b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4204836117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.4204836117
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.2427938431
Short name T1083
Test name
Test status
Simulation time 640953748 ps
CPU time 0.83 seconds
Started Jun 11 12:30:48 PM PDT 24
Finished Jun 11 12:30:51 PM PDT 24
Peak memory 197348 kb
Host smart-c2bac247-222c-40c2-91e6-cd4fff16850b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427938431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.2427938431
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_perf.3834541266
Short name T1070
Test name
Test status
Simulation time 17514275086 ps
CPU time 220.6 seconds
Started Jun 11 12:30:49 PM PDT 24
Finished Jun 11 12:34:32 PM PDT 24
Peak memory 200352 kb
Host smart-2bf203c2-10b7-49a2-93bf-f92404015181
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3834541266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.3834541266
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.3965042135
Short name T833
Test name
Test status
Simulation time 5707204848 ps
CPU time 24.44 seconds
Started Jun 11 12:30:47 PM PDT 24
Finished Jun 11 12:31:14 PM PDT 24
Peak memory 199100 kb
Host smart-05236141-b0cd-4433-85f8-715e090e2f7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3965042135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.3965042135
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.1683037717
Short name T450
Test name
Test status
Simulation time 30806724467 ps
CPU time 25.75 seconds
Started Jun 11 12:30:47 PM PDT 24
Finished Jun 11 12:31:14 PM PDT 24
Peak memory 200204 kb
Host smart-1f696d13-11b7-42cc-9dfe-435434529c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683037717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.1683037717
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.2251427891
Short name T253
Test name
Test status
Simulation time 4832187438 ps
CPU time 1.7 seconds
Started Jun 11 12:30:46 PM PDT 24
Finished Jun 11 12:30:50 PM PDT 24
Peak memory 196524 kb
Host smart-a73d56e7-7186-4b8f-8ebb-1c87c071f03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251427891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.2251427891
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.2523460679
Short name T841
Test name
Test status
Simulation time 5795453992 ps
CPU time 16.1 seconds
Started Jun 11 12:30:47 PM PDT 24
Finished Jun 11 12:31:05 PM PDT 24
Peak memory 200316 kb
Host smart-8ef6047b-01b6-4da7-98c0-249784684228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523460679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.2523460679
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.1874705809
Short name T811
Test name
Test status
Simulation time 58732687461 ps
CPU time 657.8 seconds
Started Jun 11 12:30:48 PM PDT 24
Finished Jun 11 12:41:48 PM PDT 24
Peak memory 216740 kb
Host smart-18c69b46-0cd6-42ef-969e-1fcbeb6174f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874705809 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.1874705809
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.3690085029
Short name T245
Test name
Test status
Simulation time 6439919525 ps
CPU time 18.47 seconds
Started Jun 11 12:30:47 PM PDT 24
Finished Jun 11 12:31:07 PM PDT 24
Peak memory 200336 kb
Host smart-d7e88ceb-9997-4f5d-baba-1082cfac8298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690085029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.3690085029
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.2223030087
Short name T581
Test name
Test status
Simulation time 18863270544 ps
CPU time 32.9 seconds
Started Jun 11 12:30:46 PM PDT 24
Finished Jun 11 12:31:21 PM PDT 24
Peak memory 200276 kb
Host smart-81116417-7efa-44e5-8aa6-525d2374577f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223030087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.2223030087
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.1805098680
Short name T369
Test name
Test status
Simulation time 41392220 ps
CPU time 0.55 seconds
Started Jun 11 12:30:51 PM PDT 24
Finished Jun 11 12:30:54 PM PDT 24
Peak memory 195992 kb
Host smart-0a44359d-bd49-4e43-a313-04998ce521e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805098680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.1805098680
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.3294495107
Short name T824
Test name
Test status
Simulation time 21509974407 ps
CPU time 11.79 seconds
Started Jun 11 12:30:49 PM PDT 24
Finished Jun 11 12:31:03 PM PDT 24
Peak memory 200484 kb
Host smart-c3fdafc5-77fe-49d1-9a36-fde28d055266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294495107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.3294495107
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.1324833185
Short name T780
Test name
Test status
Simulation time 140742792657 ps
CPU time 54.51 seconds
Started Jun 11 12:30:49 PM PDT 24
Finished Jun 11 12:31:46 PM PDT 24
Peak memory 200288 kb
Host smart-22b7544b-9ce8-4735-9a8b-4db6f73b15da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324833185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.1324833185
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.521255454
Short name T939
Test name
Test status
Simulation time 29322217430 ps
CPU time 52.73 seconds
Started Jun 11 12:30:50 PM PDT 24
Finished Jun 11 12:31:45 PM PDT 24
Peak memory 200288 kb
Host smart-5ed9a81c-3087-40dd-a4aa-6741110e2e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521255454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.521255454
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.245977584
Short name T266
Test name
Test status
Simulation time 64534985965 ps
CPU time 24.37 seconds
Started Jun 11 12:30:48 PM PDT 24
Finished Jun 11 12:31:15 PM PDT 24
Peak memory 200212 kb
Host smart-2d131453-80b1-49d6-b8b8-648a3294f04c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245977584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.245977584
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.1330983655
Short name T692
Test name
Test status
Simulation time 164718137943 ps
CPU time 251.61 seconds
Started Jun 11 12:30:50 PM PDT 24
Finished Jun 11 12:35:04 PM PDT 24
Peak memory 200368 kb
Host smart-d7a08fb1-bba0-4b61-a1a2-5cd77a6f4181
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1330983655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.1330983655
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.3249906002
Short name T384
Test name
Test status
Simulation time 4756946753 ps
CPU time 1.5 seconds
Started Jun 11 12:30:52 PM PDT 24
Finished Jun 11 12:30:55 PM PDT 24
Peak memory 198024 kb
Host smart-b48f9a6e-5ea1-4427-95b5-3958904c8b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249906002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.3249906002
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.1175424303
Short name T402
Test name
Test status
Simulation time 63518914785 ps
CPU time 27.69 seconds
Started Jun 11 12:30:47 PM PDT 24
Finished Jun 11 12:31:17 PM PDT 24
Peak memory 200376 kb
Host smart-5c04e427-36de-41bb-bc1f-9b90a8233be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175424303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.1175424303
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.3308777066
Short name T889
Test name
Test status
Simulation time 15851949097 ps
CPU time 199.45 seconds
Started Jun 11 12:30:49 PM PDT 24
Finished Jun 11 12:34:11 PM PDT 24
Peak memory 200076 kb
Host smart-9481d798-a2a3-4772-8281-b6cd95ba7f09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3308777066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.3308777066
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.1748090480
Short name T675
Test name
Test status
Simulation time 5139545179 ps
CPU time 40.73 seconds
Started Jun 11 12:30:50 PM PDT 24
Finished Jun 11 12:31:33 PM PDT 24
Peak memory 199660 kb
Host smart-3ac2623a-28b2-4265-97cf-360f6d71dbc5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1748090480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.1748090480
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.3696681815
Short name T732
Test name
Test status
Simulation time 152751062572 ps
CPU time 63.25 seconds
Started Jun 11 12:30:49 PM PDT 24
Finished Jun 11 12:31:54 PM PDT 24
Peak memory 200568 kb
Host smart-184c34de-13ec-4a94-9187-8686d8ebd937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696681815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.3696681815
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.479583581
Short name T665
Test name
Test status
Simulation time 50538991202 ps
CPU time 38.45 seconds
Started Jun 11 12:30:48 PM PDT 24
Finished Jun 11 12:31:28 PM PDT 24
Peak memory 196420 kb
Host smart-3d2c02a6-077f-426a-9e2c-63b9070501d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479583581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.479583581
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.2699824597
Short name T513
Test name
Test status
Simulation time 696250608 ps
CPU time 1.37 seconds
Started Jun 11 12:30:48 PM PDT 24
Finished Jun 11 12:30:52 PM PDT 24
Peak memory 198996 kb
Host smart-013aa284-c488-4db9-86d7-84b60608fca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699824597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.2699824597
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.3787232585
Short name T265
Test name
Test status
Simulation time 226491514074 ps
CPU time 99.88 seconds
Started Jun 11 12:30:49 PM PDT 24
Finished Jun 11 12:32:31 PM PDT 24
Peak memory 200400 kb
Host smart-aa4c495a-f5c2-46c1-a409-23d2a38ab5e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787232585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.3787232585
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.799087937
Short name T852
Test name
Test status
Simulation time 77207492214 ps
CPU time 567.92 seconds
Started Jun 11 12:30:49 PM PDT 24
Finished Jun 11 12:40:19 PM PDT 24
Peak memory 216948 kb
Host smart-fac1e7f2-2ed7-427b-834a-19acd65ebe0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799087937 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.799087937
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.1800171396
Short name T534
Test name
Test status
Simulation time 949163731 ps
CPU time 3.81 seconds
Started Jun 11 12:30:52 PM PDT 24
Finished Jun 11 12:30:58 PM PDT 24
Peak memory 198892 kb
Host smart-b44f5fd1-d551-476e-b3a4-07a9001e5992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800171396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.1800171396
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.2718611652
Short name T300
Test name
Test status
Simulation time 98123272207 ps
CPU time 90.97 seconds
Started Jun 11 12:30:45 PM PDT 24
Finished Jun 11 12:32:17 PM PDT 24
Peak memory 200260 kb
Host smart-f8d3b86e-830d-48fb-a364-362f9c0e718d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718611652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.2718611652
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.566800028
Short name T592
Test name
Test status
Simulation time 19621393 ps
CPU time 0.56 seconds
Started Jun 11 12:31:01 PM PDT 24
Finished Jun 11 12:31:03 PM PDT 24
Peak memory 195724 kb
Host smart-b7671361-e23e-4d5e-9972-736a8a2e1f3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566800028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.566800028
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.1195168301
Short name T109
Test name
Test status
Simulation time 222232340367 ps
CPU time 176.02 seconds
Started Jun 11 12:30:48 PM PDT 24
Finished Jun 11 12:33:46 PM PDT 24
Peak memory 200128 kb
Host smart-a54541c9-2f83-4c7b-952f-ada4bf5fcfd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195168301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.1195168301
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.830372985
Short name T761
Test name
Test status
Simulation time 17462275691 ps
CPU time 24.97 seconds
Started Jun 11 12:30:48 PM PDT 24
Finished Jun 11 12:31:16 PM PDT 24
Peak memory 199732 kb
Host smart-c04933ec-1c6c-423f-9ceb-ccf1d7aab08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830372985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.830372985
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.224955878
Short name T996
Test name
Test status
Simulation time 36668750532 ps
CPU time 58.77 seconds
Started Jun 11 12:30:47 PM PDT 24
Finished Jun 11 12:31:48 PM PDT 24
Peak memory 200184 kb
Host smart-1a72ac67-42d2-494a-9733-da676b024db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224955878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.224955878
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.2549274311
Short name T794
Test name
Test status
Simulation time 10449239603 ps
CPU time 4.11 seconds
Started Jun 11 12:31:03 PM PDT 24
Finished Jun 11 12:31:09 PM PDT 24
Peak memory 196584 kb
Host smart-d60f8801-9481-412a-be31-a0d45b5156b8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549274311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.2549274311
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.1456034152
Short name T435
Test name
Test status
Simulation time 60891377928 ps
CPU time 219.04 seconds
Started Jun 11 12:31:00 PM PDT 24
Finished Jun 11 12:34:41 PM PDT 24
Peak memory 200328 kb
Host smart-52fe18ec-6907-417e-8cf8-9c8756dcfda8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1456034152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.1456034152
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.1267356612
Short name T1067
Test name
Test status
Simulation time 7432190645 ps
CPU time 4.52 seconds
Started Jun 11 12:31:10 PM PDT 24
Finished Jun 11 12:31:16 PM PDT 24
Peak memory 199768 kb
Host smart-593ca685-9fea-430d-bbad-a941cc048771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267356612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.1267356612
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_perf.1120430009
Short name T752
Test name
Test status
Simulation time 11249710990 ps
CPU time 127.24 seconds
Started Jun 11 12:31:01 PM PDT 24
Finished Jun 11 12:33:10 PM PDT 24
Peak memory 200248 kb
Host smart-271047f0-6cfb-4ef6-8943-a49768df6f17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1120430009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.1120430009
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.2370389895
Short name T352
Test name
Test status
Simulation time 1901119331 ps
CPU time 2.36 seconds
Started Jun 11 12:30:52 PM PDT 24
Finished Jun 11 12:30:56 PM PDT 24
Peak memory 198428 kb
Host smart-0f31b2a7-6936-44d3-8d94-a0aa55e8e989
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2370389895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.2370389895
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.3122460022
Short name T282
Test name
Test status
Simulation time 21282703592 ps
CPU time 37.63 seconds
Started Jun 11 12:31:03 PM PDT 24
Finished Jun 11 12:31:42 PM PDT 24
Peak memory 200356 kb
Host smart-816b6983-7a28-42e0-a282-c54e56c60fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122460022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.3122460022
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.2880381908
Short name T316
Test name
Test status
Simulation time 7001506936 ps
CPU time 3.55 seconds
Started Jun 11 12:31:03 PM PDT 24
Finished Jun 11 12:31:09 PM PDT 24
Peak memory 196324 kb
Host smart-ddc033ca-f743-4694-963f-4eb6e4f558df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880381908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.2880381908
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.1267614947
Short name T461
Test name
Test status
Simulation time 10541306050 ps
CPU time 14.52 seconds
Started Jun 11 12:30:48 PM PDT 24
Finished Jun 11 12:31:05 PM PDT 24
Peak memory 200368 kb
Host smart-ed897c09-a5fc-441a-b64e-5648e424eb66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267614947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.1267614947
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.497979679
Short name T893
Test name
Test status
Simulation time 343495734403 ps
CPU time 419.4 seconds
Started Jun 11 12:31:02 PM PDT 24
Finished Jun 11 12:38:04 PM PDT 24
Peak memory 200620 kb
Host smart-81e8ab2f-8716-4b13-a554-a86fd7fe6e9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497979679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.497979679
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.2009901332
Short name T887
Test name
Test status
Simulation time 62992143555 ps
CPU time 587.4 seconds
Started Jun 11 12:31:01 PM PDT 24
Finished Jun 11 12:40:51 PM PDT 24
Peak memory 215124 kb
Host smart-0eda3167-1173-4f33-96da-9e0f5f3769b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009901332 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.2009901332
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.2703522724
Short name T717
Test name
Test status
Simulation time 1073250290 ps
CPU time 2.03 seconds
Started Jun 11 12:31:01 PM PDT 24
Finished Jun 11 12:31:05 PM PDT 24
Peak memory 199236 kb
Host smart-56641ed9-d81b-434a-ab2e-f61c29d2e966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703522724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.2703522724
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.1822007109
Short name T957
Test name
Test status
Simulation time 52610117215 ps
CPU time 19.62 seconds
Started Jun 11 12:30:51 PM PDT 24
Finished Jun 11 12:31:13 PM PDT 24
Peak memory 200088 kb
Host smart-048361f7-c348-41c7-9dba-55478d9208dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822007109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.1822007109
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.3997822161
Short name T554
Test name
Test status
Simulation time 12486527 ps
CPU time 0.55 seconds
Started Jun 11 12:31:05 PM PDT 24
Finished Jun 11 12:31:08 PM PDT 24
Peak memory 195700 kb
Host smart-f44c5bf8-79b0-4233-8985-68a8810cc2b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997822161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.3997822161
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.450979968
Short name T1024
Test name
Test status
Simulation time 33771332424 ps
CPU time 10.05 seconds
Started Jun 11 12:31:00 PM PDT 24
Finished Jun 11 12:31:12 PM PDT 24
Peak memory 200196 kb
Host smart-13031b14-cf90-4fc2-9c48-4a12b463c64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450979968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.450979968
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.2864726398
Short name T615
Test name
Test status
Simulation time 161756795244 ps
CPU time 118.76 seconds
Started Jun 11 12:31:02 PM PDT 24
Finished Jun 11 12:33:03 PM PDT 24
Peak memory 200264 kb
Host smart-90e291e5-ad22-459d-9c32-0fdccee707e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864726398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.2864726398
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.631997876
Short name T170
Test name
Test status
Simulation time 115512026190 ps
CPU time 11.52 seconds
Started Jun 11 12:30:59 PM PDT 24
Finished Jun 11 12:31:11 PM PDT 24
Peak memory 200272 kb
Host smart-5bcdfbbf-8c09-4a04-9b0d-df25271db125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631997876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.631997876
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.2391126157
Short name T1022
Test name
Test status
Simulation time 48867479645 ps
CPU time 64.86 seconds
Started Jun 11 12:31:04 PM PDT 24
Finished Jun 11 12:32:11 PM PDT 24
Peak memory 200244 kb
Host smart-dbaa523a-32e8-4f3b-b1d9-fe69a9f11f69
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391126157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.2391126157
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.826003592
Short name T570
Test name
Test status
Simulation time 102816532414 ps
CPU time 385.64 seconds
Started Jun 11 12:31:01 PM PDT 24
Finished Jun 11 12:37:28 PM PDT 24
Peak memory 200232 kb
Host smart-ab2c7da7-9684-4793-94cb-a16f006eb5e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=826003592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.826003592
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.349986468
Short name T596
Test name
Test status
Simulation time 6969931556 ps
CPU time 7.28 seconds
Started Jun 11 12:31:01 PM PDT 24
Finished Jun 11 12:31:10 PM PDT 24
Peak memory 200200 kb
Host smart-5a4d1eca-d5cc-4932-9679-7ae8f9ce3abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349986468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.349986468
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_perf.3882362968
Short name T379
Test name
Test status
Simulation time 19125859440 ps
CPU time 286.09 seconds
Started Jun 11 12:31:04 PM PDT 24
Finished Jun 11 12:35:52 PM PDT 24
Peak memory 200280 kb
Host smart-fea3739c-22ef-46d7-849f-df02bb3298af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3882362968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.3882362968
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.2646786801
Short name T735
Test name
Test status
Simulation time 5381463799 ps
CPU time 23.26 seconds
Started Jun 11 12:31:01 PM PDT 24
Finished Jun 11 12:31:26 PM PDT 24
Peak memory 198436 kb
Host smart-fa5dd5cf-12b8-442a-bb2b-65f779e72650
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2646786801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.2646786801
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.2800481228
Short name T582
Test name
Test status
Simulation time 196257233739 ps
CPU time 197.5 seconds
Started Jun 11 12:31:00 PM PDT 24
Finished Jun 11 12:34:19 PM PDT 24
Peak memory 200336 kb
Host smart-210a41c0-b4a3-414e-ada6-fdfe58d4c6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800481228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.2800481228
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.1492014247
Short name T357
Test name
Test status
Simulation time 4665047996 ps
CPU time 8.28 seconds
Started Jun 11 12:31:00 PM PDT 24
Finished Jun 11 12:31:10 PM PDT 24
Peak memory 196388 kb
Host smart-04e2e9bb-c0d0-4721-81ad-b2c398945e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492014247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.1492014247
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.4004741945
Short name T458
Test name
Test status
Simulation time 268862913 ps
CPU time 1.28 seconds
Started Jun 11 12:31:05 PM PDT 24
Finished Jun 11 12:31:08 PM PDT 24
Peak memory 198732 kb
Host smart-728ba2cb-49dd-46a9-ab76-64346536afc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004741945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.4004741945
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.2293264711
Short name T454
Test name
Test status
Simulation time 1014938165 ps
CPU time 3.29 seconds
Started Jun 11 12:31:01 PM PDT 24
Finished Jun 11 12:31:06 PM PDT 24
Peak memory 198784 kb
Host smart-40041378-a826-4484-810b-b3b69f59b145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293264711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.2293264711
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.585422318
Short name T496
Test name
Test status
Simulation time 78133740337 ps
CPU time 28.07 seconds
Started Jun 11 12:31:02 PM PDT 24
Finished Jun 11 12:31:32 PM PDT 24
Peak memory 200340 kb
Host smart-ece89629-2c95-4fc5-9bb1-4f939573de37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585422318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.585422318
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.3906132995
Short name T372
Test name
Test status
Simulation time 14384848 ps
CPU time 0.57 seconds
Started Jun 11 12:31:02 PM PDT 24
Finished Jun 11 12:31:05 PM PDT 24
Peak memory 195632 kb
Host smart-ced3ff7a-f3e3-4068-ae57-37d488ae8652
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906132995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.3906132995
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.4051312706
Short name T572
Test name
Test status
Simulation time 242067564302 ps
CPU time 105.27 seconds
Started Jun 11 12:31:10 PM PDT 24
Finished Jun 11 12:32:57 PM PDT 24
Peak memory 200092 kb
Host smart-bf4b2c92-3b24-432a-b612-1f2201a35262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051312706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.4051312706
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.1282053482
Short name T775
Test name
Test status
Simulation time 96239848269 ps
CPU time 29.56 seconds
Started Jun 11 12:31:02 PM PDT 24
Finished Jun 11 12:31:33 PM PDT 24
Peak memory 200256 kb
Host smart-fca1ac92-b09c-42fd-9133-22b576ba65fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282053482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.1282053482
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.3411750988
Short name T753
Test name
Test status
Simulation time 61880051939 ps
CPU time 57.75 seconds
Started Jun 11 12:31:01 PM PDT 24
Finished Jun 11 12:32:01 PM PDT 24
Peak memory 200316 kb
Host smart-b3766554-e562-403f-b262-395800eecf21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411750988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.3411750988
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.886987258
Short name T577
Test name
Test status
Simulation time 33453982978 ps
CPU time 22.06 seconds
Started Jun 11 12:31:05 PM PDT 24
Finished Jun 11 12:31:29 PM PDT 24
Peak memory 200252 kb
Host smart-81f5c9a8-170a-44df-a6e6-cbcac00cc50e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886987258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.886987258
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.1846909461
Short name T895
Test name
Test status
Simulation time 82505449300 ps
CPU time 227.88 seconds
Started Jun 11 12:31:03 PM PDT 24
Finished Jun 11 12:34:53 PM PDT 24
Peak memory 200152 kb
Host smart-efa6c876-14c3-4bc8-b61b-827fd803e8df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1846909461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.1846909461
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.1513177758
Short name T1058
Test name
Test status
Simulation time 116075262 ps
CPU time 0.66 seconds
Started Jun 11 12:31:01 PM PDT 24
Finished Jun 11 12:31:04 PM PDT 24
Peak memory 195984 kb
Host smart-9f072295-4867-4ee8-bfb9-85540da86270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513177758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.1513177758
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_perf.1250283715
Short name T894
Test name
Test status
Simulation time 25695878756 ps
CPU time 208.21 seconds
Started Jun 11 12:31:02 PM PDT 24
Finished Jun 11 12:34:33 PM PDT 24
Peak memory 200264 kb
Host smart-7827e60f-7ff9-4b4e-a6cd-6e1c48cf950d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1250283715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.1250283715
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.3560434095
Short name T476
Test name
Test status
Simulation time 6464523261 ps
CPU time 62.72 seconds
Started Jun 11 12:31:02 PM PDT 24
Finished Jun 11 12:32:07 PM PDT 24
Peak memory 198464 kb
Host smart-1bb356ec-bfe0-4b31-9f31-2156714e5fba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3560434095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.3560434095
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.3945294829
Short name T152
Test name
Test status
Simulation time 109568081566 ps
CPU time 47.46 seconds
Started Jun 11 12:31:01 PM PDT 24
Finished Jun 11 12:31:49 PM PDT 24
Peak memory 200236 kb
Host smart-71baebe2-061a-4b70-b59b-60d416645311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945294829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.3945294829
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.2653750787
Short name T301
Test name
Test status
Simulation time 41367504588 ps
CPU time 19.08 seconds
Started Jun 11 12:31:05 PM PDT 24
Finished Jun 11 12:31:26 PM PDT 24
Peak memory 196132 kb
Host smart-fc42c82c-c79f-493e-9d3a-64c8b9696b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653750787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.2653750787
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.3962707949
Short name T770
Test name
Test status
Simulation time 858772915 ps
CPU time 1.94 seconds
Started Jun 11 12:31:01 PM PDT 24
Finished Jun 11 12:31:04 PM PDT 24
Peak memory 200168 kb
Host smart-db0b74ae-6283-4e2b-bc4e-6b31002a9854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962707949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.3962707949
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.4025515967
Short name T712
Test name
Test status
Simulation time 47771850883 ps
CPU time 83.51 seconds
Started Jun 11 12:31:04 PM PDT 24
Finished Jun 11 12:32:30 PM PDT 24
Peak memory 200296 kb
Host smart-2e1a29d5-3d7a-4066-adf9-fd9f0390cf6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025515967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.4025515967
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.4177676651
Short name T757
Test name
Test status
Simulation time 7417658791 ps
CPU time 11.3 seconds
Started Jun 11 12:31:00 PM PDT 24
Finished Jun 11 12:31:13 PM PDT 24
Peak memory 200248 kb
Host smart-7e9aac69-f210-4239-952c-a3e124b52a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177676651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.4177676651
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.866062181
Short name T1078
Test name
Test status
Simulation time 98387807604 ps
CPU time 92.3 seconds
Started Jun 11 12:31:02 PM PDT 24
Finished Jun 11 12:32:36 PM PDT 24
Peak memory 200388 kb
Host smart-f3816fc7-ccb8-47f5-8cfb-eecd85382da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866062181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.866062181
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.3827723957
Short name T6
Test name
Test status
Simulation time 14061186 ps
CPU time 0.54 seconds
Started Jun 11 12:31:04 PM PDT 24
Finished Jun 11 12:31:07 PM PDT 24
Peak memory 195728 kb
Host smart-810a4c70-c2c2-4de2-ac1f-b2090e4e8a42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827723957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.3827723957
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.3697814669
Short name T1057
Test name
Test status
Simulation time 124817300824 ps
CPU time 50.02 seconds
Started Jun 11 12:31:01 PM PDT 24
Finished Jun 11 12:31:52 PM PDT 24
Peak memory 200172 kb
Host smart-4e5e1f49-3c45-4b3a-962b-37ea9846e4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697814669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.3697814669
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.1709067749
Short name T923
Test name
Test status
Simulation time 338693808010 ps
CPU time 150.06 seconds
Started Jun 11 12:31:01 PM PDT 24
Finished Jun 11 12:33:33 PM PDT 24
Peak memory 200156 kb
Host smart-4b5341fc-b02e-4df3-b3d3-65c7a1cdbead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709067749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.1709067749
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.3929432429
Short name T921
Test name
Test status
Simulation time 39548626424 ps
CPU time 22.85 seconds
Started Jun 11 12:31:03 PM PDT 24
Finished Jun 11 12:31:28 PM PDT 24
Peak memory 200096 kb
Host smart-562d419d-2fa5-4341-ad26-047aedcc50a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929432429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.3929432429
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.3075654886
Short name T494
Test name
Test status
Simulation time 8992201401 ps
CPU time 2.54 seconds
Started Jun 11 12:31:05 PM PDT 24
Finished Jun 11 12:31:09 PM PDT 24
Peak memory 200540 kb
Host smart-b6ae3a0a-9830-4c54-be1d-ed4ef1d1cee2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075654886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.3075654886
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.2002610215
Short name T779
Test name
Test status
Simulation time 145402547872 ps
CPU time 485.82 seconds
Started Jun 11 12:31:10 PM PDT 24
Finished Jun 11 12:39:17 PM PDT 24
Peak memory 200160 kb
Host smart-b4cf6ac2-3c9c-4957-8db6-fbe08376da96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2002610215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.2002610215
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.1870381902
Short name T470
Test name
Test status
Simulation time 13147700427 ps
CPU time 4.22 seconds
Started Jun 11 12:31:03 PM PDT 24
Finished Jun 11 12:31:09 PM PDT 24
Peak memory 200332 kb
Host smart-d4bec46c-5f31-407b-8d5d-ac83ce6f5fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870381902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.1870381902
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_perf.4093499434
Short name T573
Test name
Test status
Simulation time 6093752121 ps
CPU time 137.27 seconds
Started Jun 11 12:31:05 PM PDT 24
Finished Jun 11 12:33:24 PM PDT 24
Peak memory 200300 kb
Host smart-2666184c-d234-4f90-97f0-32670080f85b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4093499434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.4093499434
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.1790894077
Short name T763
Test name
Test status
Simulation time 1396182553 ps
CPU time 1.77 seconds
Started Jun 11 12:31:08 PM PDT 24
Finished Jun 11 12:31:12 PM PDT 24
Peak memory 198200 kb
Host smart-656a83f7-6ea5-4095-8d69-6ddb674e2d98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1790894077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.1790894077
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.3824064368
Short name T877
Test name
Test status
Simulation time 78908022912 ps
CPU time 41.77 seconds
Started Jun 11 12:31:04 PM PDT 24
Finished Jun 11 12:31:48 PM PDT 24
Peak memory 200200 kb
Host smart-197b64ae-39a1-4a3d-b19f-9fa1e2768e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824064368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.3824064368
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.1545703141
Short name T952
Test name
Test status
Simulation time 5364485606 ps
CPU time 4.88 seconds
Started Jun 11 12:31:03 PM PDT 24
Finished Jun 11 12:31:10 PM PDT 24
Peak memory 196492 kb
Host smart-6963b629-0c89-4e6c-bd3a-272ff36285a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545703141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.1545703141
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.2861525298
Short name T488
Test name
Test status
Simulation time 6254146688 ps
CPU time 17.93 seconds
Started Jun 11 12:31:05 PM PDT 24
Finished Jun 11 12:31:25 PM PDT 24
Peak memory 199628 kb
Host smart-20a6ff7f-e919-4560-9813-178d8239e3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861525298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.2861525298
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.713350845
Short name T34
Test name
Test status
Simulation time 45047641836 ps
CPU time 378.74 seconds
Started Jun 11 12:31:06 PM PDT 24
Finished Jun 11 12:37:27 PM PDT 24
Peak memory 216396 kb
Host smart-5d825ac2-2b37-4100-a259-c593a5cf5781
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713350845 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.713350845
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.2727329698
Short name T303
Test name
Test status
Simulation time 6235409137 ps
CPU time 8.7 seconds
Started Jun 11 12:31:05 PM PDT 24
Finished Jun 11 12:31:16 PM PDT 24
Peak memory 200184 kb
Host smart-e524d2ec-b6b8-4c7c-ae44-4883cadd4420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727329698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.2727329698
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.2553383513
Short name T428
Test name
Test status
Simulation time 19146667211 ps
CPU time 31.38 seconds
Started Jun 11 12:31:02 PM PDT 24
Finished Jun 11 12:31:35 PM PDT 24
Peak memory 200356 kb
Host smart-2b392a02-8fcb-49cc-a444-84f87d2f13aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553383513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.2553383513
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.1880129583
Short name T394
Test name
Test status
Simulation time 126917950 ps
CPU time 0.53 seconds
Started Jun 11 12:31:02 PM PDT 24
Finished Jun 11 12:31:05 PM PDT 24
Peak memory 195224 kb
Host smart-d5995c47-d90b-4ccc-a435-48ed58ec6add
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880129583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.1880129583
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.2683145291
Short name T1087
Test name
Test status
Simulation time 67228176822 ps
CPU time 109.71 seconds
Started Jun 11 12:31:02 PM PDT 24
Finished Jun 11 12:32:54 PM PDT 24
Peak memory 200316 kb
Host smart-44f5c695-c335-48a3-bcc9-24365a92c531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683145291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.2683145291
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.2760685509
Short name T696
Test name
Test status
Simulation time 27263671249 ps
CPU time 11.6 seconds
Started Jun 11 12:31:04 PM PDT 24
Finished Jun 11 12:31:18 PM PDT 24
Peak memory 199616 kb
Host smart-6b44e5c5-72b1-4ea6-a61f-7828cc5faed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760685509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.2760685509
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.3039415441
Short name T252
Test name
Test status
Simulation time 113555279430 ps
CPU time 179.97 seconds
Started Jun 11 12:31:05 PM PDT 24
Finished Jun 11 12:34:07 PM PDT 24
Peak memory 200244 kb
Host smart-c81c1b89-98dc-44bb-bcb7-8b2f53bf58bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039415441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.3039415441
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.1333435176
Short name T680
Test name
Test status
Simulation time 46307272703 ps
CPU time 60.42 seconds
Started Jun 11 12:31:06 PM PDT 24
Finished Jun 11 12:32:08 PM PDT 24
Peak memory 200560 kb
Host smart-5287524f-b238-420d-8c4d-4eca1bc94efa
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333435176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.1333435176
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.506175098
Short name T860
Test name
Test status
Simulation time 125510053234 ps
CPU time 613.05 seconds
Started Jun 11 12:31:04 PM PDT 24
Finished Jun 11 12:41:19 PM PDT 24
Peak memory 200220 kb
Host smart-dbde8c0f-0b27-4f89-a17e-0f7d942d0bd5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=506175098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.506175098
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.831287784
Short name T579
Test name
Test status
Simulation time 4173437771 ps
CPU time 7.83 seconds
Started Jun 11 12:31:05 PM PDT 24
Finished Jun 11 12:31:15 PM PDT 24
Peak memory 197500 kb
Host smart-47c314d1-ca41-406d-841e-ce3cb3cc322e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831287784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.831287784
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_perf.442549923
Short name T89
Test name
Test status
Simulation time 25856880785 ps
CPU time 748.62 seconds
Started Jun 11 12:31:03 PM PDT 24
Finished Jun 11 12:43:34 PM PDT 24
Peak memory 200312 kb
Host smart-66f1149a-cfe8-47a4-8170-6812a9fe6a7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=442549923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.442549923
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.571134829
Short name T843
Test name
Test status
Simulation time 4000850421 ps
CPU time 28.02 seconds
Started Jun 11 12:31:03 PM PDT 24
Finished Jun 11 12:31:33 PM PDT 24
Peak memory 198692 kb
Host smart-e7ef9025-70e7-4399-a16f-d2a772d00fd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=571134829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.571134829
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.4067719579
Short name T774
Test name
Test status
Simulation time 12616026600 ps
CPU time 16.76 seconds
Started Jun 11 12:31:04 PM PDT 24
Finished Jun 11 12:31:23 PM PDT 24
Peak memory 200384 kb
Host smart-df77e13d-154c-449e-b358-88c71b8045bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067719579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.4067719579
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.2348980520
Short name T571
Test name
Test status
Simulation time 646241386 ps
CPU time 0.85 seconds
Started Jun 11 12:31:04 PM PDT 24
Finished Jun 11 12:31:07 PM PDT 24
Peak memory 195752 kb
Host smart-64943dd9-8ec4-4b2c-a4a3-fac52ba6cd78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348980520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.2348980520
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.2968498913
Short name T79
Test name
Test status
Simulation time 5767456742 ps
CPU time 6.64 seconds
Started Jun 11 12:31:05 PM PDT 24
Finished Jun 11 12:31:14 PM PDT 24
Peak memory 200564 kb
Host smart-a48c3572-b894-4431-9c8d-30c0b4d9da4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968498913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.2968498913
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.1447840808
Short name T871
Test name
Test status
Simulation time 1087069520 ps
CPU time 1.62 seconds
Started Jun 11 12:31:02 PM PDT 24
Finished Jun 11 12:31:05 PM PDT 24
Peak memory 198132 kb
Host smart-b542430f-0663-4d2d-8ac9-021e8e2abbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447840808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.1447840808
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.3405794485
Short name T764
Test name
Test status
Simulation time 62407580738 ps
CPU time 130.3 seconds
Started Jun 11 12:31:06 PM PDT 24
Finished Jun 11 12:33:18 PM PDT 24
Peak memory 200348 kb
Host smart-e46c9946-d653-48c9-bb7b-d429ea3d1643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405794485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.3405794485
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.3492986954
Short name T427
Test name
Test status
Simulation time 12021617 ps
CPU time 0.56 seconds
Started Jun 11 12:31:12 PM PDT 24
Finished Jun 11 12:31:15 PM PDT 24
Peak memory 195624 kb
Host smart-710aac21-2b9a-4772-9208-b1669b7899c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492986954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.3492986954
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.4111329708
Short name T989
Test name
Test status
Simulation time 218432054642 ps
CPU time 434.79 seconds
Started Jun 11 12:31:12 PM PDT 24
Finished Jun 11 12:38:29 PM PDT 24
Peak memory 200192 kb
Host smart-e056f665-70db-41a1-a518-803d93209c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111329708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.4111329708
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.481520391
Short name T765
Test name
Test status
Simulation time 84230997414 ps
CPU time 140.54 seconds
Started Jun 11 12:31:11 PM PDT 24
Finished Jun 11 12:33:34 PM PDT 24
Peak memory 200184 kb
Host smart-60134c6d-983c-4ec0-a7ff-eaa8450ef45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481520391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.481520391
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.1608210385
Short name T799
Test name
Test status
Simulation time 82191663301 ps
CPU time 80.65 seconds
Started Jun 11 12:31:11 PM PDT 24
Finished Jun 11 12:32:34 PM PDT 24
Peak memory 200244 kb
Host smart-e7d3fd5f-e901-4e69-ba0d-a5273e28b820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608210385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.1608210385
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.3114005297
Short name T681
Test name
Test status
Simulation time 156020184943 ps
CPU time 522.83 seconds
Started Jun 11 12:31:16 PM PDT 24
Finished Jun 11 12:40:02 PM PDT 24
Peak memory 200156 kb
Host smart-89058c86-726f-49f7-839f-cdc313ac0638
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3114005297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.3114005297
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.1319952518
Short name T727
Test name
Test status
Simulation time 5963664790 ps
CPU time 7.46 seconds
Started Jun 11 12:31:14 PM PDT 24
Finished Jun 11 12:31:24 PM PDT 24
Peak memory 200304 kb
Host smart-6752fced-3e93-46c9-abbe-e24b02bb801a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319952518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.1319952518
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_perf.1647580431
Short name T985
Test name
Test status
Simulation time 16329023711 ps
CPU time 881.08 seconds
Started Jun 11 12:31:18 PM PDT 24
Finished Jun 11 12:46:02 PM PDT 24
Peak memory 200340 kb
Host smart-44d6383d-0352-4e1d-802d-54bbbfc7b9c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1647580431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.1647580431
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.2930653175
Short name T709
Test name
Test status
Simulation time 5284060191 ps
CPU time 22.13 seconds
Started Jun 11 12:31:16 PM PDT 24
Finished Jun 11 12:31:42 PM PDT 24
Peak memory 198376 kb
Host smart-db304009-306e-4bc1-a71e-6a68645ebd94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2930653175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.2930653175
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.78341637
Short name T558
Test name
Test status
Simulation time 66322220024 ps
CPU time 35.69 seconds
Started Jun 11 12:31:14 PM PDT 24
Finished Jun 11 12:31:53 PM PDT 24
Peak memory 200260 kb
Host smart-ee8cfcd6-1a76-437b-acfb-02407ef060ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78341637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.78341637
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.1030353856
Short name T299
Test name
Test status
Simulation time 3441874432 ps
CPU time 6.18 seconds
Started Jun 11 12:31:16 PM PDT 24
Finished Jun 11 12:31:26 PM PDT 24
Peak memory 196276 kb
Host smart-91a51881-aca4-4e41-94e1-f3e89d4f8cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030353856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.1030353856
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.4113804534
Short name T350
Test name
Test status
Simulation time 484896148 ps
CPU time 1.56 seconds
Started Jun 11 12:31:03 PM PDT 24
Finished Jun 11 12:31:07 PM PDT 24
Peak memory 199224 kb
Host smart-cce504af-7030-42e4-986a-adf68bf43e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113804534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.4113804534
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.182768167
Short name T317
Test name
Test status
Simulation time 7500563876 ps
CPU time 7.3 seconds
Started Jun 11 12:31:14 PM PDT 24
Finished Jun 11 12:31:24 PM PDT 24
Peak memory 200276 kb
Host smart-5bae7118-78bf-4f17-a330-5c89c115b95a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182768167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.182768167
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.3898151510
Short name T1086
Test name
Test status
Simulation time 9073554745 ps
CPU time 9.69 seconds
Started Jun 11 12:31:14 PM PDT 24
Finished Jun 11 12:31:27 PM PDT 24
Peak memory 200164 kb
Host smart-d5be74f6-0e6b-4574-a30b-5eb00f60d2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898151510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.3898151510
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.2805730370
Short name T635
Test name
Test status
Simulation time 6995686551 ps
CPU time 3.42 seconds
Started Jun 11 12:31:18 PM PDT 24
Finished Jun 11 12:31:24 PM PDT 24
Peak memory 197196 kb
Host smart-da115738-ad06-45a4-9aec-450a2169883f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805730370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.2805730370
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.3300510802
Short name T785
Test name
Test status
Simulation time 46030891 ps
CPU time 0.56 seconds
Started Jun 11 12:31:13 PM PDT 24
Finished Jun 11 12:31:17 PM PDT 24
Peak memory 195692 kb
Host smart-80df92fe-1591-4131-8a9b-e83bf14dde49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300510802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.3300510802
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.4257318727
Short name T963
Test name
Test status
Simulation time 122940861312 ps
CPU time 29.61 seconds
Started Jun 11 12:31:13 PM PDT 24
Finished Jun 11 12:31:45 PM PDT 24
Peak memory 200356 kb
Host smart-7a84540c-5a33-4c04-818a-acae6b4192e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257318727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.4257318727
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.2558674298
Short name T742
Test name
Test status
Simulation time 64763236234 ps
CPU time 30.9 seconds
Started Jun 11 12:31:15 PM PDT 24
Finished Jun 11 12:31:49 PM PDT 24
Peak memory 200064 kb
Host smart-cef306a8-a829-437c-b125-da50174801b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558674298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.2558674298
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_intr.2435145829
Short name T97
Test name
Test status
Simulation time 64167432135 ps
CPU time 29.2 seconds
Started Jun 11 12:31:14 PM PDT 24
Finished Jun 11 12:31:46 PM PDT 24
Peak memory 200040 kb
Host smart-bfa0a701-2393-45e2-8ae5-fc0d8297f6a2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435145829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.2435145829
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.3517699277
Short name T563
Test name
Test status
Simulation time 43252625375 ps
CPU time 152.89 seconds
Started Jun 11 12:31:14 PM PDT 24
Finished Jun 11 12:33:49 PM PDT 24
Peak memory 200256 kb
Host smart-6cf5a96d-a3ff-4e63-8ebc-d2a2543561b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3517699277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.3517699277
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.3259722605
Short name T325
Test name
Test status
Simulation time 9005679498 ps
CPU time 17.19 seconds
Started Jun 11 12:31:12 PM PDT 24
Finished Jun 11 12:31:31 PM PDT 24
Peak memory 200152 kb
Host smart-c3d1ee46-257c-4cb2-a6d8-7e25fb1dfb41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259722605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.3259722605
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_perf.1883924935
Short name T994
Test name
Test status
Simulation time 12758141710 ps
CPU time 400.32 seconds
Started Jun 11 12:31:15 PM PDT 24
Finished Jun 11 12:37:59 PM PDT 24
Peak memory 200264 kb
Host smart-d833a2cb-edf0-41df-ab36-4030f43b489c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1883924935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.1883924935
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.4259268683
Short name T20
Test name
Test status
Simulation time 2012966965 ps
CPU time 12 seconds
Started Jun 11 12:31:10 PM PDT 24
Finished Jun 11 12:31:24 PM PDT 24
Peak memory 198720 kb
Host smart-20cee3ac-292a-4cc9-853e-0b093e30fcd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4259268683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.4259268683
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.2997297812
Short name T693
Test name
Test status
Simulation time 60331663048 ps
CPU time 35.22 seconds
Started Jun 11 12:31:17 PM PDT 24
Finished Jun 11 12:31:55 PM PDT 24
Peak memory 200208 kb
Host smart-1f8badba-8a16-4bf6-9e36-fc27a91f9366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997297812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.2997297812
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.1632744976
Short name T583
Test name
Test status
Simulation time 1665160403 ps
CPU time 1.91 seconds
Started Jun 11 12:31:15 PM PDT 24
Finished Jun 11 12:31:20 PM PDT 24
Peak memory 195544 kb
Host smart-a15762bb-b713-4fb6-aab8-4f949a777054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632744976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.1632744976
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.721084282
Short name T444
Test name
Test status
Simulation time 261155040 ps
CPU time 1.05 seconds
Started Jun 11 12:31:16 PM PDT 24
Finished Jun 11 12:31:20 PM PDT 24
Peak memory 198588 kb
Host smart-8c2c5efe-b4f7-434e-94c7-9b82e501a329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721084282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.721084282
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.927150952
Short name T822
Test name
Test status
Simulation time 390895375203 ps
CPU time 477.09 seconds
Started Jun 11 12:31:16 PM PDT 24
Finished Jun 11 12:39:16 PM PDT 24
Peak memory 200168 kb
Host smart-6d1f28b3-2c9f-493c-b4b2-403b972862ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927150952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.927150952
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.900609973
Short name T947
Test name
Test status
Simulation time 52628680131 ps
CPU time 633.19 seconds
Started Jun 11 12:31:13 PM PDT 24
Finished Jun 11 12:41:49 PM PDT 24
Peak memory 216796 kb
Host smart-817e2768-37bb-4437-88e3-01a4580123d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900609973 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.900609973
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.877918097
Short name T306
Test name
Test status
Simulation time 1010909433 ps
CPU time 3.37 seconds
Started Jun 11 12:31:15 PM PDT 24
Finished Jun 11 12:31:22 PM PDT 24
Peak memory 198948 kb
Host smart-3f732408-b4c0-40f1-bad0-e17e8ff9a659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877918097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.877918097
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.995489798
Short name T297
Test name
Test status
Simulation time 57591736879 ps
CPU time 24.28 seconds
Started Jun 11 12:31:13 PM PDT 24
Finished Jun 11 12:31:41 PM PDT 24
Peak memory 200288 kb
Host smart-178bbb41-51d4-4b66-b594-c301c52adfd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995489798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.995489798
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.2048406430
Short name T365
Test name
Test status
Simulation time 12141886 ps
CPU time 0.53 seconds
Started Jun 11 12:31:18 PM PDT 24
Finished Jun 11 12:31:21 PM PDT 24
Peak memory 194692 kb
Host smart-26e15706-e067-447a-8115-224b345960a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048406430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.2048406430
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.3856099968
Short name T254
Test name
Test status
Simulation time 192231155674 ps
CPU time 293.13 seconds
Started Jun 11 12:31:15 PM PDT 24
Finished Jun 11 12:36:12 PM PDT 24
Peak memory 200348 kb
Host smart-671dacc4-8335-4946-9a11-bc84935484b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856099968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.3856099968
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.2330995227
Short name T441
Test name
Test status
Simulation time 30913876005 ps
CPU time 70.62 seconds
Started Jun 11 12:31:17 PM PDT 24
Finished Jun 11 12:32:31 PM PDT 24
Peak memory 200312 kb
Host smart-cfeca174-5b5c-4f47-9257-fe4fee1d4c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330995227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.2330995227
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.1924442951
Short name T209
Test name
Test status
Simulation time 38794278704 ps
CPU time 24.37 seconds
Started Jun 11 12:31:15 PM PDT 24
Finished Jun 11 12:31:43 PM PDT 24
Peak memory 200296 kb
Host smart-6b46d4c0-5085-4585-b05f-3cda55c05cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924442951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.1924442951
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.2935405627
Short name T684
Test name
Test status
Simulation time 6011011638 ps
CPU time 21.89 seconds
Started Jun 11 12:31:13 PM PDT 24
Finished Jun 11 12:31:38 PM PDT 24
Peak memory 199364 kb
Host smart-7319fe6b-dd7e-42e0-9125-4bc0dfd93416
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935405627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.2935405627
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.2838696330
Short name T842
Test name
Test status
Simulation time 72122330378 ps
CPU time 360.51 seconds
Started Jun 11 12:31:15 PM PDT 24
Finished Jun 11 12:37:19 PM PDT 24
Peak memory 200376 kb
Host smart-c0a68bac-3d87-4ec1-b88d-c65f0de6fef2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2838696330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.2838696330
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.190259276
Short name T393
Test name
Test status
Simulation time 11972352126 ps
CPU time 11.44 seconds
Started Jun 11 12:31:17 PM PDT 24
Finished Jun 11 12:31:32 PM PDT 24
Peak memory 199556 kb
Host smart-2f9de8fc-6054-4f94-97de-9e0450915258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190259276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.190259276
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_perf.1755196533
Short name T610
Test name
Test status
Simulation time 12276714125 ps
CPU time 373.56 seconds
Started Jun 11 12:31:12 PM PDT 24
Finished Jun 11 12:37:28 PM PDT 24
Peak memory 200340 kb
Host smart-7bbf6fc6-f215-4a16-b432-6afcad832bf8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1755196533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.1755196533
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.3268366391
Short name T967
Test name
Test status
Simulation time 4203991372 ps
CPU time 18.3 seconds
Started Jun 11 12:31:18 PM PDT 24
Finished Jun 11 12:31:39 PM PDT 24
Peak memory 198580 kb
Host smart-1cbccf67-e609-4d56-8fd6-67a63f278275
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3268366391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.3268366391
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.1702099832
Short name T490
Test name
Test status
Simulation time 141598389532 ps
CPU time 24.73 seconds
Started Jun 11 12:31:16 PM PDT 24
Finished Jun 11 12:31:44 PM PDT 24
Peak memory 200352 kb
Host smart-47e9abb9-3ed9-49f3-a042-21fd6ddd82a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702099832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.1702099832
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.119283611
Short name T856
Test name
Test status
Simulation time 4402209046 ps
CPU time 3.94 seconds
Started Jun 11 12:31:17 PM PDT 24
Finished Jun 11 12:31:24 PM PDT 24
Peak memory 196184 kb
Host smart-79596f29-8fe7-4ea0-a91a-59da58bde937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119283611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.119283611
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.3103338416
Short name T363
Test name
Test status
Simulation time 739055076 ps
CPU time 1.65 seconds
Started Jun 11 12:31:12 PM PDT 24
Finished Jun 11 12:31:16 PM PDT 24
Peak memory 199688 kb
Host smart-6b506470-b51c-4dd7-87a0-ec4ba2908b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103338416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.3103338416
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.679906452
Short name T146
Test name
Test status
Simulation time 505953051670 ps
CPU time 1286.04 seconds
Started Jun 11 12:31:13 PM PDT 24
Finished Jun 11 12:52:42 PM PDT 24
Peak memory 200188 kb
Host smart-ddea381c-4f01-481a-a1e8-3f2271817b9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679906452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.679906452
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.2410880657
Short name T997
Test name
Test status
Simulation time 11266051436 ps
CPU time 135.6 seconds
Started Jun 11 12:31:17 PM PDT 24
Finished Jun 11 12:33:35 PM PDT 24
Peak memory 216036 kb
Host smart-d00447cb-8703-4064-aed6-557c434d815d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410880657 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.2410880657
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.2799902333
Short name T714
Test name
Test status
Simulation time 323102195 ps
CPU time 1.26 seconds
Started Jun 11 12:31:15 PM PDT 24
Finished Jun 11 12:31:20 PM PDT 24
Peak memory 197440 kb
Host smart-7c3a2a8c-bc4b-43f5-8fbb-bbe9e8d0e077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799902333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.2799902333
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.2435816526
Short name T746
Test name
Test status
Simulation time 23934205476 ps
CPU time 21.65 seconds
Started Jun 11 12:31:13 PM PDT 24
Finished Jun 11 12:31:37 PM PDT 24
Peak memory 200368 kb
Host smart-878aec88-100a-421d-9a2a-b7d25a7ce3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435816526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.2435816526
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.3288990666
Short name T557
Test name
Test status
Simulation time 21598048 ps
CPU time 0.52 seconds
Started Jun 11 12:29:08 PM PDT 24
Finished Jun 11 12:29:10 PM PDT 24
Peak memory 195880 kb
Host smart-e6a7e5a7-9f3e-4103-a00a-d28615cb5cac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288990666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.3288990666
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.4122571270
Short name T1036
Test name
Test status
Simulation time 18170420513 ps
CPU time 15.09 seconds
Started Jun 11 12:29:03 PM PDT 24
Finished Jun 11 12:29:20 PM PDT 24
Peak memory 200220 kb
Host smart-b52b0f94-a3c8-4ca8-a1c8-55e699fbda04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122571270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.4122571270
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.319770895
Short name T818
Test name
Test status
Simulation time 163735607874 ps
CPU time 260.15 seconds
Started Jun 11 12:29:21 PM PDT 24
Finished Jun 11 12:33:43 PM PDT 24
Peak memory 200188 kb
Host smart-15f48b19-ebc0-4cba-a062-f2cbab0d99a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319770895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.319770895
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_intr.880838303
Short name T814
Test name
Test status
Simulation time 77735588901 ps
CPU time 12.35 seconds
Started Jun 11 12:29:01 PM PDT 24
Finished Jun 11 12:29:16 PM PDT 24
Peak memory 200320 kb
Host smart-07223a92-491c-41cf-8d81-47256083b329
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880838303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.880838303
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.1886063632
Short name T931
Test name
Test status
Simulation time 118011022845 ps
CPU time 771.55 seconds
Started Jun 11 12:29:10 PM PDT 24
Finished Jun 11 12:42:03 PM PDT 24
Peak memory 200148 kb
Host smart-53f849fa-10cb-4a3a-8597-84cdd6c1497a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1886063632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.1886063632
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.2179576244
Short name T1063
Test name
Test status
Simulation time 3039255386 ps
CPU time 1.4 seconds
Started Jun 11 12:29:00 PM PDT 24
Finished Jun 11 12:29:02 PM PDT 24
Peak memory 196904 kb
Host smart-fd075267-0ee4-4a3e-8c21-ecf11383c6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179576244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.2179576244
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_perf.4106654374
Short name T505
Test name
Test status
Simulation time 8508003603 ps
CPU time 493.23 seconds
Started Jun 11 12:29:15 PM PDT 24
Finished Jun 11 12:37:29 PM PDT 24
Peak memory 200180 kb
Host smart-6c3d440c-7254-4343-b61e-fae2966f83b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4106654374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.4106654374
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.37965704
Short name T802
Test name
Test status
Simulation time 4902439875 ps
CPU time 38.86 seconds
Started Jun 11 12:29:13 PM PDT 24
Finished Jun 11 12:29:53 PM PDT 24
Peak memory 200292 kb
Host smart-abc9fc29-7138-438c-8b5a-80c38a818e52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=37965704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.37965704
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.43792172
Short name T73
Test name
Test status
Simulation time 2850425006 ps
CPU time 6.07 seconds
Started Jun 11 12:30:17 PM PDT 24
Finished Jun 11 12:30:26 PM PDT 24
Peak memory 199236 kb
Host smart-a29ad60b-c616-4405-b986-31414bcc4049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43792172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.43792172
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.2261031802
Short name T756
Test name
Test status
Simulation time 4851601687 ps
CPU time 2.51 seconds
Started Jun 11 12:30:17 PM PDT 24
Finished Jun 11 12:30:22 PM PDT 24
Peak memory 196004 kb
Host smart-903c008e-d145-4006-8709-729afe41b92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261031802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.2261031802
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.1353194702
Short name T982
Test name
Test status
Simulation time 430005146 ps
CPU time 2.61 seconds
Started Jun 11 12:29:05 PM PDT 24
Finished Jun 11 12:29:10 PM PDT 24
Peak memory 199920 kb
Host smart-a4b1c9f2-7db9-4a4c-b162-2c0710e27533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353194702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.1353194702
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.1290490815
Short name T979
Test name
Test status
Simulation time 93737741660 ps
CPU time 880.86 seconds
Started Jun 11 12:30:15 PM PDT 24
Finished Jun 11 12:44:59 PM PDT 24
Peak memory 199828 kb
Host smart-6ef74659-4996-40bd-9147-bcb63ed57d0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290490815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.1290490815
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.3062169586
Short name T689
Test name
Test status
Simulation time 382905363991 ps
CPU time 917.3 seconds
Started Jun 11 12:29:10 PM PDT 24
Finished Jun 11 12:44:28 PM PDT 24
Peak memory 225088 kb
Host smart-dca9e956-373c-476f-ab33-da764e992616
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062169586 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.3062169586
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.1256213597
Short name T459
Test name
Test status
Simulation time 766100304 ps
CPU time 2.53 seconds
Started Jun 11 12:29:21 PM PDT 24
Finished Jun 11 12:29:25 PM PDT 24
Peak memory 198636 kb
Host smart-d8a874b6-4940-47b5-9e74-afc11126aa54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256213597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.1256213597
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.3610470746
Short name T331
Test name
Test status
Simulation time 20268025992 ps
CPU time 43.55 seconds
Started Jun 11 12:28:56 PM PDT 24
Finished Jun 11 12:29:41 PM PDT 24
Peak memory 200316 kb
Host smart-05526c3e-3ef6-41c0-8739-8e46b7d92462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610470746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.3610470746
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.648855582
Short name T1007
Test name
Test status
Simulation time 51353689468 ps
CPU time 21.35 seconds
Started Jun 11 12:31:15 PM PDT 24
Finished Jun 11 12:31:40 PM PDT 24
Peak memory 200368 kb
Host smart-9ab276bb-23be-4ffa-9063-73d8d7aa0d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648855582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.648855582
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.3699183684
Short name T606
Test name
Test status
Simulation time 140341947695 ps
CPU time 409.4 seconds
Started Jun 11 12:31:15 PM PDT 24
Finished Jun 11 12:38:08 PM PDT 24
Peak memory 216724 kb
Host smart-5d62e46f-09c9-4803-bdbb-f103680c8331
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699183684 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.3699183684
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.3519183585
Short name T327
Test name
Test status
Simulation time 42152897186 ps
CPU time 35.66 seconds
Started Jun 11 12:31:11 PM PDT 24
Finished Jun 11 12:31:49 PM PDT 24
Peak memory 200112 kb
Host smart-40133727-2899-4f5e-a753-f37bd99c8358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519183585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.3519183585
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.190419349
Short name T679
Test name
Test status
Simulation time 8897977415 ps
CPU time 79.46 seconds
Started Jun 11 12:31:18 PM PDT 24
Finished Jun 11 12:32:40 PM PDT 24
Peak memory 216092 kb
Host smart-6d0b57ad-a3fb-453c-b3af-1ab01e6b37ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190419349 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.190419349
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.3989376565
Short name T857
Test name
Test status
Simulation time 51027654430 ps
CPU time 78.01 seconds
Started Jun 11 12:31:18 PM PDT 24
Finished Jun 11 12:32:39 PM PDT 24
Peak memory 200332 kb
Host smart-29cc47ea-94f6-418b-9388-0549165650b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989376565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.3989376565
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.4089114086
Short name T83
Test name
Test status
Simulation time 19653271512 ps
CPU time 183.28 seconds
Started Jun 11 12:31:17 PM PDT 24
Finished Jun 11 12:34:23 PM PDT 24
Peak memory 215492 kb
Host smart-0425d0e9-5b6c-45b8-843b-dc28edc23656
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089114086 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.4089114086
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.3690657848
Short name T659
Test name
Test status
Simulation time 76392438402 ps
CPU time 92.14 seconds
Started Jun 11 12:31:14 PM PDT 24
Finished Jun 11 12:32:49 PM PDT 24
Peak memory 200348 kb
Host smart-05bb62d0-013d-4bea-8ff7-cc37cfd02298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690657848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.3690657848
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.2602508476
Short name T309
Test name
Test status
Simulation time 46645204059 ps
CPU time 63.93 seconds
Started Jun 11 12:31:18 PM PDT 24
Finished Jun 11 12:32:25 PM PDT 24
Peak memory 200264 kb
Host smart-be121621-a03f-40b5-87d8-5e8567600006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602508476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.2602508476
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.1744382808
Short name T884
Test name
Test status
Simulation time 59537314116 ps
CPU time 292.46 seconds
Started Jun 11 12:31:15 PM PDT 24
Finished Jun 11 12:36:11 PM PDT 24
Peak memory 208576 kb
Host smart-807094ca-c355-47af-b282-abd7a607ee0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744382808 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.1744382808
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.3137671913
Short name T949
Test name
Test status
Simulation time 118991521638 ps
CPU time 46.18 seconds
Started Jun 11 12:31:16 PM PDT 24
Finished Jun 11 12:32:05 PM PDT 24
Peak memory 200348 kb
Host smart-1f4580eb-37f1-4aae-97de-ab46ac898ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137671913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.3137671913
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.3050074620
Short name T933
Test name
Test status
Simulation time 97133015513 ps
CPU time 381.36 seconds
Started Jun 11 12:31:16 PM PDT 24
Finished Jun 11 12:37:41 PM PDT 24
Peak memory 216888 kb
Host smart-15b3cc17-938e-452f-83d3-30f6c4b8ffce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050074620 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.3050074620
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.2922602249
Short name T1060
Test name
Test status
Simulation time 21839508611 ps
CPU time 36.39 seconds
Started Jun 11 12:31:14 PM PDT 24
Finished Jun 11 12:31:53 PM PDT 24
Peak memory 200324 kb
Host smart-43012316-531f-4fe4-bf66-81945ff65ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922602249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.2922602249
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.448456933
Short name T723
Test name
Test status
Simulation time 29983056464 ps
CPU time 689.97 seconds
Started Jun 11 12:31:13 PM PDT 24
Finished Jun 11 12:42:46 PM PDT 24
Peak memory 216788 kb
Host smart-589a5903-4226-428c-96f6-e14bd8eafee7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448456933 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.448456933
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.2332027117
Short name T106
Test name
Test status
Simulation time 32546592814 ps
CPU time 58.07 seconds
Started Jun 11 12:31:16 PM PDT 24
Finished Jun 11 12:32:18 PM PDT 24
Peak memory 200348 kb
Host smart-2712c8d0-b027-423e-9a9f-7899e0987bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332027117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.2332027117
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.466045923
Short name T1046
Test name
Test status
Simulation time 20175073883 ps
CPU time 505.4 seconds
Started Jun 11 12:31:13 PM PDT 24
Finished Jun 11 12:39:41 PM PDT 24
Peak memory 216892 kb
Host smart-028e10d4-3a49-45b5-ac3e-72bdc5d08de9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466045923 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.466045923
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.2368112256
Short name T443
Test name
Test status
Simulation time 11793526154 ps
CPU time 5.16 seconds
Started Jun 11 12:31:14 PM PDT 24
Finished Jun 11 12:31:22 PM PDT 24
Peak memory 200048 kb
Host smart-71a2112b-456e-4309-aefb-119ac7ca3e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368112256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.2368112256
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.748068030
Short name T321
Test name
Test status
Simulation time 11968899259 ps
CPU time 162.19 seconds
Started Jun 11 12:31:29 PM PDT 24
Finished Jun 11 12:34:12 PM PDT 24
Peak memory 208580 kb
Host smart-5ee6b31e-8cf8-40e7-939a-228aaf87a4d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748068030 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.748068030
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.3938318285
Short name T555
Test name
Test status
Simulation time 35525730 ps
CPU time 0.53 seconds
Started Jun 11 12:30:17 PM PDT 24
Finished Jun 11 12:30:21 PM PDT 24
Peak memory 195264 kb
Host smart-f550f2f1-94d9-4897-917f-625ee9962759
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938318285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.3938318285
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.1010607374
Short name T1017
Test name
Test status
Simulation time 52234080712 ps
CPU time 91.56 seconds
Started Jun 11 12:30:05 PM PDT 24
Finished Jun 11 12:31:40 PM PDT 24
Peak memory 198652 kb
Host smart-f0ebfc73-50e4-4e4b-9688-fd437969673b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010607374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.1010607374
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.3859963468
Short name T448
Test name
Test status
Simulation time 71848309080 ps
CPU time 55.86 seconds
Started Jun 11 12:29:16 PM PDT 24
Finished Jun 11 12:30:13 PM PDT 24
Peak memory 199840 kb
Host smart-4b685c07-e79a-4d16-971e-67e0b319e86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859963468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.3859963468
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.2525802180
Short name T892
Test name
Test status
Simulation time 26678657515 ps
CPU time 46.43 seconds
Started Jun 11 12:29:18 PM PDT 24
Finished Jun 11 12:30:06 PM PDT 24
Peak memory 200148 kb
Host smart-b754db25-e0c1-41c6-a8d9-869098258aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525802180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.2525802180
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.3990613124
Short name T685
Test name
Test status
Simulation time 22469116969 ps
CPU time 44.18 seconds
Started Jun 11 12:29:29 PM PDT 24
Finished Jun 11 12:30:15 PM PDT 24
Peak memory 200212 kb
Host smart-2eeaa6f1-c104-42c1-9acf-ad681e961c10
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990613124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.3990613124
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.989350620
Short name T404
Test name
Test status
Simulation time 94731478909 ps
CPU time 367.21 seconds
Started Jun 11 12:30:17 PM PDT 24
Finished Jun 11 12:36:27 PM PDT 24
Peak memory 199884 kb
Host smart-69f1d788-efc1-4f7b-b485-515f89ce4437
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=989350620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.989350620
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.497732491
Short name T391
Test name
Test status
Simulation time 2970635397 ps
CPU time 5.49 seconds
Started Jun 11 12:30:17 PM PDT 24
Finished Jun 11 12:30:25 PM PDT 24
Peak memory 198996 kb
Host smart-471c7fab-f405-4451-8a2a-1eb8233c3969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497732491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.497732491
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_perf.3085235730
Short name T405
Test name
Test status
Simulation time 18512100445 ps
CPU time 1021.45 seconds
Started Jun 11 12:28:58 PM PDT 24
Finished Jun 11 12:46:01 PM PDT 24
Peak memory 200284 kb
Host smart-f24dd23c-f17a-42e5-897c-9f88f845d751
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3085235730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.3085235730
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.3062836293
Short name T891
Test name
Test status
Simulation time 2115308222 ps
CPU time 9.83 seconds
Started Jun 11 12:28:57 PM PDT 24
Finished Jun 11 12:29:09 PM PDT 24
Peak memory 198708 kb
Host smart-75368a8e-0c63-4176-92aa-bbe382e3fe7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3062836293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.3062836293
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.152981472
Short name T1090
Test name
Test status
Simulation time 79907017785 ps
CPU time 39.74 seconds
Started Jun 11 12:30:05 PM PDT 24
Finished Jun 11 12:30:48 PM PDT 24
Peak memory 198508 kb
Host smart-b57f279b-be7e-42f4-ac40-a12d06ccf56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152981472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.152981472
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.1424853687
Short name T556
Test name
Test status
Simulation time 37884987206 ps
CPU time 59.81 seconds
Started Jun 11 12:29:15 PM PDT 24
Finished Jun 11 12:30:16 PM PDT 24
Peak memory 196204 kb
Host smart-591d46d3-4b87-4e8c-af30-c0bd481d42fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424853687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.1424853687
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.2627200346
Short name T275
Test name
Test status
Simulation time 507623180 ps
CPU time 3.51 seconds
Started Jun 11 12:28:57 PM PDT 24
Finished Jun 11 12:29:02 PM PDT 24
Peak memory 199888 kb
Host smart-cd301579-9d78-431f-bba5-6a58e3ae49ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627200346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.2627200346
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.1633029779
Short name T272
Test name
Test status
Simulation time 1686842941 ps
CPU time 2.41 seconds
Started Jun 11 12:28:58 PM PDT 24
Finished Jun 11 12:29:02 PM PDT 24
Peak memory 198552 kb
Host smart-1505e2ab-f6c0-4ffa-827e-c980b9f22afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633029779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.1633029779
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.1364011599
Short name T738
Test name
Test status
Simulation time 20727612919 ps
CPU time 13.66 seconds
Started Jun 11 12:28:57 PM PDT 24
Finished Jun 11 12:29:13 PM PDT 24
Peak memory 200068 kb
Host smart-d63eaa59-9ce1-40a7-bafd-82ffaa6b75b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364011599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.1364011599
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.1089180549
Short name T84
Test name
Test status
Simulation time 97987103071 ps
CPU time 1308.49 seconds
Started Jun 11 12:31:26 PM PDT 24
Finished Jun 11 12:53:15 PM PDT 24
Peak memory 216820 kb
Host smart-efc07eec-8591-42b1-951a-1bb40771fa5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089180549 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.1089180549
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.1157362612
Short name T663
Test name
Test status
Simulation time 58639193712 ps
CPU time 94.58 seconds
Started Jun 11 12:31:32 PM PDT 24
Finished Jun 11 12:33:08 PM PDT 24
Peak memory 200348 kb
Host smart-5885dee2-1562-4bc6-9b91-c76312226ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157362612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.1157362612
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.3115643937
Short name T86
Test name
Test status
Simulation time 62850364115 ps
CPU time 425.64 seconds
Started Jun 11 12:31:26 PM PDT 24
Finished Jun 11 12:38:33 PM PDT 24
Peak memory 216724 kb
Host smart-74327eda-0fc4-44c0-af87-35e73baa6a58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115643937 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.3115643937
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.2921147547
Short name T141
Test name
Test status
Simulation time 20865747714 ps
CPU time 31.78 seconds
Started Jun 11 12:31:26 PM PDT 24
Finished Jun 11 12:31:59 PM PDT 24
Peak memory 200052 kb
Host smart-b91db6d7-67b2-4d16-a098-682848e782ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921147547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.2921147547
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.1135013997
Short name T1049
Test name
Test status
Simulation time 62233888146 ps
CPU time 926.59 seconds
Started Jun 11 12:31:27 PM PDT 24
Finished Jun 11 12:46:55 PM PDT 24
Peak memory 225072 kb
Host smart-e7ca65a1-7c7d-4089-8c93-8b965fcbcd7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135013997 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.1135013997
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.1983986566
Short name T904
Test name
Test status
Simulation time 59826826656 ps
CPU time 139.49 seconds
Started Jun 11 12:31:27 PM PDT 24
Finished Jun 11 12:33:48 PM PDT 24
Peak memory 200344 kb
Host smart-625a3c7f-ba6b-41ca-965e-725522139799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983986566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.1983986566
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.894100145
Short name T168
Test name
Test status
Simulation time 281633285586 ps
CPU time 50.34 seconds
Started Jun 11 12:31:26 PM PDT 24
Finished Jun 11 12:32:17 PM PDT 24
Peak memory 200296 kb
Host smart-74c5119e-3424-4124-ab61-26030a38f8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894100145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.894100145
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.3794285186
Short name T1076
Test name
Test status
Simulation time 120582098124 ps
CPU time 98.62 seconds
Started Jun 11 12:31:27 PM PDT 24
Finished Jun 11 12:33:07 PM PDT 24
Peak memory 216004 kb
Host smart-76461ca5-7cb7-4300-912e-40de2b942b00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794285186 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.3794285186
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.3246248699
Short name T238
Test name
Test status
Simulation time 85249092234 ps
CPU time 130.68 seconds
Started Jun 11 12:31:29 PM PDT 24
Finished Jun 11 12:33:41 PM PDT 24
Peak memory 200376 kb
Host smart-eeb4bdb1-0a20-467c-bedd-3c6f300aa8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246248699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.3246248699
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.2230387353
Short name T99
Test name
Test status
Simulation time 80967875034 ps
CPU time 1857.3 seconds
Started Jun 11 12:31:34 PM PDT 24
Finished Jun 11 01:02:32 PM PDT 24
Peak memory 216720 kb
Host smart-c8ed5e8b-9074-4820-8c12-ec0dc67346a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230387353 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.2230387353
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.4140101145
Short name T181
Test name
Test status
Simulation time 55227253758 ps
CPU time 40.24 seconds
Started Jun 11 12:31:27 PM PDT 24
Finished Jun 11 12:32:09 PM PDT 24
Peak memory 200568 kb
Host smart-9102241c-b2c4-45ca-a506-7d941e758140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140101145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.4140101145
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.3027125732
Short name T17
Test name
Test status
Simulation time 115130652162 ps
CPU time 1173.96 seconds
Started Jun 11 12:31:26 PM PDT 24
Finished Jun 11 12:51:02 PM PDT 24
Peak memory 224976 kb
Host smart-f71f47c1-5fd9-4c6b-a70d-3cefbe20a434
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027125732 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.3027125732
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.886870317
Short name T972
Test name
Test status
Simulation time 5989890537 ps
CPU time 9.75 seconds
Started Jun 11 12:31:27 PM PDT 24
Finished Jun 11 12:31:38 PM PDT 24
Peak memory 198692 kb
Host smart-d4b73936-3329-4c4c-ab5c-851098b8eec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886870317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.886870317
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.220764803
Short name T29
Test name
Test status
Simulation time 12943445781 ps
CPU time 145.36 seconds
Started Jun 11 12:31:25 PM PDT 24
Finished Jun 11 12:33:51 PM PDT 24
Peak memory 216800 kb
Host smart-8bd39da5-2d58-43d7-9524-d05d9f287317
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220764803 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.220764803
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.3043700448
Short name T850
Test name
Test status
Simulation time 17669809822 ps
CPU time 176.86 seconds
Started Jun 11 12:31:26 PM PDT 24
Finished Jun 11 12:34:25 PM PDT 24
Peak memory 216836 kb
Host smart-edde8f90-ace6-402c-9a70-f3f5af23dfb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043700448 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.3043700448
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.3570669807
Short name T134
Test name
Test status
Simulation time 21704212868 ps
CPU time 12.69 seconds
Started Jun 11 12:31:26 PM PDT 24
Finished Jun 11 12:31:40 PM PDT 24
Peak memory 200284 kb
Host smart-1ceed22b-c0c3-4f4b-8211-7f9494e6b5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570669807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.3570669807
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.1112997241
Short name T975
Test name
Test status
Simulation time 15381294 ps
CPU time 0.56 seconds
Started Jun 11 12:29:16 PM PDT 24
Finished Jun 11 12:29:18 PM PDT 24
Peak memory 195708 kb
Host smart-01b4e31f-da16-46c1-94b1-78279083dd62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112997241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.1112997241
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.1864512069
Short name T1091
Test name
Test status
Simulation time 47988223382 ps
CPU time 65.23 seconds
Started Jun 11 12:30:17 PM PDT 24
Finished Jun 11 12:31:25 PM PDT 24
Peak memory 199900 kb
Host smart-9640ace9-a9dc-4c2d-a773-748fe69133f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864512069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.1864512069
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.2583260353
Short name T1051
Test name
Test status
Simulation time 112467727838 ps
CPU time 50.72 seconds
Started Jun 11 12:29:05 PM PDT 24
Finished Jun 11 12:29:58 PM PDT 24
Peak memory 199768 kb
Host smart-584e3e6a-cf0a-4fce-b68e-4381b1ce3653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583260353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.2583260353
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.139311633
Short name T176
Test name
Test status
Simulation time 44585726551 ps
CPU time 81.21 seconds
Started Jun 11 12:29:16 PM PDT 24
Finished Jun 11 12:30:38 PM PDT 24
Peak memory 200220 kb
Host smart-f50a69bb-4239-41ce-825c-45ea95f7b088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139311633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.139311633
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.1785962945
Short name T875
Test name
Test status
Simulation time 77290833616 ps
CPU time 114.36 seconds
Started Jun 11 12:29:19 PM PDT 24
Finished Jun 11 12:31:14 PM PDT 24
Peak memory 200180 kb
Host smart-bae16e30-c1ee-471f-a966-2c39df5f8ec0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785962945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.1785962945
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.1373272071
Short name T483
Test name
Test status
Simulation time 85601550851 ps
CPU time 675.36 seconds
Started Jun 11 12:29:05 PM PDT 24
Finished Jun 11 12:40:22 PM PDT 24
Peak memory 200264 kb
Host smart-3dd8c20b-fe91-4372-beef-79bf852aaa23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1373272071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.1373272071
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.1228129202
Short name T965
Test name
Test status
Simulation time 3035133839 ps
CPU time 7.09 seconds
Started Jun 11 12:29:11 PM PDT 24
Finished Jun 11 12:29:19 PM PDT 24
Peak memory 199692 kb
Host smart-484ef650-3797-4cf3-82f0-2c8cd2231e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228129202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.1228129202
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_perf.3954616652
Short name T815
Test name
Test status
Simulation time 21418681206 ps
CPU time 379.5 seconds
Started Jun 11 12:29:09 PM PDT 24
Finished Jun 11 12:35:30 PM PDT 24
Peak memory 200300 kb
Host smart-323bf019-690b-4700-af46-9f0a66c21611
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3954616652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.3954616652
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.4294629072
Short name T905
Test name
Test status
Simulation time 4903082738 ps
CPU time 15.12 seconds
Started Jun 11 12:29:10 PM PDT 24
Finished Jun 11 12:29:27 PM PDT 24
Peak memory 199772 kb
Host smart-95b40549-657d-4298-849c-d66a6b2c87b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4294629072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.4294629072
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.752841554
Short name T543
Test name
Test status
Simulation time 36524669301 ps
CPU time 54.02 seconds
Started Jun 11 12:29:13 PM PDT 24
Finished Jun 11 12:30:08 PM PDT 24
Peak memory 200096 kb
Host smart-f008d325-e739-4cf0-8e55-3dcc078d8159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752841554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.752841554
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.2247640427
Short name T827
Test name
Test status
Simulation time 41209814372 ps
CPU time 33.38 seconds
Started Jun 11 12:29:20 PM PDT 24
Finished Jun 11 12:29:55 PM PDT 24
Peak memory 196108 kb
Host smart-acd85ccd-98d3-4fe0-be64-e444f4895e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247640427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.2247640427
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.1257826293
Short name T847
Test name
Test status
Simulation time 675022242 ps
CPU time 1.77 seconds
Started Jun 11 12:29:24 PM PDT 24
Finished Jun 11 12:29:27 PM PDT 24
Peak memory 199136 kb
Host smart-25925623-5b3b-4537-b1c6-3b080acd4345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257826293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.1257826293
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.2129865680
Short name T881
Test name
Test status
Simulation time 212308992752 ps
CPU time 1335.87 seconds
Started Jun 11 12:29:14 PM PDT 24
Finished Jun 11 12:51:31 PM PDT 24
Peak memory 225368 kb
Host smart-25b86039-bad9-4797-86ea-4b69f265fc1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129865680 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.2129865680
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.1453713519
Short name T312
Test name
Test status
Simulation time 7398615696 ps
CPU time 21.62 seconds
Started Jun 11 12:29:34 PM PDT 24
Finished Jun 11 12:29:57 PM PDT 24
Peak memory 200300 kb
Host smart-f7773c3a-e1b6-4a3f-97fe-cc2303fb60d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453713519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.1453713519
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.1543204970
Short name T457
Test name
Test status
Simulation time 16358484980 ps
CPU time 7.7 seconds
Started Jun 11 12:30:17 PM PDT 24
Finished Jun 11 12:30:28 PM PDT 24
Peak memory 199836 kb
Host smart-ee5b9238-19f9-4060-8d84-cd0f54552dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543204970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.1543204970
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.4209210799
Short name T82
Test name
Test status
Simulation time 65966402437 ps
CPU time 204.1 seconds
Started Jun 11 12:31:28 PM PDT 24
Finished Jun 11 12:34:54 PM PDT 24
Peak memory 208684 kb
Host smart-1360238e-d851-4a88-84fb-1534c69b725e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209210799 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.4209210799
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.2075287385
Short name T1096
Test name
Test status
Simulation time 148918818119 ps
CPU time 140.99 seconds
Started Jun 11 12:31:29 PM PDT 24
Finished Jun 11 12:33:51 PM PDT 24
Peak memory 200292 kb
Host smart-a574de42-432a-4317-b71f-f74668b7ae2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075287385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.2075287385
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.4287077885
Short name T839
Test name
Test status
Simulation time 19424695331 ps
CPU time 453.75 seconds
Started Jun 11 12:31:27 PM PDT 24
Finished Jun 11 12:39:02 PM PDT 24
Peak memory 216024 kb
Host smart-260eea8a-0bab-486b-bd07-d2042b9a7392
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287077885 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.4287077885
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.3377274010
Short name T193
Test name
Test status
Simulation time 92411244864 ps
CPU time 101.65 seconds
Started Jun 11 12:31:28 PM PDT 24
Finished Jun 11 12:33:11 PM PDT 24
Peak memory 200248 kb
Host smart-b3da8c8e-5c2c-460b-870e-f435a423af51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377274010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.3377274010
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.2975789715
Short name T302
Test name
Test status
Simulation time 112959404067 ps
CPU time 104.44 seconds
Started Jun 11 12:31:33 PM PDT 24
Finished Jun 11 12:33:18 PM PDT 24
Peak memory 200348 kb
Host smart-8d80cefa-f1db-4915-97c0-95b751f95605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975789715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.2975789715
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.2082427665
Short name T468
Test name
Test status
Simulation time 23224139965 ps
CPU time 9.79 seconds
Started Jun 11 12:31:27 PM PDT 24
Finished Jun 11 12:31:38 PM PDT 24
Peak memory 199140 kb
Host smart-3e6c23f3-7d57-4512-af25-089e18ce70aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082427665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.2082427665
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.3422451906
Short name T1006
Test name
Test status
Simulation time 62817903073 ps
CPU time 299.32 seconds
Started Jun 11 12:31:30 PM PDT 24
Finished Jun 11 12:36:30 PM PDT 24
Peak memory 216860 kb
Host smart-c1ed68a9-54ae-4b3e-a67e-c61e5705d6c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422451906 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.3422451906
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.4277496531
Short name T228
Test name
Test status
Simulation time 166551398978 ps
CPU time 87.85 seconds
Started Jun 11 12:31:29 PM PDT 24
Finished Jun 11 12:32:59 PM PDT 24
Peak memory 200308 kb
Host smart-98b99ba8-c836-44a2-a5b0-d65e9a55d4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277496531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.4277496531
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.3090511314
Short name T669
Test name
Test status
Simulation time 47580770198 ps
CPU time 19.86 seconds
Started Jun 11 12:31:27 PM PDT 24
Finished Jun 11 12:31:48 PM PDT 24
Peak memory 200268 kb
Host smart-a2ad9919-c0b0-4f75-b671-606157400549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090511314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.3090511314
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.1700445365
Short name T323
Test name
Test status
Simulation time 71158989072 ps
CPU time 1237.89 seconds
Started Jun 11 12:31:29 PM PDT 24
Finished Jun 11 12:52:08 PM PDT 24
Peak memory 216680 kb
Host smart-d17c527c-b15d-4f2d-8001-2e3cd2cf5adf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700445365 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.1700445365
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.1354150304
Short name T179
Test name
Test status
Simulation time 65749942730 ps
CPU time 95.69 seconds
Started Jun 11 12:31:29 PM PDT 24
Finished Jun 11 12:33:06 PM PDT 24
Peak memory 200264 kb
Host smart-c5ac1cf7-f811-4399-a9f1-78522937ffe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354150304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.1354150304
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.1979830406
Short name T988
Test name
Test status
Simulation time 64701466017 ps
CPU time 782.6 seconds
Started Jun 11 12:31:26 PM PDT 24
Finished Jun 11 12:44:29 PM PDT 24
Peak memory 225080 kb
Host smart-1597688c-f15a-4d16-a7ab-011c750995f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979830406 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.1979830406
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.3122743422
Short name T758
Test name
Test status
Simulation time 94235515195 ps
CPU time 44.94 seconds
Started Jun 11 12:31:28 PM PDT 24
Finished Jun 11 12:32:14 PM PDT 24
Peak memory 200256 kb
Host smart-14570e12-04a5-4469-9a5d-ef9756c7e806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122743422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.3122743422
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.1216407565
Short name T831
Test name
Test status
Simulation time 28484760857 ps
CPU time 18.98 seconds
Started Jun 11 12:31:27 PM PDT 24
Finished Jun 11 12:31:47 PM PDT 24
Peak memory 199580 kb
Host smart-403b4596-1477-4ccd-9309-3f39c6b91f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216407565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.1216407565
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.2597508711
Short name T7
Test name
Test status
Simulation time 11428113 ps
CPU time 0.59 seconds
Started Jun 11 12:29:11 PM PDT 24
Finished Jun 11 12:29:13 PM PDT 24
Peak memory 195688 kb
Host smart-ba14c752-e21c-4f65-bab9-c327853516e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597508711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.2597508711
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.4100056292
Short name T359
Test name
Test status
Simulation time 8645220929 ps
CPU time 16.03 seconds
Started Jun 11 12:29:05 PM PDT 24
Finished Jun 11 12:29:23 PM PDT 24
Peak memory 200288 kb
Host smart-82fa6013-111c-4ce6-ac72-964721dc27ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100056292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.4100056292
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.3372117515
Short name T805
Test name
Test status
Simulation time 26492632463 ps
CPU time 46.11 seconds
Started Jun 11 12:29:15 PM PDT 24
Finished Jun 11 12:30:02 PM PDT 24
Peak memory 200496 kb
Host smart-46875d77-5d55-423d-aafe-93557b9b8b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372117515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.3372117515
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.2532632546
Short name T94
Test name
Test status
Simulation time 33185941917 ps
CPU time 17.34 seconds
Started Jun 11 12:29:12 PM PDT 24
Finished Jun 11 12:29:30 PM PDT 24
Peak memory 200356 kb
Host smart-fda1894e-a7b1-4802-ab59-de6278449c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532632546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.2532632546
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.223057115
Short name T96
Test name
Test status
Simulation time 48530179281 ps
CPU time 19.59 seconds
Started Jun 11 12:29:27 PM PDT 24
Finished Jun 11 12:29:49 PM PDT 24
Peak memory 200272 kb
Host smart-f2d175d0-9ef2-4496-a0aa-f5068f1fa337
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223057115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.223057115
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.323684048
Short name T460
Test name
Test status
Simulation time 114641126536 ps
CPU time 180.42 seconds
Started Jun 11 12:29:08 PM PDT 24
Finished Jun 11 12:32:10 PM PDT 24
Peak memory 200304 kb
Host smart-2885f4d4-1e4c-46fa-805e-bdc32dfa2fdf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=323684048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.323684048
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.333467376
Short name T691
Test name
Test status
Simulation time 11307719759 ps
CPU time 8.23 seconds
Started Jun 11 12:29:09 PM PDT 24
Finished Jun 11 12:29:18 PM PDT 24
Peak memory 200072 kb
Host smart-84588c3b-ff1b-4296-8dbe-48dcb159ae93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333467376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.333467376
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_perf.2426170732
Short name T410
Test name
Test status
Simulation time 13209390815 ps
CPU time 641.59 seconds
Started Jun 11 12:29:12 PM PDT 24
Finished Jun 11 12:39:55 PM PDT 24
Peak memory 200312 kb
Host smart-405bf454-e55f-439c-b7c1-584ba1d7e6d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2426170732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.2426170732
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.372064827
Short name T1073
Test name
Test status
Simulation time 5242514301 ps
CPU time 44.81 seconds
Started Jun 11 12:29:10 PM PDT 24
Finished Jun 11 12:29:56 PM PDT 24
Peak memory 199640 kb
Host smart-62caa06a-a397-4b5e-bd2c-114db0d0780f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=372064827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.372064827
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.799474625
Short name T608
Test name
Test status
Simulation time 79437262692 ps
CPU time 41.18 seconds
Started Jun 11 12:29:10 PM PDT 24
Finished Jun 11 12:29:52 PM PDT 24
Peak memory 200104 kb
Host smart-7353b5aa-37d6-4f26-b1f1-f58b7646a135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799474625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.799474625
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.731516201
Short name T590
Test name
Test status
Simulation time 2833482654 ps
CPU time 5.51 seconds
Started Jun 11 12:29:09 PM PDT 24
Finished Jun 11 12:29:15 PM PDT 24
Peak memory 195944 kb
Host smart-924f27c1-7533-4326-84ca-d4ea86ee3b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731516201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.731516201
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.1475483477
Short name T285
Test name
Test status
Simulation time 464601156 ps
CPU time 1.4 seconds
Started Jun 11 12:29:02 PM PDT 24
Finished Jun 11 12:29:06 PM PDT 24
Peak memory 198848 kb
Host smart-67138664-76a9-4e8a-b96c-839773792b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475483477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.1475483477
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.2912293327
Short name T237
Test name
Test status
Simulation time 385074834707 ps
CPU time 331.81 seconds
Started Jun 11 12:29:08 PM PDT 24
Finished Jun 11 12:34:41 PM PDT 24
Peak memory 200284 kb
Host smart-c54a3cf3-594e-49c2-adb9-59e2bfdcf5d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912293327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.2912293327
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.1021060995
Short name T290
Test name
Test status
Simulation time 1238731358 ps
CPU time 2.27 seconds
Started Jun 11 12:29:10 PM PDT 24
Finished Jun 11 12:29:13 PM PDT 24
Peak memory 199440 kb
Host smart-221b91d6-417e-430b-baab-5ac70a2d5e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021060995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.1021060995
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.2067040457
Short name T449
Test name
Test status
Simulation time 39421025947 ps
CPU time 53.7 seconds
Started Jun 11 12:29:10 PM PDT 24
Finished Jun 11 12:30:05 PM PDT 24
Peak memory 200288 kb
Host smart-eafc03f0-03f7-490c-a074-e280e08930a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067040457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.2067040457
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.2742907302
Short name T643
Test name
Test status
Simulation time 110652320935 ps
CPU time 101.12 seconds
Started Jun 11 12:31:28 PM PDT 24
Finished Jun 11 12:33:10 PM PDT 24
Peak memory 200268 kb
Host smart-9da15e5b-6261-43a7-aaa5-dfdea1ff9c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742907302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.2742907302
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.2777286319
Short name T630
Test name
Test status
Simulation time 25741729018 ps
CPU time 289.48 seconds
Started Jun 11 12:31:27 PM PDT 24
Finished Jun 11 12:36:18 PM PDT 24
Peak memory 215696 kb
Host smart-b20ef124-0d8e-4239-ac37-b937fdaf20c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777286319 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.2777286319
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.327887118
Short name T922
Test name
Test status
Simulation time 46556172842 ps
CPU time 18.26 seconds
Started Jun 11 12:31:29 PM PDT 24
Finished Jun 11 12:31:49 PM PDT 24
Peak memory 200312 kb
Host smart-fda89d52-970f-4b54-9cfa-fec3ff4e3d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327887118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.327887118
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.96104770
Short name T98
Test name
Test status
Simulation time 31700260477 ps
CPU time 311.81 seconds
Started Jun 11 12:31:28 PM PDT 24
Finished Jun 11 12:36:41 PM PDT 24
Peak memory 216820 kb
Host smart-cb0fc77e-2cf8-418e-821f-ec686abe7b6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96104770 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.96104770
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.3699304659
Short name T943
Test name
Test status
Simulation time 119308714149 ps
CPU time 34.34 seconds
Started Jun 11 12:31:27 PM PDT 24
Finished Jun 11 12:32:02 PM PDT 24
Peak memory 200068 kb
Host smart-785c3851-6d9b-44e3-bbdb-8b52c61ee01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699304659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.3699304659
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.1744399610
Short name T100
Test name
Test status
Simulation time 182776489063 ps
CPU time 1025.87 seconds
Started Jun 11 12:31:28 PM PDT 24
Finished Jun 11 12:48:36 PM PDT 24
Peak memory 216740 kb
Host smart-8f4f6c18-cdc1-4624-8c2d-796b80137436
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744399610 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.1744399610
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.1641204962
Short name T227
Test name
Test status
Simulation time 34084578039 ps
CPU time 20.85 seconds
Started Jun 11 12:31:28 PM PDT 24
Finished Jun 11 12:31:50 PM PDT 24
Peak memory 200328 kb
Host smart-b105e809-c974-4615-a805-8b11566debd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641204962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.1641204962
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.470211196
Short name T920
Test name
Test status
Simulation time 103773748505 ps
CPU time 84.6 seconds
Started Jun 11 12:31:27 PM PDT 24
Finished Jun 11 12:32:53 PM PDT 24
Peak memory 200264 kb
Host smart-d3ce2eb0-1ae4-461a-888c-a6ce55dfbea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470211196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.470211196
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.3983167891
Short name T908
Test name
Test status
Simulation time 120941148678 ps
CPU time 181.98 seconds
Started Jun 11 12:31:30 PM PDT 24
Finished Jun 11 12:34:33 PM PDT 24
Peak memory 200248 kb
Host smart-245bda99-a485-4b7e-a7ec-4b2dff21ce38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983167891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.3983167891
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.3685046910
Short name T469
Test name
Test status
Simulation time 167659630679 ps
CPU time 251.34 seconds
Started Jun 11 12:31:31 PM PDT 24
Finished Jun 11 12:35:43 PM PDT 24
Peak memory 200312 kb
Host smart-fccb6aa6-9abf-40c8-8624-c154b503db7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685046910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.3685046910
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.1380075717
Short name T719
Test name
Test status
Simulation time 182972425039 ps
CPU time 302.15 seconds
Started Jun 11 12:31:32 PM PDT 24
Finished Jun 11 12:36:35 PM PDT 24
Peak memory 200348 kb
Host smart-7c590921-0f88-4477-9599-ebf9f9a4a16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380075717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.1380075717
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.2941914465
Short name T885
Test name
Test status
Simulation time 33866667107 ps
CPU time 48.53 seconds
Started Jun 11 12:31:29 PM PDT 24
Finished Jun 11 12:32:19 PM PDT 24
Peak memory 200284 kb
Host smart-fddb3658-0b06-4cba-abf2-e49aed006646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941914465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.2941914465
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.2318265469
Short name T525
Test name
Test status
Simulation time 159740645397 ps
CPU time 497.27 seconds
Started Jun 11 12:31:30 PM PDT 24
Finished Jun 11 12:39:49 PM PDT 24
Peak memory 215252 kb
Host smart-4a72aab8-4e3d-461a-956a-6f776b187d8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318265469 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.2318265469
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.1091350065
Short name T173
Test name
Test status
Simulation time 100741567605 ps
CPU time 196.01 seconds
Started Jun 11 12:31:34 PM PDT 24
Finished Jun 11 12:34:50 PM PDT 24
Peak memory 200188 kb
Host smart-bc143e94-3bd2-4978-b454-de810ca07b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091350065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.1091350065
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.2816318041
Short name T422
Test name
Test status
Simulation time 48041256 ps
CPU time 0.54 seconds
Started Jun 11 12:29:14 PM PDT 24
Finished Jun 11 12:29:16 PM PDT 24
Peak memory 195736 kb
Host smart-4f4abd08-bc75-496d-9a7c-8229b448e395
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816318041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.2816318041
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.842198718
Short name T138
Test name
Test status
Simulation time 47532186881 ps
CPU time 22.49 seconds
Started Jun 11 12:29:10 PM PDT 24
Finished Jun 11 12:29:34 PM PDT 24
Peak memory 200200 kb
Host smart-f0d04918-f980-43b6-b427-97b0f70b996e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842198718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.842198718
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.2145651499
Short name T516
Test name
Test status
Simulation time 26504268794 ps
CPU time 16.58 seconds
Started Jun 11 12:29:03 PM PDT 24
Finished Jun 11 12:29:22 PM PDT 24
Peak memory 199944 kb
Host smart-5a4c332b-4b58-4164-aaaa-a690e54188db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145651499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.2145651499
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.3452325502
Short name T197
Test name
Test status
Simulation time 105484806736 ps
CPU time 24.8 seconds
Started Jun 11 12:29:08 PM PDT 24
Finished Jun 11 12:29:34 PM PDT 24
Peak memory 200208 kb
Host smart-4bb0274b-2278-49a0-aa52-c5db41cbe424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452325502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.3452325502
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.4259543680
Short name T397
Test name
Test status
Simulation time 32632335012 ps
CPU time 21.23 seconds
Started Jun 11 12:29:14 PM PDT 24
Finished Jun 11 12:29:36 PM PDT 24
Peak memory 200248 kb
Host smart-fc03eac0-32c6-4876-bc26-fc2dd20a7a0c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259543680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.4259543680
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.4185861413
Short name T750
Test name
Test status
Simulation time 92577642163 ps
CPU time 196.1 seconds
Started Jun 11 12:29:21 PM PDT 24
Finished Jun 11 12:32:38 PM PDT 24
Peak memory 200352 kb
Host smart-e8a5be58-69f3-45a6-9998-37b17870de54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4185861413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.4185861413
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.1517021590
Short name T353
Test name
Test status
Simulation time 3795723463 ps
CPU time 3.59 seconds
Started Jun 11 12:29:24 PM PDT 24
Finished Jun 11 12:29:29 PM PDT 24
Peak memory 197652 kb
Host smart-0c54339f-19c6-48d4-a0a7-9849c52c913d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517021590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.1517021590
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_perf.1384153197
Short name T1095
Test name
Test status
Simulation time 16930957968 ps
CPU time 180.81 seconds
Started Jun 11 12:29:36 PM PDT 24
Finished Jun 11 12:32:38 PM PDT 24
Peak memory 200264 kb
Host smart-8f3282c7-c4db-4fcf-a6d3-04e0af907ecc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1384153197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.1384153197
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.181635133
Short name T652
Test name
Test status
Simulation time 1484861758 ps
CPU time 4.87 seconds
Started Jun 11 12:29:25 PM PDT 24
Finished Jun 11 12:29:31 PM PDT 24
Peak memory 198860 kb
Host smart-967ec7b5-28fa-4b58-a636-20aa3fe38689
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=181635133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.181635133
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.3672952268
Short name T143
Test name
Test status
Simulation time 89869200354 ps
CPU time 75.25 seconds
Started Jun 11 12:29:18 PM PDT 24
Finished Jun 11 12:30:34 PM PDT 24
Peak memory 200312 kb
Host smart-ea1d0ff1-4026-4c40-8e83-1c0586c44c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672952268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.3672952268
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.2451849494
Short name T88
Test name
Test status
Simulation time 5116962082 ps
CPU time 2.58 seconds
Started Jun 11 12:29:16 PM PDT 24
Finished Jun 11 12:29:20 PM PDT 24
Peak memory 196532 kb
Host smart-f2bb016c-ba3a-41c3-81f9-2ac2f85ea916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451849494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.2451849494
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.200128414
Short name T371
Test name
Test status
Simulation time 452831429 ps
CPU time 1.98 seconds
Started Jun 11 12:29:23 PM PDT 24
Finished Jun 11 12:29:26 PM PDT 24
Peak memory 198676 kb
Host smart-f63f7b24-2b29-4f05-a7f4-0377c3d412f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200128414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.200128414
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.183131883
Short name T242
Test name
Test status
Simulation time 188249164445 ps
CPU time 258.6 seconds
Started Jun 11 12:29:24 PM PDT 24
Finished Jun 11 12:33:44 PM PDT 24
Peak memory 200348 kb
Host smart-dbe6108c-1539-4998-ba18-767fc1058d66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183131883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.183131883
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.989113672
Short name T713
Test name
Test status
Simulation time 209495729811 ps
CPU time 643.91 seconds
Started Jun 11 12:29:14 PM PDT 24
Finished Jun 11 12:40:00 PM PDT 24
Peak memory 216768 kb
Host smart-b2f0a072-a4c7-43d8-8466-82ab52f6f51b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989113672 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.989113672
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.3567574274
Short name T898
Test name
Test status
Simulation time 1055978753 ps
CPU time 1.63 seconds
Started Jun 11 12:29:23 PM PDT 24
Finished Jun 11 12:29:26 PM PDT 24
Peak memory 199488 kb
Host smart-09f3b540-4dd5-4cde-bd7c-c7330f5ed29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567574274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.3567574274
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.1096516467
Short name T829
Test name
Test status
Simulation time 136040417054 ps
CPU time 201.11 seconds
Started Jun 11 12:29:15 PM PDT 24
Finished Jun 11 12:32:38 PM PDT 24
Peak memory 200272 kb
Host smart-6b39994a-d98a-4f03-88fb-11970a72e2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096516467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.1096516467
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.761847888
Short name T932
Test name
Test status
Simulation time 10415826072 ps
CPU time 16.58 seconds
Started Jun 11 12:31:29 PM PDT 24
Finished Jun 11 12:31:47 PM PDT 24
Peak memory 200296 kb
Host smart-00f4586c-fc59-476b-aec3-19618707f0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761847888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.761847888
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.183150455
Short name T971
Test name
Test status
Simulation time 206415555965 ps
CPU time 58.23 seconds
Started Jun 11 12:31:29 PM PDT 24
Finished Jun 11 12:32:29 PM PDT 24
Peak memory 200356 kb
Host smart-2ca56e63-c825-480c-848f-631c8e82e8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183150455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.183150455
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.3328748356
Short name T812
Test name
Test status
Simulation time 119240022535 ps
CPU time 677.85 seconds
Started Jun 11 12:31:34 PM PDT 24
Finished Jun 11 12:42:52 PM PDT 24
Peak memory 216488 kb
Host smart-157db810-d83f-47ea-bb0d-42f6124c99f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328748356 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.3328748356
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.2061340977
Short name T320
Test name
Test status
Simulation time 77467583095 ps
CPU time 26.21 seconds
Started Jun 11 12:31:44 PM PDT 24
Finished Jun 11 12:32:11 PM PDT 24
Peak memory 200252 kb
Host smart-869b8ef8-0187-448e-b452-84b4b0841e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061340977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.2061340977
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.1864047693
Short name T129
Test name
Test status
Simulation time 26134684507 ps
CPU time 29.51 seconds
Started Jun 11 12:31:39 PM PDT 24
Finished Jun 11 12:32:09 PM PDT 24
Peak memory 200328 kb
Host smart-04d7f012-a88e-487a-92a4-28b505d28801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864047693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.1864047693
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.32078300
Short name T35
Test name
Test status
Simulation time 66101581547 ps
CPU time 331.8 seconds
Started Jun 11 12:31:38 PM PDT 24
Finished Jun 11 12:37:11 PM PDT 24
Peak memory 216740 kb
Host smart-25a619da-d8f6-4545-9e05-de5cf209eccc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32078300 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.32078300
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.1449365806
Short name T189
Test name
Test status
Simulation time 24659544191 ps
CPU time 18.4 seconds
Started Jun 11 12:31:38 PM PDT 24
Finished Jun 11 12:31:58 PM PDT 24
Peak memory 200308 kb
Host smart-35e37d78-29e8-4c02-aa0b-617e6558c6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449365806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.1449365806
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.2716482180
Short name T968
Test name
Test status
Simulation time 36280880615 ps
CPU time 336.35 seconds
Started Jun 11 12:31:54 PM PDT 24
Finished Jun 11 12:37:32 PM PDT 24
Peak memory 208664 kb
Host smart-df62fe26-d845-4161-b879-e1246ec304c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716482180 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.2716482180
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.882531291
Short name T1053
Test name
Test status
Simulation time 178618914876 ps
CPU time 27.18 seconds
Started Jun 11 12:31:40 PM PDT 24
Finished Jun 11 12:32:09 PM PDT 24
Peak memory 200248 kb
Host smart-31481699-6cc1-4482-ace8-c1f583c5e7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882531291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.882531291
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.2838831894
Short name T654
Test name
Test status
Simulation time 22833109902 ps
CPU time 340.88 seconds
Started Jun 11 12:31:38 PM PDT 24
Finished Jun 11 12:37:21 PM PDT 24
Peak memory 208612 kb
Host smart-779cd758-5f39-4006-9fbc-8271a4ebedbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838831894 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.2838831894
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.3192618066
Short name T740
Test name
Test status
Simulation time 155901042941 ps
CPU time 58.29 seconds
Started Jun 11 12:31:47 PM PDT 24
Finished Jun 11 12:32:46 PM PDT 24
Peak memory 200260 kb
Host smart-4656e3b2-9406-43aa-9324-584abd43d549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192618066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.3192618066
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.3783351286
Short name T636
Test name
Test status
Simulation time 137133295724 ps
CPU time 377.3 seconds
Started Jun 11 12:31:39 PM PDT 24
Finished Jun 11 12:37:58 PM PDT 24
Peak memory 216496 kb
Host smart-e3f7bab8-76d9-4e03-b981-f79ae48a1548
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783351286 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.3783351286
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.2840942312
Short name T240
Test name
Test status
Simulation time 378990954129 ps
CPU time 68.85 seconds
Started Jun 11 12:31:39 PM PDT 24
Finished Jun 11 12:32:49 PM PDT 24
Peak memory 200316 kb
Host smart-033c1537-7e1b-44c6-8b8b-a2a9a0dabb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840942312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.2840942312
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.3949287727
Short name T81
Test name
Test status
Simulation time 8061576370 ps
CPU time 75.94 seconds
Started Jun 11 12:31:47 PM PDT 24
Finished Jun 11 12:33:04 PM PDT 24
Peak memory 208644 kb
Host smart-4a85b6b2-6bda-4fb8-a40f-a2981ce9d961
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949287727 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.3949287727
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.1317756002
Short name T187
Test name
Test status
Simulation time 11756546720 ps
CPU time 10.98 seconds
Started Jun 11 12:31:46 PM PDT 24
Finished Jun 11 12:31:58 PM PDT 24
Peak memory 200092 kb
Host smart-5cc8d98f-4870-4050-9a44-88c0d932af2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317756002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.1317756002
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.3895023770
Short name T26
Test name
Test status
Simulation time 66993594477 ps
CPU time 384.02 seconds
Started Jun 11 12:31:41 PM PDT 24
Finished Jun 11 12:38:06 PM PDT 24
Peak memory 216192 kb
Host smart-4dcf23b1-80a3-4c6a-9757-55c48cc4b254
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895023770 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.3895023770
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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