Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}
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Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 13 0 13 100.00
Crosses 36 0 36 100.00


Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_intr 9 0 9 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_cg_cc 36 0 36 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 9 0 9 100.00


User Defined Bins for cp_intr

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
all_values[0] 94856 1 T1 233 T2 100 T3 39
all_values[1] 94856 1 T1 233 T2 100 T3 39
all_values[2] 94856 1 T1 233 T2 100 T3 39
all_values[3] 94856 1 T1 233 T2 100 T3 39
all_values[4] 94856 1 T1 233 T2 100 T3 39
all_values[5] 94856 1 T1 233 T2 100 T3 39
all_values[6] 94856 1 T1 233 T2 100 T3 39
all_values[7] 94856 1 T1 233 T2 100 T3 39
all_values[8] 94856 1 T1 233 T2 100 T3 39


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 429157 1 T1 928 T2 429 T3 151
auto[1] 424547 1 T1 1169 T2 471 T3 200


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 779750 1 T1 1726 T2 681 T3 311
auto[1] 73954 1 T1 371 T2 219 T3 40


Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 36 0 36 100.00


Automatically Generated Cross Bins for intr_cg_cc

Bins
cp_intr   cp_intr_en   cp_intr_state   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
all_values[0] auto[0] auto[0] 30721 1 T1 5 T2 10 T3 11
all_values[0] auto[0] auto[1] 18424 1 T1 34 T2 90 T3 14
all_values[0] auto[1] auto[0] 27082 1 T1 44 T3 10 T4 235
all_values[0] auto[1] auto[1] 18629 1 T1 150 T3 4 T4 113
all_values[1] auto[0] auto[0] 47914 1 T1 109 T2 40 T3 13
all_values[1] auto[0] auto[1] 1586 1 T2 7 T3 8 T4 1
all_values[1] auto[1] auto[0] 44073 1 T1 123 T2 36 T3 12
all_values[1] auto[1] auto[1] 1283 1 T1 1 T2 17 T3 6
all_values[2] auto[0] auto[0] 45578 1 T1 111 T2 82 T3 19
all_values[2] auto[0] auto[1] 2344 1 T1 2 T3 4 T4 6
all_values[2] auto[1] auto[0] 44767 1 T1 118 T2 18 T3 13
all_values[2] auto[1] auto[1] 2167 1 T1 2 T3 3 T4 21
all_values[3] auto[0] auto[0] 49489 1 T1 118 T2 79 T3 29
all_values[3] auto[0] auto[1] 282 1 T2 3 T4 2 T6 2
all_values[3] auto[1] auto[0] 44794 1 T1 115 T2 16 T3 10
all_values[3] auto[1] auto[1] 291 1 T2 2 T4 4 T12 1
all_values[4] auto[0] auto[0] 46828 1 T1 117 T2 9 T3 14
all_values[4] auto[0] auto[1] 337 1 T2 9 T4 1 T13 12
all_values[4] auto[1] auto[0] 47291 1 T1 116 T2 73 T3 25
all_values[4] auto[1] auto[1] 400 1 T2 9 T4 2 T12 2
all_values[5] auto[0] auto[0] 48133 1 T1 49 T3 2 T4 197
all_values[5] auto[0] auto[1] 148 1 T4 3 T17 1 T25 2
all_values[5] auto[1] auto[0] 46437 1 T1 184 T2 100 T3 37
all_values[5] auto[1] auto[1] 138 1 T25 1 T29 6 T30 4
all_values[6] auto[0] auto[0] 45873 1 T1 117 T2 29 T3 13
all_values[6] auto[0] auto[1] 133 1 T29 2 T31 3 T120 2
all_values[6] auto[1] auto[0] 48713 1 T1 116 T2 71 T3 26
all_values[6] auto[1] auto[1] 137 1 T4 2 T29 2 T30 4
all_values[7] auto[0] auto[0] 48060 1 T1 147 T2 36 T3 6
all_values[7] auto[0] auto[1] 356 1 T14 1 T17 18 T25 1
all_values[7] auto[1] auto[0] 46114 1 T1 86 T2 62 T3 33
all_values[7] auto[1] auto[1] 326 1 T2 2 T14 1 T17 1
all_values[8] auto[0] auto[0] 30461 1 T1 13 T2 6 T3 17
all_values[8] auto[0] auto[1] 12490 1 T1 106 T2 29 T3 1
all_values[8] auto[1] auto[0] 37422 1 T1 38 T2 14 T3 21
all_values[8] auto[1] auto[1] 14483 1 T1 76 T2 51 T4 31