Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg
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Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv


Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 13 0 13 100.00
Crosses 22 0 22 100.00


Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_dir 2 0 2 100.00 100 1 1 0
cp_rst_pos 11 0 11 100.00 100 1 1 0


Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
uart_reset_cg_cc 22 0 22 100.00 100 1 1 0


Summary for Variable cp_dir

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_dir

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[UartTx] 2212 1 T1 1 T2 1 T3 1
auto[UartRx] 2212 1 T1 1 T2 1 T3 1


Summary for Variable cp_rst_pos

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 11 0 11 100.00


User Defined Bins for cp_rst_pos

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0] 4042 1 T1 2 T2 2 T3 2
values[1] 32 1 T26 1 T38 2 T120 2
values[2] 26 1 T17 1 T26 2 T27 1
values[3] 36 1 T4 1 T9 1 T26 2
values[4] 36 1 T4 1 T29 1 T31 1
values[5] 31 1 T17 1 T26 1 T30 1
values[6] 40 1 T9 1 T29 2 T31 1
values[7] 31 1 T17 1 T25 1 T26 2
values[8] 42 1 T4 1 T25 1 T26 1
values[9] 48 1 T4 1 T25 1 T26 1
values[10] 39 1 T4 1 T26 1 T27 1


Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 22 0 22 100.00


Automatically Generated Cross Bins for uart_reset_cg_cc

Bins
cp_dir   cp_rst_pos   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[UartTx] values[0] 2079 1 T1 1 T2 1 T3 1
auto[UartTx] values[1] 10 1 T38 1 T110 1 T325 1
auto[UartTx] values[2] 10 1 T17 1 T282 1 T117 1
auto[UartTx] values[3] 12 1 T9 1 T26 1 T282 1
auto[UartTx] values[4] 17 1 T4 1 T110 1 T111 1
auto[UartTx] values[5] 10 1 T38 1 T117 1 T326 1
auto[UartTx] values[6] 11 1 T9 1 T29 1 T111 1
auto[UartTx] values[7] 8 1 T120 1 T327 1 T326 1
auto[UartTx] values[8] 17 1 T4 1 T26 1 T27 1
auto[UartTx] values[9] 17 1 T25 1 T31 1 T48 1
auto[UartTx] values[10] 14 1 T29 1 T111 1 T158 2
auto[UartRx] values[0] 1963 1 T1 1 T2 1 T3 1
auto[UartRx] values[1] 22 1 T26 1 T38 1 T120 2
auto[UartRx] values[2] 16 1 T26 2 T27 1 T28 1
auto[UartRx] values[3] 24 1 T4 1 T26 1 T28 1
auto[UartRx] values[4] 19 1 T29 1 T31 1 T109 1
auto[UartRx] values[5] 21 1 T17 1 T26 1 T30 1
auto[UartRx] values[6] 29 1 T29 1 T31 1 T120 1
auto[UartRx] values[7] 23 1 T17 1 T25 1 T26 2
auto[UartRx] values[8] 25 1 T25 1 T27 1 T29 1
auto[UartRx] values[9] 31 1 T4 1 T26 1 T27 1
auto[UartRx] values[10] 25 1 T4 1 T26 1 T27 1