Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1949	1			T1	3		T3	1		T4	3
auto[BaudRate115200]	1679	1			T2	4		T4	1		T5	3
auto[BaudRate230400]	1755	1			T3	1		T4	6		T5	2
auto[BaudRate128Kbps]	1676	1			T1	2		T3	3		T4	4
auto[BaudRate256Kbps]	1950	1			T1	1		T4	5		T5	1
auto[BaudRate1Mbps]	1533	1			T1	1		T3	5		T4	7
auto[BaudRate1p5Mbps]	1093	1			T1	2		T4	1		T6	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1010	1			T6	10		T86	8		T328	38
freqs[25]	1371	1			T12	1		T114	10		T15	13
freqs[48]	406	1			T10	5		T125	10		T25	15
freqs[50]	404	1			T3	10		T13	2		T124	16
freqs[100]	877	1			T1	9		T8	1		T85	5

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	123	1			T6	1		T86	2		T328	12
auto[BaudRate9600]	freqs[25]	204	1			T114	1		T15	13		T38	4
auto[BaudRate9600]	freqs[48]	62	1			T10	1		T25	3		T134	2
auto[BaudRate9600]	freqs[50]	142	1			T3	1		T124	4		T254	1
auto[BaudRate9600]	freqs[100]	120	1			T1	3		T8	1		T280	1
auto[BaudRate115200]	freqs[24]	129	1			T6	1		T86	1		T328	3
auto[BaudRate115200]	freqs[25]	198	1			T12	1		T114	3		T179	2
auto[BaudRate115200]	freqs[48]	63	1			T125	1		T25	4		T329	2
auto[BaudRate115200]	freqs[50]	49	1			T13	1		T124	3		T254	2
auto[BaudRate115200]	freqs[100]	120	1			T34	1		T26	2		T129	2
auto[BaudRate230400]	freqs[24]	153	1			T86	2		T328	9		T147	1
auto[BaudRate230400]	freqs[25]	242	1			T179	3		T131	1		T38	8
auto[BaudRate230400]	freqs[48]	60	1			T125	2		T25	1		T134	1
auto[BaudRate230400]	freqs[50]	43	1			T3	1		T13	1		T254	1
auto[BaudRate230400]	freqs[100]	111	1			T26	6		T129	3		T308	1
auto[BaudRate128Kbps]	freqs[24]	165	1			T6	3		T147	3		T115	1
auto[BaudRate128Kbps]	freqs[25]	181	1			T114	1		T131	1		T38	5
auto[BaudRate128Kbps]	freqs[48]	50	1			T25	1		T134	1		T110	2
auto[BaudRate128Kbps]	freqs[50]	38	1			T3	3		T124	1		T254	1
auto[BaudRate128Kbps]	freqs[100]	121	1			T1	2		T85	2		T26	3
auto[BaudRate256Kbps]	freqs[24]	179	1			T6	1		T328	8		T147	1
auto[BaudRate256Kbps]	freqs[25]	211	1			T114	1		T38	9		T145	2
auto[BaudRate256Kbps]	freqs[48]	56	1			T125	3		T25	3		T329	2
auto[BaudRate256Kbps]	freqs[50]	38	1			T124	2		T40	1		T183	5
auto[BaudRate256Kbps]	freqs[100]	158	1			T1	1		T85	1		T280	1
auto[BaudRate1Mbps]	freqs[24]	158	1			T6	3		T86	3		T328	3
auto[BaudRate1Mbps]	freqs[25]	218	1			T114	1		T179	1		T131	1
auto[BaudRate1Mbps]	freqs[48]	56	1			T10	2		T125	2		T25	3
auto[BaudRate1Mbps]	freqs[50]	51	1			T3	5		T124	2		T254	2
auto[BaudRate1Mbps]	freqs[100]	123	1			T1	1		T85	1		T34	1
auto[BaudRate1p5Mbps]	freqs[25]	117	1			T114	3		T131	1		T38	5
auto[BaudRate1p5Mbps]	freqs[48]	59	1			T10	2		T125	2		T134	1
auto[BaudRate1p5Mbps]	freqs[50]	43	1			T124	4		T254	1		T40	4
auto[BaudRate1p5Mbps]	freqs[100]	124	1			T1	2		T85	1		T34	3

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded