Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.40	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	13	117	90.00

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	13	117	90.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	28180305	1			T1	494		T2	12818		T3	91
all_levels[1]	174176	1			T1	68		T3	23		T4	103
all_levels[2]	1786	1			T1	9		T3	10		T4	6
all_levels[3]	889	1			T3	3		T4	3		T83	2
all_levels[4]	638	1			T3	2		T4	4		T83	1
all_levels[5]	473	1			T4	1		T112	2		T113	1
all_levels[6]	356	1			T1	2		T3	1		T32	1
all_levels[7]	319	1			T1	2		T3	1		T4	1
all_levels[8]	277	1			T1	4		T3	2		T83	2
all_levels[9]	227	1			T3	1		T32	5		T123	2
all_levels[10]	179	1			T3	1		T83	4		T123	2
all_levels[11]	177	1			T32	1		T85	1		T14	1
all_levels[12]	141	1			T123	1		T26	2		T16	1
all_levels[13]	146	1			T1	1		T123	2		T124	1
all_levels[14]	127	1			T3	1		T14	1		T26	1
all_levels[15]	135	1			T3	1		T123	1		T125	3
all_levels[16]	109	1			T3	2		T125	1		T126	2
all_levels[17]	103	1			T3	1		T123	1		T14	1
all_levels[18]	102	1			T1	1		T3	3		T123	1
all_levels[19]	91	1			T123	1		T127	1		T128	2
all_levels[20]	69	1			T14	2		T126	2		T129	1
all_levels[21]	77	1			T126	1		T29	1		T130	1
all_levels[22]	53	1			T16	1		T29	1		T31	1
all_levels[23]	41	1			T16	1		T131	1		T31	1
all_levels[24]	63	1			T3	1		T14	1		T132	2
all_levels[25]	51	1			T84	1		T114	3		T123	2
all_levels[26]	38	1			T3	1		T14	1		T26	2
all_levels[27]	54	1			T3	1		T114	1		T14	1
all_levels[28]	38	1			T16	1		T115	1		T133	1
all_levels[29]	35	1			T14	1		T125	1		T28	1
all_levels[30]	47	1			T3	3		T14	1		T134	1
all_levels[31]	46	1			T3	2		T86	3		T14	2
all_levels[32]	44	1			T3	2		T32	1		T135	1
all_levels[33]	17	1			T1	2		T125	3		T128	1
all_levels[34]	17	1			T3	1		T136	1		T137	1
all_levels[35]	26	1			T138	2		T139	1		T140	1
all_levels[36]	23	1			T114	1		T141	1		T132	1
all_levels[37]	23	1			T125	1		T140	1		T142	1
all_levels[38]	21	1			T125	1		T143	1		T144	1
all_levels[39]	21	1			T114	2		T145	2		T146	2
all_levels[40]	16	1			T16	1		T31	1		T128	1
all_levels[41]	16	1			T114	1		T147	1		T148	1
all_levels[42]	11	1			T149	1		T150	1		T151	1
all_levels[43]	11	1			T125	1		T131	1		T128	1
all_levels[44]	14	1			T45	1		T152	1		T120	1
all_levels[45]	11	1			T125	1		T26	1		T153	2
all_levels[46]	10	1			T154	1		T110	1		T155	1
all_levels[47]	9	1			T32	1		T143	1		T139	1
all_levels[48]	18	1			T10	1		T131	1		T31	1
all_levels[49]	26	1			T3	1		T14	1		T16	1
all_levels[50]	12	1			T128	2		T156	1		T157	1
all_levels[51]	7	1			T158	1		T159	1		T157	1
all_levels[52]	8	1			T120	2		T143	1		T160	1
all_levels[53]	9	1			T161	1		T162	1		T163	1
all_levels[54]	20	1			T148	1		T118	1		T128	1
all_levels[55]	11	1			T10	1		T117	1		T164	2
all_levels[56]	9	1			T14	1		T165	2		T166	1
all_levels[57]	6	1			T167	1		T168	1		T169	1
all_levels[58]	4	1			T1	1		T14	1		T170	1
all_levels[59]	9	1			T154	1		T157	4		T171	2
all_levels[60]	6	1			T172	1		T117	1		T173	1
all_levels[61]	6	1			T165	2		T174	1		T69	1
all_levels[62]	7	1			T139	1		T159	1		T175	1
all_levels[63]	2	1			T141	1		T176	1		-	-
all_levels[64]	139	1			T6	1		T32	2		T114	5

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28357391

1

T1

578

T2

12778

T3

155

auto[1]

4566

1

T1

6

T2

40

T4

7

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	13	117	90.00	13

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[23]]	[auto[1]]	0	1	1
[all_levels[38]]	[auto[1]]	0	1	1
[all_levels[41] , all_levels[42] , all_levels[43]]	[auto[1]]	--	--	3
[all_levels[50] , all_levels[51]]	[auto[1]]	--	--	2
[all_levels[53]]	[auto[1]]	0	1	1
[all_levels[55]]	[auto[1]]	0	1	1
[all_levels[57] , all_levels[58]]	[auto[1]]	--	--	2
[all_levels[60]]	[auto[1]]	0	1	1
[all_levels[63]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	28176236	1			T1	492		T2	12778		T3	91
all_levels[0]	auto[1]	4069	1			T1	2		T2	40		T4	7
all_levels[1]	auto[0]	174087	1			T1	68		T3	23		T4	103
all_levels[1]	auto[1]	89	1			T6	2		T172	1		T36	1
all_levels[2]	auto[0]	1761	1			T1	9		T3	10		T4	6
all_levels[2]	auto[1]	25	1			T5	2		T123	1		T129	1
all_levels[3]	auto[0]	856	1			T3	3		T4	3		T83	2
all_levels[3]	auto[1]	33	1			T109	2		T177	2		T178	5
all_levels[4]	auto[0]	619	1			T3	2		T4	4		T83	1
all_levels[4]	auto[1]	19	1			T179	1		T129	2		T180	1
all_levels[5]	auto[0]	456	1			T4	1		T112	2		T113	1
all_levels[5]	auto[1]	17	1			T125	2		T136	2		T181	1
all_levels[6]	auto[0]	338	1			T1	2		T3	1		T32	1
all_levels[6]	auto[1]	18	1			T126	2		T182	2		T183	2
all_levels[7]	auto[0]	302	1			T1	2		T3	1		T4	1
all_levels[7]	auto[1]	17	1			T184	3		T185	1		T186	4
all_levels[8]	auto[0]	259	1			T1	1		T3	2		T83	2
all_levels[8]	auto[1]	18	1			T1	3		T187	1		T188	3
all_levels[9]	auto[0]	210	1			T3	1		T32	2		T123	2
all_levels[9]	auto[1]	17	1			T32	3		T189	2		T190	2
all_levels[10]	auto[0]	172	1			T3	1		T83	4		T123	2
all_levels[10]	auto[1]	7	1			T136	3		T191	1		T192	2
all_levels[11]	auto[0]	166	1			T32	1		T85	1		T14	1
all_levels[11]	auto[1]	11	1			T36	1		T193	1		T194	2
all_levels[12]	auto[0]	133	1			T123	1		T26	2		T16	1
all_levels[12]	auto[1]	8	1			T182	2		T195	1		T196	1
all_levels[13]	auto[0]	138	1			T1	1		T123	2		T124	1
all_levels[13]	auto[1]	8	1			T133	1		T183	2		T197	1
all_levels[14]	auto[0]	118	1			T3	1		T14	1		T26	1
all_levels[14]	auto[1]	9	1			T198	1		T199	2		T200	1
all_levels[15]	auto[0]	121	1			T3	1		T123	1		T125	2
all_levels[15]	auto[1]	14	1			T125	1		T127	2		T201	1
all_levels[16]	auto[0]	100	1			T3	2		T125	1		T126	2
all_levels[16]	auto[1]	9	1			T179	1		T128	2		T202	1
all_levels[17]	auto[0]	91	1			T3	1		T123	1		T14	1
all_levels[17]	auto[1]	12	1			T203	1		T204	1		T205	1
all_levels[18]	auto[0]	92	1			T1	1		T3	3		T123	1
all_levels[18]	auto[1]	10	1			T127	2		T132	2		T109	1
all_levels[19]	auto[0]	76	1			T123	1		T127	1		T128	2
all_levels[19]	auto[1]	15	1			T202	1		T206	2		T194	1
all_levels[20]	auto[0]	66	1			T14	2		T126	2		T129	1
all_levels[20]	auto[1]	3	1			T207	3		-	-		-	-
all_levels[21]	auto[0]	67	1			T126	1		T29	1		T130	1
all_levels[21]	auto[1]	10	1			T208	3		T209	1		T210	2
all_levels[22]	auto[0]	52	1			T16	1		T29	1		T31	1
all_levels[22]	auto[1]	1	1			T211	1		-	-		-	-
all_levels[23]	auto[0]	41	1			T16	1		T131	1		T31	1
all_levels[24]	auto[0]	55	1			T3	1		T14	1		T132	2
all_levels[24]	auto[1]	8	1			T42	1		T184	1		T212	1
all_levels[25]	auto[0]	44	1			T84	1		T114	1		T123	2
all_levels[25]	auto[1]	7	1			T114	2		T182	1		T213	2
all_levels[26]	auto[0]	36	1			T3	1		T14	1		T26	2
all_levels[26]	auto[1]	2	1			T141	1		T214	1		-	-
all_levels[27]	auto[0]	46	1			T3	1		T114	1		T14	1
all_levels[27]	auto[1]	8	1			T215	1		T216	1		T217	4
all_levels[28]	auto[0]	34	1			T16	1		T115	1		T133	1
all_levels[28]	auto[1]	4	1			T191	1		T201	2		T218	1
all_levels[29]	auto[0]	32	1			T14	1		T125	1		T28	1
all_levels[29]	auto[1]	3	1			T219	2		T220	1		-	-
all_levels[30]	auto[0]	46	1			T3	3		T14	1		T134	1
all_levels[30]	auto[1]	1	1			T221	1		-	-		-	-
all_levels[31]	auto[0]	36	1			T3	2		T86	1		T14	2
all_levels[31]	auto[1]	10	1			T86	2		T130	3		T136	1
all_levels[32]	auto[0]	37	1			T3	2		T32	1		T135	1
all_levels[32]	auto[1]	7	1			T222	1		T223	1		T161	1
all_levels[33]	auto[0]	14	1			T1	1		T125	1		T128	1
all_levels[33]	auto[1]	3	1			T1	1		T125	2		-	-
all_levels[34]	auto[0]	16	1			T3	1		T136	1		T137	1
all_levels[34]	auto[1]	1	1			T224	1		-	-		-	-
all_levels[35]	auto[0]	21	1			T138	1		T139	1		T140	1
all_levels[35]	auto[1]	5	1			T138	1		T225	3		T226	1
all_levels[36]	auto[0]	20	1			T114	1		T141	1		T132	1
all_levels[36]	auto[1]	3	1			T227	2		T228	1		-	-
all_levels[37]	auto[0]	19	1			T125	1		T140	1		T142	1
all_levels[37]	auto[1]	4	1			T229	3		T230	1		-	-
all_levels[38]	auto[0]	21	1			T125	1		T143	1		T144	1
all_levels[39]	auto[0]	18	1			T114	2		T145	1		T146	2
all_levels[39]	auto[1]	3	1			T145	1		T231	1		T232	1
all_levels[40]	auto[0]	14	1			T16	1		T31	1		T128	1
all_levels[40]	auto[1]	2	1			T168	1		T233	1		-	-
all_levels[41]	auto[0]	16	1			T114	1		T147	1		T148	1
all_levels[42]	auto[0]	11	1			T149	1		T150	1		T151	1
all_levels[43]	auto[0]	11	1			T125	1		T131	1		T128	1
all_levels[44]	auto[0]	13	1			T45	1		T152	1		T120	1
all_levels[44]	auto[1]	1	1			T213	1		-	-		-	-
all_levels[45]	auto[0]	10	1			T125	1		T26	1		T153	2
all_levels[45]	auto[1]	1	1			T234	1		-	-		-	-
all_levels[46]	auto[0]	9	1			T154	1		T110	1		T155	1
all_levels[46]	auto[1]	1	1			T235	1		-	-		-	-
all_levels[47]	auto[0]	8	1			T32	1		T143	1		T139	1
all_levels[47]	auto[1]	1	1			T236	1		-	-		-	-
all_levels[48]	auto[0]	15	1			T10	1		T131	1		T31	1
all_levels[48]	auto[1]	3	1			T237	3		-	-		-	-
all_levels[49]	auto[0]	21	1			T3	1		T14	1		T16	1
all_levels[49]	auto[1]	5	1			T131	1		T203	1		T218	1
all_levels[50]	auto[0]	12	1			T128	2		T156	1		T157	1
all_levels[51]	auto[0]	7	1			T158	1		T159	1		T157	1
all_levels[52]	auto[0]	7	1			T120	1		T143	1		T160	1
all_levels[52]	auto[1]	1	1			T120	1		-	-		-	-
all_levels[53]	auto[0]	9	1			T161	1		T162	1		T163	1
all_levels[54]	auto[0]	16	1			T148	1		T118	1		T128	1
all_levels[54]	auto[1]	4	1			T238	1		T239	1		T240	2
all_levels[55]	auto[0]	11	1			T10	1		T117	1		T164	2
all_levels[56]	auto[0]	8	1			T14	1		T165	1		T166	1
all_levels[56]	auto[1]	1	1			T165	1		-	-		-	-
all_levels[57]	auto[0]	6	1			T167	1		T168	1		T169	1
all_levels[58]	auto[0]	4	1			T1	1		T14	1		T170	1
all_levels[59]	auto[0]	5	1			T154	1		T157	1		T171	1
all_levels[59]	auto[1]	4	1			T157	3		T171	1		-	-
all_levels[60]	auto[0]	6	1			T172	1		T117	1		T173	1
all_levels[61]	auto[0]	5	1			T165	1		T174	1		T69	1
all_levels[61]	auto[1]	1	1			T165	1		-	-		-	-
all_levels[62]	auto[0]	6	1			T139	1		T159	1		T175	1
all_levels[62]	auto[1]	1	1			T235	1		-	-		-	-
all_levels[63]	auto[0]	2	1			T141	1		T176	1		-	-
all_levels[64]	auto[0]	107	1			T6	1		T32	1		T114	1
all_levels[64]	auto[1]	32	1			T32	1		T114	4		T141	2