Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	94856	1			T1	233		T2	100		T3	39
all_pins[1]	94856	1			T1	233		T2	100		T3	39
all_pins[2]	94856	1			T1	233		T2	100		T3	39
all_pins[3]	94856	1			T1	233		T2	100		T3	39
all_pins[4]	94856	1			T1	233		T2	100		T3	39
all_pins[5]	94856	1			T1	233		T2	100		T3	39
all_pins[6]	94856	1			T1	233		T2	100		T3	39
all_pins[7]	94856	1			T1	233		T2	100		T3	39
all_pins[8]	94856	1			T1	233		T2	100		T3	39

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	815049	1			T1	1868		T2	808		T3	338
values[0x1]	38655	1			T1	229		T2	92		T3	13
transitions[0x0=>0x1]	30886	1			T1	154		T2	89		T3	13
transitions[0x1=>0x0]	30707	1			T1	153		T2	90		T3	13

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	76152	1			T1	83		T2	100		T3	35
all_pins[0]	values[0x1]	18704	1			T1	150		T3	4		T4	113
all_pins[0]	transitions[0x0=>0x1]	18282	1			T1	149		T3	4		T4	112
all_pins[0]	transitions[0x1=>0x0]	859	1			T2	17		T3	6		T4	1
all_pins[1]	values[0x0]	93575	1			T1	232		T2	83		T3	33
all_pins[1]	values[0x1]	1281	1			T1	1		T2	17		T3	6
all_pins[1]	transitions[0x0=>0x1]	1176	1			T1	1		T2	17		T3	6
all_pins[1]	transitions[0x1=>0x0]	2119	1			T1	2		T3	3		T4	21
all_pins[2]	values[0x0]	92632	1			T1	231		T2	100		T3	36
all_pins[2]	values[0x1]	2224	1			T1	2		T3	3		T4	21
all_pins[2]	transitions[0x0=>0x1]	2163	1			T1	2		T3	3		T4	18
all_pins[2]	transitions[0x1=>0x0]	230	1			T2	2		T4	1		T12	1
all_pins[3]	values[0x0]	94565	1			T1	233		T2	98		T3	39
all_pins[3]	values[0x1]	291	1			T2	2		T4	4		T12	1
all_pins[3]	transitions[0x0=>0x1]	255	1			T2	2		T4	2		T12	1
all_pins[3]	transitions[0x1=>0x0]	364	1			T2	9		T12	2		T13	2
all_pins[4]	values[0x0]	94456	1			T1	233		T2	91		T3	39
all_pins[4]	values[0x1]	400	1			T2	9		T4	2		T12	2
all_pins[4]	transitions[0x0=>0x1]	350	1			T2	7		T4	2		T12	2
all_pins[4]	transitions[0x1=>0x0]	137	1			T2	2		T13	2		T25	1
all_pins[5]	values[0x0]	94669	1			T1	233		T2	96		T3	39
all_pins[5]	values[0x1]	187	1			T2	4		T13	2		T17	4
all_pins[5]	transitions[0x0=>0x1]	160	1			T2	4		T13	2		T17	4
all_pins[5]	transitions[0x1=>0x0]	675	1			T2	6		T4	3		T6	2
all_pins[6]	values[0x0]	94154	1			T1	233		T2	94		T3	39
all_pins[6]	values[0x1]	702	1			T2	6		T4	3		T6	2
all_pins[6]	transitions[0x0=>0x1]	665	1			T2	6		T4	3		T6	2
all_pins[6]	transitions[0x1=>0x0]	289	1			T2	2		T14	1		T17	1
all_pins[7]	values[0x0]	94530	1			T1	233		T2	98		T3	39
all_pins[7]	values[0x1]	326	1			T2	2		T14	1		T17	1
all_pins[7]	transitions[0x0=>0x1]	198	1			T2	2		T14	1		T17	1
all_pins[7]	transitions[0x1=>0x0]	14412	1			T1	76		T2	52		T4	32
all_pins[8]	values[0x0]	80316	1			T1	157		T2	48		T3	39
all_pins[8]	values[0x1]	14540	1			T1	76		T2	52		T4	32
all_pins[8]	transitions[0x0=>0x1]	7637	1			T1	2		T2	51		T4	27
all_pins[8]	transitions[0x1=>0x0]	11622	1			T1	75		T3	4		T4	108