Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	5933652	1			T1	442		T2	19		T3	13
all_levels[1]	1104822	1			T1	3		T2	3067		T3	32
all_levels[2]	536721	1			T1	11		T3	3		T4	2462
all_levels[3]	322742	1			T1	11		T3	4		T4	2199
all_levels[4]	257952	1			T1	3		T3	2		T4	2791
all_levels[5]	233829	1			T1	13		T3	1		T4	2657
all_levels[6]	205094	1			T1	3		T3	3		T4	2547
all_levels[7]	434538	1			T1	2		T3	1		T4	2846
all_levels[8]	298466	1			T1	2		T3	2		T4	2914
all_levels[9]	262815	1			T1	3		T3	1		T4	2340
all_levels[10]	261181	1			T1	7		T3	1		T4	2369
all_levels[11]	332960	1			T1	1		T3	2		T4	1646
all_levels[12]	178501	1			T1	4		T3	76		T4	2944
all_levels[13]	195379	1			T1	4		T3	2		T4	3936
all_levels[14]	209528	1			T1	2		T4	3885		T112	6
all_levels[15]	192713	1			T1	5		T2	21		T3	3
all_levels[16]	336458	1			T1	2		T2	9707		T3	2
all_levels[17]	220004	1			T1	3		T4	19805		T85	1
all_levels[18]	220671	1			T1	2		T4	3196		T83	14
all_levels[19]	179572	1			T1	3		T4	3335		T86	1
all_levels[20]	207758	1			T1	6		T4	3859		T112	4
all_levels[21]	428518	1			T1	7		T4	2954		T86	2
all_levels[22]	146382	1			T1	3		T4	2284		T85	4
all_levels[23]	220168	1			T1	6		T3	7		T4	3310
all_levels[24]	152079	1			T1	2		T3	1		T4	3577
all_levels[25]	176951	1			T4	2538		T33	1		T123	1
all_levels[26]	181268	1			T1	5		T4	3601		T33	4
all_levels[27]	321186	1			T1	1		T4	3558		T85	2
all_levels[28]	415500	1			T1	7		T4	2523		T86	1
all_levels[29]	170667	1			T1	8		T4	2790		T113	4
all_levels[30]	168627	1			T1	2		T4	3495		T85	2
all_levels[31]	661162	1			T1	5		T4	4308		T5	3
all_levels[32]	13193690	1			T1	8		T4	38966		T6	6

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28357391

1

T1

578

T2

12778

T3

155

auto[1]

4163

1

T1

8

T2

36

T3

1

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	5931327	1			T1	436		T2	1		T3	13
all_levels[0]	auto[1]	2325	1			T1	6		T2	18		T4	5
all_levels[1]	auto[0]	1104566	1			T1	3		T2	3067		T3	32
all_levels[1]	auto[1]	256	1			T6	2		T33	1		T125	1
all_levels[2]	auto[0]	536670	1			T1	11		T3	3		T4	2462
all_levels[2]	auto[1]	51	1			T146	4		T278	3		T219	1
all_levels[3]	auto[0]	322577	1			T1	11		T3	4		T4	2199
all_levels[3]	auto[1]	165	1			T5	1		T84	1		T109	2
all_levels[4]	auto[0]	257924	1			T1	3		T3	2		T4	2791
all_levels[4]	auto[1]	28	1			T288	2		T265	2		T330	2
all_levels[5]	auto[0]	233806	1			T1	13		T3	1		T4	2657
all_levels[5]	auto[1]	23	1			T6	1		T123	1		T148	1
all_levels[6]	auto[0]	205063	1			T1	3		T3	3		T4	2547
all_levels[6]	auto[1]	31	1			T36	1		T29	1		T110	2
all_levels[7]	auto[0]	434353	1			T1	2		T3	1		T4	2846
all_levels[7]	auto[1]	185	1			T187	1		T189	2		T266	1
all_levels[8]	auto[0]	298448	1			T1	2		T3	2		T4	2914
all_levels[8]	auto[1]	18	1			T32	1		T132	1		T145	1
all_levels[9]	auto[0]	262801	1			T1	3		T3	1		T4	2340
all_levels[9]	auto[1]	14	1			T133	1		T183	1		T201	1
all_levels[10]	auto[0]	261163	1			T1	7		T3	1		T4	2369
all_levels[10]	auto[1]	18	1			T320	1		T127	3		T331	2
all_levels[11]	auto[0]	332947	1			T1	1		T3	2		T4	1646
all_levels[11]	auto[1]	13	1			T109	2		T310	1		T208	1
all_levels[12]	auto[0]	178477	1			T1	4		T3	76		T4	2944
all_levels[12]	auto[1]	24	1			T16	1		T40	1		T145	1
all_levels[13]	auto[0]	195352	1			T1	4		T3	2		T4	3936
all_levels[13]	auto[1]	27	1			T33	1		T127	2		T312	2
all_levels[14]	auto[0]	209500	1			T1	2		T4	3885		T112	5
all_levels[14]	auto[1]	28	1			T112	1		T126	1		T272	1
all_levels[15]	auto[0]	192608	1			T1	4		T2	3		T3	3
all_levels[15]	auto[1]	105	1			T1	1		T2	18		T12	5
all_levels[16]	auto[0]	336419	1			T1	2		T2	9707		T3	2
all_levels[16]	auto[1]	39	1			T124	1		T208	1		T180	1
all_levels[17]	auto[0]	219978	1			T1	3		T4	19804		T85	1
all_levels[17]	auto[1]	26	1			T4	1		T16	1		T132	2
all_levels[18]	auto[0]	220653	1			T1	2		T4	3196		T83	14
all_levels[18]	auto[1]	18	1			T114	1		T86	1		T33	1
all_levels[19]	auto[0]	179548	1			T1	3		T4	3335		T86	1
all_levels[19]	auto[1]	24	1			T33	3		T154	1		T139	1
all_levels[20]	auto[0]	207739	1			T1	6		T4	3859		T112	4
all_levels[20]	auto[1]	19	1			T213	1		T238	1		T332	1
all_levels[21]	auto[0]	428499	1			T1	7		T4	2954		T86	2
all_levels[21]	auto[1]	19	1			T16	1		T252	1		T333	1
all_levels[22]	auto[0]	146360	1			T1	3		T4	2284		T85	3
all_levels[22]	auto[1]	22	1			T85	1		T298	1		T334	1
all_levels[23]	auto[0]	220153	1			T1	6		T3	6		T4	3310
all_levels[23]	auto[1]	15	1			T3	1		T36	2		T290	3
all_levels[24]	auto[0]	152063	1			T1	2		T3	1		T4	3577
all_levels[24]	auto[1]	16	1			T44	1		T187	1		T190	1
all_levels[25]	auto[0]	176933	1			T4	2538		T33	1		T123	1
all_levels[25]	auto[1]	18	1			T259	2		T265	1		T102	1
all_levels[26]	auto[0]	181255	1			T1	5		T4	3601		T33	4
all_levels[26]	auto[1]	13	1			T126	1		T335	1		T336	1
all_levels[27]	auto[0]	321176	1			T1	1		T4	3558		T85	2
all_levels[27]	auto[1]	10	1			T313	1		T206	3		T337	1
all_levels[28]	auto[0]	415470	1			T1	7		T4	2523		T86	1
all_levels[28]	auto[1]	30	1			T172	1		T213	3		T239	2
all_levels[29]	auto[0]	170644	1			T1	8		T4	2790		T113	4
all_levels[29]	auto[1]	23	1			T126	2		T129	1		T198	2
all_levels[30]	auto[0]	168605	1			T1	2		T4	3495		T85	2
all_levels[30]	auto[1]	22	1			T198	1		T187	2		T189	1
all_levels[31]	auto[0]	661145	1			T1	5		T4	4308		T5	1
all_levels[31]	auto[1]	17	1			T5	2		T253	1		T338	1
all_levels[32]	auto[0]	13193169	1			T1	7		T4	38965		T6	2
all_levels[32]	auto[1]	521	1			T1	1		T4	1		T6	4