Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	605	1			T4	7		T17	4		T25	4
all_values[1]	605	1			T4	7		T17	4		T25	4
all_values[2]	605	1			T4	7		T17	4		T25	4
all_values[3]	605	1			T4	7		T17	4		T25	4
all_values[4]	605	1			T4	7		T17	4		T25	4
all_values[5]	605	1			T4	7		T17	4		T25	4
all_values[6]	605	1			T4	7		T17	4		T25	4
all_values[7]	605	1			T4	7		T17	4		T25	4
all_values[8]	605	1			T4	7		T17	4		T25	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2894

1

T4

24

T17

18

T25

23

auto[1]

2551

1

T4

39

T17

18

T25

13

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1745

1

T4

20

T17

12

T25

12

auto[1]

3700

1

T4

43

T17

24

T25

24

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3169

1

T4

36

T17

24

T25

27

auto[1]

2276

1

T4

27

T17

12

T25

9

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	169	1			T4	1		T17	3		T25	3
all_values[0]	auto[0]	auto[1]	auto[1]	172	1			T4	2		T17	1		T25	1
all_values[0]	auto[1]	auto[0]	auto[1]	124	1			T4	2		T29	4		T30	3
all_values[0]	auto[1]	auto[1]	auto[1]	140	1			T4	2		T29	3		T30	2
all_values[1]	auto[0]	auto[0]	auto[0]	195	1			T4	3		T25	3		T29	7
all_values[1]	auto[0]	auto[1]	auto[0]	177	1			T4	1		T17	3		T25	1
all_values[1]	auto[1]	auto[0]	auto[1]	120	1			T4	1		T29	2		T30	4
all_values[1]	auto[1]	auto[1]	auto[1]	113	1			T4	2		T17	1		T29	2
all_values[2]	auto[0]	auto[0]	auto[0]	125	1			T4	1		T29	3		T30	4
all_values[2]	auto[0]	auto[0]	auto[1]	60	1			T25	1		T30	1		T31	2
all_values[2]	auto[0]	auto[1]	auto[0]	122	1			T29	5		T30	3		T31	3
all_values[2]	auto[0]	auto[1]	auto[1]	50	1			T4	2		T17	2		T25	1
all_values[2]	auto[1]	auto[0]	auto[1]	137	1			T4	2		T17	2		T25	2
all_values[2]	auto[1]	auto[1]	auto[1]	111	1			T4	2		T29	2		T30	1
all_values[3]	auto[0]	auto[0]	auto[0]	107	1			T17	1		T29	2		T30	2
all_values[3]	auto[0]	auto[0]	auto[1]	64	1			T29	2		T30	2		T31	3
all_values[3]	auto[0]	auto[1]	auto[0]	96	1			T17	2		T29	4		T30	2
all_values[3]	auto[0]	auto[1]	auto[1]	81	1			T4	4		T25	2		T30	2
all_values[3]	auto[1]	auto[0]	auto[1]	137	1			T4	1		T25	1		T29	3
all_values[3]	auto[1]	auto[1]	auto[1]	120	1			T4	2		T17	1		T25	1
all_values[4]	auto[0]	auto[0]	auto[0]	125	1			T17	1		T25	2		T29	4
all_values[4]	auto[0]	auto[0]	auto[1]	66	1			T4	1		T17	2		T29	1
all_values[4]	auto[0]	auto[1]	auto[0]	108	1			T4	2		T25	2		T29	4
all_values[4]	auto[0]	auto[1]	auto[1]	56	1			T4	1		T29	1		T31	2
all_values[4]	auto[1]	auto[0]	auto[1]	151	1			T4	1		T29	4		T30	3
all_values[4]	auto[1]	auto[1]	auto[1]	99	1			T4	2		T17	1		T31	2
all_values[5]	auto[0]	auto[0]	auto[0]	119	1			T4	1		T17	1		T25	1
all_values[5]	auto[0]	auto[0]	auto[1]	66	1			T4	1		T25	1		T29	2
all_values[5]	auto[0]	auto[1]	auto[0]	96	1			T4	1		T29	2		T31	3
all_values[5]	auto[0]	auto[1]	auto[1]	62	1			T25	1		T29	2		T30	3
all_values[5]	auto[1]	auto[0]	auto[1]	141	1			T4	2		T17	3		T25	1
all_values[5]	auto[1]	auto[1]	auto[1]	121	1			T4	2		T29	4		T30	1
all_values[6]	auto[0]	auto[0]	auto[0]	138	1			T4	1		T25	2		T29	2
all_values[6]	auto[0]	auto[0]	auto[1]	56	1			T4	1		T29	1		T31	3
all_values[6]	auto[0]	auto[1]	auto[0]	113	1			T4	3		T17	3		T29	3
all_values[6]	auto[0]	auto[1]	auto[1]	62	1			T29	2		T30	3		T31	1
all_values[6]	auto[1]	auto[0]	auto[1]	130	1			T25	1		T29	4		T31	3
all_values[6]	auto[1]	auto[1]	auto[1]	106	1			T4	2		T17	1		T25	1
all_values[7]	auto[0]	auto[0]	auto[0]	121	1			T4	3		T29	1		T30	10
all_values[7]	auto[0]	auto[0]	auto[1]	71	1			T29	3		T118	2		T119	1
all_values[7]	auto[0]	auto[1]	auto[0]	103	1			T4	4		T17	1		T25	1
all_values[7]	auto[0]	auto[1]	auto[1]	47	1			T25	1		T120	3		T118	2
all_values[7]	auto[1]	auto[0]	auto[1]	146	1			T17	1		T25	2		T29	6
all_values[7]	auto[1]	auto[1]	auto[1]	117	1			T17	2		T29	2		T30	1
all_values[8]	auto[0]	auto[0]	auto[1]	183	1			T4	2		T17	4		T25	3
all_values[8]	auto[0]	auto[1]	auto[1]	159	1			T4	1		T25	1		T29	3
all_values[8]	auto[1]	auto[0]	auto[1]	143	1			T29	2		T30	2		T31	2
all_values[8]	auto[1]	auto[1]	auto[1]	120	1			T4	4		T30	1		T31	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal