Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.10 99.10 97.65 100.00 98.38 100.00 99.48


Total test records in report: 1231
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T1035 /workspace/coverage/default/0.uart_rx_parity_err.2806464348 Jun 13 01:00:28 PM PDT 24 Jun 13 01:00:46 PM PDT 24 36878825702 ps
T1036 /workspace/coverage/default/1.uart_loopback.873768377 Jun 13 01:00:38 PM PDT 24 Jun 13 01:00:40 PM PDT 24 2425669700 ps
T1037 /workspace/coverage/default/22.uart_intr.2957495934 Jun 13 01:01:53 PM PDT 24 Jun 13 01:01:56 PM PDT 24 7621913008 ps
T1038 /workspace/coverage/default/2.uart_rx_oversample.777470206 Jun 13 01:00:38 PM PDT 24 Jun 13 01:00:44 PM PDT 24 4663925552 ps
T1039 /workspace/coverage/default/26.uart_fifo_overflow.180672339 Jun 13 01:01:55 PM PDT 24 Jun 13 01:04:34 PM PDT 24 155808077087 ps
T1040 /workspace/coverage/default/3.uart_rx_parity_err.2618579376 Jun 13 01:00:41 PM PDT 24 Jun 13 01:01:56 PM PDT 24 242089068653 ps
T1041 /workspace/coverage/default/25.uart_fifo_full.4047404537 Jun 13 01:01:54 PM PDT 24 Jun 13 01:02:46 PM PDT 24 68163826194 ps
T1042 /workspace/coverage/default/1.uart_perf.3977915086 Jun 13 01:00:36 PM PDT 24 Jun 13 01:03:36 PM PDT 24 11079870349 ps
T1043 /workspace/coverage/default/17.uart_stress_all.4263169015 Jun 13 01:01:18 PM PDT 24 Jun 13 01:04:59 PM PDT 24 388576769735 ps
T1044 /workspace/coverage/default/30.uart_tx_ovrd.3448537463 Jun 13 01:02:29 PM PDT 24 Jun 13 01:02:31 PM PDT 24 406190011 ps
T1045 /workspace/coverage/default/47.uart_intr.3107549926 Jun 13 01:02:42 PM PDT 24 Jun 13 01:02:48 PM PDT 24 4427312807 ps
T1046 /workspace/coverage/default/30.uart_long_xfer_wo_dly.3296045054 Jun 13 01:02:29 PM PDT 24 Jun 13 01:13:39 PM PDT 24 121474218414 ps
T1047 /workspace/coverage/default/43.uart_long_xfer_wo_dly.3045296827 Jun 13 01:02:41 PM PDT 24 Jun 13 01:18:50 PM PDT 24 137777314955 ps
T1048 /workspace/coverage/default/32.uart_fifo_full.1928815160 Jun 13 01:32:51 PM PDT 24 Jun 13 01:33:41 PM PDT 24 28841212245 ps
T1049 /workspace/coverage/default/40.uart_alert_test.4141128698 Jun 13 01:17:55 PM PDT 24 Jun 13 01:17:56 PM PDT 24 14009270 ps
T1050 /workspace/coverage/default/36.uart_fifo_full.1300461781 Jun 13 01:55:07 PM PDT 24 Jun 13 01:55:26 PM PDT 24 59136260311 ps
T54 /workspace/coverage/default/74.uart_stress_all_with_rand_reset.2173608861 Jun 13 02:10:08 PM PDT 24 Jun 13 02:26:54 PM PDT 24 259415369897 ps
T1051 /workspace/coverage/default/34.uart_fifo_overflow.3851176478 Jun 13 01:59:10 PM PDT 24 Jun 13 01:59:36 PM PDT 24 93473225391 ps
T1052 /workspace/coverage/default/4.uart_rx_parity_err.3573303769 Jun 13 01:00:46 PM PDT 24 Jun 13 01:01:28 PM PDT 24 25305642466 ps
T1053 /workspace/coverage/default/37.uart_fifo_reset.2174786781 Jun 13 02:20:06 PM PDT 24 Jun 13 02:23:02 PM PDT 24 95491370814 ps
T1054 /workspace/coverage/default/0.uart_rx_start_bit_filter.3733412651 Jun 13 01:00:27 PM PDT 24 Jun 13 01:00:35 PM PDT 24 4021195172 ps
T1055 /workspace/coverage/default/12.uart_intr.814316934 Jun 13 01:01:01 PM PDT 24 Jun 13 01:01:29 PM PDT 24 22726575195 ps
T1056 /workspace/coverage/default/31.uart_fifo_overflow.1137955880 Jun 13 01:02:23 PM PDT 24 Jun 13 01:02:46 PM PDT 24 249007514982 ps
T1057 /workspace/coverage/default/296.uart_fifo_reset.3507930693 Jun 13 02:47:21 PM PDT 24 Jun 13 02:48:27 PM PDT 24 47353316611 ps
T1058 /workspace/coverage/default/39.uart_rx_start_bit_filter.2875197938 Jun 13 01:53:58 PM PDT 24 Jun 13 01:54:55 PM PDT 24 34174993948 ps
T1059 /workspace/coverage/default/140.uart_fifo_reset.3930443743 Jun 13 02:15:47 PM PDT 24 Jun 13 02:17:06 PM PDT 24 289385002794 ps
T1060 /workspace/coverage/default/26.uart_smoke.3913062289 Jun 13 01:01:56 PM PDT 24 Jun 13 01:01:58 PM PDT 24 314247446 ps
T1061 /workspace/coverage/default/197.uart_fifo_reset.1228314865 Jun 13 01:27:38 PM PDT 24 Jun 13 01:29:01 PM PDT 24 72114777691 ps
T1062 /workspace/coverage/default/101.uart_fifo_reset.2385088466 Jun 13 01:43:31 PM PDT 24 Jun 13 01:44:17 PM PDT 24 27443156789 ps
T1063 /workspace/coverage/default/47.uart_stress_all.313106899 Jun 13 01:02:43 PM PDT 24 Jun 13 01:05:00 PM PDT 24 118584044784 ps
T1064 /workspace/coverage/default/39.uart_long_xfer_wo_dly.1718888380 Jun 13 01:02:34 PM PDT 24 Jun 13 01:24:30 PM PDT 24 167631021483 ps
T1065 /workspace/coverage/default/89.uart_fifo_reset.3867720666 Jun 13 02:56:09 PM PDT 24 Jun 13 02:56:27 PM PDT 24 16905290908 ps
T1066 /workspace/coverage/default/27.uart_fifo_full.4147711528 Jun 13 01:02:04 PM PDT 24 Jun 13 01:02:07 PM PDT 24 8459495958 ps
T1067 /workspace/coverage/default/60.uart_stress_all_with_rand_reset.1348462239 Jun 13 01:19:07 PM PDT 24 Jun 13 01:28:46 PM PDT 24 172810078743 ps
T1068 /workspace/coverage/default/31.uart_rx_oversample.1132738134 Jun 13 01:02:21 PM PDT 24 Jun 13 01:02:38 PM PDT 24 6884068235 ps
T1069 /workspace/coverage/default/23.uart_alert_test.544223446 Jun 13 01:01:48 PM PDT 24 Jun 13 01:01:49 PM PDT 24 12657032 ps
T1070 /workspace/coverage/default/43.uart_smoke.1335789210 Jun 13 01:02:41 PM PDT 24 Jun 13 01:02:44 PM PDT 24 626417155 ps
T1071 /workspace/coverage/default/98.uart_fifo_reset.1304124217 Jun 13 02:57:08 PM PDT 24 Jun 13 02:57:41 PM PDT 24 20472005860 ps
T1072 /workspace/coverage/default/1.uart_fifo_overflow.938021289 Jun 13 01:00:38 PM PDT 24 Jun 13 01:02:22 PM PDT 24 206625102700 ps
T1073 /workspace/coverage/default/6.uart_tx_rx.1359235060 Jun 13 01:00:51 PM PDT 24 Jun 13 01:01:12 PM PDT 24 116851228401 ps
T1074 /workspace/coverage/default/22.uart_rx_oversample.1649432604 Jun 13 01:01:45 PM PDT 24 Jun 13 01:01:50 PM PDT 24 2507345494 ps
T1075 /workspace/coverage/default/51.uart_stress_all_with_rand_reset.3037567529 Jun 13 01:02:50 PM PDT 24 Jun 13 01:12:47 PM PDT 24 49106616273 ps
T1076 /workspace/coverage/default/48.uart_fifo_overflow.2612102872 Jun 13 01:02:43 PM PDT 24 Jun 13 01:03:21 PM PDT 24 39239580494 ps
T1077 /workspace/coverage/default/31.uart_rx_parity_err.3991768170 Jun 13 01:02:29 PM PDT 24 Jun 13 01:03:22 PM PDT 24 143305669027 ps
T1078 /workspace/coverage/default/12.uart_tx_rx.899683402 Jun 13 01:01:04 PM PDT 24 Jun 13 01:01:51 PM PDT 24 26523872006 ps
T1079 /workspace/coverage/default/23.uart_perf.2531704190 Jun 13 01:01:48 PM PDT 24 Jun 13 01:13:00 PM PDT 24 15851492642 ps
T1080 /workspace/coverage/default/24.uart_rx_oversample.3581196815 Jun 13 01:01:50 PM PDT 24 Jun 13 01:01:54 PM PDT 24 1913199056 ps
T1081 /workspace/coverage/default/11.uart_rx_parity_err.3186355243 Jun 13 01:01:04 PM PDT 24 Jun 13 01:02:10 PM PDT 24 87138128068 ps
T1082 /workspace/coverage/default/48.uart_alert_test.3427539102 Jun 13 01:20:27 PM PDT 24 Jun 13 01:20:28 PM PDT 24 10666915 ps
T224 /workspace/coverage/default/284.uart_fifo_reset.4132920708 Jun 13 02:33:27 PM PDT 24 Jun 13 02:34:00 PM PDT 24 66542606111 ps
T1083 /workspace/coverage/default/184.uart_fifo_reset.3689740130 Jun 13 02:10:27 PM PDT 24 Jun 13 02:10:37 PM PDT 24 51965892662 ps
T1084 /workspace/coverage/default/21.uart_rx_oversample.2048483893 Jun 13 01:01:39 PM PDT 24 Jun 13 01:01:58 PM PDT 24 2655789459 ps
T1085 /workspace/coverage/default/163.uart_fifo_reset.3351731428 Jun 13 01:02:58 PM PDT 24 Jun 13 01:03:34 PM PDT 24 73746317685 ps
T1086 /workspace/coverage/default/2.uart_loopback.2751560707 Jun 13 01:00:38 PM PDT 24 Jun 13 01:00:42 PM PDT 24 2422462780 ps
T1087 /workspace/coverage/default/44.uart_rx_oversample.3322092458 Jun 13 02:04:33 PM PDT 24 Jun 13 02:04:58 PM PDT 24 6509385735 ps
T1088 /workspace/coverage/default/34.uart_rx_oversample.1530215859 Jun 13 02:30:00 PM PDT 24 Jun 13 02:30:44 PM PDT 24 4757825283 ps
T1089 /workspace/coverage/default/4.uart_intr.2064998206 Jun 13 01:00:41 PM PDT 24 Jun 13 01:01:50 PM PDT 24 160902489257 ps
T1090 /workspace/coverage/default/194.uart_fifo_reset.1657450798 Jun 13 02:18:17 PM PDT 24 Jun 13 02:18:41 PM PDT 24 17602192121 ps
T1091 /workspace/coverage/default/3.uart_loopback.1498276527 Jun 13 01:00:42 PM PDT 24 Jun 13 01:00:44 PM PDT 24 1609924689 ps
T1092 /workspace/coverage/default/120.uart_fifo_reset.1547862989 Jun 13 02:12:59 PM PDT 24 Jun 13 02:15:06 PM PDT 24 25879209203 ps
T1093 /workspace/coverage/default/5.uart_long_xfer_wo_dly.4062782523 Jun 13 01:00:51 PM PDT 24 Jun 13 01:02:11 PM PDT 24 27250234664 ps
T1094 /workspace/coverage/default/273.uart_fifo_reset.3918169251 Jun 13 01:03:03 PM PDT 24 Jun 13 01:03:16 PM PDT 24 16417292390 ps
T1095 /workspace/coverage/default/15.uart_alert_test.4163390386 Jun 13 01:01:06 PM PDT 24 Jun 13 01:01:08 PM PDT 24 39608055 ps
T1096 /workspace/coverage/default/128.uart_fifo_reset.2354820830 Jun 13 01:02:53 PM PDT 24 Jun 13 01:03:40 PM PDT 24 110110972575 ps
T1097 /workspace/coverage/default/14.uart_rx_oversample.2628571946 Jun 13 01:01:08 PM PDT 24 Jun 13 01:01:30 PM PDT 24 4635307763 ps
T1098 /workspace/coverage/default/45.uart_long_xfer_wo_dly.236279945 Jun 13 01:16:24 PM PDT 24 Jun 13 01:27:54 PM PDT 24 105257293545 ps
T1099 /workspace/coverage/cover_reg_top/40.uart_intr_test.3089529812 Jun 13 12:59:51 PM PDT 24 Jun 13 12:59:53 PM PDT 24 24065790 ps
T1100 /workspace/coverage/cover_reg_top/7.uart_intr_test.3463826937 Jun 13 12:59:31 PM PDT 24 Jun 13 12:59:33 PM PDT 24 13234493 ps
T87 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.463066669 Jun 13 12:59:46 PM PDT 24 Jun 13 12:59:48 PM PDT 24 177179062 ps
T74 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.61822731 Jun 13 12:59:38 PM PDT 24 Jun 13 12:59:40 PM PDT 24 59534943 ps
T1101 /workspace/coverage/cover_reg_top/10.uart_intr_test.4074956666 Jun 13 12:59:29 PM PDT 24 Jun 13 12:59:31 PM PDT 24 15458359 ps
T1102 /workspace/coverage/cover_reg_top/43.uart_intr_test.2578760701 Jun 13 12:59:51 PM PDT 24 Jun 13 12:59:53 PM PDT 24 58906266 ps
T1103 /workspace/coverage/cover_reg_top/19.uart_intr_test.3585135427 Jun 13 12:59:44 PM PDT 24 Jun 13 12:59:46 PM PDT 24 31419330 ps
T75 /workspace/coverage/cover_reg_top/5.uart_csr_rw.2022602992 Jun 13 12:59:29 PM PDT 24 Jun 13 12:59:31 PM PDT 24 16093579 ps
T1104 /workspace/coverage/cover_reg_top/30.uart_intr_test.12980257 Jun 13 12:59:53 PM PDT 24 Jun 13 12:59:54 PM PDT 24 43481902 ps
T1105 /workspace/coverage/cover_reg_top/44.uart_intr_test.3648889614 Jun 13 12:59:52 PM PDT 24 Jun 13 12:59:54 PM PDT 24 23147312 ps
T1106 /workspace/coverage/cover_reg_top/41.uart_intr_test.3447857971 Jun 13 12:59:52 PM PDT 24 Jun 13 12:59:54 PM PDT 24 86553185 ps
T76 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.3812473514 Jun 13 12:59:25 PM PDT 24 Jun 13 12:59:28 PM PDT 24 20975151 ps
T1107 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1347434641 Jun 13 12:59:23 PM PDT 24 Jun 13 12:59:26 PM PDT 24 263557141 ps
T55 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.456263503 Jun 13 12:59:23 PM PDT 24 Jun 13 12:59:25 PM PDT 24 18921813 ps
T77 /workspace/coverage/cover_reg_top/14.uart_csr_rw.4294577085 Jun 13 12:59:37 PM PDT 24 Jun 13 12:59:39 PM PDT 24 75935355 ps
T78 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.445680303 Jun 13 12:59:38 PM PDT 24 Jun 13 12:59:40 PM PDT 24 45183360 ps
T88 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.812962290 Jun 13 12:59:38 PM PDT 24 Jun 13 12:59:41 PM PDT 24 997950770 ps
T1108 /workspace/coverage/cover_reg_top/16.uart_intr_test.1944790724 Jun 13 12:59:44 PM PDT 24 Jun 13 12:59:46 PM PDT 24 17243990 ps
T89 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2798834011 Jun 13 12:59:17 PM PDT 24 Jun 13 12:59:20 PM PDT 24 156502272 ps
T79 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.277129165 Jun 13 12:59:48 PM PDT 24 Jun 13 12:59:50 PM PDT 24 423203677 ps
T1109 /workspace/coverage/cover_reg_top/6.uart_tl_errors.1916870915 Jun 13 12:59:29 PM PDT 24 Jun 13 12:59:33 PM PDT 24 152150104 ps
T1110 /workspace/coverage/cover_reg_top/6.uart_intr_test.3441802109 Jun 13 12:59:28 PM PDT 24 Jun 13 12:59:30 PM PDT 24 24183259 ps
T1111 /workspace/coverage/cover_reg_top/48.uart_intr_test.3687904615 Jun 13 01:00:02 PM PDT 24 Jun 13 01:00:04 PM PDT 24 25167027 ps
T1112 /workspace/coverage/cover_reg_top/28.uart_intr_test.2573201639 Jun 13 12:59:52 PM PDT 24 Jun 13 12:59:54 PM PDT 24 12182875 ps
T80 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1275908215 Jun 13 12:59:29 PM PDT 24 Jun 13 12:59:31 PM PDT 24 14900760 ps
T1113 /workspace/coverage/cover_reg_top/3.uart_tl_errors.244576627 Jun 13 12:59:25 PM PDT 24 Jun 13 12:59:29 PM PDT 24 86625180 ps
T1114 /workspace/coverage/cover_reg_top/21.uart_intr_test.2236134326 Jun 13 12:59:50 PM PDT 24 Jun 13 12:59:52 PM PDT 24 11527171 ps
T81 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.815475783 Jun 13 12:59:31 PM PDT 24 Jun 13 12:59:33 PM PDT 24 21895912 ps
T82 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.1939106446 Jun 13 12:59:37 PM PDT 24 Jun 13 12:59:39 PM PDT 24 31470988 ps
T1115 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2480075829 Jun 13 12:59:42 PM PDT 24 Jun 13 12:59:44 PM PDT 24 119073035 ps
T1116 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1131742062 Jun 13 12:59:45 PM PDT 24 Jun 13 12:59:48 PM PDT 24 58795752 ps
T1117 /workspace/coverage/cover_reg_top/3.uart_intr_test.2347574599 Jun 13 12:59:25 PM PDT 24 Jun 13 12:59:27 PM PDT 24 14918001 ps
T97 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.1632644781 Jun 13 12:59:45 PM PDT 24 Jun 13 12:59:47 PM PDT 24 90023957 ps
T1118 /workspace/coverage/cover_reg_top/5.uart_tl_errors.3155257783 Jun 13 12:59:29 PM PDT 24 Jun 13 12:59:33 PM PDT 24 127426518 ps
T1119 /workspace/coverage/cover_reg_top/46.uart_intr_test.2698911933 Jun 13 12:59:50 PM PDT 24 Jun 13 12:59:52 PM PDT 24 35797616 ps
T1120 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1169705722 Jun 13 12:59:33 PM PDT 24 Jun 13 12:59:35 PM PDT 24 29820429 ps
T1121 /workspace/coverage/cover_reg_top/7.uart_csr_rw.2433010281 Jun 13 12:59:28 PM PDT 24 Jun 13 12:59:30 PM PDT 24 15605892 ps
T56 /workspace/coverage/cover_reg_top/12.uart_csr_rw.4112877438 Jun 13 12:59:40 PM PDT 24 Jun 13 12:59:41 PM PDT 24 30889553 ps
T1122 /workspace/coverage/cover_reg_top/17.uart_intr_test.2560953208 Jun 13 12:59:43 PM PDT 24 Jun 13 12:59:44 PM PDT 24 30830805 ps
T1123 /workspace/coverage/cover_reg_top/11.uart_csr_rw.792453287 Jun 13 12:59:34 PM PDT 24 Jun 13 12:59:36 PM PDT 24 46264804 ps
T1124 /workspace/coverage/cover_reg_top/42.uart_intr_test.2931804685 Jun 13 12:59:51 PM PDT 24 Jun 13 12:59:53 PM PDT 24 17220261 ps
T1125 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1377194204 Jun 13 12:59:45 PM PDT 24 Jun 13 12:59:48 PM PDT 24 28808385 ps
T1126 /workspace/coverage/cover_reg_top/31.uart_intr_test.1670174026 Jun 13 12:59:50 PM PDT 24 Jun 13 12:59:51 PM PDT 24 77169281 ps
T1127 /workspace/coverage/cover_reg_top/5.uart_intr_test.3835036449 Jun 13 12:59:37 PM PDT 24 Jun 13 12:59:39 PM PDT 24 40451355 ps
T1128 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3836900828 Jun 13 12:59:36 PM PDT 24 Jun 13 12:59:38 PM PDT 24 18229049 ps
T1129 /workspace/coverage/cover_reg_top/29.uart_intr_test.1643732749 Jun 13 12:59:51 PM PDT 24 Jun 13 12:59:52 PM PDT 24 13835032 ps
T1130 /workspace/coverage/cover_reg_top/9.uart_tl_errors.588507019 Jun 13 12:59:36 PM PDT 24 Jun 13 12:59:39 PM PDT 24 794379536 ps
T1131 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.2701616743 Jun 13 12:59:25 PM PDT 24 Jun 13 12:59:28 PM PDT 24 79718927 ps
T1132 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.779349090 Jun 13 12:59:17 PM PDT 24 Jun 13 12:59:22 PM PDT 24 313875859 ps
T1133 /workspace/coverage/cover_reg_top/16.uart_csr_rw.1558386490 Jun 13 12:59:42 PM PDT 24 Jun 13 12:59:44 PM PDT 24 18260622 ps
T1134 /workspace/coverage/cover_reg_top/19.uart_tl_errors.482220645 Jun 13 12:59:47 PM PDT 24 Jun 13 12:59:50 PM PDT 24 67048344 ps
T1135 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3346721820 Jun 13 12:59:45 PM PDT 24 Jun 13 12:59:48 PM PDT 24 15798492 ps
T1136 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.35317635 Jun 13 12:59:18 PM PDT 24 Jun 13 12:59:21 PM PDT 24 12269053 ps
T57 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.3796025222 Jun 13 12:59:32 PM PDT 24 Jun 13 12:59:34 PM PDT 24 52464873 ps
T1137 /workspace/coverage/cover_reg_top/8.uart_tl_errors.4080768 Jun 13 12:59:31 PM PDT 24 Jun 13 12:59:35 PM PDT 24 33558501 ps
T1138 /workspace/coverage/cover_reg_top/0.uart_tl_errors.2986249239 Jun 13 12:59:16 PM PDT 24 Jun 13 12:59:19 PM PDT 24 105398279 ps
T1139 /workspace/coverage/cover_reg_top/4.uart_tl_errors.658638133 Jun 13 12:59:22 PM PDT 24 Jun 13 12:59:24 PM PDT 24 482526467 ps
T1140 /workspace/coverage/cover_reg_top/49.uart_intr_test.3423713647 Jun 13 12:59:57 PM PDT 24 Jun 13 01:00:00 PM PDT 24 18744019 ps
T1141 /workspace/coverage/cover_reg_top/32.uart_intr_test.2503649334 Jun 13 12:59:56 PM PDT 24 Jun 13 12:59:57 PM PDT 24 157304441 ps
T1142 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.843361377 Jun 13 12:59:27 PM PDT 24 Jun 13 12:59:29 PM PDT 24 53869572 ps
T1143 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2651923688 Jun 13 12:59:45 PM PDT 24 Jun 13 12:59:48 PM PDT 24 90567383 ps
T1144 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3833293853 Jun 13 12:59:24 PM PDT 24 Jun 13 12:59:27 PM PDT 24 34506923 ps
T95 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2310465947 Jun 13 12:59:27 PM PDT 24 Jun 13 12:59:30 PM PDT 24 107133829 ps
T1145 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3628080972 Jun 13 12:59:37 PM PDT 24 Jun 13 12:59:40 PM PDT 24 26863979 ps
T1146 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.1729964451 Jun 13 12:59:24 PM PDT 24 Jun 13 12:59:27 PM PDT 24 15422475 ps
T1147 /workspace/coverage/cover_reg_top/10.uart_tl_errors.3535755405 Jun 13 12:59:32 PM PDT 24 Jun 13 12:59:34 PM PDT 24 46526933 ps
T1148 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1152829820 Jun 13 12:59:31 PM PDT 24 Jun 13 12:59:33 PM PDT 24 21171646 ps
T90 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.87041570 Jun 13 12:59:21 PM PDT 24 Jun 13 12:59:23 PM PDT 24 352429043 ps
T1149 /workspace/coverage/cover_reg_top/3.uart_csr_rw.1698905172 Jun 13 12:59:22 PM PDT 24 Jun 13 12:59:24 PM PDT 24 75279179 ps
T1150 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1232527149 Jun 13 12:59:24 PM PDT 24 Jun 13 12:59:27 PM PDT 24 48913531 ps
T93 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.444912406 Jun 13 12:59:50 PM PDT 24 Jun 13 12:59:52 PM PDT 24 177535746 ps
T1151 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1316977999 Jun 13 12:59:48 PM PDT 24 Jun 13 12:59:50 PM PDT 24 23466717 ps
T1152 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.864503483 Jun 13 12:59:25 PM PDT 24 Jun 13 12:59:28 PM PDT 24 168006572 ps
T96 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.4294914737 Jun 13 12:59:24 PM PDT 24 Jun 13 12:59:27 PM PDT 24 38981575 ps
T1153 /workspace/coverage/cover_reg_top/17.uart_csr_rw.427308154 Jun 13 12:59:43 PM PDT 24 Jun 13 12:59:44 PM PDT 24 49655382 ps
T1154 /workspace/coverage/cover_reg_top/11.uart_tl_errors.69795720 Jun 13 12:59:33 PM PDT 24 Jun 13 12:59:36 PM PDT 24 99906612 ps
T1155 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1481004665 Jun 13 12:59:31 PM PDT 24 Jun 13 12:59:33 PM PDT 24 191478326 ps
T1156 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1795490909 Jun 13 12:59:45 PM PDT 24 Jun 13 12:59:48 PM PDT 24 14385204 ps
T1157 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2454663808 Jun 13 12:59:33 PM PDT 24 Jun 13 12:59:36 PM PDT 24 88079199 ps
T1158 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.167799193 Jun 13 12:59:47 PM PDT 24 Jun 13 12:59:50 PM PDT 24 35313381 ps
T1159 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.153208081 Jun 13 12:59:39 PM PDT 24 Jun 13 12:59:41 PM PDT 24 66247825 ps
T1160 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.675817679 Jun 13 12:59:29 PM PDT 24 Jun 13 12:59:32 PM PDT 24 32975932 ps
T1161 /workspace/coverage/cover_reg_top/13.uart_csr_rw.1713613645 Jun 13 12:59:40 PM PDT 24 Jun 13 12:59:41 PM PDT 24 18050634 ps
T58 /workspace/coverage/cover_reg_top/8.uart_csr_rw.2771697069 Jun 13 12:59:37 PM PDT 24 Jun 13 12:59:39 PM PDT 24 34065642 ps
T1162 /workspace/coverage/cover_reg_top/45.uart_intr_test.3687367290 Jun 13 12:59:55 PM PDT 24 Jun 13 12:59:56 PM PDT 24 27906346 ps
T1163 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.4150233016 Jun 13 12:59:33 PM PDT 24 Jun 13 12:59:35 PM PDT 24 289612055 ps
T1164 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3160462924 Jun 13 12:59:25 PM PDT 24 Jun 13 12:59:28 PM PDT 24 79104174 ps
T91 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.871141983 Jun 13 12:59:45 PM PDT 24 Jun 13 12:59:48 PM PDT 24 144403081 ps
T1165 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3021744951 Jun 13 12:59:28 PM PDT 24 Jun 13 12:59:30 PM PDT 24 166351784 ps
T1166 /workspace/coverage/cover_reg_top/15.uart_intr_test.3177535090 Jun 13 12:59:50 PM PDT 24 Jun 13 12:59:52 PM PDT 24 34369784 ps
T71 /workspace/coverage/cover_reg_top/10.uart_csr_rw.3847100197 Jun 13 12:59:32 PM PDT 24 Jun 13 12:59:34 PM PDT 24 15411371 ps
T1167 /workspace/coverage/cover_reg_top/1.uart_intr_test.734058132 Jun 13 12:59:26 PM PDT 24 Jun 13 12:59:28 PM PDT 24 15043591 ps
T1168 /workspace/coverage/cover_reg_top/14.uart_tl_errors.3213006899 Jun 13 12:59:39 PM PDT 24 Jun 13 12:59:42 PM PDT 24 1114377302 ps
T1169 /workspace/coverage/cover_reg_top/9.uart_csr_rw.243145523 Jun 13 12:59:31 PM PDT 24 Jun 13 12:59:33 PM PDT 24 13743574 ps
T1170 /workspace/coverage/cover_reg_top/36.uart_intr_test.2558377457 Jun 13 12:59:52 PM PDT 24 Jun 13 12:59:54 PM PDT 24 52577002 ps
T1171 /workspace/coverage/cover_reg_top/1.uart_tl_errors.3522914200 Jun 13 12:59:25 PM PDT 24 Jun 13 12:59:28 PM PDT 24 358281172 ps
T94 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.785301957 Jun 13 12:59:37 PM PDT 24 Jun 13 12:59:40 PM PDT 24 283495566 ps
T1172 /workspace/coverage/cover_reg_top/0.uart_intr_test.211371201 Jun 13 12:59:17 PM PDT 24 Jun 13 12:59:20 PM PDT 24 49579430 ps
T121 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.2481326653 Jun 13 12:59:29 PM PDT 24 Jun 13 12:59:32 PM PDT 24 392054119 ps
T1173 /workspace/coverage/cover_reg_top/7.uart_tl_errors.1767586908 Jun 13 12:59:28 PM PDT 24 Jun 13 12:59:31 PM PDT 24 570178768 ps
T1174 /workspace/coverage/cover_reg_top/27.uart_intr_test.769960604 Jun 13 12:59:51 PM PDT 24 Jun 13 12:59:53 PM PDT 24 10847650 ps
T1175 /workspace/coverage/cover_reg_top/13.uart_tl_errors.3598767448 Jun 13 12:59:39 PM PDT 24 Jun 13 12:59:41 PM PDT 24 169398210 ps
T1176 /workspace/coverage/cover_reg_top/17.uart_tl_errors.438071492 Jun 13 12:59:45 PM PDT 24 Jun 13 12:59:49 PM PDT 24 401233200 ps
T1177 /workspace/coverage/cover_reg_top/23.uart_intr_test.2496556479 Jun 13 12:59:46 PM PDT 24 Jun 13 12:59:48 PM PDT 24 28109364 ps
T1178 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3946940365 Jun 13 12:59:25 PM PDT 24 Jun 13 12:59:28 PM PDT 24 121379179 ps
T1179 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.91463403 Jun 13 12:59:30 PM PDT 24 Jun 13 12:59:32 PM PDT 24 409505646 ps
T1180 /workspace/coverage/cover_reg_top/2.uart_intr_test.3752795638 Jun 13 12:59:23 PM PDT 24 Jun 13 12:59:24 PM PDT 24 30556885 ps
T1181 /workspace/coverage/cover_reg_top/14.uart_intr_test.236798397 Jun 13 12:59:38 PM PDT 24 Jun 13 12:59:40 PM PDT 24 54270571 ps
T1182 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.2920968707 Jun 13 12:59:36 PM PDT 24 Jun 13 12:59:37 PM PDT 24 20188083 ps
T1183 /workspace/coverage/cover_reg_top/18.uart_tl_errors.884912052 Jun 13 12:59:45 PM PDT 24 Jun 13 12:59:47 PM PDT 24 52913038 ps
T1184 /workspace/coverage/cover_reg_top/19.uart_csr_rw.1182634493 Jun 13 12:59:50 PM PDT 24 Jun 13 12:59:52 PM PDT 24 25207348 ps
T1185 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2885594260 Jun 13 12:59:24 PM PDT 24 Jun 13 12:59:26 PM PDT 24 27170578 ps
T1186 /workspace/coverage/cover_reg_top/16.uart_tl_errors.2499087238 Jun 13 12:59:44 PM PDT 24 Jun 13 12:59:47 PM PDT 24 57598968 ps
T1187 /workspace/coverage/cover_reg_top/25.uart_intr_test.488228751 Jun 13 12:59:48 PM PDT 24 Jun 13 12:59:50 PM PDT 24 40862287 ps
T59 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.3722528531 Jun 13 12:59:24 PM PDT 24 Jun 13 12:59:27 PM PDT 24 65362074 ps
T1188 /workspace/coverage/cover_reg_top/15.uart_csr_rw.2563454699 Jun 13 12:59:49 PM PDT 24 Jun 13 12:59:51 PM PDT 24 55141619 ps
T60 /workspace/coverage/cover_reg_top/18.uart_csr_rw.106090075 Jun 13 12:59:45 PM PDT 24 Jun 13 12:59:47 PM PDT 24 45547327 ps
T1189 /workspace/coverage/cover_reg_top/13.uart_intr_test.3863807463 Jun 13 12:59:41 PM PDT 24 Jun 13 12:59:42 PM PDT 24 17419481 ps
T1190 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3237733828 Jun 13 12:59:46 PM PDT 24 Jun 13 12:59:48 PM PDT 24 19134019 ps
T1191 /workspace/coverage/cover_reg_top/1.uart_csr_rw.994650501 Jun 13 12:59:25 PM PDT 24 Jun 13 12:59:27 PM PDT 24 93835323 ps
T92 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.3490594105 Jun 13 12:59:33 PM PDT 24 Jun 13 12:59:36 PM PDT 24 192419875 ps
T1192 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.1365077258 Jun 13 12:59:47 PM PDT 24 Jun 13 12:59:50 PM PDT 24 54941772 ps
T1193 /workspace/coverage/cover_reg_top/15.uart_tl_errors.463114965 Jun 13 12:59:37 PM PDT 24 Jun 13 12:59:40 PM PDT 24 176696824 ps
T1194 /workspace/coverage/cover_reg_top/35.uart_intr_test.407112368 Jun 13 12:59:56 PM PDT 24 Jun 13 12:59:57 PM PDT 24 14437821 ps
T1195 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3255940215 Jun 13 12:59:40 PM PDT 24 Jun 13 12:59:43 PM PDT 24 159330745 ps
T1196 /workspace/coverage/cover_reg_top/34.uart_intr_test.1698747053 Jun 13 12:59:51 PM PDT 24 Jun 13 12:59:53 PM PDT 24 14333196 ps
T1197 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.425595784 Jun 13 12:59:30 PM PDT 24 Jun 13 12:59:32 PM PDT 24 277199788 ps
T1198 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.3080039413 Jun 13 12:59:28 PM PDT 24 Jun 13 12:59:31 PM PDT 24 25914466 ps
T1199 /workspace/coverage/cover_reg_top/38.uart_intr_test.506535949 Jun 13 12:59:56 PM PDT 24 Jun 13 12:59:58 PM PDT 24 51149534 ps
T72 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.882975789 Jun 13 12:59:25 PM PDT 24 Jun 13 12:59:28 PM PDT 24 57957891 ps
T1200 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2875117341 Jun 13 12:59:24 PM PDT 24 Jun 13 12:59:26 PM PDT 24 13611076 ps
T1201 /workspace/coverage/cover_reg_top/0.uart_csr_rw.1353264884 Jun 13 12:59:18 PM PDT 24 Jun 13 12:59:21 PM PDT 24 140341031 ps
T1202 /workspace/coverage/cover_reg_top/47.uart_intr_test.638295880 Jun 13 12:59:57 PM PDT 24 Jun 13 12:59:58 PM PDT 24 23824423 ps
T122 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3688028760 Jun 13 12:59:26 PM PDT 24 Jun 13 12:59:29 PM PDT 24 326291122 ps
T1203 /workspace/coverage/cover_reg_top/8.uart_intr_test.383636328 Jun 13 12:59:32 PM PDT 24 Jun 13 12:59:34 PM PDT 24 12931388 ps
T1204 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.454442744 Jun 13 12:59:36 PM PDT 24 Jun 13 12:59:38 PM PDT 24 42172508 ps
T1205 /workspace/coverage/cover_reg_top/2.uart_tl_errors.3296617701 Jun 13 12:59:24 PM PDT 24 Jun 13 12:59:27 PM PDT 24 37829593 ps
T1206 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.2222385137 Jun 13 12:59:41 PM PDT 24 Jun 13 12:59:43 PM PDT 24 72020870 ps
T1207 /workspace/coverage/cover_reg_top/37.uart_intr_test.4153917259 Jun 13 12:59:56 PM PDT 24 Jun 13 12:59:58 PM PDT 24 10351154 ps
T1208 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.405050831 Jun 13 12:59:28 PM PDT 24 Jun 13 12:59:30 PM PDT 24 24811774 ps
T1209 /workspace/coverage/cover_reg_top/24.uart_intr_test.613410034 Jun 13 12:59:52 PM PDT 24 Jun 13 12:59:54 PM PDT 24 16552743 ps
T1210 /workspace/coverage/cover_reg_top/4.uart_intr_test.2670714467 Jun 13 12:59:28 PM PDT 24 Jun 13 12:59:30 PM PDT 24 14233184 ps
T1211 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1210083776 Jun 13 12:59:24 PM PDT 24 Jun 13 12:59:26 PM PDT 24 22475318 ps
T73 /workspace/coverage/cover_reg_top/4.uart_csr_rw.3775681691 Jun 13 12:59:25 PM PDT 24 Jun 13 12:59:28 PM PDT 24 17709310 ps
T1212 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.716938045 Jun 13 12:59:31 PM PDT 24 Jun 13 12:59:33 PM PDT 24 68076567 ps
T1213 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3445562499 Jun 13 12:59:37 PM PDT 24 Jun 13 12:59:39 PM PDT 24 26441660 ps
T61 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.307043546 Jun 13 12:59:24 PM PDT 24 Jun 13 12:59:28 PM PDT 24 356461546 ps
T1214 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3876878138 Jun 13 12:59:29 PM PDT 24 Jun 13 12:59:32 PM PDT 24 180150245 ps
T1215 /workspace/coverage/cover_reg_top/9.uart_intr_test.1368489682 Jun 13 12:59:36 PM PDT 24 Jun 13 12:59:38 PM PDT 24 46036328 ps
T1216 /workspace/coverage/cover_reg_top/20.uart_intr_test.2872321257 Jun 13 12:59:48 PM PDT 24 Jun 13 12:59:50 PM PDT 24 43842300 ps
T1217 /workspace/coverage/cover_reg_top/39.uart_intr_test.4137213672 Jun 13 12:59:51 PM PDT 24 Jun 13 12:59:53 PM PDT 24 53157292 ps
T1218 /workspace/coverage/cover_reg_top/26.uart_intr_test.393105068 Jun 13 12:59:57 PM PDT 24 Jun 13 12:59:58 PM PDT 24 47935399 ps
T1219 /workspace/coverage/cover_reg_top/33.uart_intr_test.1776085419 Jun 13 12:59:50 PM PDT 24 Jun 13 12:59:52 PM PDT 24 12683178 ps
T1220 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3429106664 Jun 13 12:59:25 PM PDT 24 Jun 13 12:59:27 PM PDT 24 27907168 ps
T1221 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.1243012059 Jun 13 12:59:27 PM PDT 24 Jun 13 12:59:30 PM PDT 24 69534142 ps
T1222 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.2965933757 Jun 13 12:59:41 PM PDT 24 Jun 13 12:59:43 PM PDT 24 108635966 ps
T1223 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.3013163458 Jun 13 12:59:30 PM PDT 24 Jun 13 12:59:33 PM PDT 24 51958252 ps
T1224 /workspace/coverage/cover_reg_top/6.uart_csr_rw.1983180018 Jun 13 12:59:31 PM PDT 24 Jun 13 12:59:33 PM PDT 24 52189991 ps
T1225 /workspace/coverage/cover_reg_top/18.uart_intr_test.3273372577 Jun 13 12:59:46 PM PDT 24 Jun 13 12:59:48 PM PDT 24 80740349 ps
T1226 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2577648826 Jun 13 12:59:24 PM PDT 24 Jun 13 12:59:27 PM PDT 24 45183510 ps
T1227 /workspace/coverage/cover_reg_top/12.uart_intr_test.3086664240 Jun 13 12:59:36 PM PDT 24 Jun 13 12:59:38 PM PDT 24 11971065 ps
T1228 /workspace/coverage/cover_reg_top/2.uart_csr_rw.3365185839 Jun 13 12:59:26 PM PDT 24 Jun 13 12:59:28 PM PDT 24 19016500 ps
T1229 /workspace/coverage/cover_reg_top/12.uart_tl_errors.2209891385 Jun 13 12:59:41 PM PDT 24 Jun 13 12:59:44 PM PDT 24 171334776 ps
T1230 /workspace/coverage/cover_reg_top/22.uart_intr_test.2145173449 Jun 13 12:59:45 PM PDT 24 Jun 13 12:59:47 PM PDT 24 45268597 ps
T1231 /workspace/coverage/cover_reg_top/11.uart_intr_test.3617481715 Jun 13 12:59:37 PM PDT 24 Jun 13 12:59:39 PM PDT 24 41051128 ps

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.2169604377
Short name T4
Test name
Test status
Simulation time 109307590406 ps
CPU time 834.35 seconds
Started Jun 13 01:01:20 PM PDT 24
Finished Jun 13 01:15:15 PM PDT 24
Peak memory 217188 kb
Host smart-90694bcd-f38b-4fb8-a1c6-6b999bd9eba8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169604377 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.2169604377
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.1909967611
Short name T38
Test name
Test status
Simulation time 150186753630 ps
CPU time 638.28 seconds
Started Jun 13 01:01:31 PM PDT 24
Finished Jun 13 01:12:10 PM PDT 24
Peak memory 217244 kb
Host smart-1dacc1dc-5a78-46bf-8052-58fd90857a77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909967611 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.1909967611
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.3259202878
Short name T14
Test name
Test status
Simulation time 138431756139 ps
CPU time 90.86 seconds
Started Jun 13 01:02:42 PM PDT 24
Finished Jun 13 01:04:14 PM PDT 24
Peak memory 200744 kb
Host smart-68fa7ab9-62ed-4035-aa41-8cb9794deb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259202878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.3259202878
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.4219929261
Short name T29
Test name
Test status
Simulation time 60692842392 ps
CPU time 570.27 seconds
Started Jun 13 01:33:30 PM PDT 24
Finished Jun 13 01:43:01 PM PDT 24
Peak memory 217300 kb
Host smart-028f0b78-cc62-4e09-851a-d62a42028f44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219929261 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.4219929261
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_stress_all.2851307053
Short name T128
Test name
Test status
Simulation time 191060604139 ps
CPU time 147.22 seconds
Started Jun 13 01:01:03 PM PDT 24
Finished Jun 13 01:03:31 PM PDT 24
Peak memory 200804 kb
Host smart-ded5c2c8-3e83-4636-be61-ad8238e8d2d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851307053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.2851307053
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all.2519200004
Short name T16
Test name
Test status
Simulation time 258646303820 ps
CPU time 144.08 seconds
Started Jun 13 01:02:35 PM PDT 24
Finished Jun 13 01:04:59 PM PDT 24
Peak memory 200764 kb
Host smart-3fa0c286-8664-4555-af3c-6377ff8adb79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519200004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.2519200004
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.3578808070
Short name T17
Test name
Test status
Simulation time 108580591828 ps
CPU time 368.22 seconds
Started Jun 13 01:16:54 PM PDT 24
Finished Jun 13 01:23:04 PM PDT 24
Peak memory 216956 kb
Host smart-be7014f4-a7f7-45b1-852c-2247bf452519
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578808070 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.3578808070
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.3169643193
Short name T109
Test name
Test status
Simulation time 460026754480 ps
CPU time 456.03 seconds
Started Jun 13 01:51:42 PM PDT 24
Finished Jun 13 01:59:20 PM PDT 24
Peak memory 217272 kb
Host smart-44167fd7-3795-4602-87f9-8604b34856a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169643193 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.3169643193
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.2342022579
Short name T31
Test name
Test status
Simulation time 260953916893 ps
CPU time 378.46 seconds
Started Jun 13 01:02:28 PM PDT 24
Finished Jun 13 01:08:47 PM PDT 24
Peak memory 208940 kb
Host smart-17ddf521-1c11-4aa5-b1f0-c298869195fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342022579 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.2342022579
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_stress_all.3131731773
Short name T140
Test name
Test status
Simulation time 537762631160 ps
CPU time 1441.28 seconds
Started Jun 13 01:00:53 PM PDT 24
Finished Jun 13 01:24:57 PM PDT 24
Peak memory 200736 kb
Host smart-e77e20f9-fc3c-4f26-8932-e806020a4be4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131731773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.3131731773
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.812962290
Short name T88
Test name
Test status
Simulation time 997950770 ps
CPU time 1.49 seconds
Started Jun 13 12:59:38 PM PDT 24
Finished Jun 13 12:59:41 PM PDT 24
Peak memory 199272 kb
Host smart-8e646266-392c-4b29-a7fb-39dc397b6aff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812962290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.812962290
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.506316942
Short name T263
Test name
Test status
Simulation time 64721935837 ps
CPU time 439.5 seconds
Started Jun 13 02:25:00 PM PDT 24
Finished Jun 13 02:32:20 PM PDT 24
Peak memory 200768 kb
Host smart-49f82a77-28e8-43e6-b5ac-beb2fb30bc6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=506316942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.506316942
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.3657150467
Short name T1
Test name
Test status
Simulation time 195066002987 ps
CPU time 309.43 seconds
Started Jun 13 01:00:42 PM PDT 24
Finished Jun 13 01:05:52 PM PDT 24
Peak memory 200772 kb
Host smart-3d8b3099-e980-4dcc-99a6-db0169b2be83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657150467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.3657150467
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_alert_test.4016243904
Short name T20
Test name
Test status
Simulation time 21838477 ps
CPU time 0.62 seconds
Started Jun 13 01:00:37 PM PDT 24
Finished Jun 13 01:00:39 PM PDT 24
Peak memory 195528 kb
Host smart-0057a996-a24f-4276-a735-f29004f43344
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016243904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.4016243904
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.941719216
Short name T117
Test name
Test status
Simulation time 251810031174 ps
CPU time 806.64 seconds
Started Jun 13 01:00:53 PM PDT 24
Finished Jun 13 01:14:22 PM PDT 24
Peak memory 226504 kb
Host smart-bc6b6da7-e3b3-41fe-9452-ddd2b0a9291b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941719216 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.941719216
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_rx.3489745028
Short name T264
Test name
Test status
Simulation time 262595219936 ps
CPU time 154.86 seconds
Started Jun 13 01:05:57 PM PDT 24
Finished Jun 13 01:08:32 PM PDT 24
Peak memory 200720 kb
Host smart-3d0058d5-b882-4b17-9158-e1637cbc1c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489745028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.3489745028
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.187924508
Short name T254
Test name
Test status
Simulation time 73269435753 ps
CPU time 54.15 seconds
Started Jun 13 01:29:43 PM PDT 24
Finished Jun 13 01:30:38 PM PDT 24
Peak memory 200828 kb
Host smart-c60d614d-0956-4777-ad39-169907f6fab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187924508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.187924508
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_sec_cm.3894731000
Short name T98
Test name
Test status
Simulation time 59108361 ps
CPU time 0.86 seconds
Started Jun 13 01:00:41 PM PDT 24
Finished Jun 13 01:00:42 PM PDT 24
Peak memory 219236 kb
Host smart-a573dea0-a285-4c9f-9cff-da420c5b9674
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894731000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.3894731000
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.926754909
Short name T110
Test name
Test status
Simulation time 107915822261 ps
CPU time 545.13 seconds
Started Jun 13 02:03:07 PM PDT 24
Finished Jun 13 02:12:14 PM PDT 24
Peak memory 217280 kb
Host smart-09691391-c43d-480d-ab58-3e537dd6dad9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926754909 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.926754909
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.3873586792
Short name T26
Test name
Test status
Simulation time 75159648724 ps
CPU time 1193.62 seconds
Started Jun 13 01:55:00 PM PDT 24
Finished Jun 13 02:14:55 PM PDT 24
Peak memory 217216 kb
Host smart-64c9c55f-d0fa-4fd7-8fc0-e68a5cc36c05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873586792 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.3873586792
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.4112877438
Short name T56
Test name
Test status
Simulation time 30889553 ps
CPU time 0.63 seconds
Started Jun 13 12:59:40 PM PDT 24
Finished Jun 13 12:59:41 PM PDT 24
Peak memory 195400 kb
Host smart-5f232d37-d4c8-4b30-b5b8-47e9e8e1f100
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112877438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.4112877438
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.1397263385
Short name T154
Test name
Test status
Simulation time 186804256066 ps
CPU time 78.87 seconds
Started Jun 13 01:44:09 PM PDT 24
Finished Jun 13 01:45:29 PM PDT 24
Peak memory 200820 kb
Host smart-a3311d68-bdcf-473c-9c16-0268226161d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397263385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.1397263385
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_stress_all.1897437484
Short name T146
Test name
Test status
Simulation time 182886050341 ps
CPU time 281.85 seconds
Started Jun 13 01:02:26 PM PDT 24
Finished Jun 13 01:07:08 PM PDT 24
Peak memory 200716 kb
Host smart-367995cc-a4d5-4ef4-9202-4bfc846dfbab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897437484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.1897437484
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.585414752
Short name T357
Test name
Test status
Simulation time 75436055531 ps
CPU time 453.03 seconds
Started Jun 13 01:00:39 PM PDT 24
Finished Jun 13 01:08:13 PM PDT 24
Peak memory 200812 kb
Host smart-b149af2f-26e4-4c1e-93ae-61d5452bb176
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=585414752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.585414752
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.3473479300
Short name T288
Test name
Test status
Simulation time 197160278910 ps
CPU time 64.34 seconds
Started Jun 13 01:59:47 PM PDT 24
Finished Jun 13 02:00:53 PM PDT 24
Peak memory 200824 kb
Host smart-bff662fc-0837-490f-9094-7834de102b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473479300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.3473479300
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_stress_all.3124614164
Short name T168
Test name
Test status
Simulation time 301152902216 ps
CPU time 289.62 seconds
Started Jun 13 01:01:34 PM PDT 24
Finished Jun 13 01:06:24 PM PDT 24
Peak memory 200600 kb
Host smart-53994df0-6c6c-4e56-bb00-329955933b9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124614164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.3124614164
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.106090075
Short name T60
Test name
Test status
Simulation time 45547327 ps
CPU time 0.61 seconds
Started Jun 13 12:59:45 PM PDT 24
Finished Jun 13 12:59:47 PM PDT 24
Peak memory 195504 kb
Host smart-4e839e33-e195-4feb-a0cd-3bc5ad1d6942
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106090075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.106090075
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.1909699233
Short name T165
Test name
Test status
Simulation time 39326099971 ps
CPU time 39.42 seconds
Started Jun 13 01:00:51 PM PDT 24
Finished Jun 13 01:01:30 PM PDT 24
Peak memory 200736 kb
Host smart-1d2dcc76-56f8-45a7-975f-669ec56bb822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909699233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.1909699233
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_stress_all.3607979753
Short name T119
Test name
Test status
Simulation time 189130355363 ps
CPU time 1457.21 seconds
Started Jun 13 01:02:11 PM PDT 24
Finished Jun 13 01:26:29 PM PDT 24
Peak memory 200764 kb
Host smart-9ddf930b-7d34-4f68-b09d-c2f42448d504
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607979753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.3607979753
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.3932738327
Short name T111
Test name
Test status
Simulation time 130871441504 ps
CPU time 563.04 seconds
Started Jun 13 01:14:42 PM PDT 24
Finished Jun 13 01:24:05 PM PDT 24
Peak memory 217244 kb
Host smart-79016395-a09e-4644-9272-b03811275c63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932738327 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.3932738327
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.3960072413
Short name T291
Test name
Test status
Simulation time 72549277352 ps
CPU time 134.68 seconds
Started Jun 13 01:46:31 PM PDT 24
Finished Jun 13 01:48:47 PM PDT 24
Peak memory 200776 kb
Host smart-5f02ed5a-dd1a-4be6-81e5-8a68c08f96c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960072413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.3960072413
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.102100700
Short name T139
Test name
Test status
Simulation time 82572901032 ps
CPU time 34.74 seconds
Started Jun 13 01:03:41 PM PDT 24
Finished Jun 13 01:04:17 PM PDT 24
Peak memory 200760 kb
Host smart-0a78983c-16cb-4ab8-b217-03ba8e1d074a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102100700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.102100700
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.4253749232
Short name T141
Test name
Test status
Simulation time 17463369560 ps
CPU time 27.66 seconds
Started Jun 13 01:03:13 PM PDT 24
Finished Jun 13 01:03:42 PM PDT 24
Peak memory 200732 kb
Host smart-125b88fa-7fc9-49e2-9de0-993215cef8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253749232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.4253749232
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3688028760
Short name T122
Test name
Test status
Simulation time 326291122 ps
CPU time 1.34 seconds
Started Jun 13 12:59:26 PM PDT 24
Finished Jun 13 12:59:29 PM PDT 24
Peak memory 199284 kb
Host smart-5de3bb7c-7bbc-471d-bc92-3970394c0bbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688028760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.3688028760
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/default/2.uart_stress_all.3694135976
Short name T200
Test name
Test status
Simulation time 220204277059 ps
CPU time 360.96 seconds
Started Jun 13 01:00:44 PM PDT 24
Finished Jun 13 01:06:45 PM PDT 24
Peak memory 200704 kb
Host smart-3c329292-5532-4a0e-acda-129c7ebabc06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694135976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.3694135976
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.3714410124
Short name T171
Test name
Test status
Simulation time 126854255096 ps
CPU time 80.71 seconds
Started Jun 13 01:03:04 PM PDT 24
Finished Jun 13 01:04:25 PM PDT 24
Peak memory 200616 kb
Host smart-54c08665-0093-4565-be93-12b42c6f9054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714410124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.3714410124
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.1002183932
Short name T217
Test name
Test status
Simulation time 556443347376 ps
CPU time 1878.91 seconds
Started Jun 13 01:29:24 PM PDT 24
Finished Jun 13 02:00:45 PM PDT 24
Peak memory 226764 kb
Host smart-36bbd39e-ec72-4f5b-bea1-e96f91620f53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002183932 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.1002183932
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.3647196577
Short name T120
Test name
Test status
Simulation time 49272489963 ps
CPU time 596.66 seconds
Started Jun 13 01:23:20 PM PDT 24
Finished Jun 13 01:33:18 PM PDT 24
Peak memory 216296 kb
Host smart-a6a4a5ee-3540-4b82-9fd1-75b841ca4ee0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647196577 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.3647196577
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.220414122
Short name T201
Test name
Test status
Simulation time 14920654284 ps
CPU time 23.01 seconds
Started Jun 13 01:15:11 PM PDT 24
Finished Jun 13 01:15:35 PM PDT 24
Peak memory 200852 kb
Host smart-00b1bb93-1d8e-457d-bde8-bee04b46b567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220414122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.220414122
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.3845634496
Short name T115
Test name
Test status
Simulation time 47645832629 ps
CPU time 25.12 seconds
Started Jun 13 01:02:30 PM PDT 24
Finished Jun 13 01:02:56 PM PDT 24
Peak memory 200804 kb
Host smart-39164ec0-7209-42aa-9b95-c37a90d4e5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845634496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.3845634496
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.185341284
Short name T220
Test name
Test status
Simulation time 226775499082 ps
CPU time 210.03 seconds
Started Jun 13 01:29:55 PM PDT 24
Finished Jun 13 01:33:26 PM PDT 24
Peak memory 200760 kb
Host smart-fe59a3fc-43db-4ef7-bc14-ed97a8717c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185341284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.185341284
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.1323156186
Short name T209
Test name
Test status
Simulation time 129595090472 ps
CPU time 202.86 seconds
Started Jun 13 01:02:56 PM PDT 24
Finished Jun 13 01:06:19 PM PDT 24
Peak memory 200640 kb
Host smart-0eb69c25-b49d-48f9-bea3-cda13e1b19e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323156186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.1323156186
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.2879706088
Short name T136
Test name
Test status
Simulation time 16096724415 ps
CPU time 31.08 seconds
Started Jun 13 01:20:12 PM PDT 24
Finished Jun 13 01:20:44 PM PDT 24
Peak memory 200720 kb
Host smart-bcb81fa9-7bff-4cab-8ddd-5b7f414b4dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879706088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.2879706088
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.1312056828
Short name T206
Test name
Test status
Simulation time 107500214559 ps
CPU time 43.04 seconds
Started Jun 13 01:38:13 PM PDT 24
Finished Jun 13 01:38:57 PM PDT 24
Peak memory 200760 kb
Host smart-a3e6a3df-b596-4dff-8eb0-0e941b9fb35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312056828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.1312056828
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.3067259180
Short name T184
Test name
Test status
Simulation time 29623419800 ps
CPU time 51.46 seconds
Started Jun 13 01:25:23 PM PDT 24
Finished Jun 13 01:26:15 PM PDT 24
Peak memory 200792 kb
Host smart-056f8826-9e49-4b3c-9f7a-385e1bbe11f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067259180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.3067259180
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.2390789341
Short name T229
Test name
Test status
Simulation time 1263821035937 ps
CPU time 1548.77 seconds
Started Jun 13 01:01:01 PM PDT 24
Finished Jun 13 01:26:50 PM PDT 24
Peak memory 226476 kb
Host smart-50051fcf-af7e-437e-9150-27db4a808149
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390789341 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.2390789341
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.1607785806
Short name T222
Test name
Test status
Simulation time 34444933608 ps
CPU time 22.58 seconds
Started Jun 13 02:09:55 PM PDT 24
Finished Jun 13 02:10:20 PM PDT 24
Peak memory 200728 kb
Host smart-9d32ddd0-b145-4d91-83da-718b8eb2ca28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607785806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.1607785806
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.3472022464
Short name T213
Test name
Test status
Simulation time 22340935397 ps
CPU time 31.76 seconds
Started Jun 13 02:04:40 PM PDT 24
Finished Jun 13 02:05:13 PM PDT 24
Peak memory 200772 kb
Host smart-3e62e12d-e26e-4c4a-a679-c233647339f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472022464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.3472022464
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_tx_rx.4175549909
Short name T124
Test name
Test status
Simulation time 74692042531 ps
CPU time 75.59 seconds
Started Jun 13 01:01:50 PM PDT 24
Finished Jun 13 01:03:07 PM PDT 24
Peak memory 200748 kb
Host smart-0d6df02c-58c2-430d-8fc4-dc632926f232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175549909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.4175549909
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.2326186358
Short name T235
Test name
Test status
Simulation time 105531638417 ps
CPU time 251.68 seconds
Started Jun 13 01:04:19 PM PDT 24
Finished Jun 13 01:08:31 PM PDT 24
Peak memory 200680 kb
Host smart-00a48790-88fa-4a8f-9b9b-7ababfc03330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326186358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.2326186358
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.987785475
Short name T266
Test name
Test status
Simulation time 64074259730 ps
CPU time 30.91 seconds
Started Jun 13 01:01:06 PM PDT 24
Finished Jun 13 01:01:38 PM PDT 24
Peak memory 200696 kb
Host smart-b1b75262-388b-4cb3-99cd-55aa0a8a647b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987785475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.987785475
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.1790360486
Short name T158
Test name
Test status
Simulation time 131090670593 ps
CPU time 486.96 seconds
Started Jun 13 01:01:12 PM PDT 24
Finished Jun 13 01:09:19 PM PDT 24
Peak memory 217236 kb
Host smart-e6468bd9-d15a-4dcd-a4d1-368e9f9ee6ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790360486 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.1790360486
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_stress_all.4263169015
Short name T1043
Test name
Test status
Simulation time 388576769735 ps
CPU time 219.93 seconds
Started Jun 13 01:01:18 PM PDT 24
Finished Jun 13 01:04:59 PM PDT 24
Peak memory 200812 kb
Host smart-d29403de-b286-4325-8a07-68724856ed9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263169015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.4263169015
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.4060876149
Short name T240
Test name
Test status
Simulation time 97038778291 ps
CPU time 98.09 seconds
Started Jun 13 01:26:02 PM PDT 24
Finished Jun 13 01:27:43 PM PDT 24
Peak memory 200840 kb
Host smart-71232162-8e1b-4ca0-b8f2-6f2566d15caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060876149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.4060876149
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.2896615796
Short name T221
Test name
Test status
Simulation time 149246895712 ps
CPU time 62.41 seconds
Started Jun 13 01:37:10 PM PDT 24
Finished Jun 13 01:38:13 PM PDT 24
Peak memory 200804 kb
Host smart-fcef2ab9-451f-4889-bd64-f40f81cba655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896615796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.2896615796
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.484138089
Short name T931
Test name
Test status
Simulation time 94510412419 ps
CPU time 153.63 seconds
Started Jun 13 01:05:34 PM PDT 24
Finished Jun 13 01:08:15 PM PDT 24
Peak memory 200712 kb
Host smart-5b5de1a9-33bf-4ce7-808b-b52200253285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484138089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.484138089
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2310465947
Short name T95
Test name
Test status
Simulation time 107133829 ps
CPU time 1.39 seconds
Started Jun 13 12:59:27 PM PDT 24
Finished Jun 13 12:59:30 PM PDT 24
Peak memory 199340 kb
Host smart-a2cbab85-9113-49e8-9547-6f585c8ab932
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310465947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.2310465947
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.1241380496
Short name T465
Test name
Test status
Simulation time 62153082732 ps
CPU time 33.11 seconds
Started Jun 13 01:00:41 PM PDT 24
Finished Jun 13 01:01:16 PM PDT 24
Peak memory 200788 kb
Host smart-f85708a0-e748-4f1c-bdf5-441239de4d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241380496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.1241380496
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_tx_rx.18116597
Short name T247
Test name
Test status
Simulation time 25856317016 ps
CPU time 41.35 seconds
Started Jun 13 01:00:27 PM PDT 24
Finished Jun 13 01:01:09 PM PDT 24
Peak memory 200820 kb
Host smart-b758ad68-18a8-4ed1-b924-7faf439cdc88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18116597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.18116597
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.4151065667
Short name T661
Test name
Test status
Simulation time 7443133067 ps
CPU time 5.81 seconds
Started Jun 13 01:47:44 PM PDT 24
Finished Jun 13 01:47:52 PM PDT 24
Peak memory 200740 kb
Host smart-0ba31d30-b854-4eec-b6be-95c73e8e7808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151065667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.4151065667
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.1758269641
Short name T174
Test name
Test status
Simulation time 316866768333 ps
CPU time 152.63 seconds
Started Jun 13 01:44:48 PM PDT 24
Finished Jun 13 01:47:21 PM PDT 24
Peak memory 200736 kb
Host smart-6fda24e7-7989-4ed3-a0e2-2fcfa7599f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758269641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.1758269641
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.1584262198
Short name T131
Test name
Test status
Simulation time 22429218837 ps
CPU time 10.03 seconds
Started Jun 13 01:56:41 PM PDT 24
Finished Jun 13 01:56:54 PM PDT 24
Peak memory 200508 kb
Host smart-358ad29d-fbf4-44e0-9844-c821f4db1858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584262198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.1584262198
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.2402079655
Short name T138
Test name
Test status
Simulation time 21012327454 ps
CPU time 36.21 seconds
Started Jun 13 02:23:39 PM PDT 24
Finished Jun 13 02:24:15 PM PDT 24
Peak memory 200760 kb
Host smart-a90e789c-a4de-454a-8959-3598c38f71a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402079655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.2402079655
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.2693387112
Short name T228
Test name
Test status
Simulation time 81859179423 ps
CPU time 184.56 seconds
Started Jun 13 01:24:07 PM PDT 24
Finished Jun 13 01:27:12 PM PDT 24
Peak memory 200776 kb
Host smart-f7d934c8-06c1-4862-a802-4fe7e8d46f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693387112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.2693387112
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.3347003903
Short name T237
Test name
Test status
Simulation time 133671103345 ps
CPU time 420.27 seconds
Started Jun 13 01:21:28 PM PDT 24
Finished Jun 13 01:28:29 PM PDT 24
Peak memory 200660 kb
Host smart-f2df3c4e-96c5-4add-b5bd-ff718fa18288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347003903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.3347003903
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.3326130797
Short name T145
Test name
Test status
Simulation time 84725935505 ps
CPU time 35.51 seconds
Started Jun 13 01:58:54 PM PDT 24
Finished Jun 13 01:59:31 PM PDT 24
Peak memory 200820 kb
Host smart-eda0417b-0e81-478b-88ee-fc7f8b1ab67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326130797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.3326130797
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.3079978050
Short name T234
Test name
Test status
Simulation time 8019986309 ps
CPU time 12.44 seconds
Started Jun 13 02:37:50 PM PDT 24
Finished Jun 13 02:38:05 PM PDT 24
Peak memory 200568 kb
Host smart-65c6dc03-8c03-47e9-8db0-cdf22bb08ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079978050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.3079978050
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.2102567752
Short name T211
Test name
Test status
Simulation time 97455029265 ps
CPU time 37.77 seconds
Started Jun 13 01:31:41 PM PDT 24
Finished Jun 13 01:32:20 PM PDT 24
Peak memory 200832 kb
Host smart-9391e78a-1817-4f28-a00a-0b55357c4947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102567752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.2102567752
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.4132920708
Short name T224
Test name
Test status
Simulation time 66542606111 ps
CPU time 32.17 seconds
Started Jun 13 02:33:27 PM PDT 24
Finished Jun 13 02:34:00 PM PDT 24
Peak memory 200816 kb
Host smart-9de8e185-fc91-4328-97fb-c58289b73609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132920708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.4132920708
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.56369920
Short name T207
Test name
Test status
Simulation time 134057536342 ps
CPU time 198.15 seconds
Started Jun 13 01:18:09 PM PDT 24
Finished Jun 13 01:21:28 PM PDT 24
Peak memory 200680 kb
Host smart-b76acbc5-3692-4873-8ccc-39957c2e38f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56369920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.56369920
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.1847453408
Short name T236
Test name
Test status
Simulation time 47863379775 ps
CPU time 158.09 seconds
Started Jun 13 01:28:29 PM PDT 24
Finished Jun 13 01:31:07 PM PDT 24
Peak memory 217112 kb
Host smart-0188976f-1ecb-4c64-b27a-d372b9530b07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847453408 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.1847453408
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1232527149
Short name T1150
Test name
Test status
Simulation time 48913531 ps
CPU time 0.68 seconds
Started Jun 13 12:59:24 PM PDT 24
Finished Jun 13 12:59:27 PM PDT 24
Peak memory 195360 kb
Host smart-16efeaee-b004-46ca-a1af-a630d8d6082b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232527149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.1232527149
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.779349090
Short name T1132
Test name
Test status
Simulation time 313875859 ps
CPU time 2.43 seconds
Started Jun 13 12:59:17 PM PDT 24
Finished Jun 13 12:59:22 PM PDT 24
Peak memory 197488 kb
Host smart-ca4832fb-2cf8-4582-9632-c68ae854415d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779349090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.779349090
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.35317635
Short name T1136
Test name
Test status
Simulation time 12269053 ps
CPU time 0.61 seconds
Started Jun 13 12:59:18 PM PDT 24
Finished Jun 13 12:59:21 PM PDT 24
Peak memory 195344 kb
Host smart-9017e4ab-1229-4768-812e-2675659f142d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35317635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.35317635
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3160462924
Short name T1164
Test name
Test status
Simulation time 79104174 ps
CPU time 1.18 seconds
Started Jun 13 12:59:25 PM PDT 24
Finished Jun 13 12:59:28 PM PDT 24
Peak memory 199968 kb
Host smart-53254637-1a4e-4788-a068-677087e271de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160462924 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.3160462924
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.1353264884
Short name T1201
Test name
Test status
Simulation time 140341031 ps
CPU time 0.61 seconds
Started Jun 13 12:59:18 PM PDT 24
Finished Jun 13 12:59:21 PM PDT 24
Peak memory 195428 kb
Host smart-1c61846d-0758-4c57-b5f0-ce578efb0f57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353264884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.1353264884
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.211371201
Short name T1172
Test name
Test status
Simulation time 49579430 ps
CPU time 0.57 seconds
Started Jun 13 12:59:17 PM PDT 24
Finished Jun 13 12:59:20 PM PDT 24
Peak memory 194280 kb
Host smart-eaa7c027-eadf-4676-bc84-3d9e6821e344
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211371201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.211371201
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.864503483
Short name T1152
Test name
Test status
Simulation time 168006572 ps
CPU time 0.63 seconds
Started Jun 13 12:59:25 PM PDT 24
Finished Jun 13 12:59:28 PM PDT 24
Peak memory 194880 kb
Host smart-e9a4a7a6-be5e-4421-a9fc-2fb52ed48a9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864503483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr_
outstanding.864503483
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.2986249239
Short name T1138
Test name
Test status
Simulation time 105398279 ps
CPU time 1.43 seconds
Started Jun 13 12:59:16 PM PDT 24
Finished Jun 13 12:59:19 PM PDT 24
Peak memory 199944 kb
Host smart-54f82a6d-5042-4fc3-8b1d-ba5f3e66af56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986249239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.2986249239
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2798834011
Short name T89
Test name
Test status
Simulation time 156502272 ps
CPU time 0.92 seconds
Started Jun 13 12:59:17 PM PDT 24
Finished Jun 13 12:59:20 PM PDT 24
Peak memory 198976 kb
Host smart-28bb54af-556e-41f1-a724-457979f4986e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798834011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.2798834011
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.882975789
Short name T72
Test name
Test status
Simulation time 57957891 ps
CPU time 0.77 seconds
Started Jun 13 12:59:25 PM PDT 24
Finished Jun 13 12:59:28 PM PDT 24
Peak memory 196240 kb
Host smart-33827a55-fb03-4353-b591-dca85bd586c5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882975789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.882975789
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.1243012059
Short name T1221
Test name
Test status
Simulation time 69534142 ps
CPU time 1.41 seconds
Started Jun 13 12:59:27 PM PDT 24
Finished Jun 13 12:59:30 PM PDT 24
Peak memory 197456 kb
Host smart-9f86caba-4efe-4179-b3dc-2ade3bf6b23b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243012059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.1243012059
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.2875117341
Short name T1200
Test name
Test status
Simulation time 13611076 ps
CPU time 0.61 seconds
Started Jun 13 12:59:24 PM PDT 24
Finished Jun 13 12:59:26 PM PDT 24
Peak memory 195348 kb
Host smart-778bcf85-1b2a-4f82-8093-301c7f8dcf78
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875117341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.2875117341
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1210083776
Short name T1211
Test name
Test status
Simulation time 22475318 ps
CPU time 1.07 seconds
Started Jun 13 12:59:24 PM PDT 24
Finished Jun 13 12:59:26 PM PDT 24
Peak memory 199964 kb
Host smart-833f24b7-3e68-4e57-a5be-2409c5c2f388
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210083776 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.1210083776
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.994650501
Short name T1191
Test name
Test status
Simulation time 93835323 ps
CPU time 0.58 seconds
Started Jun 13 12:59:25 PM PDT 24
Finished Jun 13 12:59:27 PM PDT 24
Peak memory 195340 kb
Host smart-56682bf4-a21d-41a9-9746-730a9ce5a542
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994650501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.994650501
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.734058132
Short name T1167
Test name
Test status
Simulation time 15043591 ps
CPU time 0.56 seconds
Started Jun 13 12:59:26 PM PDT 24
Finished Jun 13 12:59:28 PM PDT 24
Peak memory 194328 kb
Host smart-164fda0e-b2ab-4864-98b6-81784be859f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734058132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.734058132
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3946940365
Short name T1178
Test name
Test status
Simulation time 121379179 ps
CPU time 0.65 seconds
Started Jun 13 12:59:25 PM PDT 24
Finished Jun 13 12:59:28 PM PDT 24
Peak memory 194708 kb
Host smart-a90ff4f6-6d8c-4e13-82fa-5cc80c5a3f25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946940365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.3946940365
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.3522914200
Short name T1171
Test name
Test status
Simulation time 358281172 ps
CPU time 1.11 seconds
Started Jun 13 12:59:25 PM PDT 24
Finished Jun 13 12:59:28 PM PDT 24
Peak memory 199784 kb
Host smart-b30affb8-4b9b-4e07-8388-ff0aad9cfd7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522914200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.3522914200
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1169705722
Short name T1120
Test name
Test status
Simulation time 29820429 ps
CPU time 0.88 seconds
Started Jun 13 12:59:33 PM PDT 24
Finished Jun 13 12:59:35 PM PDT 24
Peak memory 199624 kb
Host smart-f98b8b79-c4b1-49b7-99b8-2bb1c7f53e8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169705722 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.1169705722
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.3847100197
Short name T71
Test name
Test status
Simulation time 15411371 ps
CPU time 0.56 seconds
Started Jun 13 12:59:32 PM PDT 24
Finished Jun 13 12:59:34 PM PDT 24
Peak memory 195340 kb
Host smart-072df7a3-c9b9-4d91-a237-f25e121f7fe3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847100197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.3847100197
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.4074956666
Short name T1101
Test name
Test status
Simulation time 15458359 ps
CPU time 0.61 seconds
Started Jun 13 12:59:29 PM PDT 24
Finished Jun 13 12:59:31 PM PDT 24
Peak memory 194292 kb
Host smart-86585b65-c8ef-40e6-a288-27c84e28c2e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074956666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.4074956666
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.815475783
Short name T81
Test name
Test status
Simulation time 21895912 ps
CPU time 0.68 seconds
Started Jun 13 12:59:31 PM PDT 24
Finished Jun 13 12:59:33 PM PDT 24
Peak memory 195824 kb
Host smart-949272fc-47a0-4dc1-bec3-b316d7ec2173
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815475783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_csr
_outstanding.815475783
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.3535755405
Short name T1147
Test name
Test status
Simulation time 46526933 ps
CPU time 1.19 seconds
Started Jun 13 12:59:32 PM PDT 24
Finished Jun 13 12:59:34 PM PDT 24
Peak memory 199736 kb
Host smart-98db36d1-e361-4884-8fad-0818f45c57bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535755405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.3535755405
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2454663808
Short name T1157
Test name
Test status
Simulation time 88079199 ps
CPU time 0.89 seconds
Started Jun 13 12:59:33 PM PDT 24
Finished Jun 13 12:59:36 PM PDT 24
Peak memory 198452 kb
Host smart-d1de16d1-eb50-442b-bd05-22b928a568dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454663808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.2454663808
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.153208081
Short name T1159
Test name
Test status
Simulation time 66247825 ps
CPU time 0.79 seconds
Started Jun 13 12:59:39 PM PDT 24
Finished Jun 13 12:59:41 PM PDT 24
Peak memory 199612 kb
Host smart-360e59ef-4744-469f-b4ca-7eb0c2a8d42f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153208081 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.153208081
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.792453287
Short name T1123
Test name
Test status
Simulation time 46264804 ps
CPU time 0.58 seconds
Started Jun 13 12:59:34 PM PDT 24
Finished Jun 13 12:59:36 PM PDT 24
Peak memory 195360 kb
Host smart-48fc3105-b3da-4f53-b18b-ce241e2eadf2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792453287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.792453287
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.3617481715
Short name T1231
Test name
Test status
Simulation time 41051128 ps
CPU time 0.58 seconds
Started Jun 13 12:59:37 PM PDT 24
Finished Jun 13 12:59:39 PM PDT 24
Peak memory 194392 kb
Host smart-de6a63d8-6fbe-4fa6-9d10-64792bf3a16a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617481715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.3617481715
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.2920968707
Short name T1182
Test name
Test status
Simulation time 20188083 ps
CPU time 0.67 seconds
Started Jun 13 12:59:36 PM PDT 24
Finished Jun 13 12:59:37 PM PDT 24
Peak memory 195652 kb
Host smart-5fac25bd-abe9-4d17-b525-eeecc11e9a4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920968707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.2920968707
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.69795720
Short name T1154
Test name
Test status
Simulation time 99906612 ps
CPU time 1.92 seconds
Started Jun 13 12:59:33 PM PDT 24
Finished Jun 13 12:59:36 PM PDT 24
Peak memory 199944 kb
Host smart-ef9e4b1a-1fd3-4fc3-8d39-6e08be9a7f4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69795720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.69795720
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.2222385137
Short name T1206
Test name
Test status
Simulation time 72020870 ps
CPU time 1.3 seconds
Started Jun 13 12:59:41 PM PDT 24
Finished Jun 13 12:59:43 PM PDT 24
Peak memory 199212 kb
Host smart-3e5e904f-4318-4b0d-8d96-9c4b5cc2430c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222385137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.2222385137
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.2965933757
Short name T1222
Test name
Test status
Simulation time 108635966 ps
CPU time 0.96 seconds
Started Jun 13 12:59:41 PM PDT 24
Finished Jun 13 12:59:43 PM PDT 24
Peak memory 200056 kb
Host smart-379f8d46-67a9-4398-97df-159eb45ccb84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965933757 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.2965933757
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.3086664240
Short name T1227
Test name
Test status
Simulation time 11971065 ps
CPU time 0.55 seconds
Started Jun 13 12:59:36 PM PDT 24
Finished Jun 13 12:59:38 PM PDT 24
Peak memory 194304 kb
Host smart-b05d8929-da07-4f62-a51d-d9062af858a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086664240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.3086664240
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.61822731
Short name T74
Test name
Test status
Simulation time 59534943 ps
CPU time 0.61 seconds
Started Jun 13 12:59:38 PM PDT 24
Finished Jun 13 12:59:40 PM PDT 24
Peak memory 196440 kb
Host smart-221d562b-8e7d-4a0e-9687-254714ba5ab2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61822731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_csr_
outstanding.61822731
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.2209891385
Short name T1229
Test name
Test status
Simulation time 171334776 ps
CPU time 1.97 seconds
Started Jun 13 12:59:41 PM PDT 24
Finished Jun 13 12:59:44 PM PDT 24
Peak memory 200204 kb
Host smart-44b9f88b-35ea-48c8-99a6-83b018ff6647
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209891385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.2209891385
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3255940215
Short name T1195
Test name
Test status
Simulation time 159330745 ps
CPU time 1.37 seconds
Started Jun 13 12:59:40 PM PDT 24
Finished Jun 13 12:59:43 PM PDT 24
Peak memory 199216 kb
Host smart-a89316ee-4e52-4c90-bd0c-1a9bbbfe5a34
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255940215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.3255940215
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3836900828
Short name T1128
Test name
Test status
Simulation time 18229049 ps
CPU time 0.64 seconds
Started Jun 13 12:59:36 PM PDT 24
Finished Jun 13 12:59:38 PM PDT 24
Peak memory 197608 kb
Host smart-b4b4749e-218e-4c9c-a14c-500e8163a4aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836900828 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.3836900828
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.1713613645
Short name T1161
Test name
Test status
Simulation time 18050634 ps
CPU time 0.64 seconds
Started Jun 13 12:59:40 PM PDT 24
Finished Jun 13 12:59:41 PM PDT 24
Peak memory 195412 kb
Host smart-6e4ad687-57fc-450a-a12a-1a23c0dde138
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713613645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.1713613645
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.3863807463
Short name T1189
Test name
Test status
Simulation time 17419481 ps
CPU time 0.56 seconds
Started Jun 13 12:59:41 PM PDT 24
Finished Jun 13 12:59:42 PM PDT 24
Peak memory 194288 kb
Host smart-cb6f9021-639b-4881-8bbc-f414f47e9249
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863807463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.3863807463
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.1939106446
Short name T82
Test name
Test status
Simulation time 31470988 ps
CPU time 0.69 seconds
Started Jun 13 12:59:37 PM PDT 24
Finished Jun 13 12:59:39 PM PDT 24
Peak memory 195568 kb
Host smart-26a4ee63-e06a-40cd-99a8-cf450ef1ccda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939106446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.1939106446
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.3598767448
Short name T1175
Test name
Test status
Simulation time 169398210 ps
CPU time 1.75 seconds
Started Jun 13 12:59:39 PM PDT 24
Finished Jun 13 12:59:41 PM PDT 24
Peak memory 199908 kb
Host smart-39d223a0-b70f-4124-a7b7-93114fa0cc73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598767448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.3598767448
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.454442744
Short name T1204
Test name
Test status
Simulation time 42172508 ps
CPU time 0.99 seconds
Started Jun 13 12:59:36 PM PDT 24
Finished Jun 13 12:59:38 PM PDT 24
Peak memory 199104 kb
Host smart-edf8128f-2068-4acb-8cd6-6febbbadcd36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454442744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.454442744
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3445562499
Short name T1213
Test name
Test status
Simulation time 26441660 ps
CPU time 0.8 seconds
Started Jun 13 12:59:37 PM PDT 24
Finished Jun 13 12:59:39 PM PDT 24
Peak memory 198960 kb
Host smart-49cf407c-4889-4d52-ad66-20dc88a9cb28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445562499 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.3445562499
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.4294577085
Short name T77
Test name
Test status
Simulation time 75935355 ps
CPU time 0.6 seconds
Started Jun 13 12:59:37 PM PDT 24
Finished Jun 13 12:59:39 PM PDT 24
Peak memory 195324 kb
Host smart-5d2c1837-3b70-41ea-b22d-fa7a200e22e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294577085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.4294577085
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.236798397
Short name T1181
Test name
Test status
Simulation time 54270571 ps
CPU time 0.57 seconds
Started Jun 13 12:59:38 PM PDT 24
Finished Jun 13 12:59:40 PM PDT 24
Peak memory 194328 kb
Host smart-92401b7a-117f-44ad-9805-037e063a0ad1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236798397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.236798397
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.445680303
Short name T78
Test name
Test status
Simulation time 45183360 ps
CPU time 0.64 seconds
Started Jun 13 12:59:38 PM PDT 24
Finished Jun 13 12:59:40 PM PDT 24
Peak memory 194660 kb
Host smart-ac5705aa-0333-4c47-8b68-32a2b305b24b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445680303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_csr
_outstanding.445680303
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.3213006899
Short name T1168
Test name
Test status
Simulation time 1114377302 ps
CPU time 2.12 seconds
Started Jun 13 12:59:39 PM PDT 24
Finished Jun 13 12:59:42 PM PDT 24
Peak memory 199944 kb
Host smart-9a7eff8d-5b57-4f70-a0db-54cb0a98c8e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213006899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.3213006899
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2480075829
Short name T1115
Test name
Test status
Simulation time 119073035 ps
CPU time 1.11 seconds
Started Jun 13 12:59:42 PM PDT 24
Finished Jun 13 12:59:44 PM PDT 24
Peak memory 199904 kb
Host smart-085f60ef-0649-4c8a-92c1-95413df4fe29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480075829 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.2480075829
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.2563454699
Short name T1188
Test name
Test status
Simulation time 55141619 ps
CPU time 0.69 seconds
Started Jun 13 12:59:49 PM PDT 24
Finished Jun 13 12:59:51 PM PDT 24
Peak memory 195456 kb
Host smart-09d07782-b6c7-424a-ae3e-2a8d85d7ef80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563454699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.2563454699
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.3177535090
Short name T1166
Test name
Test status
Simulation time 34369784 ps
CPU time 0.6 seconds
Started Jun 13 12:59:50 PM PDT 24
Finished Jun 13 12:59:52 PM PDT 24
Peak memory 194400 kb
Host smart-3ebfccf4-4f32-40cb-9cad-d29eb066bb22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177535090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.3177535090
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.167799193
Short name T1158
Test name
Test status
Simulation time 35313381 ps
CPU time 0.71 seconds
Started Jun 13 12:59:47 PM PDT 24
Finished Jun 13 12:59:50 PM PDT 24
Peak memory 195796 kb
Host smart-ce7e4b6b-9be0-446a-84af-bd4c6b762b67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167799193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_csr
_outstanding.167799193
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.463114965
Short name T1193
Test name
Test status
Simulation time 176696824 ps
CPU time 2.09 seconds
Started Jun 13 12:59:37 PM PDT 24
Finished Jun 13 12:59:40 PM PDT 24
Peak memory 199936 kb
Host smart-e976fff0-73a0-4e11-a005-a39b4b3d7bd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463114965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.463114965
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.463066669
Short name T87
Test name
Test status
Simulation time 177179062 ps
CPU time 1.02 seconds
Started Jun 13 12:59:46 PM PDT 24
Finished Jun 13 12:59:48 PM PDT 24
Peak memory 199152 kb
Host smart-5ad559a1-fb45-41fb-998b-127fe11ae698
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463066669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.463066669
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3346721820
Short name T1135
Test name
Test status
Simulation time 15798492 ps
CPU time 0.8 seconds
Started Jun 13 12:59:45 PM PDT 24
Finished Jun 13 12:59:48 PM PDT 24
Peak memory 199808 kb
Host smart-e406055b-7a07-403f-80bc-ff2ec012819e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346721820 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.3346721820
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.1558386490
Short name T1133
Test name
Test status
Simulation time 18260622 ps
CPU time 0.63 seconds
Started Jun 13 12:59:42 PM PDT 24
Finished Jun 13 12:59:44 PM PDT 24
Peak memory 195404 kb
Host smart-4b641dbd-8ad7-459f-ae13-0034bdca893e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558386490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.1558386490
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.1944790724
Short name T1108
Test name
Test status
Simulation time 17243990 ps
CPU time 0.58 seconds
Started Jun 13 12:59:44 PM PDT 24
Finished Jun 13 12:59:46 PM PDT 24
Peak memory 194328 kb
Host smart-f883d94c-d8c9-445f-b44c-7ca39fa27876
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944790724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.1944790724
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1795490909
Short name T1156
Test name
Test status
Simulation time 14385204 ps
CPU time 0.67 seconds
Started Jun 13 12:59:45 PM PDT 24
Finished Jun 13 12:59:48 PM PDT 24
Peak memory 195664 kb
Host smart-9b17c604-b0f9-433c-aea4-aaab2c29b269
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795490909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.1795490909
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.2499087238
Short name T1186
Test name
Test status
Simulation time 57598968 ps
CPU time 1.46 seconds
Started Jun 13 12:59:44 PM PDT 24
Finished Jun 13 12:59:47 PM PDT 24
Peak memory 199944 kb
Host smart-21c9f5ac-4c83-41b6-bd62-0b6f11d9a09f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499087238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.2499087238
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.1632644781
Short name T97
Test name
Test status
Simulation time 90023957 ps
CPU time 1.29 seconds
Started Jun 13 12:59:45 PM PDT 24
Finished Jun 13 12:59:47 PM PDT 24
Peak memory 199144 kb
Host smart-b101a584-2c5d-4440-b1e2-380551b4b5b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632644781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.1632644781
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2651923688
Short name T1143
Test name
Test status
Simulation time 90567383 ps
CPU time 0.77 seconds
Started Jun 13 12:59:45 PM PDT 24
Finished Jun 13 12:59:48 PM PDT 24
Peak memory 198652 kb
Host smart-6b323444-018f-4a57-acd0-8f8c2ab56333
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651923688 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.2651923688
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.427308154
Short name T1153
Test name
Test status
Simulation time 49655382 ps
CPU time 0.62 seconds
Started Jun 13 12:59:43 PM PDT 24
Finished Jun 13 12:59:44 PM PDT 24
Peak memory 195432 kb
Host smart-e27a1cd5-741c-46ae-a5e2-5330186b21f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427308154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.427308154
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.2560953208
Short name T1122
Test name
Test status
Simulation time 30830805 ps
CPU time 0.6 seconds
Started Jun 13 12:59:43 PM PDT 24
Finished Jun 13 12:59:44 PM PDT 24
Peak memory 194400 kb
Host smart-d0694a1b-16e5-4b57-bb50-545edd5b5d7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560953208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.2560953208
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.277129165
Short name T79
Test name
Test status
Simulation time 423203677 ps
CPU time 0.73 seconds
Started Jun 13 12:59:48 PM PDT 24
Finished Jun 13 12:59:50 PM PDT 24
Peak memory 197664 kb
Host smart-03d8e7a3-4fa2-4ad9-af8e-347f81a0bec2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277129165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr
_outstanding.277129165
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.438071492
Short name T1176
Test name
Test status
Simulation time 401233200 ps
CPU time 2.08 seconds
Started Jun 13 12:59:45 PM PDT 24
Finished Jun 13 12:59:49 PM PDT 24
Peak memory 199916 kb
Host smart-01484514-334e-499d-a3b4-8354f528145e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438071492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.438071492
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.1365077258
Short name T1192
Test name
Test status
Simulation time 54941772 ps
CPU time 1.02 seconds
Started Jun 13 12:59:47 PM PDT 24
Finished Jun 13 12:59:50 PM PDT 24
Peak memory 199096 kb
Host smart-38dee00b-b09b-4173-980a-a89ec857878a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365077258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.1365077258
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1316977999
Short name T1151
Test name
Test status
Simulation time 23466717 ps
CPU time 1.06 seconds
Started Jun 13 12:59:48 PM PDT 24
Finished Jun 13 12:59:50 PM PDT 24
Peak memory 199844 kb
Host smart-d99a2fbe-631c-4545-93a2-5ece77471a8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316977999 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.1316977999
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.3273372577
Short name T1225
Test name
Test status
Simulation time 80740349 ps
CPU time 0.58 seconds
Started Jun 13 12:59:46 PM PDT 24
Finished Jun 13 12:59:48 PM PDT 24
Peak memory 194396 kb
Host smart-4105381c-9460-4f8d-b95f-156272946560
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273372577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3273372577
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3237733828
Short name T1190
Test name
Test status
Simulation time 19134019 ps
CPU time 0.76 seconds
Started Jun 13 12:59:46 PM PDT 24
Finished Jun 13 12:59:48 PM PDT 24
Peak memory 196084 kb
Host smart-20ffbf1c-1e4c-4bce-90f6-e03a368a9dbd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237733828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.3237733828
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.884912052
Short name T1183
Test name
Test status
Simulation time 52913038 ps
CPU time 1.41 seconds
Started Jun 13 12:59:45 PM PDT 24
Finished Jun 13 12:59:47 PM PDT 24
Peak memory 199928 kb
Host smart-9d9777d7-6a15-41ed-8984-0e44dc541fbf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884912052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.884912052
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.871141983
Short name T91
Test name
Test status
Simulation time 144403081 ps
CPU time 0.93 seconds
Started Jun 13 12:59:45 PM PDT 24
Finished Jun 13 12:59:48 PM PDT 24
Peak memory 198768 kb
Host smart-3e12752e-bb09-435f-9e35-5042613a4b2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871141983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.871141983
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1131742062
Short name T1116
Test name
Test status
Simulation time 58795752 ps
CPU time 0.79 seconds
Started Jun 13 12:59:45 PM PDT 24
Finished Jun 13 12:59:48 PM PDT 24
Peak memory 199552 kb
Host smart-92a00818-029d-407f-b16d-0cd6c7e923e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131742062 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.1131742062
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.1182634493
Short name T1184
Test name
Test status
Simulation time 25207348 ps
CPU time 0.59 seconds
Started Jun 13 12:59:50 PM PDT 24
Finished Jun 13 12:59:52 PM PDT 24
Peak memory 195324 kb
Host smart-6f2c4389-a2a0-4583-b601-a093660b81f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182634493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.1182634493
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.3585135427
Short name T1103
Test name
Test status
Simulation time 31419330 ps
CPU time 0.58 seconds
Started Jun 13 12:59:44 PM PDT 24
Finished Jun 13 12:59:46 PM PDT 24
Peak memory 194280 kb
Host smart-cf5414b6-651a-4bb9-9130-1f0795f6a0b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585135427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.3585135427
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1377194204
Short name T1125
Test name
Test status
Simulation time 28808385 ps
CPU time 0.75 seconds
Started Jun 13 12:59:45 PM PDT 24
Finished Jun 13 12:59:48 PM PDT 24
Peak memory 196936 kb
Host smart-549ed4fd-c33b-4137-be12-49e48a51453f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377194204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.1377194204
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.482220645
Short name T1134
Test name
Test status
Simulation time 67048344 ps
CPU time 1.62 seconds
Started Jun 13 12:59:47 PM PDT 24
Finished Jun 13 12:59:50 PM PDT 24
Peak memory 199940 kb
Host smart-69523e7d-c10a-48be-977f-2ce99c0f7574
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482220645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.482220645
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.444912406
Short name T93
Test name
Test status
Simulation time 177535746 ps
CPU time 0.92 seconds
Started Jun 13 12:59:50 PM PDT 24
Finished Jun 13 12:59:52 PM PDT 24
Peak memory 198956 kb
Host smart-bde55a9d-c3bc-43fb-a7da-4f760b1136af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444912406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.444912406
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3429106664
Short name T1220
Test name
Test status
Simulation time 27907168 ps
CPU time 0.76 seconds
Started Jun 13 12:59:25 PM PDT 24
Finished Jun 13 12:59:27 PM PDT 24
Peak memory 196196 kb
Host smart-1776d1fa-b8ae-47c3-8d68-6e9d881b13aa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429106664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.3429106664
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.3722528531
Short name T59
Test name
Test status
Simulation time 65362074 ps
CPU time 1.38 seconds
Started Jun 13 12:59:24 PM PDT 24
Finished Jun 13 12:59:27 PM PDT 24
Peak memory 197724 kb
Host smart-e2c78404-bfe4-48b7-bf70-08c33ced9853
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722528531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.3722528531
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.1729964451
Short name T1146
Test name
Test status
Simulation time 15422475 ps
CPU time 0.56 seconds
Started Jun 13 12:59:24 PM PDT 24
Finished Jun 13 12:59:27 PM PDT 24
Peak memory 195364 kb
Host smart-66099583-9fac-4a0a-a105-8b6355b16ad5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729964451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.1729964451
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.843361377
Short name T1142
Test name
Test status
Simulation time 53869572 ps
CPU time 0.7 seconds
Started Jun 13 12:59:27 PM PDT 24
Finished Jun 13 12:59:29 PM PDT 24
Peak memory 198372 kb
Host smart-fc93e2b8-5506-4874-8aeb-20964db2a742
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843361377 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.843361377
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.3365185839
Short name T1228
Test name
Test status
Simulation time 19016500 ps
CPU time 0.63 seconds
Started Jun 13 12:59:26 PM PDT 24
Finished Jun 13 12:59:28 PM PDT 24
Peak memory 195660 kb
Host smart-56502f20-1055-43b2-bd26-46ddcfa2f90c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365185839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.3365185839
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.3752795638
Short name T1180
Test name
Test status
Simulation time 30556885 ps
CPU time 0.58 seconds
Started Jun 13 12:59:23 PM PDT 24
Finished Jun 13 12:59:24 PM PDT 24
Peak memory 194388 kb
Host smart-2916785b-14c3-49f2-9a72-e8f3c2b54fe3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752795638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.3752795638
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3833293853
Short name T1144
Test name
Test status
Simulation time 34506923 ps
CPU time 0.64 seconds
Started Jun 13 12:59:24 PM PDT 24
Finished Jun 13 12:59:27 PM PDT 24
Peak memory 195676 kb
Host smart-32a73e07-0c5e-4f3b-a542-0dbe784a0b72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833293853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.3833293853
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.3296617701
Short name T1205
Test name
Test status
Simulation time 37829593 ps
CPU time 1.78 seconds
Started Jun 13 12:59:24 PM PDT 24
Finished Jun 13 12:59:27 PM PDT 24
Peak memory 199864 kb
Host smart-af8bd4f7-39c5-42ee-ae75-bcf41661b669
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296617701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.3296617701
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.4294914737
Short name T96
Test name
Test status
Simulation time 38981575 ps
CPU time 0.96 seconds
Started Jun 13 12:59:24 PM PDT 24
Finished Jun 13 12:59:27 PM PDT 24
Peak memory 198864 kb
Host smart-53c5e194-0e02-46f8-ba77-bd31fe5eeedc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294914737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.4294914737
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.2872321257
Short name T1216
Test name
Test status
Simulation time 43842300 ps
CPU time 0.58 seconds
Started Jun 13 12:59:48 PM PDT 24
Finished Jun 13 12:59:50 PM PDT 24
Peak memory 194356 kb
Host smart-abc1c792-133a-4b64-bdfd-8bf38b6f880d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872321257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.2872321257
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.2236134326
Short name T1114
Test name
Test status
Simulation time 11527171 ps
CPU time 0.54 seconds
Started Jun 13 12:59:50 PM PDT 24
Finished Jun 13 12:59:52 PM PDT 24
Peak memory 194308 kb
Host smart-94840b5e-1e65-44c8-95b8-4c95d7314fe8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236134326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.2236134326
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.2145173449
Short name T1230
Test name
Test status
Simulation time 45268597 ps
CPU time 0.62 seconds
Started Jun 13 12:59:45 PM PDT 24
Finished Jun 13 12:59:47 PM PDT 24
Peak memory 194328 kb
Host smart-d92a7083-d72c-4392-bd55-cde288cc11ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145173449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.2145173449
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.2496556479
Short name T1177
Test name
Test status
Simulation time 28109364 ps
CPU time 0.6 seconds
Started Jun 13 12:59:46 PM PDT 24
Finished Jun 13 12:59:48 PM PDT 24
Peak memory 194384 kb
Host smart-9305528a-f478-4787-8902-c5e66fc2a078
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496556479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.2496556479
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.613410034
Short name T1209
Test name
Test status
Simulation time 16552743 ps
CPU time 0.63 seconds
Started Jun 13 12:59:52 PM PDT 24
Finished Jun 13 12:59:54 PM PDT 24
Peak memory 194356 kb
Host smart-9efa8a2f-bc10-4d90-a7cf-875c15a7b310
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613410034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.613410034
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.488228751
Short name T1187
Test name
Test status
Simulation time 40862287 ps
CPU time 0.59 seconds
Started Jun 13 12:59:48 PM PDT 24
Finished Jun 13 12:59:50 PM PDT 24
Peak memory 194392 kb
Host smart-8fa36892-955b-4702-93f8-9f2a71a0765f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488228751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.488228751
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.393105068
Short name T1218
Test name
Test status
Simulation time 47935399 ps
CPU time 0.6 seconds
Started Jun 13 12:59:57 PM PDT 24
Finished Jun 13 12:59:58 PM PDT 24
Peak memory 194384 kb
Host smart-81c945c5-b6ae-4efb-9291-a30ec24bcd38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393105068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.393105068
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.769960604
Short name T1174
Test name
Test status
Simulation time 10847650 ps
CPU time 0.58 seconds
Started Jun 13 12:59:51 PM PDT 24
Finished Jun 13 12:59:53 PM PDT 24
Peak memory 194332 kb
Host smart-e08d9147-0a28-42a6-9f36-af4d369217fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769960604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.769960604
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.2573201639
Short name T1112
Test name
Test status
Simulation time 12182875 ps
CPU time 0.54 seconds
Started Jun 13 12:59:52 PM PDT 24
Finished Jun 13 12:59:54 PM PDT 24
Peak memory 194328 kb
Host smart-8df85eb5-a90b-4706-af99-c968f9d0e7c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573201639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.2573201639
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.1643732749
Short name T1129
Test name
Test status
Simulation time 13835032 ps
CPU time 0.56 seconds
Started Jun 13 12:59:51 PM PDT 24
Finished Jun 13 12:59:52 PM PDT 24
Peak memory 194296 kb
Host smart-213c3f55-5979-44c7-a10b-a556a6066dfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643732749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.1643732749
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2885594260
Short name T1185
Test name
Test status
Simulation time 27170578 ps
CPU time 0.67 seconds
Started Jun 13 12:59:24 PM PDT 24
Finished Jun 13 12:59:26 PM PDT 24
Peak memory 194696 kb
Host smart-63abf3a4-7d0b-4d1e-bf20-93aefe855710
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885594260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.2885594260
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.307043546
Short name T61
Test name
Test status
Simulation time 356461546 ps
CPU time 1.5 seconds
Started Jun 13 12:59:24 PM PDT 24
Finished Jun 13 12:59:28 PM PDT 24
Peak memory 197536 kb
Host smart-faef1fae-d2f5-4ef3-a460-694665bbac40
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307043546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.307043546
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.456263503
Short name T55
Test name
Test status
Simulation time 18921813 ps
CPU time 0.61 seconds
Started Jun 13 12:59:23 PM PDT 24
Finished Jun 13 12:59:25 PM PDT 24
Peak memory 195352 kb
Host smart-b50ddae3-017c-4958-b6a2-fea4f6b0a620
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456263503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.456263503
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.2701616743
Short name T1131
Test name
Test status
Simulation time 79718927 ps
CPU time 1.24 seconds
Started Jun 13 12:59:25 PM PDT 24
Finished Jun 13 12:59:28 PM PDT 24
Peak memory 199908 kb
Host smart-a2962c00-c77d-4076-a83b-1f8e6b104a9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701616743 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.2701616743
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.1698905172
Short name T1149
Test name
Test status
Simulation time 75279179 ps
CPU time 0.62 seconds
Started Jun 13 12:59:22 PM PDT 24
Finished Jun 13 12:59:24 PM PDT 24
Peak memory 195444 kb
Host smart-a1f0e5d5-dd54-43ef-9c27-c55db48193f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698905172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.1698905172
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.2347574599
Short name T1117
Test name
Test status
Simulation time 14918001 ps
CPU time 0.55 seconds
Started Jun 13 12:59:25 PM PDT 24
Finished Jun 13 12:59:27 PM PDT 24
Peak memory 194360 kb
Host smart-a9ac4476-7859-4958-9894-78ef9b02c272
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347574599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.2347574599
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.3812473514
Short name T76
Test name
Test status
Simulation time 20975151 ps
CPU time 0.63 seconds
Started Jun 13 12:59:25 PM PDT 24
Finished Jun 13 12:59:28 PM PDT 24
Peak memory 195492 kb
Host smart-77a8ed78-fb5d-414a-8fe9-0872efffa2b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812473514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.3812473514
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.244576627
Short name T1113
Test name
Test status
Simulation time 86625180 ps
CPU time 1.74 seconds
Started Jun 13 12:59:25 PM PDT 24
Finished Jun 13 12:59:29 PM PDT 24
Peak memory 199940 kb
Host smart-50f450c4-48a5-4ea4-8858-c6aeef16d261
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244576627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.244576627
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.12980257
Short name T1104
Test name
Test status
Simulation time 43481902 ps
CPU time 0.59 seconds
Started Jun 13 12:59:53 PM PDT 24
Finished Jun 13 12:59:54 PM PDT 24
Peak memory 194396 kb
Host smart-effc5cef-6f2c-4684-8c30-988a6463c665
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12980257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.12980257
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.1670174026
Short name T1126
Test name
Test status
Simulation time 77169281 ps
CPU time 0.58 seconds
Started Jun 13 12:59:50 PM PDT 24
Finished Jun 13 12:59:51 PM PDT 24
Peak memory 194352 kb
Host smart-e805f706-6412-4aea-8c81-6ea8ec387509
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670174026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.1670174026
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.2503649334
Short name T1141
Test name
Test status
Simulation time 157304441 ps
CPU time 0.57 seconds
Started Jun 13 12:59:56 PM PDT 24
Finished Jun 13 12:59:57 PM PDT 24
Peak memory 194388 kb
Host smart-7abc22c6-4403-4f0a-ae6c-958ebc171fa8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503649334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.2503649334
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.1776085419
Short name T1219
Test name
Test status
Simulation time 12683178 ps
CPU time 0.57 seconds
Started Jun 13 12:59:50 PM PDT 24
Finished Jun 13 12:59:52 PM PDT 24
Peak memory 194332 kb
Host smart-ed80f039-fba4-45b5-a61b-445147893b15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776085419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.1776085419
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.1698747053
Short name T1196
Test name
Test status
Simulation time 14333196 ps
CPU time 0.54 seconds
Started Jun 13 12:59:51 PM PDT 24
Finished Jun 13 12:59:53 PM PDT 24
Peak memory 194332 kb
Host smart-6226fd81-4bc8-41d9-8bca-f23a408e4a7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698747053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.1698747053
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.407112368
Short name T1194
Test name
Test status
Simulation time 14437821 ps
CPU time 0.59 seconds
Started Jun 13 12:59:56 PM PDT 24
Finished Jun 13 12:59:57 PM PDT 24
Peak memory 194316 kb
Host smart-692c180d-3f48-47eb-ac9d-5995cbff1be5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407112368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.407112368
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.2558377457
Short name T1170
Test name
Test status
Simulation time 52577002 ps
CPU time 0.57 seconds
Started Jun 13 12:59:52 PM PDT 24
Finished Jun 13 12:59:54 PM PDT 24
Peak memory 194308 kb
Host smart-daf93da2-0014-4bfa-87a7-bbf9a5424826
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558377457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.2558377457
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.4153917259
Short name T1207
Test name
Test status
Simulation time 10351154 ps
CPU time 0.58 seconds
Started Jun 13 12:59:56 PM PDT 24
Finished Jun 13 12:59:58 PM PDT 24
Peak memory 194384 kb
Host smart-d783a421-04a4-435c-9b4a-19a79c06821a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153917259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.4153917259
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.506535949
Short name T1199
Test name
Test status
Simulation time 51149534 ps
CPU time 0.6 seconds
Started Jun 13 12:59:56 PM PDT 24
Finished Jun 13 12:59:58 PM PDT 24
Peak memory 194384 kb
Host smart-7de15a8c-5f06-430b-a0d1-213e023d2c48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506535949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.506535949
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.4137213672
Short name T1217
Test name
Test status
Simulation time 53157292 ps
CPU time 0.58 seconds
Started Jun 13 12:59:51 PM PDT 24
Finished Jun 13 12:59:53 PM PDT 24
Peak memory 194316 kb
Host smart-605a7595-67a0-4b44-a5f4-c533e597cf47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137213672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.4137213672
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.3796025222
Short name T57
Test name
Test status
Simulation time 52464873 ps
CPU time 0.8 seconds
Started Jun 13 12:59:32 PM PDT 24
Finished Jun 13 12:59:34 PM PDT 24
Peak memory 196444 kb
Host smart-884658d2-d50f-4b0c-a33f-0509e837e061
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796025222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.3796025222
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1347434641
Short name T1107
Test name
Test status
Simulation time 263557141 ps
CPU time 1.51 seconds
Started Jun 13 12:59:23 PM PDT 24
Finished Jun 13 12:59:26 PM PDT 24
Peak memory 197576 kb
Host smart-e417a354-4057-4a94-9fce-27199b701042
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347434641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.1347434641
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2577648826
Short name T1226
Test name
Test status
Simulation time 45183510 ps
CPU time 0.56 seconds
Started Jun 13 12:59:24 PM PDT 24
Finished Jun 13 12:59:27 PM PDT 24
Peak memory 195344 kb
Host smart-661fc94d-0ba1-48e4-b39f-5179380d002d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577648826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.2577648826
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.675817679
Short name T1160
Test name
Test status
Simulation time 32975932 ps
CPU time 1.24 seconds
Started Jun 13 12:59:29 PM PDT 24
Finished Jun 13 12:59:32 PM PDT 24
Peak memory 199972 kb
Host smart-11faa47b-ab85-4d56-b5ff-b50751d4b656
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675817679 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.675817679
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.3775681691
Short name T73
Test name
Test status
Simulation time 17709310 ps
CPU time 0.63 seconds
Started Jun 13 12:59:25 PM PDT 24
Finished Jun 13 12:59:28 PM PDT 24
Peak memory 195392 kb
Host smart-ca0a2726-56d0-419b-bfa5-4b7f28dd8660
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775681691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.3775681691
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.2670714467
Short name T1210
Test name
Test status
Simulation time 14233184 ps
CPU time 0.57 seconds
Started Jun 13 12:59:28 PM PDT 24
Finished Jun 13 12:59:30 PM PDT 24
Peak memory 194292 kb
Host smart-c2924eca-5caf-49bf-8e45-8c43c1e64706
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670714467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.2670714467
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.91463403
Short name T1179
Test name
Test status
Simulation time 409505646 ps
CPU time 0.79 seconds
Started Jun 13 12:59:30 PM PDT 24
Finished Jun 13 12:59:32 PM PDT 24
Peak memory 197076 kb
Host smart-e14d1c87-c66d-4536-b31f-4c4b0e296b3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91463403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_o
utstanding.91463403
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.658638133
Short name T1139
Test name
Test status
Simulation time 482526467 ps
CPU time 1.25 seconds
Started Jun 13 12:59:22 PM PDT 24
Finished Jun 13 12:59:24 PM PDT 24
Peak memory 199864 kb
Host smart-aa9988e6-0ab6-40f4-b3ec-917a5857d8b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658638133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.658638133
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.87041570
Short name T90
Test name
Test status
Simulation time 352429043 ps
CPU time 1.27 seconds
Started Jun 13 12:59:21 PM PDT 24
Finished Jun 13 12:59:23 PM PDT 24
Peak memory 199140 kb
Host smart-02a97f1b-f348-43fa-ba11-82ad50025725
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87041570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.87041570
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.3089529812
Short name T1099
Test name
Test status
Simulation time 24065790 ps
CPU time 0.6 seconds
Started Jun 13 12:59:51 PM PDT 24
Finished Jun 13 12:59:53 PM PDT 24
Peak memory 194352 kb
Host smart-1fdfbc6a-26e3-45fa-a1f1-cfb9b0cfc026
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089529812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.3089529812
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.3447857971
Short name T1106
Test name
Test status
Simulation time 86553185 ps
CPU time 0.61 seconds
Started Jun 13 12:59:52 PM PDT 24
Finished Jun 13 12:59:54 PM PDT 24
Peak memory 194380 kb
Host smart-69391c02-3230-4adb-89d5-6aec94048020
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447857971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.3447857971
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.2931804685
Short name T1124
Test name
Test status
Simulation time 17220261 ps
CPU time 0.6 seconds
Started Jun 13 12:59:51 PM PDT 24
Finished Jun 13 12:59:53 PM PDT 24
Peak memory 194396 kb
Host smart-d8a71022-4297-47a8-9f1d-a01db183205f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931804685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.2931804685
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.2578760701
Short name T1102
Test name
Test status
Simulation time 58906266 ps
CPU time 0.57 seconds
Started Jun 13 12:59:51 PM PDT 24
Finished Jun 13 12:59:53 PM PDT 24
Peak memory 194396 kb
Host smart-9182ce19-06fb-4cb7-9fe4-356de98667b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578760701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.2578760701
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.3648889614
Short name T1105
Test name
Test status
Simulation time 23147312 ps
CPU time 0.56 seconds
Started Jun 13 12:59:52 PM PDT 24
Finished Jun 13 12:59:54 PM PDT 24
Peak memory 194312 kb
Host smart-ff699afe-38e2-495b-96ed-1e0794c55cfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648889614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.3648889614
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.3687367290
Short name T1162
Test name
Test status
Simulation time 27906346 ps
CPU time 0.56 seconds
Started Jun 13 12:59:55 PM PDT 24
Finished Jun 13 12:59:56 PM PDT 24
Peak memory 194384 kb
Host smart-64b6c13c-fbad-4f89-a46b-cfa321748ade
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687367290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.3687367290
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.2698911933
Short name T1119
Test name
Test status
Simulation time 35797616 ps
CPU time 0.57 seconds
Started Jun 13 12:59:50 PM PDT 24
Finished Jun 13 12:59:52 PM PDT 24
Peak memory 194336 kb
Host smart-d687cfaf-754d-4a72-83b0-241d2c716e1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698911933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.2698911933
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.638295880
Short name T1202
Test name
Test status
Simulation time 23824423 ps
CPU time 0.58 seconds
Started Jun 13 12:59:57 PM PDT 24
Finished Jun 13 12:59:58 PM PDT 24
Peak memory 194384 kb
Host smart-49903bc7-59f1-4e99-a98d-9092e89c87c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638295880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.638295880
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.3687904615
Short name T1111
Test name
Test status
Simulation time 25167027 ps
CPU time 0.57 seconds
Started Jun 13 01:00:02 PM PDT 24
Finished Jun 13 01:00:04 PM PDT 24
Peak memory 194628 kb
Host smart-d8cc8d7b-7aa9-4523-9949-9be49d9b84e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687904615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.3687904615
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.3423713647
Short name T1140
Test name
Test status
Simulation time 18744019 ps
CPU time 0.56 seconds
Started Jun 13 12:59:57 PM PDT 24
Finished Jun 13 01:00:00 PM PDT 24
Peak memory 194404 kb
Host smart-62493fbc-5c28-4464-8245-5696baf7b0ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423713647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.3423713647
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3876878138
Short name T1214
Test name
Test status
Simulation time 180150245 ps
CPU time 1.35 seconds
Started Jun 13 12:59:29 PM PDT 24
Finished Jun 13 12:59:32 PM PDT 24
Peak memory 199928 kb
Host smart-f757eaf0-5da1-41e7-8804-eed9e02b094f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876878138 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.3876878138
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.2022602992
Short name T75
Test name
Test status
Simulation time 16093579 ps
CPU time 0.61 seconds
Started Jun 13 12:59:29 PM PDT 24
Finished Jun 13 12:59:31 PM PDT 24
Peak memory 195408 kb
Host smart-92b16204-54ff-443c-91c2-5d2066101020
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022602992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.2022602992
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.3835036449
Short name T1127
Test name
Test status
Simulation time 40451355 ps
CPU time 0.59 seconds
Started Jun 13 12:59:37 PM PDT 24
Finished Jun 13 12:59:39 PM PDT 24
Peak memory 194388 kb
Host smart-de8919b9-d690-4cfb-a00e-a60dd8e975f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835036449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.3835036449
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.3080039413
Short name T1198
Test name
Test status
Simulation time 25914466 ps
CPU time 0.76 seconds
Started Jun 13 12:59:28 PM PDT 24
Finished Jun 13 12:59:31 PM PDT 24
Peak memory 197424 kb
Host smart-e51c4e76-ad51-48f6-a13a-afba73e1c916
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080039413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.3080039413
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.3155257783
Short name T1118
Test name
Test status
Simulation time 127426518 ps
CPU time 2.47 seconds
Started Jun 13 12:59:29 PM PDT 24
Finished Jun 13 12:59:33 PM PDT 24
Peak memory 199900 kb
Host smart-50524e1f-e187-4598-ba41-fb60e7c04516
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155257783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.3155257783
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.3013163458
Short name T1223
Test name
Test status
Simulation time 51958252 ps
CPU time 0.97 seconds
Started Jun 13 12:59:30 PM PDT 24
Finished Jun 13 12:59:33 PM PDT 24
Peak memory 198988 kb
Host smart-458e12af-c478-4f2a-9c1d-5357bc434558
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013163458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.3013163458
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3021744951
Short name T1165
Test name
Test status
Simulation time 166351784 ps
CPU time 0.77 seconds
Started Jun 13 12:59:28 PM PDT 24
Finished Jun 13 12:59:30 PM PDT 24
Peak memory 199224 kb
Host smart-e38f83d7-6293-4b13-b81d-517fb4f0b2b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021744951 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.3021744951
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.1983180018
Short name T1224
Test name
Test status
Simulation time 52189991 ps
CPU time 0.6 seconds
Started Jun 13 12:59:31 PM PDT 24
Finished Jun 13 12:59:33 PM PDT 24
Peak memory 195416 kb
Host smart-4f95f38b-5b32-4fe3-abb9-cb268f80973d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983180018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.1983180018
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.3441802109
Short name T1110
Test name
Test status
Simulation time 24183259 ps
CPU time 0.55 seconds
Started Jun 13 12:59:28 PM PDT 24
Finished Jun 13 12:59:30 PM PDT 24
Peak memory 194296 kb
Host smart-230c4dd6-52c1-4933-ac7d-ba6f93fc0f7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441802109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.3441802109
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.405050831
Short name T1208
Test name
Test status
Simulation time 24811774 ps
CPU time 0.64 seconds
Started Jun 13 12:59:28 PM PDT 24
Finished Jun 13 12:59:30 PM PDT 24
Peak memory 195660 kb
Host smart-f4530d71-25e0-4b98-9068-20d3527539d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405050831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_
outstanding.405050831
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.1916870915
Short name T1109
Test name
Test status
Simulation time 152150104 ps
CPU time 2.33 seconds
Started Jun 13 12:59:29 PM PDT 24
Finished Jun 13 12:59:33 PM PDT 24
Peak memory 199928 kb
Host smart-cf59987e-bc3d-4b20-ac08-07aaf311b22c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916870915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.1916870915
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.3490594105
Short name T92
Test name
Test status
Simulation time 192419875 ps
CPU time 1.36 seconds
Started Jun 13 12:59:33 PM PDT 24
Finished Jun 13 12:59:36 PM PDT 24
Peak memory 199080 kb
Host smart-661fdb5b-cc14-484a-b39b-522631c542dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490594105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.3490594105
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.716938045
Short name T1212
Test name
Test status
Simulation time 68076567 ps
CPU time 0.79 seconds
Started Jun 13 12:59:31 PM PDT 24
Finished Jun 13 12:59:33 PM PDT 24
Peak memory 198376 kb
Host smart-a1888d34-aba9-4e81-bf22-24a49124ef4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716938045 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.716938045
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.2433010281
Short name T1121
Test name
Test status
Simulation time 15605892 ps
CPU time 0.58 seconds
Started Jun 13 12:59:28 PM PDT 24
Finished Jun 13 12:59:30 PM PDT 24
Peak memory 195304 kb
Host smart-f0fee706-455e-4dbe-b1fd-8436eeefa1b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433010281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.2433010281
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.3463826937
Short name T1100
Test name
Test status
Simulation time 13234493 ps
CPU time 0.58 seconds
Started Jun 13 12:59:31 PM PDT 24
Finished Jun 13 12:59:33 PM PDT 24
Peak memory 194396 kb
Host smart-c59c6b6e-8f52-426e-8933-896f764126fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463826937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.3463826937
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1152829820
Short name T1148
Test name
Test status
Simulation time 21171646 ps
CPU time 0.76 seconds
Started Jun 13 12:59:31 PM PDT 24
Finished Jun 13 12:59:33 PM PDT 24
Peak memory 197068 kb
Host smart-1416d4e7-5825-461a-b189-a3655a1dc1fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152829820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.1152829820
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.1767586908
Short name T1173
Test name
Test status
Simulation time 570178768 ps
CPU time 1.32 seconds
Started Jun 13 12:59:28 PM PDT 24
Finished Jun 13 12:59:31 PM PDT 24
Peak memory 199880 kb
Host smart-b794cc64-2b83-4142-8f08-5f7648d78e51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767586908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.1767586908
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.2481326653
Short name T121
Test name
Test status
Simulation time 392054119 ps
CPU time 1.03 seconds
Started Jun 13 12:59:29 PM PDT 24
Finished Jun 13 12:59:32 PM PDT 24
Peak memory 198956 kb
Host smart-6bc5b844-4822-48fd-887b-2931de6c5a1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481326653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.2481326653
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.4150233016
Short name T1163
Test name
Test status
Simulation time 289612055 ps
CPU time 0.74 seconds
Started Jun 13 12:59:33 PM PDT 24
Finished Jun 13 12:59:35 PM PDT 24
Peak memory 198352 kb
Host smart-2fdfc224-85fe-489e-a8d6-1625c2336cfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150233016 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.4150233016
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.2771697069
Short name T58
Test name
Test status
Simulation time 34065642 ps
CPU time 0.56 seconds
Started Jun 13 12:59:37 PM PDT 24
Finished Jun 13 12:59:39 PM PDT 24
Peak memory 195340 kb
Host smart-f967f948-231a-4fde-935f-6c11263b6f6b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771697069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.2771697069
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.383636328
Short name T1203
Test name
Test status
Simulation time 12931388 ps
CPU time 0.57 seconds
Started Jun 13 12:59:32 PM PDT 24
Finished Jun 13 12:59:34 PM PDT 24
Peak memory 194292 kb
Host smart-487fbd07-87bd-400a-96ac-164b6c0ff0bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383636328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.383636328
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.425595784
Short name T1197
Test name
Test status
Simulation time 277199788 ps
CPU time 0.76 seconds
Started Jun 13 12:59:30 PM PDT 24
Finished Jun 13 12:59:32 PM PDT 24
Peak memory 196452 kb
Host smart-f67faed0-a38c-4655-b667-97e78a5605bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425595784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr_
outstanding.425595784
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.4080768
Short name T1137
Test name
Test status
Simulation time 33558501 ps
CPU time 1.71 seconds
Started Jun 13 12:59:31 PM PDT 24
Finished Jun 13 12:59:35 PM PDT 24
Peak memory 199924 kb
Host smart-b1920d0d-7bd3-4e86-8bd1-a09b2835b140
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.4080768
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.785301957
Short name T94
Test name
Test status
Simulation time 283495566 ps
CPU time 1.37 seconds
Started Jun 13 12:59:37 PM PDT 24
Finished Jun 13 12:59:40 PM PDT 24
Peak memory 199212 kb
Host smart-d2c06658-2f82-4da4-b3a6-e9b4097ffb19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785301957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.785301957
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3628080972
Short name T1145
Test name
Test status
Simulation time 26863979 ps
CPU time 0.86 seconds
Started Jun 13 12:59:37 PM PDT 24
Finished Jun 13 12:59:40 PM PDT 24
Peak memory 199812 kb
Host smart-64022015-df39-42a9-99cf-01604dd9d68f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628080972 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.3628080972
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.243145523
Short name T1169
Test name
Test status
Simulation time 13743574 ps
CPU time 0.59 seconds
Started Jun 13 12:59:31 PM PDT 24
Finished Jun 13 12:59:33 PM PDT 24
Peak memory 195296 kb
Host smart-814e8244-034d-4b8a-a9b7-0989152138af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243145523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.243145523
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.1368489682
Short name T1215
Test name
Test status
Simulation time 46036328 ps
CPU time 0.61 seconds
Started Jun 13 12:59:36 PM PDT 24
Finished Jun 13 12:59:38 PM PDT 24
Peak memory 194320 kb
Host smart-8c01587f-8cec-42fa-a661-d3a4290ebc62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368489682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.1368489682
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1275908215
Short name T80
Test name
Test status
Simulation time 14900760 ps
CPU time 0.62 seconds
Started Jun 13 12:59:29 PM PDT 24
Finished Jun 13 12:59:31 PM PDT 24
Peak memory 195484 kb
Host smart-bb807e65-34ac-444d-b8bd-b40f2c79df15
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275908215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.1275908215
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.588507019
Short name T1130
Test name
Test status
Simulation time 794379536 ps
CPU time 2.13 seconds
Started Jun 13 12:59:36 PM PDT 24
Finished Jun 13 12:59:39 PM PDT 24
Peak memory 199960 kb
Host smart-4d43e4c6-df9f-41e7-9a7f-f16fef61149b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588507019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.588507019
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1481004665
Short name T1155
Test name
Test status
Simulation time 191478326 ps
CPU time 0.97 seconds
Started Jun 13 12:59:31 PM PDT 24
Finished Jun 13 12:59:33 PM PDT 24
Peak memory 198896 kb
Host smart-64f6c80c-abd1-40f6-a432-24cb8bd009b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481004665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.1481004665
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_fifo_full.1999512155
Short name T712
Test name
Test status
Simulation time 21338140391 ps
CPU time 18.04 seconds
Started Jun 13 01:00:35 PM PDT 24
Finished Jun 13 01:00:54 PM PDT 24
Peak memory 200804 kb
Host smart-5d169064-cd27-46a4-bc63-f5151aeae5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999512155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.1999512155
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.172680059
Short name T271
Test name
Test status
Simulation time 40261212521 ps
CPU time 13.74 seconds
Started Jun 13 01:00:37 PM PDT 24
Finished Jun 13 01:00:52 PM PDT 24
Peak memory 200484 kb
Host smart-b6202722-6c9e-4ef9-a053-0314a07b6d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172680059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.172680059
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.2435667530
Short name T518
Test name
Test status
Simulation time 10300794715 ps
CPU time 9.66 seconds
Started Jun 13 01:00:36 PM PDT 24
Finished Jun 13 01:00:47 PM PDT 24
Peak memory 198072 kb
Host smart-ec5823a6-cc6a-4738-90e2-989f1f825fd0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435667530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.2435667530
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.295750007
Short name T468
Test name
Test status
Simulation time 221766449104 ps
CPU time 169.4 seconds
Started Jun 13 01:00:33 PM PDT 24
Finished Jun 13 01:03:22 PM PDT 24
Peak memory 200796 kb
Host smart-c9e21179-3208-4c73-80a4-7695cb9794ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=295750007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.295750007
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.1141550909
Short name T970
Test name
Test status
Simulation time 4142896106 ps
CPU time 5.15 seconds
Started Jun 13 01:00:31 PM PDT 24
Finished Jun 13 01:00:36 PM PDT 24
Peak memory 200636 kb
Host smart-5334ebe3-f34b-4c0f-98ee-44485c56b872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141550909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.1141550909
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.302137058
Short name T590
Test name
Test status
Simulation time 5285989517 ps
CPU time 8.07 seconds
Started Jun 13 01:00:32 PM PDT 24
Finished Jun 13 01:00:40 PM PDT 24
Peak memory 198420 kb
Host smart-b7a434ae-c2c1-4034-9a00-ea4578684200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302137058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.302137058
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.3524108530
Short name T333
Test name
Test status
Simulation time 12087713281 ps
CPU time 132.74 seconds
Started Jun 13 01:00:38 PM PDT 24
Finished Jun 13 01:02:51 PM PDT 24
Peak memory 200800 kb
Host smart-8cfaff06-5116-4181-a6ce-9bddd3f0c632
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3524108530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.3524108530
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.2199523155
Short name T524
Test name
Test status
Simulation time 6933568761 ps
CPU time 30.86 seconds
Started Jun 13 01:00:37 PM PDT 24
Finished Jun 13 01:01:09 PM PDT 24
Peak memory 200036 kb
Host smart-83fc67ec-1152-4307-8769-87f0fc71b453
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2199523155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.2199523155
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.2806464348
Short name T1035
Test name
Test status
Simulation time 36878825702 ps
CPU time 17.27 seconds
Started Jun 13 01:00:28 PM PDT 24
Finished Jun 13 01:00:46 PM PDT 24
Peak memory 200748 kb
Host smart-fccd6d15-200b-429f-8afb-50b47b36a101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806464348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.2806464348
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.3733412651
Short name T1054
Test name
Test status
Simulation time 4021195172 ps
CPU time 6.95 seconds
Started Jun 13 01:00:27 PM PDT 24
Finished Jun 13 01:00:35 PM PDT 24
Peak memory 196760 kb
Host smart-6ae14ef4-6e4f-47c5-8487-a5ffc2cf8f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733412651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.3733412651
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.1042548073
Short name T410
Test name
Test status
Simulation time 143370564 ps
CPU time 0.75 seconds
Started Jun 13 01:00:26 PM PDT 24
Finished Jun 13 01:00:27 PM PDT 24
Peak memory 197796 kb
Host smart-dd71441f-3d6e-460a-80ea-ef03ebceb433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042548073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.1042548073
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.2299142426
Short name T404
Test name
Test status
Simulation time 4219614506 ps
CPU time 1.62 seconds
Started Jun 13 01:00:28 PM PDT 24
Finished Jun 13 01:00:30 PM PDT 24
Peak memory 200440 kb
Host smart-0691997f-49bb-4c2a-97dc-92344da9a6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299142426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.2299142426
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_alert_test.2864583032
Short name T820
Test name
Test status
Simulation time 12246742 ps
CPU time 0.55 seconds
Started Jun 13 01:00:39 PM PDT 24
Finished Jun 13 01:00:40 PM PDT 24
Peak memory 195548 kb
Host smart-93b9ba3d-235f-4e4b-ad6b-b885ba63608a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864583032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.2864583032
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.3073746348
Short name T248
Test name
Test status
Simulation time 254437173911 ps
CPU time 75.62 seconds
Started Jun 13 01:00:35 PM PDT 24
Finished Jun 13 01:01:51 PM PDT 24
Peak memory 200788 kb
Host smart-c80a8a05-2fd1-45da-9394-04038b6973f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073746348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.3073746348
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.938021289
Short name T1072
Test name
Test status
Simulation time 206625102700 ps
CPU time 103.59 seconds
Started Jun 13 01:00:38 PM PDT 24
Finished Jun 13 01:02:22 PM PDT 24
Peak memory 200760 kb
Host smart-8cc0f7f6-3c07-4f11-9ce1-4690e2f0dbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938021289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.938021289
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.3451359908
Short name T765
Test name
Test status
Simulation time 30447381857 ps
CPU time 23.62 seconds
Started Jun 13 01:00:36 PM PDT 24
Finished Jun 13 01:01:00 PM PDT 24
Peak memory 200620 kb
Host smart-2a571229-3d99-49d4-8016-51d3b545602b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451359908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.3451359908
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.2000145414
Short name T779
Test name
Test status
Simulation time 10209734846 ps
CPU time 17.69 seconds
Started Jun 13 01:00:43 PM PDT 24
Finished Jun 13 01:01:01 PM PDT 24
Peak memory 200792 kb
Host smart-ee19f9bd-c53a-41c0-8a2c-60862cef58b4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000145414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.2000145414
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_loopback.873768377
Short name T1036
Test name
Test status
Simulation time 2425669700 ps
CPU time 1.28 seconds
Started Jun 13 01:00:38 PM PDT 24
Finished Jun 13 01:00:40 PM PDT 24
Peak memory 196556 kb
Host smart-31a6f670-c1cf-46dd-b3ae-03ed6775917a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873768377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.873768377
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_perf.3977915086
Short name T1042
Test name
Test status
Simulation time 11079870349 ps
CPU time 179.08 seconds
Started Jun 13 01:00:36 PM PDT 24
Finished Jun 13 01:03:36 PM PDT 24
Peak memory 200756 kb
Host smart-b3a0e53f-501c-4675-a95b-f2bf1ff44851
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3977915086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.3977915086
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.4150247125
Short name T486
Test name
Test status
Simulation time 2956799952 ps
CPU time 13.51 seconds
Started Jun 13 01:00:39 PM PDT 24
Finished Jun 13 01:00:53 PM PDT 24
Peak memory 198988 kb
Host smart-d01672ec-f219-4f71-8d70-7b958a40dfa4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4150247125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.4150247125
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.1100851562
Short name T135
Test name
Test status
Simulation time 176173086941 ps
CPU time 56.17 seconds
Started Jun 13 01:00:36 PM PDT 24
Finished Jun 13 01:01:33 PM PDT 24
Peak memory 200820 kb
Host smart-f4f987db-7151-4858-adf8-2828f6d4e9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100851562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.1100851562
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.179028166
Short name T268
Test name
Test status
Simulation time 42837836879 ps
CPU time 13.27 seconds
Started Jun 13 01:00:36 PM PDT 24
Finished Jun 13 01:00:50 PM PDT 24
Peak memory 196732 kb
Host smart-2ad2087f-5777-4d8c-8177-9c06f60f507d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179028166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.179028166
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.1287823446
Short name T23
Test name
Test status
Simulation time 138056054 ps
CPU time 0.76 seconds
Started Jun 13 01:00:36 PM PDT 24
Finished Jun 13 01:00:37 PM PDT 24
Peak memory 218896 kb
Host smart-d3926544-1fab-4ac3-81a5-7ba5c7be46a6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287823446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.1287823446
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.2149942440
Short name T315
Test name
Test status
Simulation time 905249317 ps
CPU time 2.17 seconds
Started Jun 13 01:00:36 PM PDT 24
Finished Jun 13 01:00:39 PM PDT 24
Peak memory 200116 kb
Host smart-939e519f-96d3-4dc1-9812-ee070eb1406d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149942440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.2149942440
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.264360307
Short name T906
Test name
Test status
Simulation time 26074056708 ps
CPU time 107.84 seconds
Started Jun 13 01:00:41 PM PDT 24
Finished Jun 13 01:02:29 PM PDT 24
Peak memory 217060 kb
Host smart-77833fad-f258-4b8c-86ec-f19394adcf6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264360307 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.264360307
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.2662751907
Short name T588
Test name
Test status
Simulation time 1324427650 ps
CPU time 2.2 seconds
Started Jun 13 01:00:37 PM PDT 24
Finished Jun 13 01:00:40 PM PDT 24
Peak memory 199564 kb
Host smart-8938bb8d-d8da-4d89-9a8d-b800dfc1206d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662751907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.2662751907
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.1984467771
Short name T727
Test name
Test status
Simulation time 39465349665 ps
CPU time 13.09 seconds
Started Jun 13 01:00:39 PM PDT 24
Finished Jun 13 01:00:53 PM PDT 24
Peak memory 198756 kb
Host smart-fee14b25-cde2-4860-8b52-b159a673ed45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984467771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.1984467771
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.451528839
Short name T363
Test name
Test status
Simulation time 35060448 ps
CPU time 0.58 seconds
Started Jun 13 01:01:01 PM PDT 24
Finished Jun 13 01:01:02 PM PDT 24
Peak memory 196056 kb
Host smart-e33d926c-0970-4a87-97c6-503f937636bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451528839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.451528839
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.987309058
Short name T903
Test name
Test status
Simulation time 153837885399 ps
CPU time 176.51 seconds
Started Jun 13 01:00:55 PM PDT 24
Finished Jun 13 01:03:54 PM PDT 24
Peak memory 200768 kb
Host smart-c948f37f-59aa-444e-a8a2-476172a07dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987309058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.987309058
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.2176965087
Short name T871
Test name
Test status
Simulation time 108259145981 ps
CPU time 96.84 seconds
Started Jun 13 01:00:56 PM PDT 24
Finished Jun 13 01:02:35 PM PDT 24
Peak memory 200596 kb
Host smart-9027c9c8-3ec1-407f-bfad-049353fba34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176965087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.2176965087
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.632820826
Short name T722
Test name
Test status
Simulation time 65664369234 ps
CPU time 30.64 seconds
Started Jun 13 01:00:55 PM PDT 24
Finished Jun 13 01:01:28 PM PDT 24
Peak memory 200728 kb
Host smart-06c33214-79eb-401f-a9be-823b1890b24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632820826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.632820826
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.3723510948
Short name T47
Test name
Test status
Simulation time 50227872288 ps
CPU time 11.12 seconds
Started Jun 13 01:00:59 PM PDT 24
Finished Jun 13 01:01:11 PM PDT 24
Peak memory 200580 kb
Host smart-9a8333b3-04c7-4829-8b04-b15af056d98b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723510948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.3723510948
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.417311886
Short name T730
Test name
Test status
Simulation time 113568115628 ps
CPU time 256.18 seconds
Started Jun 13 01:01:04 PM PDT 24
Finished Jun 13 01:05:21 PM PDT 24
Peak memory 200788 kb
Host smart-ef31b4b7-27ba-4c83-aa64-996660bf71f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=417311886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.417311886
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.3907801498
Short name T645
Test name
Test status
Simulation time 10173889419 ps
CPU time 9.32 seconds
Started Jun 13 01:00:54 PM PDT 24
Finished Jun 13 01:01:05 PM PDT 24
Peak memory 200428 kb
Host smart-f5f7bbe1-4d79-46ac-baf5-e847e0b2e8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907801498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.3907801498
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_perf.1836691773
Short name T370
Test name
Test status
Simulation time 11429047874 ps
CPU time 187.47 seconds
Started Jun 13 01:00:58 PM PDT 24
Finished Jun 13 01:04:06 PM PDT 24
Peak memory 200712 kb
Host smart-d91ad7b1-483c-4540-908f-1a8d4960bc40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1836691773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.1836691773
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.1101195158
Short name T793
Test name
Test status
Simulation time 5676568659 ps
CPU time 45.17 seconds
Started Jun 13 01:01:06 PM PDT 24
Finished Jun 13 01:01:52 PM PDT 24
Peak memory 198848 kb
Host smart-0ba30826-f358-4261-846f-75f7250c0ef7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1101195158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.1101195158
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.723445078
Short name T433
Test name
Test status
Simulation time 140986516767 ps
CPU time 111.44 seconds
Started Jun 13 01:00:55 PM PDT 24
Finished Jun 13 01:02:49 PM PDT 24
Peak memory 200604 kb
Host smart-9dcd7b71-9826-4c2c-92ab-a38c74d4fead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723445078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.723445078
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.3321692544
Short name T984
Test name
Test status
Simulation time 3496985315 ps
CPU time 2.05 seconds
Started Jun 13 01:01:05 PM PDT 24
Finished Jun 13 01:01:08 PM PDT 24
Peak memory 196776 kb
Host smart-fdc05c92-029a-490d-afc7-390fa0fb359a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321692544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.3321692544
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.4201775519
Short name T457
Test name
Test status
Simulation time 5369041195 ps
CPU time 15.09 seconds
Started Jun 13 01:00:54 PM PDT 24
Finished Jun 13 01:01:11 PM PDT 24
Peak memory 200220 kb
Host smart-1f10fd0a-1e54-420d-9f66-2459fedd03de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201775519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.4201775519
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.3002159096
Short name T929
Test name
Test status
Simulation time 28571183130 ps
CPU time 51.08 seconds
Started Jun 13 01:00:59 PM PDT 24
Finished Jun 13 01:01:51 PM PDT 24
Peak memory 200820 kb
Host smart-11242fed-3cc0-47c4-8806-887260aee055
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002159096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.3002159096
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.2242367624
Short name T9
Test name
Test status
Simulation time 19164309022 ps
CPU time 167.57 seconds
Started Jun 13 01:01:00 PM PDT 24
Finished Jun 13 01:03:48 PM PDT 24
Peak memory 217032 kb
Host smart-bde68ace-69e9-4318-8857-03a673001106
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242367624 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.2242367624
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.1891390916
Short name T618
Test name
Test status
Simulation time 910565732 ps
CPU time 3.48 seconds
Started Jun 13 01:00:54 PM PDT 24
Finished Jun 13 01:01:00 PM PDT 24
Peak memory 199100 kb
Host smart-274b5a26-6a64-4d70-b3e8-a0bd32be1202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891390916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.1891390916
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.3859666965
Short name T539
Test name
Test status
Simulation time 11147563459 ps
CPU time 3.24 seconds
Started Jun 13 01:00:58 PM PDT 24
Finished Jun 13 01:01:02 PM PDT 24
Peak memory 200736 kb
Host smart-ca060615-22b0-45b0-9ced-a19c2d18b550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859666965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.3859666965
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.4195069656
Short name T877
Test name
Test status
Simulation time 144972207746 ps
CPU time 219.75 seconds
Started Jun 13 01:48:11 PM PDT 24
Finished Jun 13 01:51:51 PM PDT 24
Peak memory 200820 kb
Host smart-56ba51da-7406-4550-94cd-cbcf4afdd980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195069656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.4195069656
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.2385088466
Short name T1062
Test name
Test status
Simulation time 27443156789 ps
CPU time 44.87 seconds
Started Jun 13 01:43:31 PM PDT 24
Finished Jun 13 01:44:17 PM PDT 24
Peak memory 200732 kb
Host smart-a4330e3d-f255-40e9-9ef7-e7d0ff78a16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385088466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.2385088466
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.2884531609
Short name T864
Test name
Test status
Simulation time 9199479031 ps
CPU time 13.99 seconds
Started Jun 13 01:46:18 PM PDT 24
Finished Jun 13 01:46:33 PM PDT 24
Peak memory 200740 kb
Host smart-8e00e0e0-29de-4b7f-9c78-9b741e918963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884531609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.2884531609
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.2619440428
Short name T189
Test name
Test status
Simulation time 92620455680 ps
CPU time 242.34 seconds
Started Jun 13 01:38:37 PM PDT 24
Finished Jun 13 01:42:40 PM PDT 24
Peak memory 200808 kb
Host smart-e3280655-9d8f-44d1-8150-4f24ab45c394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619440428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.2619440428
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.3852955751
Short name T126
Test name
Test status
Simulation time 26108908466 ps
CPU time 63.73 seconds
Started Jun 13 02:08:46 PM PDT 24
Finished Jun 13 02:09:50 PM PDT 24
Peak memory 201000 kb
Host smart-127107a3-f6b0-4832-a04d-488ad1cae453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852955751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.3852955751
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.1995416623
Short name T492
Test name
Test status
Simulation time 134066581570 ps
CPU time 57.11 seconds
Started Jun 13 01:50:39 PM PDT 24
Finished Jun 13 01:51:39 PM PDT 24
Peak memory 200736 kb
Host smart-81478810-9f5b-48c2-bc10-ffcfb7839576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995416623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.1995416623
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.3187801206
Short name T633
Test name
Test status
Simulation time 59018740124 ps
CPU time 23.22 seconds
Started Jun 13 02:33:10 PM PDT 24
Finished Jun 13 02:33:35 PM PDT 24
Peak memory 200704 kb
Host smart-13e71efb-2cfe-41eb-b55e-48b4329e2f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187801206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.3187801206
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.713113064
Short name T1020
Test name
Test status
Simulation time 14919874 ps
CPU time 0.54 seconds
Started Jun 13 01:01:03 PM PDT 24
Finished Jun 13 01:01:04 PM PDT 24
Peak memory 195520 kb
Host smart-82758d9e-fd74-4e08-80ad-e452b15b1f12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713113064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.713113064
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.838594387
Short name T64
Test name
Test status
Simulation time 152897970873 ps
CPU time 62.38 seconds
Started Jun 13 01:00:59 PM PDT 24
Finished Jun 13 01:02:02 PM PDT 24
Peak memory 200724 kb
Host smart-98e93917-e562-461e-a144-d0f77afdf5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838594387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.838594387
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.701251291
Short name T558
Test name
Test status
Simulation time 74255502502 ps
CPU time 199.94 seconds
Started Jun 13 01:01:01 PM PDT 24
Finished Jun 13 01:04:22 PM PDT 24
Peak memory 200820 kb
Host smart-fb2e2b07-3ba8-4967-bf3b-4b154441b6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701251291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.701251291
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.1907367600
Short name T338
Test name
Test status
Simulation time 71019812446 ps
CPU time 111.63 seconds
Started Jun 13 01:01:01 PM PDT 24
Finished Jun 13 01:02:54 PM PDT 24
Peak memory 200760 kb
Host smart-f92520b3-6c20-4dbe-98fe-c60d7115cbe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907367600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.1907367600
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.1068495700
Short name T776
Test name
Test status
Simulation time 51610559237 ps
CPU time 30.97 seconds
Started Jun 13 01:01:03 PM PDT 24
Finished Jun 13 01:01:35 PM PDT 24
Peak memory 200804 kb
Host smart-ec6f9b18-e25f-4915-bef0-5daeab211d71
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068495700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.1068495700
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.792602541
Short name T889
Test name
Test status
Simulation time 98591447403 ps
CPU time 752.8 seconds
Started Jun 13 01:01:00 PM PDT 24
Finished Jun 13 01:13:33 PM PDT 24
Peak memory 200620 kb
Host smart-59f8f05f-dbcc-4739-a9ef-a9513ba82f60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=792602541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.792602541
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.308792296
Short name T1006
Test name
Test status
Simulation time 5638171821 ps
CPU time 5.63 seconds
Started Jun 13 01:01:02 PM PDT 24
Finished Jun 13 01:01:08 PM PDT 24
Peak memory 200584 kb
Host smart-48cc6bf9-b90e-4cf7-aec2-9bc18b41b11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308792296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.308792296
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_perf.1069325917
Short name T995
Test name
Test status
Simulation time 2694270073 ps
CPU time 173.3 seconds
Started Jun 13 01:00:59 PM PDT 24
Finished Jun 13 01:03:53 PM PDT 24
Peak memory 200696 kb
Host smart-341ad8fb-ae04-411a-8c72-6ac8f6dde8b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1069325917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.1069325917
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.4212712125
Short name T737
Test name
Test status
Simulation time 7025086152 ps
CPU time 35.9 seconds
Started Jun 13 01:00:59 PM PDT 24
Finished Jun 13 01:01:35 PM PDT 24
Peak memory 198996 kb
Host smart-5c2c09f9-98c8-4f1e-9750-24f6b7837f15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4212712125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.4212712125
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.3186355243
Short name T1081
Test name
Test status
Simulation time 87138128068 ps
CPU time 65.08 seconds
Started Jun 13 01:01:04 PM PDT 24
Finished Jun 13 01:02:10 PM PDT 24
Peak memory 200736 kb
Host smart-f21d434d-5705-401f-97b6-096d7d15279e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186355243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.3186355243
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.1205765493
Short name T284
Test name
Test status
Simulation time 47082976015 ps
CPU time 66.29 seconds
Started Jun 13 01:00:58 PM PDT 24
Finished Jun 13 01:02:05 PM PDT 24
Peak memory 196584 kb
Host smart-1f62648a-5ab2-4bd3-b4a8-451a09f875a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205765493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.1205765493
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.205671917
Short name T306
Test name
Test status
Simulation time 891036137 ps
CPU time 3.49 seconds
Started Jun 13 01:00:59 PM PDT 24
Finished Jun 13 01:01:03 PM PDT 24
Peak memory 200624 kb
Host smart-2be34f99-0d85-48ff-80c8-7427959ce507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205671917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.205671917
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.3603231822
Short name T918
Test name
Test status
Simulation time 34589246247 ps
CPU time 193.01 seconds
Started Jun 13 01:00:59 PM PDT 24
Finished Jun 13 01:04:12 PM PDT 24
Peak memory 208992 kb
Host smart-b7df5573-7367-4690-9b3b-002b35143a03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603231822 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.3603231822
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.2150523036
Short name T535
Test name
Test status
Simulation time 5973537312 ps
CPU time 12.07 seconds
Started Jun 13 01:01:01 PM PDT 24
Finished Jun 13 01:01:14 PM PDT 24
Peak memory 200608 kb
Host smart-0d974790-0928-4645-a948-4980d0091068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150523036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.2150523036
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.4151518133
Short name T503
Test name
Test status
Simulation time 73586328317 ps
CPU time 57 seconds
Started Jun 13 01:01:01 PM PDT 24
Finished Jun 13 01:01:59 PM PDT 24
Peak memory 200788 kb
Host smart-ec355f04-096e-4600-8857-d56200536f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151518133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.4151518133
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.1988918282
Short name T679
Test name
Test status
Simulation time 101413510312 ps
CPU time 153.44 seconds
Started Jun 13 01:30:39 PM PDT 24
Finished Jun 13 01:33:13 PM PDT 24
Peak memory 200836 kb
Host smart-7cde86ae-16e5-4910-a540-8aba3cbb2127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988918282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1988918282
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.405439558
Short name T130
Test name
Test status
Simulation time 40582712425 ps
CPU time 66.14 seconds
Started Jun 13 02:41:53 PM PDT 24
Finished Jun 13 02:43:01 PM PDT 24
Peak memory 200848 kb
Host smart-3ce309ec-3878-4828-99c4-321bad44adef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405439558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.405439558
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.1976167413
Short name T781
Test name
Test status
Simulation time 99103442890 ps
CPU time 172.19 seconds
Started Jun 13 01:02:48 PM PDT 24
Finished Jun 13 01:05:41 PM PDT 24
Peak memory 200764 kb
Host smart-036f3f4c-1847-425e-b538-25816b74178f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976167413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.1976167413
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.3419309476
Short name T191
Test name
Test status
Simulation time 96613790052 ps
CPU time 80.04 seconds
Started Jun 13 01:20:05 PM PDT 24
Finished Jun 13 01:21:26 PM PDT 24
Peak memory 200852 kb
Host smart-a2b9fde1-6e0c-4027-9141-7389dffaed42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419309476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.3419309476
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.732678786
Short name T185
Test name
Test status
Simulation time 34993936373 ps
CPU time 56.47 seconds
Started Jun 13 01:06:27 PM PDT 24
Finished Jun 13 01:07:24 PM PDT 24
Peak memory 200748 kb
Host smart-c1ae0b5e-dddd-4da7-9e72-3969e53e8240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732678786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.732678786
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.1221991582
Short name T912
Test name
Test status
Simulation time 41692640980 ps
CPU time 67.33 seconds
Started Jun 13 01:18:30 PM PDT 24
Finished Jun 13 01:19:38 PM PDT 24
Peak memory 200752 kb
Host smart-c5deeedb-f0d3-4d2a-b71e-feec7fd7b66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221991582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.1221991582
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.1141164302
Short name T731
Test name
Test status
Simulation time 175904628955 ps
CPU time 68.72 seconds
Started Jun 13 02:30:34 PM PDT 24
Finished Jun 13 02:31:43 PM PDT 24
Peak memory 200724 kb
Host smart-62f7c6a6-b450-4973-b7ce-cba8e26a43ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141164302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.1141164302
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.2397354616
Short name T567
Test name
Test status
Simulation time 26415354362 ps
CPU time 40.5 seconds
Started Jun 13 02:22:33 PM PDT 24
Finished Jun 13 02:23:14 PM PDT 24
Peak memory 200564 kb
Host smart-42def6a9-ea37-46b9-9549-1b80f00897b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397354616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.2397354616
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.1022407270
Short name T753
Test name
Test status
Simulation time 91053663874 ps
CPU time 61.13 seconds
Started Jun 13 01:48:05 PM PDT 24
Finished Jun 13 01:49:06 PM PDT 24
Peak memory 200852 kb
Host smart-82efb8eb-64ba-4e3b-b67c-1ddb0da359c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022407270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.1022407270
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.683059999
Short name T517
Test name
Test status
Simulation time 156428619008 ps
CPU time 121.31 seconds
Started Jun 13 02:14:15 PM PDT 24
Finished Jun 13 02:16:17 PM PDT 24
Peak memory 200828 kb
Host smart-b85f815c-cfc5-4029-a342-f8cc1882d16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683059999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.683059999
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.3008716246
Short name T817
Test name
Test status
Simulation time 18666100 ps
CPU time 0.55 seconds
Started Jun 13 01:01:03 PM PDT 24
Finished Jun 13 01:01:04 PM PDT 24
Peak memory 195508 kb
Host smart-4e496c3f-fd7f-4e89-a128-3ecc6d9b40b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008716246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.3008716246
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.1278693256
Short name T152
Test name
Test status
Simulation time 240274992973 ps
CPU time 213.58 seconds
Started Jun 13 01:01:00 PM PDT 24
Finished Jun 13 01:04:34 PM PDT 24
Peak memory 200716 kb
Host smart-6a54e082-3a0d-421a-9d27-7794748222ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278693256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.1278693256
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.3579448356
Short name T275
Test name
Test status
Simulation time 44223923493 ps
CPU time 53.13 seconds
Started Jun 13 01:01:05 PM PDT 24
Finished Jun 13 01:01:59 PM PDT 24
Peak memory 200800 kb
Host smart-da6eff3e-e006-410d-a167-6c112d0029e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579448356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.3579448356
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.1425916453
Short name T127
Test name
Test status
Simulation time 175929792761 ps
CPU time 73.31 seconds
Started Jun 13 01:01:01 PM PDT 24
Finished Jun 13 01:02:15 PM PDT 24
Peak memory 200768 kb
Host smart-fb7ba265-a08e-4d4b-bfc7-9d9392500fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425916453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.1425916453
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.814316934
Short name T1055
Test name
Test status
Simulation time 22726575195 ps
CPU time 27.05 seconds
Started Jun 13 01:01:01 PM PDT 24
Finished Jun 13 01:01:29 PM PDT 24
Peak memory 200680 kb
Host smart-9c3c753e-d716-4384-ada8-725dee286e0b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814316934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.814316934
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.1821630380
Short name T734
Test name
Test status
Simulation time 43591364264 ps
CPU time 182.92 seconds
Started Jun 13 01:01:05 PM PDT 24
Finished Jun 13 01:04:10 PM PDT 24
Peak memory 200760 kb
Host smart-2700c8ed-3279-4f8f-80b6-fb13ce09905b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1821630380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.1821630380
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.1824969069
Short name T564
Test name
Test status
Simulation time 10261144632 ps
CPU time 21.05 seconds
Started Jun 13 01:01:01 PM PDT 24
Finished Jun 13 01:01:23 PM PDT 24
Peak memory 200596 kb
Host smart-ad5578dc-19e6-4e72-9bf5-651e2e538ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824969069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.1824969069
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_perf.2632456154
Short name T262
Test name
Test status
Simulation time 3969657724 ps
CPU time 57.67 seconds
Started Jun 13 01:01:02 PM PDT 24
Finished Jun 13 01:02:00 PM PDT 24
Peak memory 200816 kb
Host smart-9a7ccc72-e483-4e6f-a90a-be322de99ee7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2632456154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.2632456154
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.1769580352
Short name T910
Test name
Test status
Simulation time 5467186526 ps
CPU time 52.2 seconds
Started Jun 13 01:01:03 PM PDT 24
Finished Jun 13 01:01:56 PM PDT 24
Peak memory 200228 kb
Host smart-21d6f996-5ce3-455a-a2ac-fc9c30c2f1a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1769580352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.1769580352
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.2860913097
Short name T1032
Test name
Test status
Simulation time 206642633033 ps
CPU time 359.51 seconds
Started Jun 13 01:00:59 PM PDT 24
Finished Jun 13 01:06:59 PM PDT 24
Peak memory 200776 kb
Host smart-5f9d2823-81ac-48f3-922c-9e4e996e7045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860913097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.2860913097
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.3327803018
Short name T836
Test name
Test status
Simulation time 3593180806 ps
CPU time 3.53 seconds
Started Jun 13 01:01:04 PM PDT 24
Finished Jun 13 01:01:09 PM PDT 24
Peak memory 196832 kb
Host smart-30268582-f720-4e58-aa38-b8bc0135941c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327803018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.3327803018
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.1580841071
Short name T494
Test name
Test status
Simulation time 736384207 ps
CPU time 2.84 seconds
Started Jun 13 01:01:05 PM PDT 24
Finished Jun 13 01:01:09 PM PDT 24
Peak memory 199076 kb
Host smart-4f5d3f96-7b4c-491c-8b9e-065df8a1b6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580841071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.1580841071
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.700131139
Short name T568
Test name
Test status
Simulation time 7775228983 ps
CPU time 14.68 seconds
Started Jun 13 01:01:01 PM PDT 24
Finished Jun 13 01:01:17 PM PDT 24
Peak memory 200704 kb
Host smart-e8d1ce89-b546-4399-881d-01d0bb003a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700131139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.700131139
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.899683402
Short name T1078
Test name
Test status
Simulation time 26523872006 ps
CPU time 47.08 seconds
Started Jun 13 01:01:04 PM PDT 24
Finished Jun 13 01:01:51 PM PDT 24
Peak memory 200776 kb
Host smart-5c638516-a029-4093-a90a-71bfca67a668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899683402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.899683402
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.1547862989
Short name T1092
Test name
Test status
Simulation time 25879209203 ps
CPU time 125.6 seconds
Started Jun 13 02:12:59 PM PDT 24
Finished Jun 13 02:15:06 PM PDT 24
Peak memory 200836 kb
Host smart-354e6a9b-cbef-4f7a-a9e7-d7d599cd18a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547862989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.1547862989
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.431805669
Short name T62
Test name
Test status
Simulation time 8189864670 ps
CPU time 15.4 seconds
Started Jun 13 01:54:32 PM PDT 24
Finished Jun 13 01:54:54 PM PDT 24
Peak memory 200784 kb
Host smart-8234765c-af34-4e35-929b-fd7e4d51ca06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431805669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.431805669
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.1688394139
Short name T1025
Test name
Test status
Simulation time 16298642250 ps
CPU time 27.52 seconds
Started Jun 13 01:24:38 PM PDT 24
Finished Jun 13 01:25:06 PM PDT 24
Peak memory 200800 kb
Host smart-0b9cfb59-40a6-4cf8-9772-b4dd0cd7a680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688394139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.1688394139
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.3301586293
Short name T392
Test name
Test status
Simulation time 41091064345 ps
CPU time 26.79 seconds
Started Jun 13 01:31:48 PM PDT 24
Finished Jun 13 01:32:15 PM PDT 24
Peak memory 200680 kb
Host smart-beb5d775-a6fd-4642-b5bc-03482ca09163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301586293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.3301586293
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.3761578814
Short name T431
Test name
Test status
Simulation time 33182349645 ps
CPU time 59.43 seconds
Started Jun 13 01:29:46 PM PDT 24
Finished Jun 13 01:30:46 PM PDT 24
Peak memory 200752 kb
Host smart-35acd797-e2f0-429f-add0-6d548337d811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761578814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.3761578814
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.2464957607
Short name T782
Test name
Test status
Simulation time 191758197768 ps
CPU time 31.63 seconds
Started Jun 13 02:08:00 PM PDT 24
Finished Jun 13 02:08:34 PM PDT 24
Peak memory 200792 kb
Host smart-72e7df89-5e0a-449b-ae08-bf71991f216e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464957607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.2464957607
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.340877406
Short name T856
Test name
Test status
Simulation time 162360287576 ps
CPU time 26.84 seconds
Started Jun 13 01:16:14 PM PDT 24
Finished Jun 13 01:16:41 PM PDT 24
Peak memory 200776 kb
Host smart-dc52a6d4-48b4-4ed8-8a8f-e1d0827f4c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340877406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.340877406
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.2354820830
Short name T1096
Test name
Test status
Simulation time 110110972575 ps
CPU time 46.36 seconds
Started Jun 13 01:02:53 PM PDT 24
Finished Jun 13 01:03:40 PM PDT 24
Peak memory 200684 kb
Host smart-19f08799-1db0-4c8e-acfb-e7db2d78d7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354820830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.2354820830
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.1313266919
Short name T192
Test name
Test status
Simulation time 12114457321 ps
CPU time 18.45 seconds
Started Jun 13 02:02:59 PM PDT 24
Finished Jun 13 02:03:19 PM PDT 24
Peak memory 200840 kb
Host smart-46cf0908-0d6b-4df8-b65a-23bd2391d44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313266919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.1313266919
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.3570694962
Short name T706
Test name
Test status
Simulation time 57024859 ps
CPU time 0.54 seconds
Started Jun 13 01:01:06 PM PDT 24
Finished Jun 13 01:01:08 PM PDT 24
Peak memory 196076 kb
Host smart-9c984cf0-e326-448c-838c-e2e96a75b8b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570694962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.3570694962
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.527947087
Short name T513
Test name
Test status
Simulation time 139378836609 ps
CPU time 224.86 seconds
Started Jun 13 01:01:02 PM PDT 24
Finished Jun 13 01:04:47 PM PDT 24
Peak memory 200728 kb
Host smart-3f2ecf43-a86f-4356-bd1c-f77555da853a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527947087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.527947087
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.488714767
Short name T383
Test name
Test status
Simulation time 36547383207 ps
CPU time 31.81 seconds
Started Jun 13 01:01:04 PM PDT 24
Finished Jun 13 01:01:36 PM PDT 24
Peak memory 200692 kb
Host smart-0e96adf6-36a6-4f2a-8918-8ec7f6d96089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488714767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.488714767
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.2160683762
Short name T230
Test name
Test status
Simulation time 33873108326 ps
CPU time 13.35 seconds
Started Jun 13 01:01:04 PM PDT 24
Finished Jun 13 01:01:19 PM PDT 24
Peak memory 200712 kb
Host smart-9a10bc37-f10b-4c22-ad72-e273d8103ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160683762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.2160683762
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.1810373063
Short name T375
Test name
Test status
Simulation time 9254635470 ps
CPU time 14.54 seconds
Started Jun 13 01:01:01 PM PDT 24
Finished Jun 13 01:01:17 PM PDT 24
Peak memory 200388 kb
Host smart-f513c7ae-560f-4d0a-93b6-a80bb7efac02
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810373063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.1810373063
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.2792307193
Short name T260
Test name
Test status
Simulation time 86535541546 ps
CPU time 135.76 seconds
Started Jun 13 01:01:06 PM PDT 24
Finished Jun 13 01:03:23 PM PDT 24
Peak memory 200744 kb
Host smart-2126df8c-580e-4d9f-8433-29468405c593
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2792307193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.2792307193
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.458630950
Short name T827
Test name
Test status
Simulation time 2447963623 ps
CPU time 2.17 seconds
Started Jun 13 01:01:08 PM PDT 24
Finished Jun 13 01:01:12 PM PDT 24
Peak memory 200144 kb
Host smart-74d928c0-95b8-4399-b09e-508ae3940f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458630950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.458630950
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_perf.3872060480
Short name T514
Test name
Test status
Simulation time 13063333061 ps
CPU time 300.15 seconds
Started Jun 13 01:01:09 PM PDT 24
Finished Jun 13 01:06:11 PM PDT 24
Peak memory 200784 kb
Host smart-160c41f3-a548-4661-b2ae-9313a9ef12d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3872060480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.3872060480
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.2924159922
Short name T759
Test name
Test status
Simulation time 4954174289 ps
CPU time 10.73 seconds
Started Jun 13 01:00:59 PM PDT 24
Finished Jun 13 01:01:10 PM PDT 24
Peak memory 199620 kb
Host smart-3541dae2-41ba-48e5-acdf-3b7dee5d37ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2924159922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.2924159922
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.737892406
Short name T376
Test name
Test status
Simulation time 31517790143 ps
CPU time 43.33 seconds
Started Jun 13 01:01:06 PM PDT 24
Finished Jun 13 01:01:50 PM PDT 24
Peak memory 200716 kb
Host smart-389dfb77-6a4a-45d9-83da-5452bed0d97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737892406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.737892406
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.2246526580
Short name T809
Test name
Test status
Simulation time 1614335384 ps
CPU time 1.27 seconds
Started Jun 13 01:01:02 PM PDT 24
Finished Jun 13 01:01:04 PM PDT 24
Peak memory 196164 kb
Host smart-1575c791-b910-4fcd-ae38-d20e72de7882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246526580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.2246526580
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.4252177971
Short name T464
Test name
Test status
Simulation time 869653662 ps
CPU time 2.5 seconds
Started Jun 13 01:01:00 PM PDT 24
Finished Jun 13 01:01:04 PM PDT 24
Peak memory 199656 kb
Host smart-5fdbe19e-f9e5-4f98-b446-deec2d718d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252177971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.4252177971
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.867676473
Short name T118
Test name
Test status
Simulation time 132286038157 ps
CPU time 294.73 seconds
Started Jun 13 01:01:05 PM PDT 24
Finished Jun 13 01:06:01 PM PDT 24
Peak memory 200792 kb
Host smart-51915f41-ffe5-4746-8d33-7fae084c2c91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867676473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.867676473
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.1373476194
Short name T937
Test name
Test status
Simulation time 72831873174 ps
CPU time 720.26 seconds
Started Jun 13 01:01:07 PM PDT 24
Finished Jun 13 01:13:09 PM PDT 24
Peak memory 212888 kb
Host smart-710f9c97-9ab7-458a-b6ee-6bb65c175007
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373476194 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.1373476194
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.3069353395
Short name T762
Test name
Test status
Simulation time 1965097606 ps
CPU time 2.79 seconds
Started Jun 13 01:01:03 PM PDT 24
Finished Jun 13 01:01:06 PM PDT 24
Peak memory 199268 kb
Host smart-56026f5b-b9bd-44c2-8ae3-a27d76a7c935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069353395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.3069353395
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.731378957
Short name T710
Test name
Test status
Simulation time 45856472378 ps
CPU time 69.11 seconds
Started Jun 13 01:00:59 PM PDT 24
Finished Jun 13 01:02:09 PM PDT 24
Peak memory 200784 kb
Host smart-971f7a86-0315-4d10-877a-468a42764386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731378957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.731378957
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.3406634636
Short name T745
Test name
Test status
Simulation time 114015405797 ps
CPU time 55.36 seconds
Started Jun 13 01:56:16 PM PDT 24
Finished Jun 13 01:57:13 PM PDT 24
Peak memory 200792 kb
Host smart-55990d5d-54d3-4847-9f2d-a0a6adb97006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406634636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.3406634636
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.1378406707
Short name T673
Test name
Test status
Simulation time 134751364611 ps
CPU time 121.84 seconds
Started Jun 13 02:11:30 PM PDT 24
Finished Jun 13 02:13:32 PM PDT 24
Peak memory 200820 kb
Host smart-75239800-1779-4979-b5e1-d41e4abf7775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378406707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.1378406707
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.1369020125
Short name T609
Test name
Test status
Simulation time 44764505773 ps
CPU time 44.03 seconds
Started Jun 13 01:06:56 PM PDT 24
Finished Jun 13 01:07:43 PM PDT 24
Peak memory 200636 kb
Host smart-bb82c08b-7531-4e6c-81de-224f8631612d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369020125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.1369020125
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.3290535568
Short name T440
Test name
Test status
Simulation time 98280691572 ps
CPU time 32.84 seconds
Started Jun 13 01:02:50 PM PDT 24
Finished Jun 13 01:03:24 PM PDT 24
Peak memory 200724 kb
Host smart-45bd27dc-79ea-4eb4-9928-5dd35acbdecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290535568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.3290535568
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.3474008794
Short name T653
Test name
Test status
Simulation time 26873337760 ps
CPU time 42.41 seconds
Started Jun 13 01:02:51 PM PDT 24
Finished Jun 13 01:03:34 PM PDT 24
Peak memory 200708 kb
Host smart-427c82ba-801c-4be9-9638-8a0d78e1b502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474008794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.3474008794
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.3575030612
Short name T172
Test name
Test status
Simulation time 128468732298 ps
CPU time 191.67 seconds
Started Jun 13 01:49:06 PM PDT 24
Finished Jun 13 01:52:20 PM PDT 24
Peak memory 200700 kb
Host smart-91cf2877-1427-42f8-b4e9-7349c6fb94b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575030612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.3575030612
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.3334644787
Short name T637
Test name
Test status
Simulation time 113479007857 ps
CPU time 50.95 seconds
Started Jun 13 01:56:55 PM PDT 24
Finished Jun 13 01:57:47 PM PDT 24
Peak memory 200756 kb
Host smart-5ea4a90b-e982-4583-a392-791d3ce4638c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334644787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.3334644787
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.855260898
Short name T6
Test name
Test status
Simulation time 119288937419 ps
CPU time 43.94 seconds
Started Jun 13 01:02:56 PM PDT 24
Finished Jun 13 01:03:41 PM PDT 24
Peak memory 200720 kb
Host smart-4e9e2577-a320-4825-b274-631bcc4d95d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855260898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.855260898
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.2167328044
Short name T337
Test name
Test status
Simulation time 44899544020 ps
CPU time 34.95 seconds
Started Jun 13 01:02:55 PM PDT 24
Finished Jun 13 01:03:31 PM PDT 24
Peak memory 200608 kb
Host smart-62ed113e-ea1b-46fa-b61c-eac9b521d683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167328044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.2167328044
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.2931842837
Short name T542
Test name
Test status
Simulation time 41214917157 ps
CPU time 35.65 seconds
Started Jun 13 01:04:09 PM PDT 24
Finished Jun 13 01:04:46 PM PDT 24
Peak memory 200828 kb
Host smart-efbb2b61-2272-4c92-92aa-99b62ba34e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931842837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.2931842837
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.956713332
Short name T691
Test name
Test status
Simulation time 23386641 ps
CPU time 0.54 seconds
Started Jun 13 01:01:06 PM PDT 24
Finished Jun 13 01:01:09 PM PDT 24
Peak memory 195548 kb
Host smart-ef0aaad2-38d8-4320-a6dd-81ec7d3a6509
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956713332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.956713332
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.3956213239
Short name T70
Test name
Test status
Simulation time 36003471510 ps
CPU time 18.29 seconds
Started Jun 13 01:01:07 PM PDT 24
Finished Jun 13 01:01:27 PM PDT 24
Peak memory 200768 kb
Host smart-52b1671a-4ed6-43e3-89fc-c166ffb51d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956213239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.3956213239
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.3467222894
Short name T69
Test name
Test status
Simulation time 191458343596 ps
CPU time 23.98 seconds
Started Jun 13 01:01:06 PM PDT 24
Finished Jun 13 01:01:32 PM PDT 24
Peak memory 200776 kb
Host smart-c7881841-8af6-4571-b4e1-073cf0c5f721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467222894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.3467222894
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.565782202
Short name T193
Test name
Test status
Simulation time 21315073445 ps
CPU time 33 seconds
Started Jun 13 01:01:06 PM PDT 24
Finished Jun 13 01:01:40 PM PDT 24
Peak memory 200688 kb
Host smart-154765c9-c9b3-48df-87f8-9089aa086d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565782202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.565782202
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.198522208
Short name T116
Test name
Test status
Simulation time 42922090108 ps
CPU time 75.52 seconds
Started Jun 13 01:01:07 PM PDT 24
Finished Jun 13 01:02:24 PM PDT 24
Peak memory 200344 kb
Host smart-78065501-93a9-467a-8b77-a8d4ed0e196b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198522208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.198522208
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.2979299502
Short name T541
Test name
Test status
Simulation time 186035941509 ps
CPU time 1070.86 seconds
Started Jun 13 01:01:09 PM PDT 24
Finished Jun 13 01:19:01 PM PDT 24
Peak memory 200760 kb
Host smart-7f00f75b-4b77-4d55-b42a-75aedec11dd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2979299502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.2979299502
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.3308621256
Short name T852
Test name
Test status
Simulation time 2102916873 ps
CPU time 4.06 seconds
Started Jun 13 01:01:05 PM PDT 24
Finished Jun 13 01:01:10 PM PDT 24
Peak memory 196656 kb
Host smart-73eeda67-6388-4c2d-a3b7-0db11d5c93e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308621256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.3308621256
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_perf.662797987
Short name T962
Test name
Test status
Simulation time 11187815339 ps
CPU time 623.96 seconds
Started Jun 13 01:01:06 PM PDT 24
Finished Jun 13 01:11:32 PM PDT 24
Peak memory 200676 kb
Host smart-758325d2-43e3-444a-b2a5-4f2f1983bef2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=662797987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.662797987
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.2628571946
Short name T1097
Test name
Test status
Simulation time 4635307763 ps
CPU time 19.81 seconds
Started Jun 13 01:01:08 PM PDT 24
Finished Jun 13 01:01:30 PM PDT 24
Peak memory 199560 kb
Host smart-b44ec254-307c-4971-b6f7-6c99cd824750
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2628571946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.2628571946
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.2503963992
Short name T840
Test name
Test status
Simulation time 20195374422 ps
CPU time 10.68 seconds
Started Jun 13 01:01:07 PM PDT 24
Finished Jun 13 01:01:19 PM PDT 24
Peak memory 200744 kb
Host smart-f2f400cc-6c50-41b5-be3b-2d0dd12d38a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503963992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.2503963992
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.145517568
Short name T704
Test name
Test status
Simulation time 4337289710 ps
CPU time 2.26 seconds
Started Jun 13 01:01:07 PM PDT 24
Finished Jun 13 01:01:12 PM PDT 24
Peak memory 197076 kb
Host smart-58da1090-8363-42f0-a58b-09275c1494d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145517568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.145517568
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.2737712953
Short name T581
Test name
Test status
Simulation time 658848050 ps
CPU time 1.99 seconds
Started Jun 13 01:01:11 PM PDT 24
Finished Jun 13 01:01:13 PM PDT 24
Peak memory 200416 kb
Host smart-d6aadb82-9deb-4904-a547-840562b72456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737712953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.2737712953
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.1085430397
Short name T186
Test name
Test status
Simulation time 409145593242 ps
CPU time 427.63 seconds
Started Jun 13 01:01:08 PM PDT 24
Finished Jun 13 01:08:18 PM PDT 24
Peak memory 200748 kb
Host smart-bd740924-3606-466e-843c-2c111d006a23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085430397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.1085430397
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.2179363284
Short name T536
Test name
Test status
Simulation time 16044772791 ps
CPU time 104.67 seconds
Started Jun 13 01:01:06 PM PDT 24
Finished Jun 13 01:02:52 PM PDT 24
Peak memory 217236 kb
Host smart-c1470c9e-4139-42a5-9d64-a647da564c31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179363284 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.2179363284
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.339791108
Short name T452
Test name
Test status
Simulation time 1521715133 ps
CPU time 2.32 seconds
Started Jun 13 01:01:15 PM PDT 24
Finished Jun 13 01:01:18 PM PDT 24
Peak memory 200608 kb
Host smart-7f506597-db1b-4183-98cc-4d208a649783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339791108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.339791108
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.593463269
Short name T885
Test name
Test status
Simulation time 53614961625 ps
CPU time 19.17 seconds
Started Jun 13 01:01:05 PM PDT 24
Finished Jun 13 01:01:25 PM PDT 24
Peak memory 200728 kb
Host smart-369c3344-a6ba-4e13-9a95-06620dd771bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593463269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.593463269
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.3930443743
Short name T1059
Test name
Test status
Simulation time 289385002794 ps
CPU time 77.03 seconds
Started Jun 13 02:15:47 PM PDT 24
Finished Jun 13 02:17:06 PM PDT 24
Peak memory 200752 kb
Host smart-bdca3fe8-a558-4639-8069-1c0f271f7486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930443743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.3930443743
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.3294164006
Short name T420
Test name
Test status
Simulation time 136859585721 ps
CPU time 18.84 seconds
Started Jun 13 01:02:55 PM PDT 24
Finished Jun 13 01:03:15 PM PDT 24
Peak memory 200688 kb
Host smart-b351f710-c9e8-4bb7-9e86-33638a1552ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294164006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.3294164006
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.960571980
Short name T855
Test name
Test status
Simulation time 77262048908 ps
CPU time 90.53 seconds
Started Jun 13 01:59:00 PM PDT 24
Finished Jun 13 02:00:32 PM PDT 24
Peak memory 200760 kb
Host smart-409fa66b-a96d-47da-9f7e-6cbc3bc3d870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960571980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.960571980
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.3434436785
Short name T1012
Test name
Test status
Simulation time 58171933875 ps
CPU time 46.64 seconds
Started Jun 13 01:02:57 PM PDT 24
Finished Jun 13 01:03:44 PM PDT 24
Peak memory 200676 kb
Host smart-1c62a324-ac9b-4bea-842d-4a892e16005b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434436785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.3434436785
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.635188891
Short name T323
Test name
Test status
Simulation time 169088472380 ps
CPU time 30.59 seconds
Started Jun 13 01:02:56 PM PDT 24
Finished Jun 13 01:03:27 PM PDT 24
Peak memory 200724 kb
Host smart-42b1e8fe-832b-423f-8074-fc0cee74970e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635188891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.635188891
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.2228332526
Short name T991
Test name
Test status
Simulation time 17127529375 ps
CPU time 27.69 seconds
Started Jun 13 01:50:55 PM PDT 24
Finished Jun 13 01:51:25 PM PDT 24
Peak memory 200828 kb
Host smart-e9aa0845-e1f0-44a2-ac3f-257fef493c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228332526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.2228332526
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.2132084019
Short name T66
Test name
Test status
Simulation time 94567543165 ps
CPU time 63.86 seconds
Started Jun 13 01:46:36 PM PDT 24
Finished Jun 13 01:47:41 PM PDT 24
Peak memory 200756 kb
Host smart-f54ece82-d970-4c6d-9295-07fa8809388b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132084019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.2132084019
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.2148575706
Short name T790
Test name
Test status
Simulation time 10566534199 ps
CPU time 15.63 seconds
Started Jun 13 02:29:33 PM PDT 24
Finished Jun 13 02:29:50 PM PDT 24
Peak memory 200904 kb
Host smart-60f73dc1-fd53-419e-a178-e6156122284a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148575706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.2148575706
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.2273487936
Short name T972
Test name
Test status
Simulation time 101515280260 ps
CPU time 189.42 seconds
Started Jun 13 01:02:54 PM PDT 24
Finished Jun 13 01:06:04 PM PDT 24
Peak memory 200756 kb
Host smart-58f9cade-cfd0-48d3-8a0c-64a750212f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273487936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.2273487936
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.4163390386
Short name T1095
Test name
Test status
Simulation time 39608055 ps
CPU time 0.57 seconds
Started Jun 13 01:01:06 PM PDT 24
Finished Jun 13 01:01:08 PM PDT 24
Peak memory 196024 kb
Host smart-75eb8738-4b5e-4702-89fc-3cb6818defe2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163390386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.4163390386
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.606724866
Short name T286
Test name
Test status
Simulation time 159583793486 ps
CPU time 118.74 seconds
Started Jun 13 01:01:09 PM PDT 24
Finished Jun 13 01:03:09 PM PDT 24
Peak memory 200748 kb
Host smart-033b0677-7c1e-44b2-9e2c-8524e4d4a70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606724866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.606724866
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.319681693
Short name T287
Test name
Test status
Simulation time 155162103449 ps
CPU time 101.33 seconds
Started Jun 13 01:01:07 PM PDT 24
Finished Jun 13 01:02:50 PM PDT 24
Peak memory 200568 kb
Host smart-4de215f6-d5ca-4dcc-9dd7-e7bf8d68a638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319681693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.319681693
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.3324213669
Short name T883
Test name
Test status
Simulation time 21287567280 ps
CPU time 15.98 seconds
Started Jun 13 01:01:07 PM PDT 24
Finished Jun 13 01:01:24 PM PDT 24
Peak memory 200804 kb
Host smart-abe8374f-75dd-4e71-a975-24f3abb58031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324213669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.3324213669
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.1457721425
Short name T833
Test name
Test status
Simulation time 4363604521 ps
CPU time 9.58 seconds
Started Jun 13 01:01:07 PM PDT 24
Finished Jun 13 01:01:19 PM PDT 24
Peak memory 200728 kb
Host smart-beb456c4-1a7b-4e02-bd9d-8707d5c5e44a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457721425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.1457721425
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.441843158
Short name T533
Test name
Test status
Simulation time 57758238768 ps
CPU time 391.3 seconds
Started Jun 13 01:01:09 PM PDT 24
Finished Jun 13 01:07:42 PM PDT 24
Peak memory 200732 kb
Host smart-b096ef28-c943-4c10-ba23-f631a3f9a885
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=441843158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.441843158
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.3915002812
Short name T966
Test name
Test status
Simulation time 5032514482 ps
CPU time 3.68 seconds
Started Jun 13 01:01:05 PM PDT 24
Finished Jun 13 01:01:10 PM PDT 24
Peak memory 200000 kb
Host smart-5279cc53-5b66-45bb-afc0-a7620a6b847a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915002812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.3915002812
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.1214034170
Short name T63
Test name
Test status
Simulation time 28041902301 ps
CPU time 16 seconds
Started Jun 13 01:01:08 PM PDT 24
Finished Jun 13 01:01:26 PM PDT 24
Peak memory 200472 kb
Host smart-4147ddd7-f9a7-47c5-ad30-9669ffc5abf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214034170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.1214034170
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.4179647975
Short name T947
Test name
Test status
Simulation time 10092668395 ps
CPU time 186.01 seconds
Started Jun 13 01:01:09 PM PDT 24
Finished Jun 13 01:04:16 PM PDT 24
Peak memory 200664 kb
Host smart-4357a9f8-8286-43eb-9d53-2fee9fe7fda3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4179647975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.4179647975
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.2530857167
Short name T8
Test name
Test status
Simulation time 1270472897 ps
CPU time 5.74 seconds
Started Jun 13 01:01:06 PM PDT 24
Finished Jun 13 01:01:14 PM PDT 24
Peak memory 198928 kb
Host smart-d0f2a48f-31fc-4b6e-bdc2-8c8928b34658
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2530857167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.2530857167
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.958285841
Short name T170
Test name
Test status
Simulation time 20137321164 ps
CPU time 27.54 seconds
Started Jun 13 01:01:07 PM PDT 24
Finished Jun 13 01:01:37 PM PDT 24
Peak memory 200808 kb
Host smart-a73c5db5-f21f-4341-9072-24c77b96e956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958285841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.958285841
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.1371172878
Short name T955
Test name
Test status
Simulation time 4157122874 ps
CPU time 1.44 seconds
Started Jun 13 01:01:07 PM PDT 24
Finished Jun 13 01:01:10 PM PDT 24
Peak memory 196856 kb
Host smart-b9c675af-3a70-4c44-935f-1023083331be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371172878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.1371172878
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.1290956620
Short name T761
Test name
Test status
Simulation time 622759381 ps
CPU time 3.1 seconds
Started Jun 13 01:01:08 PM PDT 24
Finished Jun 13 01:01:13 PM PDT 24
Peak memory 199496 kb
Host smart-a612654a-43a4-4dfa-bf97-5f337517a223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290956620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.1290956620
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.1505711087
Short name T1023
Test name
Test status
Simulation time 44878373420 ps
CPU time 255.9 seconds
Started Jun 13 01:01:07 PM PDT 24
Finished Jun 13 01:05:25 PM PDT 24
Peak memory 200704 kb
Host smart-b3fe4b79-4601-4c81-a639-24ccb6a0f1d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505711087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.1505711087
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.3167861772
Short name T483
Test name
Test status
Simulation time 897705929 ps
CPU time 2.66 seconds
Started Jun 13 01:01:11 PM PDT 24
Finished Jun 13 01:01:14 PM PDT 24
Peak memory 199496 kb
Host smart-fa8d0bf1-0bf2-4fe4-820a-13d41f240d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167861772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.3167861772
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.3375172254
Short name T1005
Test name
Test status
Simulation time 71072065912 ps
CPU time 104.75 seconds
Started Jun 13 01:01:06 PM PDT 24
Finished Jun 13 01:02:53 PM PDT 24
Peak memory 200780 kb
Host smart-99e08cd4-e14e-468d-a63a-c7d708c919bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375172254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.3375172254
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.2361968354
Short name T543
Test name
Test status
Simulation time 24962227208 ps
CPU time 11.63 seconds
Started Jun 13 02:15:11 PM PDT 24
Finished Jun 13 02:15:23 PM PDT 24
Peak memory 200736 kb
Host smart-ea1fb327-84c6-42b5-809c-342da89a6853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361968354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.2361968354
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.1219127897
Short name T1009
Test name
Test status
Simulation time 218438772879 ps
CPU time 26.42 seconds
Started Jun 13 02:09:01 PM PDT 24
Finished Jun 13 02:09:29 PM PDT 24
Peak memory 200816 kb
Host smart-4e02d9c0-d6d0-4690-84b4-84ad6abb3dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219127897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.1219127897
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.1247601932
Short name T274
Test name
Test status
Simulation time 116273686971 ps
CPU time 26.37 seconds
Started Jun 13 02:00:19 PM PDT 24
Finished Jun 13 02:00:47 PM PDT 24
Peak memory 200684 kb
Host smart-7042a877-560c-4f87-9107-60fbd2d75db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247601932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.1247601932
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.2361804828
Short name T659
Test name
Test status
Simulation time 123195872313 ps
CPU time 60.72 seconds
Started Jun 13 01:17:13 PM PDT 24
Finished Jun 13 01:18:14 PM PDT 24
Peak memory 200724 kb
Host smart-46db665e-ea90-43b4-8096-d8cd54239264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361804828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.2361804828
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.671979682
Short name T705
Test name
Test status
Simulation time 14275273840 ps
CPU time 23.66 seconds
Started Jun 13 01:24:19 PM PDT 24
Finished Jun 13 01:24:44 PM PDT 24
Peak memory 200756 kb
Host smart-0335e461-f6bb-4812-8e4c-8cc08df0ce3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671979682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.671979682
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.729453309
Short name T407
Test name
Test status
Simulation time 20751483076 ps
CPU time 28.9 seconds
Started Jun 13 01:28:55 PM PDT 24
Finished Jun 13 01:29:24 PM PDT 24
Peak memory 200780 kb
Host smart-3267f1b7-9c8d-412e-8e88-4057a726cba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729453309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.729453309
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.1789036329
Short name T441
Test name
Test status
Simulation time 17027997796 ps
CPU time 7.71 seconds
Started Jun 13 02:27:01 PM PDT 24
Finished Jun 13 02:27:09 PM PDT 24
Peak memory 200820 kb
Host smart-82a0d25f-46d1-4cd9-9bbb-ab8f863816e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789036329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.1789036329
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.1952923716
Short name T461
Test name
Test status
Simulation time 76910127768 ps
CPU time 131.65 seconds
Started Jun 13 01:03:42 PM PDT 24
Finished Jun 13 01:05:54 PM PDT 24
Peak memory 200724 kb
Host smart-ff689f47-0554-40f1-9c07-c5313ff2d494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952923716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.1952923716
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.3783924547
Short name T971
Test name
Test status
Simulation time 153171861670 ps
CPU time 65.01 seconds
Started Jun 13 01:21:28 PM PDT 24
Finished Jun 13 01:22:34 PM PDT 24
Peak memory 200780 kb
Host smart-8327a152-0c34-4af6-9cfe-af43b0bca0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783924547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.3783924547
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.720409591
Short name T1003
Test name
Test status
Simulation time 10547657 ps
CPU time 0.58 seconds
Started Jun 13 01:01:18 PM PDT 24
Finished Jun 13 01:01:19 PM PDT 24
Peak memory 195332 kb
Host smart-35947405-08e1-42ff-b977-ae76e90dc62e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720409591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.720409591
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.3460992317
Short name T311
Test name
Test status
Simulation time 263409601565 ps
CPU time 150 seconds
Started Jun 13 01:01:11 PM PDT 24
Finished Jun 13 01:03:41 PM PDT 24
Peak memory 200728 kb
Host smart-80cc14e3-260d-4f92-b1be-9fc990f5596f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460992317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.3460992317
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.1488992882
Short name T437
Test name
Test status
Simulation time 119380165272 ps
CPU time 14.45 seconds
Started Jun 13 01:01:09 PM PDT 24
Finished Jun 13 01:01:25 PM PDT 24
Peak memory 200748 kb
Host smart-1dc8c6a5-8e35-4e29-b72e-ee3f4ed409e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488992882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.1488992882
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_intr.3681002312
Short name T532
Test name
Test status
Simulation time 10431651815 ps
CPU time 18.18 seconds
Started Jun 13 01:01:15 PM PDT 24
Finished Jun 13 01:01:33 PM PDT 24
Peak memory 197376 kb
Host smart-463bb309-8af8-49f6-88e2-300db15f4e0e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681002312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.3681002312
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.3624882038
Short name T493
Test name
Test status
Simulation time 104099854331 ps
CPU time 161.69 seconds
Started Jun 13 01:01:14 PM PDT 24
Finished Jun 13 01:03:56 PM PDT 24
Peak memory 200796 kb
Host smart-5699deec-07d2-4fc3-9c1f-03f0f9ea7651
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3624882038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.3624882038
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.2842391986
Short name T746
Test name
Test status
Simulation time 9290921743 ps
CPU time 10.82 seconds
Started Jun 13 01:01:12 PM PDT 24
Finished Jun 13 01:01:23 PM PDT 24
Peak memory 200612 kb
Host smart-5f0e56ea-242e-4411-9b1d-1c1e71b89833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842391986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.2842391986
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_perf.2051781393
Short name T379
Test name
Test status
Simulation time 13404145319 ps
CPU time 79.49 seconds
Started Jun 13 01:01:13 PM PDT 24
Finished Jun 13 01:02:34 PM PDT 24
Peak memory 200872 kb
Host smart-7d6c795f-68e2-455c-bc2d-da41bbf44618
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2051781393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.2051781393
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.3874901956
Short name T103
Test name
Test status
Simulation time 3757077751 ps
CPU time 27.48 seconds
Started Jun 13 01:01:14 PM PDT 24
Finished Jun 13 01:01:42 PM PDT 24
Peak memory 199236 kb
Host smart-505ad706-a974-4914-991c-a9693699794c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3874901956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.3874901956
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.266291941
Short name T563
Test name
Test status
Simulation time 55174846789 ps
CPU time 109.18 seconds
Started Jun 13 01:01:15 PM PDT 24
Finished Jun 13 01:03:05 PM PDT 24
Peak memory 200744 kb
Host smart-83036958-225c-4e15-8aab-1b4eba4201a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266291941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.266291941
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.2233241141
Short name T395
Test name
Test status
Simulation time 33848272892 ps
CPU time 56.62 seconds
Started Jun 13 01:01:14 PM PDT 24
Finished Jun 13 01:02:12 PM PDT 24
Peak memory 197540 kb
Host smart-6c770fe4-5eab-4c7b-83cd-69e30e46e708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233241141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.2233241141
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.1442195517
Short name T511
Test name
Test status
Simulation time 729417852 ps
CPU time 1.85 seconds
Started Jun 13 01:01:09 PM PDT 24
Finished Jun 13 01:01:12 PM PDT 24
Peak memory 200204 kb
Host smart-73aa20dc-65ce-412f-a2c5-bf7dbe6b62fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442195517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.1442195517
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.892601556
Short name T556
Test name
Test status
Simulation time 25045887594 ps
CPU time 648.19 seconds
Started Jun 13 01:01:18 PM PDT 24
Finished Jun 13 01:12:07 PM PDT 24
Peak memory 200764 kb
Host smart-8bb75a02-abd5-48dc-9dbe-358944f906e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892601556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.892601556
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.4170315362
Short name T302
Test name
Test status
Simulation time 7504104377 ps
CPU time 10.48 seconds
Started Jun 13 01:01:13 PM PDT 24
Finished Jun 13 01:01:24 PM PDT 24
Peak memory 200720 kb
Host smart-88c567bb-30aa-4005-bad4-07abdd493ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170315362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.4170315362
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.114264252
Short name T760
Test name
Test status
Simulation time 90653201755 ps
CPU time 35.79 seconds
Started Jun 13 01:01:09 PM PDT 24
Finished Jun 13 01:01:46 PM PDT 24
Peak memory 200508 kb
Host smart-7e47292a-826c-4040-bba8-52a28dff2b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114264252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.114264252
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.1207700050
Short name T646
Test name
Test status
Simulation time 10004101363 ps
CPU time 24.63 seconds
Started Jun 13 01:02:56 PM PDT 24
Finished Jun 13 01:03:21 PM PDT 24
Peak memory 200792 kb
Host smart-107e4f13-8711-4327-bc32-4ddbbf788085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207700050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.1207700050
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.1327557935
Short name T495
Test name
Test status
Simulation time 112026029789 ps
CPU time 253.32 seconds
Started Jun 13 01:42:30 PM PDT 24
Finished Jun 13 01:46:45 PM PDT 24
Peak memory 200844 kb
Host smart-ecd47100-c16c-48c0-849d-838d242f4ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327557935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.1327557935
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.294252450
Short name T290
Test name
Test status
Simulation time 43173637628 ps
CPU time 68.59 seconds
Started Jun 13 02:10:47 PM PDT 24
Finished Jun 13 02:11:55 PM PDT 24
Peak memory 200808 kb
Host smart-32091d6f-b3aa-4409-84bf-ddd8c11b6180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294252450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.294252450
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.3351731428
Short name T1085
Test name
Test status
Simulation time 73746317685 ps
CPU time 35.65 seconds
Started Jun 13 01:02:58 PM PDT 24
Finished Jun 13 01:03:34 PM PDT 24
Peak memory 200748 kb
Host smart-f58c9f08-bc10-4436-8c5d-9010b15bb6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351731428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.3351731428
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.2177650909
Short name T169
Test name
Test status
Simulation time 54569351951 ps
CPU time 72.66 seconds
Started Jun 13 01:04:33 PM PDT 24
Finished Jun 13 01:05:47 PM PDT 24
Peak memory 201000 kb
Host smart-13294a75-1d7d-4313-b96e-bae3fd34ac9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177650909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.2177650909
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.1696077997
Short name T512
Test name
Test status
Simulation time 106688285485 ps
CPU time 36.9 seconds
Started Jun 13 02:06:18 PM PDT 24
Finished Jun 13 02:06:55 PM PDT 24
Peak memory 200764 kb
Host smart-343717de-7ca9-4ed1-8c22-c546f4d4495d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696077997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.1696077997
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.3406449667
Short name T1029
Test name
Test status
Simulation time 37392752365 ps
CPU time 21.96 seconds
Started Jun 13 01:18:44 PM PDT 24
Finished Jun 13 01:19:07 PM PDT 24
Peak memory 200764 kb
Host smart-9036629c-7cd4-45ec-8eae-226cd9d404b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406449667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.3406449667
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.1386554809
Short name T42
Test name
Test status
Simulation time 190634841482 ps
CPU time 87.34 seconds
Started Jun 13 02:01:06 PM PDT 24
Finished Jun 13 02:02:34 PM PDT 24
Peak memory 200756 kb
Host smart-443637cf-53dd-4477-a8bd-31fbf5cc978a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386554809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.1386554809
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.2640664610
Short name T778
Test name
Test status
Simulation time 22678234375 ps
CPU time 17.4 seconds
Started Jun 13 01:44:06 PM PDT 24
Finished Jun 13 01:44:24 PM PDT 24
Peak memory 200756 kb
Host smart-d00d48be-c50f-4578-9aea-7534d2f9581d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640664610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.2640664610
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.2132149831
Short name T1021
Test name
Test status
Simulation time 10431664746 ps
CPU time 18.1 seconds
Started Jun 13 01:18:52 PM PDT 24
Finished Jun 13 01:19:11 PM PDT 24
Peak memory 199916 kb
Host smart-e9ad9b65-0243-4d36-a2ba-abb0984e8a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132149831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.2132149831
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.3461998904
Short name T950
Test name
Test status
Simulation time 58585664 ps
CPU time 0.61 seconds
Started Jun 13 01:01:21 PM PDT 24
Finished Jun 13 01:01:22 PM PDT 24
Peak memory 195932 kb
Host smart-1af31974-681c-4708-a30b-473a505c8e29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461998904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.3461998904
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.1645057606
Short name T594
Test name
Test status
Simulation time 68402796138 ps
CPU time 28.82 seconds
Started Jun 13 01:01:21 PM PDT 24
Finished Jun 13 01:01:51 PM PDT 24
Peak memory 200744 kb
Host smart-d7e8588e-9581-4ea9-a082-68876278a5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645057606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.1645057606
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.2268364035
Short name T538
Test name
Test status
Simulation time 116932828773 ps
CPU time 50.28 seconds
Started Jun 13 01:01:18 PM PDT 24
Finished Jun 13 01:02:09 PM PDT 24
Peak memory 200724 kb
Host smart-eed56cfe-6279-4fca-ac04-b75c2640c768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268364035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.2268364035
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.803003985
Short name T951
Test name
Test status
Simulation time 81728952086 ps
CPU time 132.95 seconds
Started Jun 13 01:01:21 PM PDT 24
Finished Jun 13 01:03:34 PM PDT 24
Peak memory 200724 kb
Host smart-c1411ed1-ca6e-4ba7-9529-8282e5e27a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803003985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.803003985
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.3419319277
Short name T488
Test name
Test status
Simulation time 39769852633 ps
CPU time 68.95 seconds
Started Jun 13 01:01:20 PM PDT 24
Finished Jun 13 01:02:30 PM PDT 24
Peak memory 200764 kb
Host smart-9c40a394-8811-42b4-b2d6-39fc681f17cc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419319277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.3419319277
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.1446931703
Short name T604
Test name
Test status
Simulation time 162366689546 ps
CPU time 326.29 seconds
Started Jun 13 01:01:20 PM PDT 24
Finished Jun 13 01:06:46 PM PDT 24
Peak memory 200724 kb
Host smart-fd8c49e7-bb03-4550-90d8-e1a37258571f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1446931703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.1446931703
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.598938836
Short name T484
Test name
Test status
Simulation time 3708847257 ps
CPU time 7.08 seconds
Started Jun 13 01:01:21 PM PDT 24
Finished Jun 13 01:01:29 PM PDT 24
Peak memory 200048 kb
Host smart-881dfcd1-825f-4547-9a5c-9c22ea22d92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598938836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.598938836
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_perf.564101727
Short name T792
Test name
Test status
Simulation time 22855273415 ps
CPU time 185.69 seconds
Started Jun 13 01:01:18 PM PDT 24
Finished Jun 13 01:04:24 PM PDT 24
Peak memory 200788 kb
Host smart-5ac533b2-5e8d-4451-b41e-ead7836adc96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=564101727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.564101727
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.1364935053
Short name T711
Test name
Test status
Simulation time 4533541572 ps
CPU time 41.08 seconds
Started Jun 13 01:01:18 PM PDT 24
Finished Jun 13 01:02:00 PM PDT 24
Peak memory 199052 kb
Host smart-890d3c00-da3f-420d-91af-631523bd7fa9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1364935053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.1364935053
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.4294657225
Short name T953
Test name
Test status
Simulation time 21602642146 ps
CPU time 30.44 seconds
Started Jun 13 01:01:20 PM PDT 24
Finished Jun 13 01:01:51 PM PDT 24
Peak memory 199120 kb
Host smart-b22eb244-ae01-40da-98dd-f504d96c2ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294657225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.4294657225
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.904849733
Short name T1030
Test name
Test status
Simulation time 4893893274 ps
CPU time 7.62 seconds
Started Jun 13 01:01:19 PM PDT 24
Finished Jun 13 01:01:27 PM PDT 24
Peak memory 196776 kb
Host smart-1448647d-aacf-4d19-8fbd-369c638ea57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904849733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.904849733
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.1729772402
Short name T976
Test name
Test status
Simulation time 121122532 ps
CPU time 0.74 seconds
Started Jun 13 01:01:21 PM PDT 24
Finished Jun 13 01:01:23 PM PDT 24
Peak memory 197844 kb
Host smart-370373f7-3ab4-40c4-b7fe-21119496147e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729772402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.1729772402
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.1649253161
Short name T348
Test name
Test status
Simulation time 2207316341 ps
CPU time 2.17 seconds
Started Jun 13 01:01:19 PM PDT 24
Finished Jun 13 01:01:22 PM PDT 24
Peak memory 199252 kb
Host smart-8dc9941b-6de2-482c-8e78-790fb2347bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649253161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.1649253161
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.806852096
Short name T249
Test name
Test status
Simulation time 72117848534 ps
CPU time 142.33 seconds
Started Jun 13 01:01:19 PM PDT 24
Finished Jun 13 01:03:42 PM PDT 24
Peak memory 200820 kb
Host smart-a90aa08c-926b-48b8-beb4-bac988e1c04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806852096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.806852096
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.3961307799
Short name T798
Test name
Test status
Simulation time 79228699368 ps
CPU time 125.69 seconds
Started Jun 13 01:46:34 PM PDT 24
Finished Jun 13 01:48:41 PM PDT 24
Peak memory 200796 kb
Host smart-6c18d6cf-dd29-437b-8743-0d576a0d1ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961307799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.3961307799
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.772232782
Short name T810
Test name
Test status
Simulation time 45977713480 ps
CPU time 20.24 seconds
Started Jun 13 02:27:22 PM PDT 24
Finished Jun 13 02:27:43 PM PDT 24
Peak memory 200784 kb
Host smart-644efcb1-e801-443e-aa39-22df8f5bd44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772232782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.772232782
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.3907663523
Short name T846
Test name
Test status
Simulation time 276533634167 ps
CPU time 155.87 seconds
Started Jun 13 01:20:06 PM PDT 24
Finished Jun 13 01:22:43 PM PDT 24
Peak memory 200788 kb
Host smart-d2e1abc9-61d4-4364-affb-871cc1674889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907663523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.3907663523
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.3100828494
Short name T632
Test name
Test status
Simulation time 9211319839 ps
CPU time 9.07 seconds
Started Jun 13 01:34:33 PM PDT 24
Finished Jun 13 01:34:43 PM PDT 24
Peak memory 200732 kb
Host smart-d07618dd-4985-444c-b0e8-8058fa67c076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100828494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.3100828494
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.2438172291
Short name T153
Test name
Test status
Simulation time 114897796538 ps
CPU time 122.88 seconds
Started Jun 13 01:16:57 PM PDT 24
Finished Jun 13 01:19:00 PM PDT 24
Peak memory 200824 kb
Host smart-5a074ddf-90a0-406f-9217-961a41597b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438172291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.2438172291
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.452695744
Short name T842
Test name
Test status
Simulation time 11366022092 ps
CPU time 20.73 seconds
Started Jun 13 01:02:57 PM PDT 24
Finished Jun 13 01:03:18 PM PDT 24
Peak memory 200808 kb
Host smart-0adbd8a5-2b62-4264-b43d-132156276ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452695744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.452695744
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.833740449
Short name T758
Test name
Test status
Simulation time 58702461135 ps
CPU time 94.9 seconds
Started Jun 13 02:18:40 PM PDT 24
Finished Jun 13 02:20:24 PM PDT 24
Peak memory 200800 kb
Host smart-d1608167-82da-4f19-bd12-e7ae5cc26a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833740449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.833740449
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.1395675701
Short name T393
Test name
Test status
Simulation time 15252167 ps
CPU time 0.56 seconds
Started Jun 13 01:01:26 PM PDT 24
Finished Jun 13 01:01:29 PM PDT 24
Peak memory 196088 kb
Host smart-8a45ff51-32be-4bed-a122-480a2c42ef93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395675701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.1395675701
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.2511758330
Short name T771
Test name
Test status
Simulation time 92582707108 ps
CPU time 155.93 seconds
Started Jun 13 01:01:21 PM PDT 24
Finished Jun 13 01:03:58 PM PDT 24
Peak memory 200848 kb
Host smart-5fc0bd8a-a887-4b26-b944-8d4ac5448680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511758330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.2511758330
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.1367066599
Short name T654
Test name
Test status
Simulation time 85136457095 ps
CPU time 102.98 seconds
Started Jun 13 01:01:21 PM PDT 24
Finished Jun 13 01:03:05 PM PDT 24
Peak memory 200824 kb
Host smart-5fe9caa1-3d88-46d8-bedf-6b47f9fcc7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367066599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.1367066599
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.2240345071
Short name T597
Test name
Test status
Simulation time 28014503106 ps
CPU time 42.41 seconds
Started Jun 13 01:01:21 PM PDT 24
Finished Jun 13 01:02:04 PM PDT 24
Peak memory 200496 kb
Host smart-36a5c5ed-d4f1-4db4-b159-2f5a92cc2bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240345071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.2240345071
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.1917570134
Short name T913
Test name
Test status
Simulation time 30314773270 ps
CPU time 14.1 seconds
Started Jun 13 01:01:26 PM PDT 24
Finished Jun 13 01:01:42 PM PDT 24
Peak memory 200528 kb
Host smart-9270420b-b0aa-4a4a-b955-b6a07e770d8f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917570134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.1917570134
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.1904206634
Short name T421
Test name
Test status
Simulation time 125382336224 ps
CPU time 928.05 seconds
Started Jun 13 01:01:26 PM PDT 24
Finished Jun 13 01:16:56 PM PDT 24
Peak memory 200752 kb
Host smart-bdaf978b-4183-4eb9-ae9d-45fbcc6383b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1904206634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.1904206634
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.1780814643
Short name T340
Test name
Test status
Simulation time 3679753633 ps
CPU time 3.39 seconds
Started Jun 13 01:01:27 PM PDT 24
Finished Jun 13 01:01:33 PM PDT 24
Peak memory 200500 kb
Host smart-9462cf76-25bb-4b85-beaf-5d1978aa8340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780814643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.1780814643
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_perf.582672325
Short name T666
Test name
Test status
Simulation time 7530609007 ps
CPU time 96.11 seconds
Started Jun 13 01:01:26 PM PDT 24
Finished Jun 13 01:03:04 PM PDT 24
Peak memory 200780 kb
Host smart-a293ff86-0108-4860-a1fa-781281389386
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=582672325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.582672325
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.860632929
Short name T657
Test name
Test status
Simulation time 3906328993 ps
CPU time 29.58 seconds
Started Jun 13 01:01:21 PM PDT 24
Finished Jun 13 01:01:51 PM PDT 24
Peak memory 198896 kb
Host smart-9223997f-8c86-4a0c-b947-95446b96948b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=860632929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.860632929
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.3336150630
Short name T662
Test name
Test status
Simulation time 190316768346 ps
CPU time 306.84 seconds
Started Jun 13 01:01:26 PM PDT 24
Finished Jun 13 01:06:35 PM PDT 24
Peak memory 200744 kb
Host smart-3af660bb-3a9c-4c4d-bb72-a58a5c810dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336150630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.3336150630
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.1375865334
Short name T668
Test name
Test status
Simulation time 76477073573 ps
CPU time 108.03 seconds
Started Jun 13 01:01:27 PM PDT 24
Finished Jun 13 01:03:17 PM PDT 24
Peak memory 196608 kb
Host smart-71119655-1b66-4464-9048-31654083657e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375865334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.1375865334
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.774379079
Short name T742
Test name
Test status
Simulation time 665549447 ps
CPU time 3.19 seconds
Started Jun 13 01:01:18 PM PDT 24
Finished Jun 13 01:01:22 PM PDT 24
Peak memory 200256 kb
Host smart-0e77ef22-2a39-4683-8433-b13cbac3026c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774379079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.774379079
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.1721694860
Short name T868
Test name
Test status
Simulation time 175442414711 ps
CPU time 255.14 seconds
Started Jun 13 01:01:27 PM PDT 24
Finished Jun 13 01:05:44 PM PDT 24
Peak memory 200748 kb
Host smart-82407ddd-4bec-4c71-abb7-e0e2b3aeab8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721694860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.1721694860
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.766056120
Short name T49
Test name
Test status
Simulation time 415140420657 ps
CPU time 1159.32 seconds
Started Jun 13 01:01:27 PM PDT 24
Finished Jun 13 01:20:48 PM PDT 24
Peak memory 229840 kb
Host smart-d0dacc45-452d-4e82-82ad-ae267fdaad37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766056120 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.766056120
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.1409418040
Short name T579
Test name
Test status
Simulation time 407873740 ps
CPU time 1.55 seconds
Started Jun 13 01:01:25 PM PDT 24
Finished Jun 13 01:01:28 PM PDT 24
Peak memory 199376 kb
Host smart-c9da55ea-cf6c-4084-83c2-cb3c87c960f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409418040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.1409418040
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.295564706
Short name T764
Test name
Test status
Simulation time 22980194990 ps
CPU time 21.85 seconds
Started Jun 13 01:01:22 PM PDT 24
Finished Jun 13 01:01:44 PM PDT 24
Peak memory 200656 kb
Host smart-f68eb01c-ed7f-4486-b915-4efb744d8b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295564706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.295564706
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.4259184621
Short name T335
Test name
Test status
Simulation time 130961752266 ps
CPU time 54.97 seconds
Started Jun 13 01:26:21 PM PDT 24
Finished Jun 13 01:27:17 PM PDT 24
Peak memory 200748 kb
Host smart-4ad1572c-b291-404f-994d-19eeaf9ae556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259184621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.4259184621
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.51072331
Short name T197
Test name
Test status
Simulation time 115982703739 ps
CPU time 176.14 seconds
Started Jun 13 01:02:58 PM PDT 24
Finished Jun 13 01:05:55 PM PDT 24
Peak memory 200660 kb
Host smart-f1a9d13e-f1e3-469b-ba9b-2be95faf9ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51072331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.51072331
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.846306915
Short name T687
Test name
Test status
Simulation time 27111828266 ps
CPU time 22.2 seconds
Started Jun 13 01:18:08 PM PDT 24
Finished Jun 13 01:18:31 PM PDT 24
Peak memory 200776 kb
Host smart-e199f5c4-61fe-4ddc-b517-c1c5c72fd523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846306915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.846306915
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.438924966
Short name T298
Test name
Test status
Simulation time 88157889036 ps
CPU time 207.59 seconds
Started Jun 13 01:02:58 PM PDT 24
Finished Jun 13 01:06:26 PM PDT 24
Peak memory 200828 kb
Host smart-ed39476f-c7a6-4542-88c0-9f39cd55b463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438924966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.438924966
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.3689740130
Short name T1083
Test name
Test status
Simulation time 51965892662 ps
CPU time 9.23 seconds
Started Jun 13 02:10:27 PM PDT 24
Finished Jun 13 02:10:37 PM PDT 24
Peak memory 200832 kb
Host smart-ae01d753-397a-47c0-905a-fa35ee7554ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689740130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.3689740130
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.1754712290
Short name T107
Test name
Test status
Simulation time 199998691859 ps
CPU time 155.15 seconds
Started Jun 13 01:02:59 PM PDT 24
Finished Jun 13 01:05:34 PM PDT 24
Peak memory 200688 kb
Host smart-7a8c3c58-99ad-453b-a660-4dd8218a3402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754712290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.1754712290
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.2602836631
Short name T580
Test name
Test status
Simulation time 137559354104 ps
CPU time 52.37 seconds
Started Jun 13 01:02:57 PM PDT 24
Finished Jun 13 01:03:50 PM PDT 24
Peak memory 200736 kb
Host smart-54d720e6-c91f-4a76-b8f4-b8b83a008d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602836631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.2602836631
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.3495325434
Short name T575
Test name
Test status
Simulation time 37185403943 ps
CPU time 17.55 seconds
Started Jun 13 01:21:55 PM PDT 24
Finished Jun 13 01:22:13 PM PDT 24
Peak memory 200732 kb
Host smart-3e56fdff-82c8-459f-a9ed-360db327fbe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495325434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.3495325434
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.1097610205
Short name T330
Test name
Test status
Simulation time 26060667352 ps
CPU time 11.39 seconds
Started Jun 13 01:31:28 PM PDT 24
Finished Jun 13 01:31:40 PM PDT 24
Peak memory 200772 kb
Host smart-e406244c-587d-456c-aaab-10787844a4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097610205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.1097610205
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.3197586108
Short name T534
Test name
Test status
Simulation time 13169362 ps
CPU time 0.57 seconds
Started Jun 13 01:01:34 PM PDT 24
Finished Jun 13 01:01:35 PM PDT 24
Peak memory 196084 kb
Host smart-4393dd34-5704-4a36-af8e-66f6f1560a30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197586108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.3197586108
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.448571805
Short name T462
Test name
Test status
Simulation time 70608210292 ps
CPU time 56.35 seconds
Started Jun 13 01:01:25 PM PDT 24
Finished Jun 13 01:02:22 PM PDT 24
Peak memory 200804 kb
Host smart-458cceae-e0ea-477b-a1a6-12169083cee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448571805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.448571805
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.503368670
Short name T878
Test name
Test status
Simulation time 110534401949 ps
CPU time 227.01 seconds
Started Jun 13 01:01:28 PM PDT 24
Finished Jun 13 01:05:17 PM PDT 24
Peak memory 200760 kb
Host smart-6561fc51-292f-464f-929b-2481c6f29a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503368670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.503368670
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.490939515
Short name T553
Test name
Test status
Simulation time 13834166648 ps
CPU time 11.55 seconds
Started Jun 13 01:01:25 PM PDT 24
Finished Jun 13 01:01:37 PM PDT 24
Peak memory 198480 kb
Host smart-cdefd674-5a23-4fc0-88b3-6fb4c43f80d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490939515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.490939515
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.807438799
Short name T481
Test name
Test status
Simulation time 40484599862 ps
CPU time 69.67 seconds
Started Jun 13 01:01:29 PM PDT 24
Finished Jun 13 01:02:40 PM PDT 24
Peak memory 200744 kb
Host smart-282046f6-9556-4f3b-93a5-0a4e5045025c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807438799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.807438799
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.448955304
Short name T439
Test name
Test status
Simulation time 167558407411 ps
CPU time 324.3 seconds
Started Jun 13 01:01:36 PM PDT 24
Finished Jun 13 01:07:01 PM PDT 24
Peak memory 200764 kb
Host smart-c46fe602-2421-4627-83dd-c6c0b7c99d93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=448955304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.448955304
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.2678674270
Short name T1008
Test name
Test status
Simulation time 7391926561 ps
CPU time 7.07 seconds
Started Jun 13 01:01:35 PM PDT 24
Finished Jun 13 01:01:43 PM PDT 24
Peak memory 200492 kb
Host smart-7df38fa1-5da6-481c-87ca-f191f14b8ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678674270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.2678674270
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_perf.2840341944
Short name T756
Test name
Test status
Simulation time 19314571066 ps
CPU time 1043.57 seconds
Started Jun 13 01:01:31 PM PDT 24
Finished Jun 13 01:18:55 PM PDT 24
Peak memory 200780 kb
Host smart-fe4dd0dd-dffe-4ed1-93ee-33d11ced6e9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2840341944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.2840341944
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.4032362804
Short name T460
Test name
Test status
Simulation time 2449335707 ps
CPU time 7.89 seconds
Started Jun 13 01:01:28 PM PDT 24
Finished Jun 13 01:01:37 PM PDT 24
Peak memory 199152 kb
Host smart-712117b1-64ef-4497-8119-45a27e6c8632
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4032362804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.4032362804
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.2122625515
Short name T664
Test name
Test status
Simulation time 55945039584 ps
CPU time 27.71 seconds
Started Jun 13 01:01:31 PM PDT 24
Finished Jun 13 01:01:59 PM PDT 24
Peak memory 200744 kb
Host smart-81d70107-8425-4764-8894-4137309229a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122625515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.2122625515
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.1556888220
Short name T952
Test name
Test status
Simulation time 4597181797 ps
CPU time 7.29 seconds
Started Jun 13 01:01:33 PM PDT 24
Finished Jun 13 01:01:40 PM PDT 24
Peak memory 196780 kb
Host smart-b66fa3d2-e40d-42b5-9b5a-4ed7e4eb45eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556888220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.1556888220
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.3180034698
Short name T39
Test name
Test status
Simulation time 497645797 ps
CPU time 1.59 seconds
Started Jun 13 01:01:27 PM PDT 24
Finished Jun 13 01:01:31 PM PDT 24
Peak memory 200600 kb
Host smart-389f5a0f-2422-4a2c-beb0-db05005412d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180034698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.3180034698
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.2970393776
Short name T349
Test name
Test status
Simulation time 7797930804 ps
CPU time 12.13 seconds
Started Jun 13 01:01:35 PM PDT 24
Finished Jun 13 01:01:48 PM PDT 24
Peak memory 200528 kb
Host smart-7941dae8-75bb-4d52-a2e0-ec35b86f3222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970393776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.2970393776
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.3495948
Short name T241
Test name
Test status
Simulation time 90705662292 ps
CPU time 87.99 seconds
Started Jun 13 01:01:25 PM PDT 24
Finished Jun 13 01:02:53 PM PDT 24
Peak memory 200756 kb
Host smart-95b98b06-f08e-40fe-ba98-59b9cff4586a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.3495948
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.3427969906
Short name T805
Test name
Test status
Simulation time 9957905998 ps
CPU time 8.62 seconds
Started Jun 13 02:17:01 PM PDT 24
Finished Jun 13 02:17:16 PM PDT 24
Peak memory 200756 kb
Host smart-9753165f-02a2-4bc7-929f-98c9fe3aa92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427969906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.3427969906
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.801418829
Short name T332
Test name
Test status
Simulation time 19941641379 ps
CPU time 16.83 seconds
Started Jun 13 01:02:54 PM PDT 24
Finished Jun 13 01:03:12 PM PDT 24
Peak memory 200744 kb
Host smart-b2bc2227-690b-44bc-99c4-d8f8547134ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801418829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.801418829
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.2609383192
Short name T582
Test name
Test status
Simulation time 197142654956 ps
CPU time 55.86 seconds
Started Jun 13 02:25:20 PM PDT 24
Finished Jun 13 02:26:17 PM PDT 24
Peak memory 200788 kb
Host smart-69d7884b-9979-48b4-a863-cd6dc4e06137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609383192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.2609383192
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.3473848122
Short name T214
Test name
Test status
Simulation time 92619678333 ps
CPU time 78.97 seconds
Started Jun 13 01:02:58 PM PDT 24
Finished Jun 13 01:04:18 PM PDT 24
Peak memory 200704 kb
Host smart-ce08861f-400f-4179-bbb1-5a257efe1a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473848122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.3473848122
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.1657450798
Short name T1090
Test name
Test status
Simulation time 17602192121 ps
CPU time 17.33 seconds
Started Jun 13 02:18:17 PM PDT 24
Finished Jun 13 02:18:41 PM PDT 24
Peak memory 200808 kb
Host smart-341358a4-622e-4e0e-8776-b7268c797ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657450798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.1657450798
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.1015213426
Short name T178
Test name
Test status
Simulation time 41421717723 ps
CPU time 16.39 seconds
Started Jun 13 01:37:12 PM PDT 24
Finished Jun 13 01:37:29 PM PDT 24
Peak memory 200808 kb
Host smart-9d382750-66e9-47be-8cbd-2d1e343f03cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015213426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.1015213426
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.1228314865
Short name T1061
Test name
Test status
Simulation time 72114777691 ps
CPU time 82.35 seconds
Started Jun 13 01:27:38 PM PDT 24
Finished Jun 13 01:29:01 PM PDT 24
Peak memory 200776 kb
Host smart-c277f46a-c1a0-4f98-aacd-d7a445b4f48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228314865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.1228314865
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.3914209839
Short name T278
Test name
Test status
Simulation time 36270710802 ps
CPU time 16.39 seconds
Started Jun 13 01:21:44 PM PDT 24
Finished Jun 13 01:22:02 PM PDT 24
Peak memory 200752 kb
Host smart-e8b43ffe-9d11-413e-b5b9-b8979bb9b897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914209839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.3914209839
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.901510604
Short name T620
Test name
Test status
Simulation time 116179641704 ps
CPU time 51.81 seconds
Started Jun 13 02:13:44 PM PDT 24
Finished Jun 13 02:14:37 PM PDT 24
Peak memory 200776 kb
Host smart-23c846da-3bfd-47fe-9a68-65539172cb85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901510604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.901510604
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.4129519383
Short name T382
Test name
Test status
Simulation time 15218406 ps
CPU time 0.54 seconds
Started Jun 13 01:00:41 PM PDT 24
Finished Jun 13 01:00:42 PM PDT 24
Peak memory 195276 kb
Host smart-7fc6b8d8-0cee-4e75-9b31-89c0153514d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129519383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.4129519383
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.1348288901
Short name T155
Test name
Test status
Simulation time 135871729095 ps
CPU time 100.25 seconds
Started Jun 13 01:00:44 PM PDT 24
Finished Jun 13 01:02:24 PM PDT 24
Peak memory 200732 kb
Host smart-20afbeb1-981f-41d0-8dd0-7ac6b7909276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348288901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.1348288901
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.1606634895
Short name T870
Test name
Test status
Simulation time 24859311858 ps
CPU time 18.4 seconds
Started Jun 13 01:00:40 PM PDT 24
Finished Jun 13 01:00:59 PM PDT 24
Peak memory 200544 kb
Host smart-39da56de-49f0-4023-9f54-75eba4a3b8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606634895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.1606634895
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.1909143022
Short name T837
Test name
Test status
Simulation time 12250947937 ps
CPU time 24.62 seconds
Started Jun 13 01:00:43 PM PDT 24
Finished Jun 13 01:01:09 PM PDT 24
Peak memory 200800 kb
Host smart-2e9621a1-b76d-464a-a278-2280eec9448f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909143022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.1909143022
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.3656248495
Short name T977
Test name
Test status
Simulation time 10041557771 ps
CPU time 16.44 seconds
Started Jun 13 01:00:39 PM PDT 24
Finished Jun 13 01:00:56 PM PDT 24
Peak memory 200692 kb
Host smart-bf92a923-a25e-4ce7-947c-4ca0b6cd83aa
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656248495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.3656248495
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.3604866125
Short name T716
Test name
Test status
Simulation time 238778053581 ps
CPU time 215.86 seconds
Started Jun 13 01:00:44 PM PDT 24
Finished Jun 13 01:04:21 PM PDT 24
Peak memory 200744 kb
Host smart-cc103c76-8fd4-467a-a415-aa54d8e77740
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3604866125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.3604866125
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.2751560707
Short name T1086
Test name
Test status
Simulation time 2422462780 ps
CPU time 2.92 seconds
Started Jun 13 01:00:38 PM PDT 24
Finished Jun 13 01:00:42 PM PDT 24
Peak memory 200016 kb
Host smart-16871436-5368-4a3e-981b-c2eb7e6e950e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751560707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.2751560707
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_perf.2104649378
Short name T803
Test name
Test status
Simulation time 22859225987 ps
CPU time 1060.68 seconds
Started Jun 13 01:00:44 PM PDT 24
Finished Jun 13 01:18:25 PM PDT 24
Peak memory 200788 kb
Host smart-a46919c0-6e9a-484e-a480-e43c457628ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2104649378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.2104649378
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.777470206
Short name T1038
Test name
Test status
Simulation time 4663925552 ps
CPU time 5.17 seconds
Started Jun 13 01:00:38 PM PDT 24
Finished Jun 13 01:00:44 PM PDT 24
Peak memory 198660 kb
Host smart-d4d65b02-84ef-4ba7-8dc6-6e724d7c2408
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=777470206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.777470206
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.4098227026
Short name T898
Test name
Test status
Simulation time 73485809799 ps
CPU time 80.76 seconds
Started Jun 13 01:00:39 PM PDT 24
Finished Jun 13 01:02:00 PM PDT 24
Peak memory 200800 kb
Host smart-d3380784-1758-4693-aee9-63d36dceb7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098227026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.4098227026
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.3984484026
Short name T430
Test name
Test status
Simulation time 42237541670 ps
CPU time 17.1 seconds
Started Jun 13 01:00:34 PM PDT 24
Finished Jun 13 01:00:52 PM PDT 24
Peak memory 197068 kb
Host smart-3f1eed08-0d57-4c85-97b9-386845a6224c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984484026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.3984484026
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.1303819249
Short name T24
Test name
Test status
Simulation time 61544501 ps
CPU time 0.81 seconds
Started Jun 13 01:00:40 PM PDT 24
Finished Jun 13 01:00:42 PM PDT 24
Peak memory 219236 kb
Host smart-8d3218a6-2e0c-4697-bcbd-3182d3d0271e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303819249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.1303819249
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.2475802790
Short name T505
Test name
Test status
Simulation time 332279202 ps
CPU time 1.03 seconds
Started Jun 13 01:00:38 PM PDT 24
Finished Jun 13 01:00:40 PM PDT 24
Peak memory 199396 kb
Host smart-34b04e9b-2622-4ab6-8b0b-70df5dfc87eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475802790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.2475802790
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.955896850
Short name T25
Test name
Test status
Simulation time 123603536506 ps
CPU time 318.16 seconds
Started Jun 13 01:00:41 PM PDT 24
Finished Jun 13 01:06:01 PM PDT 24
Peak memory 216484 kb
Host smart-125767ff-1652-4270-9324-205143b6ecc3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955896850 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.955896850
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.1772206590
Short name T901
Test name
Test status
Simulation time 5872824794 ps
CPU time 16.5 seconds
Started Jun 13 01:00:42 PM PDT 24
Finished Jun 13 01:00:59 PM PDT 24
Peak memory 200664 kb
Host smart-35b75ba7-0609-4b48-9ad9-d446f5b08e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772206590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.1772206590
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.3818112192
Short name T521
Test name
Test status
Simulation time 172799110375 ps
CPU time 85.9 seconds
Started Jun 13 01:00:38 PM PDT 24
Finished Jun 13 01:02:04 PM PDT 24
Peak memory 200760 kb
Host smart-cb801971-df38-483d-a03d-0290d4ecbbf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818112192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3818112192
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.950620683
Short name T478
Test name
Test status
Simulation time 13464198 ps
CPU time 0.54 seconds
Started Jun 13 01:01:43 PM PDT 24
Finished Jun 13 01:01:44 PM PDT 24
Peak memory 195232 kb
Host smart-f556c660-b9ae-4f22-996a-1d5407aae6cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950620683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.950620683
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.2135099738
Short name T796
Test name
Test status
Simulation time 33167316098 ps
CPU time 32.56 seconds
Started Jun 13 01:01:33 PM PDT 24
Finished Jun 13 01:02:07 PM PDT 24
Peak memory 200696 kb
Host smart-776ea57a-3673-4d4d-b4a2-32d49b1cc87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135099738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.2135099738
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.118068382
Short name T159
Test name
Test status
Simulation time 48654808758 ps
CPU time 74.99 seconds
Started Jun 13 01:01:33 PM PDT 24
Finished Jun 13 01:02:49 PM PDT 24
Peak memory 200764 kb
Host smart-0d9830ff-1ffa-490d-98fc-c53a4ac1f705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118068382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.118068382
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.2909921753
Short name T824
Test name
Test status
Simulation time 73489109208 ps
CPU time 143.55 seconds
Started Jun 13 01:01:36 PM PDT 24
Finished Jun 13 01:04:00 PM PDT 24
Peak memory 200808 kb
Host smart-33007bd6-1e88-4d1a-ac47-3be94cbd78ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909921753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.2909921753
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.4093854926
Short name T446
Test name
Test status
Simulation time 8942659592 ps
CPU time 8.65 seconds
Started Jun 13 01:01:34 PM PDT 24
Finished Jun 13 01:01:43 PM PDT 24
Peak memory 200784 kb
Host smart-ca8f7150-bb89-4b1f-b72e-4349188f20a8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093854926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.4093854926
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.2861477423
Short name T667
Test name
Test status
Simulation time 46183969157 ps
CPU time 145.03 seconds
Started Jun 13 01:01:35 PM PDT 24
Finished Jun 13 01:04:01 PM PDT 24
Peak memory 200764 kb
Host smart-2248dff7-d1c6-4309-8420-5cbfb2e30de7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2861477423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.2861477423
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.3703575013
Short name T424
Test name
Test status
Simulation time 4571547890 ps
CPU time 3.57 seconds
Started Jun 13 01:01:33 PM PDT 24
Finished Jun 13 01:01:38 PM PDT 24
Peak memory 200804 kb
Host smart-9c3ecf38-1b99-4a20-a70a-41ba4459f3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703575013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.3703575013
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_perf.2412883575
Short name T324
Test name
Test status
Simulation time 5626632299 ps
CPU time 66.02 seconds
Started Jun 13 01:01:35 PM PDT 24
Finished Jun 13 01:02:41 PM PDT 24
Peak memory 200760 kb
Host smart-89aad043-242b-4cbe-ba07-69c68aef7421
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2412883575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.2412883575
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.1061945274
Short name T482
Test name
Test status
Simulation time 2859124059 ps
CPU time 18.98 seconds
Started Jun 13 01:01:33 PM PDT 24
Finished Jun 13 01:01:53 PM PDT 24
Peak memory 199792 kb
Host smart-f60761ef-fd31-4582-a1c3-78f9f2c85b40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1061945274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.1061945274
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.2477664517
Short name T281
Test name
Test status
Simulation time 27237355556 ps
CPU time 38.61 seconds
Started Jun 13 01:01:32 PM PDT 24
Finished Jun 13 01:02:11 PM PDT 24
Peak memory 200764 kb
Host smart-2ce9238f-1253-44d6-a8d6-804d0badf528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477664517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.2477664517
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.618883511
Short name T574
Test name
Test status
Simulation time 798955303 ps
CPU time 0.98 seconds
Started Jun 13 01:01:32 PM PDT 24
Finished Jun 13 01:01:33 PM PDT 24
Peak memory 196176 kb
Host smart-e21fca5c-169a-40bd-a4a9-40fc4c35debd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618883511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.618883511
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.3898736692
Short name T307
Test name
Test status
Simulation time 736993618 ps
CPU time 1.89 seconds
Started Jun 13 01:01:35 PM PDT 24
Finished Jun 13 01:01:37 PM PDT 24
Peak memory 199092 kb
Host smart-08ec80ce-ba4d-44bf-827a-6b5cc6222be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898736692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.3898736692
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.735109437
Short name T1022
Test name
Test status
Simulation time 320145138756 ps
CPU time 123.48 seconds
Started Jun 13 01:01:37 PM PDT 24
Finished Jun 13 01:03:41 PM PDT 24
Peak memory 200800 kb
Host smart-08a80efa-739b-43cb-b0f0-7ccaeb338197
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735109437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.735109437
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.2464672040
Short name T897
Test name
Test status
Simulation time 310432632305 ps
CPU time 570.92 seconds
Started Jun 13 01:01:34 PM PDT 24
Finished Jun 13 01:11:05 PM PDT 24
Peak memory 217172 kb
Host smart-4659fea1-15e3-4ccb-b3e8-4311428d08f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464672040 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.2464672040
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.2173118562
Short name T944
Test name
Test status
Simulation time 8049121846 ps
CPU time 10.22 seconds
Started Jun 13 01:01:32 PM PDT 24
Finished Jun 13 01:01:43 PM PDT 24
Peak memory 200708 kb
Host smart-ebb609a5-9282-4ffb-91eb-7a9a2f65300d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173118562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.2173118562
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.3351432510
Short name T83
Test name
Test status
Simulation time 137686073804 ps
CPU time 12.67 seconds
Started Jun 13 01:01:34 PM PDT 24
Finished Jun 13 01:01:47 PM PDT 24
Peak memory 200812 kb
Host smart-307c3d8b-32a6-4ce4-8612-e0f65a4a9bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351432510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.3351432510
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.2559278971
Short name T875
Test name
Test status
Simulation time 110860464067 ps
CPU time 89.85 seconds
Started Jun 13 02:21:50 PM PDT 24
Finished Jun 13 02:23:21 PM PDT 24
Peak memory 200772 kb
Host smart-68ee56e2-9c60-4d42-b844-1b510d316024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559278971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.2559278971
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.3554976528
Short name T784
Test name
Test status
Simulation time 135305407955 ps
CPU time 99.63 seconds
Started Jun 13 02:29:57 PM PDT 24
Finished Jun 13 02:31:37 PM PDT 24
Peak memory 200684 kb
Host smart-8dc7685c-02d3-4152-918b-e0c2950b6b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554976528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.3554976528
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.2768839527
Short name T640
Test name
Test status
Simulation time 119477064401 ps
CPU time 247.71 seconds
Started Jun 13 01:55:33 PM PDT 24
Finished Jun 13 01:59:42 PM PDT 24
Peak memory 200724 kb
Host smart-b90ad46a-8703-4101-99f3-b774a96cafa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768839527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.2768839527
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.3841025405
Short name T123
Test name
Test status
Simulation time 15778578695 ps
CPU time 32.47 seconds
Started Jun 13 02:13:00 PM PDT 24
Finished Jun 13 02:13:33 PM PDT 24
Peak memory 200832 kb
Host smart-2f792cd2-7950-43e1-b442-0f683f2d0d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841025405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.3841025405
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.1429953562
Short name T499
Test name
Test status
Simulation time 62896269323 ps
CPU time 27.57 seconds
Started Jun 13 01:02:55 PM PDT 24
Finished Jun 13 01:03:23 PM PDT 24
Peak memory 200720 kb
Host smart-10e9521b-1f25-4d3c-93fa-6a8a6a409754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429953562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.1429953562
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.4094834824
Short name T216
Test name
Test status
Simulation time 73885531000 ps
CPU time 115.73 seconds
Started Jun 13 01:02:55 PM PDT 24
Finished Jun 13 01:04:51 PM PDT 24
Peak memory 200716 kb
Host smart-a2fb115d-0501-4863-99fe-8995f08a6741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094834824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.4094834824
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.3686942183
Short name T190
Test name
Test status
Simulation time 59030276669 ps
CPU time 110.23 seconds
Started Jun 13 01:25:26 PM PDT 24
Finished Jun 13 01:27:17 PM PDT 24
Peak memory 200720 kb
Host smart-980ce988-3a76-45b9-a883-30bc9776321e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686942183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.3686942183
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.3321994199
Short name T497
Test name
Test status
Simulation time 22911842381 ps
CPU time 10.17 seconds
Started Jun 13 01:06:57 PM PDT 24
Finished Jun 13 01:07:11 PM PDT 24
Peak memory 200684 kb
Host smart-412499e8-ad14-45f6-9cc6-3ddd812ab426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321994199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.3321994199
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.688978465
Short name T561
Test name
Test status
Simulation time 16403619 ps
CPU time 0.54 seconds
Started Jun 13 01:01:40 PM PDT 24
Finished Jun 13 01:01:41 PM PDT 24
Peak memory 196068 kb
Host smart-5ffdbacc-f032-452f-9ae1-c6d0888a4f18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688978465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.688978465
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.2866145914
Short name T857
Test name
Test status
Simulation time 36557593631 ps
CPU time 55.4 seconds
Started Jun 13 01:01:40 PM PDT 24
Finished Jun 13 01:02:36 PM PDT 24
Peak memory 200752 kb
Host smart-fb86afe4-2717-48b9-bda2-2b29fec4258b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866145914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.2866145914
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.685227117
Short name T697
Test name
Test status
Simulation time 33034543936 ps
CPU time 27.59 seconds
Started Jun 13 01:01:40 PM PDT 24
Finished Jun 13 01:02:08 PM PDT 24
Peak memory 200712 kb
Host smart-3e24bf53-8d13-4f07-b415-c22815ceb52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685227117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.685227117
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.4251526476
Short name T187
Test name
Test status
Simulation time 32500711956 ps
CPU time 46.35 seconds
Started Jun 13 01:01:39 PM PDT 24
Finished Jun 13 01:02:26 PM PDT 24
Peak memory 200740 kb
Host smart-b26b0ac1-1b38-44f9-8bdf-12ce7091c0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251526476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.4251526476
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.2739843161
Short name T12
Test name
Test status
Simulation time 21971965879 ps
CPU time 12.75 seconds
Started Jun 13 01:01:39 PM PDT 24
Finished Jun 13 01:01:52 PM PDT 24
Peak memory 200776 kb
Host smart-e3bd682d-abe1-4abb-8399-2d3f407596bb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739843161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.2739843161
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.4185016440
Short name T963
Test name
Test status
Simulation time 115284573984 ps
CPU time 418.2 seconds
Started Jun 13 01:01:40 PM PDT 24
Finished Jun 13 01:08:39 PM PDT 24
Peak memory 200788 kb
Host smart-1ab619c7-9e23-489d-b80a-ec879bf025ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4185016440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.4185016440
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.1897636484
Short name T859
Test name
Test status
Simulation time 7523725483 ps
CPU time 14.66 seconds
Started Jun 13 01:01:41 PM PDT 24
Finished Jun 13 01:01:56 PM PDT 24
Peak memory 200100 kb
Host smart-ae76bb0a-1631-4c36-8dce-c428866d6287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897636484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.1897636484
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_perf.2039159717
Short name T256
Test name
Test status
Simulation time 32325125881 ps
CPU time 113.65 seconds
Started Jun 13 01:01:43 PM PDT 24
Finished Jun 13 01:03:37 PM PDT 24
Peak memory 200704 kb
Host smart-7201f98f-f456-43e7-b0f0-3ae75de42327
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2039159717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.2039159717
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.2048483893
Short name T1084
Test name
Test status
Simulation time 2655789459 ps
CPU time 18.79 seconds
Started Jun 13 01:01:39 PM PDT 24
Finished Jun 13 01:01:58 PM PDT 24
Peak memory 198900 kb
Host smart-ee0ab7e8-a90f-4793-b557-ae8927db2844
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2048483893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.2048483893
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.2768108182
Short name T547
Test name
Test status
Simulation time 26564535681 ps
CPU time 44.36 seconds
Started Jun 13 01:01:40 PM PDT 24
Finished Jun 13 01:02:25 PM PDT 24
Peak memory 200796 kb
Host smart-e3d68b3b-7b3a-40cb-b7c3-3a1bfbf8f1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768108182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.2768108182
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.882255289
Short name T425
Test name
Test status
Simulation time 31425536564 ps
CPU time 15.79 seconds
Started Jun 13 01:01:39 PM PDT 24
Finished Jun 13 01:01:55 PM PDT 24
Peak memory 196872 kb
Host smart-20c35ca0-dfdf-4591-8138-bc835e2e899b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882255289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.882255289
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.3641752685
Short name T305
Test name
Test status
Simulation time 10529429938 ps
CPU time 20.29 seconds
Started Jun 13 01:01:41 PM PDT 24
Finished Jun 13 01:02:01 PM PDT 24
Peak memory 200728 kb
Host smart-3739ab81-8469-4dfa-9cc7-47f2bd58f052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641752685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.3641752685
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.3715696908
Short name T614
Test name
Test status
Simulation time 1103646760 ps
CPU time 3.53 seconds
Started Jun 13 01:01:39 PM PDT 24
Finished Jun 13 01:01:43 PM PDT 24
Peak memory 199560 kb
Host smart-a427b868-316d-444c-bdd5-66fb6c595942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715696908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.3715696908
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.2891517788
Short name T112
Test name
Test status
Simulation time 32991798285 ps
CPU time 28.07 seconds
Started Jun 13 01:01:40 PM PDT 24
Finished Jun 13 01:02:09 PM PDT 24
Peak memory 200668 kb
Host smart-c2221ddc-02ba-4735-9245-f595d56240fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891517788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.2891517788
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.1588609182
Short name T10
Test name
Test status
Simulation time 13099121462 ps
CPU time 11.96 seconds
Started Jun 13 01:26:14 PM PDT 24
Finished Jun 13 01:26:26 PM PDT 24
Peak memory 200748 kb
Host smart-3851d7a5-30b6-43be-a56a-17880eb32d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588609182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.1588609182
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.1855791751
Short name T848
Test name
Test status
Simulation time 18097315567 ps
CPU time 28.74 seconds
Started Jun 13 01:06:12 PM PDT 24
Finished Jun 13 01:06:43 PM PDT 24
Peak memory 200660 kb
Host smart-b40c66d9-5896-476c-9fe8-d25e16fa52a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855791751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.1855791751
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.54610278
Short name T615
Test name
Test status
Simulation time 122093595256 ps
CPU time 36.14 seconds
Started Jun 13 01:36:39 PM PDT 24
Finished Jun 13 01:37:16 PM PDT 24
Peak memory 200828 kb
Host smart-c1f9ccb0-d781-416e-9937-1720683bfdaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54610278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.54610278
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.1290803220
Short name T611
Test name
Test status
Simulation time 93236412762 ps
CPU time 147.68 seconds
Started Jun 13 01:34:33 PM PDT 24
Finished Jun 13 01:37:01 PM PDT 24
Peak memory 200780 kb
Host smart-054383d8-2eea-47e0-a285-579a5c06cc56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290803220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.1290803220
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.3448162828
Short name T702
Test name
Test status
Simulation time 32165251575 ps
CPU time 52.69 seconds
Started Jun 13 01:17:11 PM PDT 24
Finished Jun 13 01:18:04 PM PDT 24
Peak memory 200752 kb
Host smart-378c7087-a793-4764-ac50-dc6571407c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448162828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.3448162828
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.193225027
Short name T750
Test name
Test status
Simulation time 22841026619 ps
CPU time 39.83 seconds
Started Jun 13 01:02:55 PM PDT 24
Finished Jun 13 01:03:36 PM PDT 24
Peak memory 200748 kb
Host smart-9e7e0774-2ecc-4cd8-b32f-e69edffb9858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193225027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.193225027
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.2158674471
Short name T800
Test name
Test status
Simulation time 79438510551 ps
CPU time 18.08 seconds
Started Jun 13 01:21:25 PM PDT 24
Finished Jun 13 01:21:44 PM PDT 24
Peak memory 200800 kb
Host smart-b345689b-697f-4971-8df5-b9f2c814e83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158674471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.2158674471
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.109114789
Short name T177
Test name
Test status
Simulation time 99841690203 ps
CPU time 14.86 seconds
Started Jun 13 02:08:19 PM PDT 24
Finished Jun 13 02:08:35 PM PDT 24
Peak memory 199556 kb
Host smart-d1a4fb15-4427-44a2-9341-97d1babf95d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109114789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.109114789
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.1481116720
Short name T624
Test name
Test status
Simulation time 34426627706 ps
CPU time 51.21 seconds
Started Jun 13 01:03:08 PM PDT 24
Finished Jun 13 01:04:00 PM PDT 24
Peak memory 200780 kb
Host smart-82f36c29-410d-48cf-aba6-d6e16b38f67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481116720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.1481116720
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.2748454159
Short name T571
Test name
Test status
Simulation time 26688057 ps
CPU time 0.56 seconds
Started Jun 13 01:01:50 PM PDT 24
Finished Jun 13 01:01:51 PM PDT 24
Peak memory 196340 kb
Host smart-1bd98cb4-bbd1-49a8-b518-aba0bf4bb2a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748454159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.2748454159
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.763265724
Short name T773
Test name
Test status
Simulation time 46572465979 ps
CPU time 14.69 seconds
Started Jun 13 01:01:38 PM PDT 24
Finished Jun 13 01:01:53 PM PDT 24
Peak memory 200796 kb
Host smart-b4a58f70-3cd9-4e49-9234-6b713f77cafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763265724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.763265724
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.4079007869
Short name T176
Test name
Test status
Simulation time 88728527468 ps
CPU time 44.07 seconds
Started Jun 13 01:01:40 PM PDT 24
Finished Jun 13 01:02:25 PM PDT 24
Peak memory 200744 kb
Host smart-cf54b3bc-9086-455c-9bfe-8ccb6b58258b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079007869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.4079007869
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.1862323602
Short name T125
Test name
Test status
Simulation time 45895128169 ps
CPU time 36.26 seconds
Started Jun 13 01:01:49 PM PDT 24
Finished Jun 13 01:02:26 PM PDT 24
Peak memory 200820 kb
Host smart-a26873ef-856b-43c3-899a-1215ac517b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862323602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.1862323602
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.2957495934
Short name T1037
Test name
Test status
Simulation time 7621913008 ps
CPU time 1.82 seconds
Started Jun 13 01:01:53 PM PDT 24
Finished Jun 13 01:01:56 PM PDT 24
Peak memory 198684 kb
Host smart-4c05a2f6-5735-4378-ac17-82c3f78efe25
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957495934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.2957495934
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.3319280536
Short name T606
Test name
Test status
Simulation time 103979214928 ps
CPU time 717 seconds
Started Jun 13 01:01:47 PM PDT 24
Finished Jun 13 01:13:44 PM PDT 24
Peak memory 200784 kb
Host smart-6dba1a66-dedd-459b-a5e6-edf20e63f1f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3319280536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.3319280536
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.1705252333
Short name T701
Test name
Test status
Simulation time 6633440325 ps
CPU time 5.87 seconds
Started Jun 13 01:01:47 PM PDT 24
Finished Jun 13 01:01:53 PM PDT 24
Peak memory 200484 kb
Host smart-9c0a7fba-7cb5-4d74-8844-2e901887b374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705252333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.1705252333
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_perf.4117269920
Short name T417
Test name
Test status
Simulation time 16900772385 ps
CPU time 146.14 seconds
Started Jun 13 01:01:50 PM PDT 24
Finished Jun 13 01:04:17 PM PDT 24
Peak memory 200776 kb
Host smart-e435bc58-58bf-44b7-9c3c-8c7d88a52ec6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4117269920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.4117269920
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.1649432604
Short name T1074
Test name
Test status
Simulation time 2507345494 ps
CPU time 4.35 seconds
Started Jun 13 01:01:45 PM PDT 24
Finished Jun 13 01:01:50 PM PDT 24
Peak memory 199904 kb
Host smart-e81fcad7-bea1-438c-aa20-2bd9e0d74c80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1649432604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.1649432604
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.1265601441
Short name T173
Test name
Test status
Simulation time 32440133344 ps
CPU time 17.1 seconds
Started Jun 13 01:01:49 PM PDT 24
Finished Jun 13 01:02:07 PM PDT 24
Peak memory 200784 kb
Host smart-02991043-dec8-452e-b244-e10dbe775ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265601441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.1265601441
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.2221287469
Short name T280
Test name
Test status
Simulation time 40924170678 ps
CPU time 58.88 seconds
Started Jun 13 01:01:46 PM PDT 24
Finished Jun 13 01:02:45 PM PDT 24
Peak memory 196768 kb
Host smart-55d76872-669f-45bd-8ff4-253f95e794d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221287469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.2221287469
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.2604452774
Short name T105
Test name
Test status
Simulation time 697261180 ps
CPU time 2.96 seconds
Started Jun 13 01:01:43 PM PDT 24
Finished Jun 13 01:01:46 PM PDT 24
Peak memory 200564 kb
Host smart-2c595959-faa5-46e4-b571-27c19ef4fcff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604452774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.2604452774
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.91922843
Short name T428
Test name
Test status
Simulation time 525805663871 ps
CPU time 51 seconds
Started Jun 13 01:01:49 PM PDT 24
Finished Jun 13 01:02:41 PM PDT 24
Peak memory 200712 kb
Host smart-0f2988e8-30ab-4203-8a21-671f7e34946c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91922843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.91922843
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.1484702307
Short name T48
Test name
Test status
Simulation time 28227779812 ps
CPU time 236.34 seconds
Started Jun 13 01:01:50 PM PDT 24
Finished Jun 13 01:05:47 PM PDT 24
Peak memory 216236 kb
Host smart-c40a10d1-e4e6-44ac-8ea3-6192c196306d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484702307 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.1484702307
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.1283761193
Short name T373
Test name
Test status
Simulation time 6666114063 ps
CPU time 13.84 seconds
Started Jun 13 01:01:48 PM PDT 24
Finished Jun 13 01:02:03 PM PDT 24
Peak memory 200568 kb
Host smart-477f7aef-42e7-42cf-bb89-5ef59aa1de2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283761193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.1283761193
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.1546441132
Short name T735
Test name
Test status
Simulation time 1626890543 ps
CPU time 3.61 seconds
Started Jun 13 01:01:38 PM PDT 24
Finished Jun 13 01:01:42 PM PDT 24
Peak memory 200720 kb
Host smart-0c16fd3a-9dee-4e55-8f7e-20105d37abd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546441132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.1546441132
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.717553783
Short name T403
Test name
Test status
Simulation time 18120907531 ps
CPU time 32.09 seconds
Started Jun 13 01:50:02 PM PDT 24
Finished Jun 13 01:50:36 PM PDT 24
Peak memory 200692 kb
Host smart-5d80fa1a-8b90-4591-9b2b-508da969cf1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717553783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.717553783
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.1977696943
Short name T251
Test name
Test status
Simulation time 50012161444 ps
CPU time 71.45 seconds
Started Jun 13 01:11:17 PM PDT 24
Finished Jun 13 01:12:29 PM PDT 24
Peak memory 200804 kb
Host smart-d330df36-9b7e-4ec0-9490-a10e1919ce32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977696943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.1977696943
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.4199836093
Short name T331
Test name
Test status
Simulation time 192694402925 ps
CPU time 111.89 seconds
Started Jun 13 01:29:04 PM PDT 24
Finished Jun 13 01:30:57 PM PDT 24
Peak memory 200792 kb
Host smart-a54d8df9-c838-4a43-8603-c10c91479d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199836093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.4199836093
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.1157969306
Short name T895
Test name
Test status
Simulation time 175046858912 ps
CPU time 92.21 seconds
Started Jun 13 02:08:45 PM PDT 24
Finished Jun 13 02:10:18 PM PDT 24
Peak memory 200764 kb
Host smart-f834cf9e-7f33-4e7c-9bb1-eb3b8649ea50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157969306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.1157969306
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.3615512094
Short name T179
Test name
Test status
Simulation time 16386481447 ps
CPU time 11.68 seconds
Started Jun 13 01:26:08 PM PDT 24
Finished Jun 13 01:26:21 PM PDT 24
Peak memory 200740 kb
Host smart-1477e5d9-fe5c-43eb-b06a-90979b43978c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615512094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.3615512094
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.2395696562
Short name T334
Test name
Test status
Simulation time 15942718493 ps
CPU time 10.71 seconds
Started Jun 13 01:26:15 PM PDT 24
Finished Jun 13 01:26:27 PM PDT 24
Peak memory 200796 kb
Host smart-3f865d6a-21a1-4df6-80a9-f502c148665c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395696562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.2395696562
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.207846463
Short name T253
Test name
Test status
Simulation time 90939913493 ps
CPU time 141.34 seconds
Started Jun 13 01:53:10 PM PDT 24
Finished Jun 13 01:55:32 PM PDT 24
Peak memory 200764 kb
Host smart-4337b16a-1145-4f91-bc12-ed82bea1507b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207846463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.207846463
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.1833894126
Short name T751
Test name
Test status
Simulation time 103397122543 ps
CPU time 156.06 seconds
Started Jun 13 01:27:14 PM PDT 24
Finished Jun 13 01:29:51 PM PDT 24
Peak memory 200808 kb
Host smart-d19d58eb-b607-4090-a583-734a0f60a360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833894126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.1833894126
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.544223446
Short name T1069
Test name
Test status
Simulation time 12657032 ps
CPU time 0.54 seconds
Started Jun 13 01:01:48 PM PDT 24
Finished Jun 13 01:01:49 PM PDT 24
Peak memory 196096 kb
Host smart-7f4e2268-0654-439d-add5-54c1d6329b33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544223446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.544223446
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.3335579054
Short name T923
Test name
Test status
Simulation time 44050500827 ps
CPU time 16.73 seconds
Started Jun 13 01:01:48 PM PDT 24
Finished Jun 13 01:02:06 PM PDT 24
Peak memory 200708 kb
Host smart-f414894e-1bbe-4551-ab04-b3531369dce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335579054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.3335579054
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.4073839486
Short name T150
Test name
Test status
Simulation time 23966720688 ps
CPU time 19.99 seconds
Started Jun 13 01:01:48 PM PDT 24
Finished Jun 13 01:02:08 PM PDT 24
Peak memory 200664 kb
Host smart-71ebdca3-38ec-49b9-b2fa-d2ad88dc9858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073839486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.4073839486
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.2559616258
Short name T223
Test name
Test status
Simulation time 12269762595 ps
CPU time 18.07 seconds
Started Jun 13 01:01:48 PM PDT 24
Finished Jun 13 01:02:07 PM PDT 24
Peak memory 200768 kb
Host smart-eb40aac6-63a0-4572-8213-fddda4488ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559616258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.2559616258
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.4072099820
Short name T674
Test name
Test status
Simulation time 24291700653 ps
CPU time 40.8 seconds
Started Jun 13 01:01:50 PM PDT 24
Finished Jun 13 01:02:32 PM PDT 24
Peak memory 200516 kb
Host smart-c346a199-8d0c-4ada-b10e-5328e3b3c305
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072099820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.4072099820
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.3199190029
Short name T455
Test name
Test status
Simulation time 146235245825 ps
CPU time 1124.28 seconds
Started Jun 13 01:01:51 PM PDT 24
Finished Jun 13 01:20:36 PM PDT 24
Peak memory 200780 kb
Host smart-f9f65196-a56e-423e-98bd-92b836e12d84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3199190029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.3199190029
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.3300577519
Short name T823
Test name
Test status
Simulation time 3359937532 ps
CPU time 7.12 seconds
Started Jun 13 01:01:47 PM PDT 24
Finished Jun 13 01:01:54 PM PDT 24
Peak memory 199948 kb
Host smart-494f28ba-82ce-4d8f-976b-4d3566538a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300577519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.3300577519
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.1947498324
Short name T733
Test name
Test status
Simulation time 36209340808 ps
CPU time 15 seconds
Started Jun 13 01:01:48 PM PDT 24
Finished Jun 13 01:02:04 PM PDT 24
Peak memory 199252 kb
Host smart-736b430c-3f57-424b-8365-5a60e136ce1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947498324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.1947498324
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.2531704190
Short name T1079
Test name
Test status
Simulation time 15851492642 ps
CPU time 670.39 seconds
Started Jun 13 01:01:48 PM PDT 24
Finished Jun 13 01:13:00 PM PDT 24
Peak memory 200256 kb
Host smart-5cb92c88-b3d3-4a78-a14f-c377b8914711
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2531704190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.2531704190
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.2546857717
Short name T804
Test name
Test status
Simulation time 5490850669 ps
CPU time 10.73 seconds
Started Jun 13 01:01:49 PM PDT 24
Finished Jun 13 01:02:01 PM PDT 24
Peak memory 199628 kb
Host smart-3971c904-e28d-4e4d-af89-610283f9b036
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2546857717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.2546857717
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.435590522
Short name T472
Test name
Test status
Simulation time 116748500003 ps
CPU time 44.74 seconds
Started Jun 13 01:01:51 PM PDT 24
Finished Jun 13 01:02:36 PM PDT 24
Peak memory 200716 kb
Host smart-ed2ef9f6-10b2-48cd-9501-91d29448f166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435590522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.435590522
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.1365634767
Short name T308
Test name
Test status
Simulation time 1961201251 ps
CPU time 3.63 seconds
Started Jun 13 01:01:48 PM PDT 24
Finished Jun 13 01:01:52 PM PDT 24
Peak memory 196156 kb
Host smart-3cae0168-5409-45ce-ace3-71f86ae927dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365634767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.1365634767
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.1557872181
Short name T270
Test name
Test status
Simulation time 270995186 ps
CPU time 1.45 seconds
Started Jun 13 01:01:47 PM PDT 24
Finished Jun 13 01:01:49 PM PDT 24
Peak memory 198920 kb
Host smart-cd272bff-fe01-451f-833e-8c1b7729432f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557872181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.1557872181
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.424885716
Short name T979
Test name
Test status
Simulation time 69279848719 ps
CPU time 148.73 seconds
Started Jun 13 01:01:48 PM PDT 24
Finished Jun 13 01:04:18 PM PDT 24
Peak memory 200576 kb
Host smart-015b21c3-03ad-4e98-86f0-a42cb280231e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424885716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.424885716
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.437360173
Short name T301
Test name
Test status
Simulation time 1758335174 ps
CPU time 2.91 seconds
Started Jun 13 01:01:46 PM PDT 24
Finished Jun 13 01:01:50 PM PDT 24
Peak memory 199128 kb
Host smart-bc59746e-7ef7-4cd9-95fd-95f278f16bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437360173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.437360173
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.1765921808
Short name T502
Test name
Test status
Simulation time 56003494839 ps
CPU time 124.94 seconds
Started Jun 13 01:01:47 PM PDT 24
Finished Jun 13 01:03:52 PM PDT 24
Peak memory 200832 kb
Host smart-79b9ffaf-09ba-46db-8694-979ef95760d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765921808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.1765921808
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.2322351230
Short name T660
Test name
Test status
Simulation time 41004074059 ps
CPU time 31.92 seconds
Started Jun 13 01:03:05 PM PDT 24
Finished Jun 13 01:03:37 PM PDT 24
Peak memory 200772 kb
Host smart-23216c94-6968-476d-afed-157c620ae0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322351230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.2322351230
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.1606103736
Short name T605
Test name
Test status
Simulation time 110275270500 ps
CPU time 74.85 seconds
Started Jun 13 01:36:13 PM PDT 24
Finished Jun 13 01:37:28 PM PDT 24
Peak memory 200824 kb
Host smart-195b3cff-6bae-465d-9696-125d6bd30a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606103736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.1606103736
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.2097924018
Short name T925
Test name
Test status
Simulation time 33385032971 ps
CPU time 15.52 seconds
Started Jun 13 01:03:00 PM PDT 24
Finished Jun 13 01:03:16 PM PDT 24
Peak memory 200692 kb
Host smart-0e66281d-5134-44f4-9ac3-8aed992c2010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097924018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.2097924018
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.915132885
Short name T500
Test name
Test status
Simulation time 122594898007 ps
CPU time 184.72 seconds
Started Jun 13 02:27:03 PM PDT 24
Finished Jun 13 02:30:08 PM PDT 24
Peak memory 200760 kb
Host smart-5301a763-74e7-461e-8cec-60742ad2853d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915132885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.915132885
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.1995197747
Short name T641
Test name
Test status
Simulation time 48177382419 ps
CPU time 138.13 seconds
Started Jun 13 02:00:14 PM PDT 24
Finished Jun 13 02:02:33 PM PDT 24
Peak memory 200840 kb
Host smart-3c2a9260-4be4-4c72-81f2-8fc7d8750421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995197747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.1995197747
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.675116985
Short name T259
Test name
Test status
Simulation time 62127192724 ps
CPU time 40.67 seconds
Started Jun 13 02:23:40 PM PDT 24
Finished Jun 13 02:24:21 PM PDT 24
Peak memory 200848 kb
Host smart-58dfba50-1618-43c1-86d7-18b86e81cb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675116985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.675116985
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.3480006490
Short name T807
Test name
Test status
Simulation time 162126919643 ps
CPU time 67.29 seconds
Started Jun 13 01:59:51 PM PDT 24
Finished Jun 13 02:00:59 PM PDT 24
Peak memory 200808 kb
Host smart-bd6d72d8-def7-425a-98f6-6314f59033fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480006490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.3480006490
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.230854164
Short name T198
Test name
Test status
Simulation time 47524469798 ps
CPU time 208.79 seconds
Started Jun 13 01:03:05 PM PDT 24
Finished Jun 13 01:06:35 PM PDT 24
Peak memory 200728 kb
Host smart-e9d9ef46-79af-4d4b-b439-bf25e8e95f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230854164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.230854164
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.3215010832
Short name T33
Test name
Test status
Simulation time 90073539674 ps
CPU time 180.9 seconds
Started Jun 13 02:17:09 PM PDT 24
Finished Jun 13 02:20:16 PM PDT 24
Peak memory 200832 kb
Host smart-089c1f33-5e89-4435-87c2-f60be812c26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215010832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.3215010832
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.1716986625
Short name T356
Test name
Test status
Simulation time 22285858 ps
CPU time 0.58 seconds
Started Jun 13 01:01:56 PM PDT 24
Finished Jun 13 01:01:58 PM PDT 24
Peak memory 194996 kb
Host smart-62b810c7-3886-42de-9964-188cf14e02ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716986625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.1716986625
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.1525406187
Short name T642
Test name
Test status
Simulation time 48821211268 ps
CPU time 78.56 seconds
Started Jun 13 01:01:48 PM PDT 24
Finished Jun 13 01:03:08 PM PDT 24
Peak memory 200716 kb
Host smart-61b51fea-a197-40f1-a1c8-37c4db0371e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525406187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.1525406187
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.3920444368
Short name T246
Test name
Test status
Simulation time 231729274584 ps
CPU time 210.19 seconds
Started Jun 13 01:01:46 PM PDT 24
Finished Jun 13 01:05:17 PM PDT 24
Peak memory 200680 kb
Host smart-136a8500-2836-460d-8034-cd134fb98978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920444368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.3920444368
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.87202373
Short name T926
Test name
Test status
Simulation time 53567079576 ps
CPU time 23.06 seconds
Started Jun 13 01:01:51 PM PDT 24
Finished Jun 13 01:02:15 PM PDT 24
Peak memory 200696 kb
Host smart-db3352fe-7b4f-4a7c-9140-d5190b4cb048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87202373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.87202373
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.1886342212
Short name T367
Test name
Test status
Simulation time 18339895029 ps
CPU time 34.53 seconds
Started Jun 13 01:01:49 PM PDT 24
Finished Jun 13 01:02:24 PM PDT 24
Peak memory 200708 kb
Host smart-92926a77-aee6-4900-959f-75453afa4153
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886342212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.1886342212
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.1487986677
Short name T390
Test name
Test status
Simulation time 78200062976 ps
CPU time 342.71 seconds
Started Jun 13 01:02:04 PM PDT 24
Finished Jun 13 01:07:48 PM PDT 24
Peak memory 200940 kb
Host smart-3d4ec08d-4a8f-4a83-a432-521d0da5173f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1487986677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.1487986677
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.4097666446
Short name T11
Test name
Test status
Simulation time 4477903437 ps
CPU time 9.86 seconds
Started Jun 13 01:01:55 PM PDT 24
Finished Jun 13 01:02:06 PM PDT 24
Peak memory 200120 kb
Host smart-45a1093a-90de-428b-84d0-3d766706d61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097666446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.4097666446
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_perf.2100235743
Short name T865
Test name
Test status
Simulation time 12983622153 ps
CPU time 89.32 seconds
Started Jun 13 01:01:55 PM PDT 24
Finished Jun 13 01:03:26 PM PDT 24
Peak memory 200744 kb
Host smart-c00913fb-5b20-456e-ab81-8a51e096cc94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2100235743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.2100235743
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.3581196815
Short name T1080
Test name
Test status
Simulation time 1913199056 ps
CPU time 3.31 seconds
Started Jun 13 01:01:50 PM PDT 24
Finished Jun 13 01:01:54 PM PDT 24
Peak memory 198684 kb
Host smart-fda78aae-3d43-4718-bbc5-32b90572b3fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3581196815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.3581196815
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.1980140489
Short name T874
Test name
Test status
Simulation time 122841316770 ps
CPU time 14.68 seconds
Started Jun 13 01:01:55 PM PDT 24
Finished Jun 13 01:02:11 PM PDT 24
Peak memory 200760 kb
Host smart-476a17a7-103d-4afb-849f-a4b70ca40f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980140489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.1980140489
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.2989696754
Short name T869
Test name
Test status
Simulation time 3205731424 ps
CPU time 1.9 seconds
Started Jun 13 01:02:03 PM PDT 24
Finished Jun 13 01:02:06 PM PDT 24
Peak memory 197820 kb
Host smart-0278437c-6cfe-43c5-b3b8-fadbbf378095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989696754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.2989696754
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.1214306720
Short name T907
Test name
Test status
Simulation time 444677553 ps
CPU time 1.77 seconds
Started Jun 13 01:01:51 PM PDT 24
Finished Jun 13 01:01:53 PM PDT 24
Peak memory 200604 kb
Host smart-f9c28c5c-cac1-4300-9390-79d57981b099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214306720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.1214306720
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.208874960
Short name T825
Test name
Test status
Simulation time 1867348966 ps
CPU time 3.11 seconds
Started Jun 13 01:01:55 PM PDT 24
Finished Jun 13 01:01:59 PM PDT 24
Peak memory 200328 kb
Host smart-64a4e743-6d6b-4461-8797-c6d87d9e2499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208874960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.208874960
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.1017621292
Short name T188
Test name
Test status
Simulation time 154149571281 ps
CPU time 31.65 seconds
Started Jun 13 01:03:00 PM PDT 24
Finished Jun 13 01:03:32 PM PDT 24
Peak memory 200792 kb
Host smart-76a02fa0-05bc-49cd-89c8-66cc2f2d65dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017621292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.1017621292
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.2491230384
Short name T936
Test name
Test status
Simulation time 14761053285 ps
CPU time 12.79 seconds
Started Jun 13 02:17:00 PM PDT 24
Finished Jun 13 02:17:19 PM PDT 24
Peak memory 200760 kb
Host smart-be50bd22-df5c-4966-8c28-7515c777b272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491230384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.2491230384
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.2375226642
Short name T195
Test name
Test status
Simulation time 69702958092 ps
CPU time 108.06 seconds
Started Jun 13 01:48:22 PM PDT 24
Finished Jun 13 01:50:12 PM PDT 24
Peak memory 200668 kb
Host smart-863957e0-b09c-480c-8382-6c8923ee371d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375226642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.2375226642
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.2362091316
Short name T232
Test name
Test status
Simulation time 37339008129 ps
CPU time 18.06 seconds
Started Jun 13 01:11:15 PM PDT 24
Finished Jun 13 01:11:34 PM PDT 24
Peak memory 200736 kb
Host smart-4cf58406-aeec-4dcb-9fa4-436b22fc2af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362091316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.2362091316
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.331749081
Short name T5
Test name
Test status
Simulation time 157271167288 ps
CPU time 49.06 seconds
Started Jun 13 01:30:01 PM PDT 24
Finished Jun 13 01:30:51 PM PDT 24
Peak memory 200836 kb
Host smart-98033e2c-91a5-4eec-93b5-54e5b8d64971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331749081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.331749081
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.1573531047
Short name T592
Test name
Test status
Simulation time 141987569939 ps
CPU time 55.99 seconds
Started Jun 13 02:00:33 PM PDT 24
Finished Jun 13 02:01:30 PM PDT 24
Peak memory 200760 kb
Host smart-4df1cb63-7cd3-445a-a02e-b855e741b9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573531047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.1573531047
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.1500815671
Short name T319
Test name
Test status
Simulation time 11952115869 ps
CPU time 10.98 seconds
Started Jun 13 02:37:38 PM PDT 24
Finished Jun 13 02:37:50 PM PDT 24
Peak memory 200768 kb
Host smart-0daaca5b-4431-4694-a54f-12ccc09e08bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500815671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.1500815671
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.116693381
Short name T560
Test name
Test status
Simulation time 6745647034 ps
CPU time 12.35 seconds
Started Jun 13 01:03:05 PM PDT 24
Finished Jun 13 01:03:18 PM PDT 24
Peak memory 200800 kb
Host smart-f71e1a40-5a47-4ff6-949b-fc8e692fe27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116693381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.116693381
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.3363640404
Short name T570
Test name
Test status
Simulation time 33977776487 ps
CPU time 21.23 seconds
Started Jun 13 01:03:00 PM PDT 24
Finished Jun 13 01:03:22 PM PDT 24
Peak memory 200732 kb
Host smart-8b616b5f-c05d-4e53-bdde-21dec864bc9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363640404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.3363640404
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.4169407130
Short name T724
Test name
Test status
Simulation time 14103469 ps
CPU time 0.54 seconds
Started Jun 13 01:01:57 PM PDT 24
Finished Jun 13 01:01:58 PM PDT 24
Peak memory 196108 kb
Host smart-c9aeb0cd-f282-4b08-8e67-d6f035186bea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169407130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.4169407130
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.4047404537
Short name T1041
Test name
Test status
Simulation time 68163826194 ps
CPU time 50.75 seconds
Started Jun 13 01:01:54 PM PDT 24
Finished Jun 13 01:02:46 PM PDT 24
Peak memory 200720 kb
Host smart-b6cf6f3f-6872-41ba-a035-cbbde0b7b2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047404537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.4047404537
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.2992135186
Short name T520
Test name
Test status
Simulation time 110836516067 ps
CPU time 164.82 seconds
Started Jun 13 01:01:56 PM PDT 24
Finished Jun 13 01:04:42 PM PDT 24
Peak memory 200800 kb
Host smart-3d7d57f9-cdcb-43bf-af51-8f41b76a8f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992135186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.2992135186
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.805688127
Short name T299
Test name
Test status
Simulation time 119870023001 ps
CPU time 169.63 seconds
Started Jun 13 01:01:53 PM PDT 24
Finished Jun 13 01:04:44 PM PDT 24
Peak memory 200724 kb
Host smart-ce65c8cd-c3d0-4574-b1d2-e000883953c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805688127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.805688127
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.1422790982
Short name T466
Test name
Test status
Simulation time 65090249595 ps
CPU time 27.23 seconds
Started Jun 13 01:01:53 PM PDT 24
Finished Jun 13 01:02:21 PM PDT 24
Peak memory 200764 kb
Host smart-1ed70958-fedd-4503-b770-1f0e3ee2c455
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422790982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.1422790982
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.1089144722
Short name T244
Test name
Test status
Simulation time 86878425988 ps
CPU time 499.42 seconds
Started Jun 13 01:02:04 PM PDT 24
Finished Jun 13 01:10:24 PM PDT 24
Peak memory 200964 kb
Host smart-44b1b33f-5cd8-41e0-8340-089588af36aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1089144722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.1089144722
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.2372680261
Short name T354
Test name
Test status
Simulation time 2917101682 ps
CPU time 2.26 seconds
Started Jun 13 01:01:56 PM PDT 24
Finished Jun 13 01:01:59 PM PDT 24
Peak memory 199888 kb
Host smart-83905690-0bf8-4df1-a99d-7e294e565ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372680261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.2372680261
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_perf.1602033646
Short name T603
Test name
Test status
Simulation time 17256173231 ps
CPU time 784.02 seconds
Started Jun 13 01:01:54 PM PDT 24
Finished Jun 13 01:14:59 PM PDT 24
Peak memory 200800 kb
Host smart-b86bd692-2610-4535-a363-a24278742e15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1602033646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.1602033646
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.2323230428
Short name T954
Test name
Test status
Simulation time 7822819555 ps
CPU time 32.9 seconds
Started Jun 13 01:01:56 PM PDT 24
Finished Jun 13 01:02:30 PM PDT 24
Peak memory 200712 kb
Host smart-e218f503-3eac-4ae0-b6e8-a9642bf871e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2323230428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.2323230428
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.169614289
Short name T442
Test name
Test status
Simulation time 34481857900 ps
CPU time 17.61 seconds
Started Jun 13 01:01:55 PM PDT 24
Finished Jun 13 01:02:15 PM PDT 24
Peak memory 200744 kb
Host smart-68fac613-e897-4c21-b543-b3bd0fa72dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169614289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.169614289
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.1823020207
Short name T351
Test name
Test status
Simulation time 1519466904 ps
CPU time 1.89 seconds
Started Jun 13 01:01:57 PM PDT 24
Finished Jun 13 01:02:00 PM PDT 24
Peak memory 196060 kb
Host smart-6be42e59-2680-489d-a5d8-8d24b109b8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823020207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.1823020207
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.885510450
Short name T698
Test name
Test status
Simulation time 332331366 ps
CPU time 1.34 seconds
Started Jun 13 01:02:04 PM PDT 24
Finished Jun 13 01:02:06 PM PDT 24
Peak memory 199804 kb
Host smart-92610f03-4f89-41c2-b15d-527dfe47afda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885510450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.885510450
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.3410060542
Short name T958
Test name
Test status
Simulation time 185844592255 ps
CPU time 71.23 seconds
Started Jun 13 01:01:56 PM PDT 24
Finished Jun 13 01:03:09 PM PDT 24
Peak memory 200664 kb
Host smart-7ce2530b-dcf9-4acb-a050-f7197ae1a7b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410060542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.3410060542
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.2397719888
Short name T866
Test name
Test status
Simulation time 24876131509 ps
CPU time 681.21 seconds
Started Jun 13 01:01:53 PM PDT 24
Finished Jun 13 01:13:15 PM PDT 24
Peak memory 217236 kb
Host smart-0bb434d5-61b6-431b-8a3b-08299c052373
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397719888 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.2397719888
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.4097804750
Short name T436
Test name
Test status
Simulation time 1774958347 ps
CPU time 1.55 seconds
Started Jun 13 01:02:05 PM PDT 24
Finished Jun 13 01:02:07 PM PDT 24
Peak memory 199216 kb
Host smart-ca259bd5-25c4-409b-b13d-433c13d84372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097804750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.4097804750
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.2396068770
Short name T310
Test name
Test status
Simulation time 186957902664 ps
CPU time 23.04 seconds
Started Jun 13 01:02:00 PM PDT 24
Finished Jun 13 01:02:24 PM PDT 24
Peak memory 200692 kb
Host smart-5f75cefc-f2e2-4b59-a294-d81b9cc54dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396068770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.2396068770
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.654321806
Short name T100
Test name
Test status
Simulation time 54115605275 ps
CPU time 83.2 seconds
Started Jun 13 01:31:05 PM PDT 24
Finished Jun 13 01:32:28 PM PDT 24
Peak memory 200780 kb
Host smart-a86f948c-c3b7-43f3-9e8f-be776d1041a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654321806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.654321806
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.3277772287
Short name T157
Test name
Test status
Simulation time 66869999329 ps
CPU time 28.89 seconds
Started Jun 13 01:29:54 PM PDT 24
Finished Jun 13 01:30:23 PM PDT 24
Peak memory 200816 kb
Host smart-4f783f31-165e-4c09-ac3c-89d18890f645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277772287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.3277772287
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.2703878195
Short name T133
Test name
Test status
Simulation time 24576007264 ps
CPU time 38.26 seconds
Started Jun 13 01:57:10 PM PDT 24
Finished Jun 13 01:57:50 PM PDT 24
Peak memory 200748 kb
Host smart-9f47f32d-879e-4514-97b2-d9dd4c97abd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703878195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.2703878195
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.428563797
Short name T821
Test name
Test status
Simulation time 124742363788 ps
CPU time 55 seconds
Started Jun 13 01:24:17 PM PDT 24
Finished Jun 13 01:25:12 PM PDT 24
Peak memory 200780 kb
Host smart-52e03751-12d7-4bd8-9ae0-daf2cc405e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428563797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.428563797
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.527546026
Short name T934
Test name
Test status
Simulation time 31298274886 ps
CPU time 22.98 seconds
Started Jun 13 01:29:25 PM PDT 24
Finished Jun 13 01:29:50 PM PDT 24
Peak memory 200804 kb
Host smart-383726e1-9e63-4270-94af-8259ad5ddec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527546026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.527546026
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.1841897234
Short name T132
Test name
Test status
Simulation time 16280135626 ps
CPU time 18.68 seconds
Started Jun 13 01:24:04 PM PDT 24
Finished Jun 13 01:24:24 PM PDT 24
Peak memory 200840 kb
Host smart-de78e9f3-a391-433d-b2f8-61bc29079453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841897234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.1841897234
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.2867347866
Short name T795
Test name
Test status
Simulation time 172746220472 ps
CPU time 113.11 seconds
Started Jun 13 01:03:02 PM PDT 24
Finished Jun 13 01:04:56 PM PDT 24
Peak memory 200552 kb
Host smart-b85858e3-177e-40ea-8d1d-b0cc56fecd99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867347866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.2867347866
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.3655979540
Short name T166
Test name
Test status
Simulation time 49308738895 ps
CPU time 32.08 seconds
Started Jun 13 01:28:10 PM PDT 24
Finished Jun 13 01:28:42 PM PDT 24
Peak memory 200752 kb
Host smart-aa966447-7ced-4695-99f0-5d9fefc8c950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655979540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.3655979540
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.879755004
Short name T366
Test name
Test status
Simulation time 91840921435 ps
CPU time 39.9 seconds
Started Jun 13 01:14:20 PM PDT 24
Finished Jun 13 01:15:01 PM PDT 24
Peak memory 200792 kb
Host smart-60b9d732-c50f-4cce-a88b-8488d09bd19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879755004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.879755004
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.1798172521
Short name T838
Test name
Test status
Simulation time 102943149545 ps
CPU time 152.11 seconds
Started Jun 13 02:14:45 PM PDT 24
Finished Jun 13 02:17:18 PM PDT 24
Peak memory 200788 kb
Host smart-d6730a85-d34c-43cf-b907-a88f2c98f06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798172521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.1798172521
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.3309530394
Short name T352
Test name
Test status
Simulation time 35564918 ps
CPU time 0.57 seconds
Started Jun 13 01:02:00 PM PDT 24
Finished Jun 13 01:02:01 PM PDT 24
Peak memory 195540 kb
Host smart-5fab932c-0e99-496e-a42e-dd4e8522ae1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309530394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.3309530394
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.3927671734
Short name T142
Test name
Test status
Simulation time 117511639869 ps
CPU time 246.07 seconds
Started Jun 13 01:01:57 PM PDT 24
Finished Jun 13 01:06:05 PM PDT 24
Peak memory 200688 kb
Host smart-7afd96e8-12b4-42ef-b102-9f213177bd42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927671734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.3927671734
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.180672339
Short name T1039
Test name
Test status
Simulation time 155808077087 ps
CPU time 158.39 seconds
Started Jun 13 01:01:55 PM PDT 24
Finished Jun 13 01:04:34 PM PDT 24
Peak memory 200712 kb
Host smart-1b387c48-bfc2-4524-bb8d-edaca5c60bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180672339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.180672339
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.796105142
Short name T250
Test name
Test status
Simulation time 110111033396 ps
CPU time 30.54 seconds
Started Jun 13 01:01:55 PM PDT 24
Finished Jun 13 01:02:27 PM PDT 24
Peak memory 200724 kb
Host smart-a4c89fbc-913e-4977-aa7f-f336da8e95ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796105142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.796105142
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.1142220060
Short name T826
Test name
Test status
Simulation time 68302665102 ps
CPU time 377.6 seconds
Started Jun 13 01:02:04 PM PDT 24
Finished Jun 13 01:08:22 PM PDT 24
Peak memory 200708 kb
Host smart-76453a97-112d-407b-85fb-cdf04b4c9f9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1142220060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.1142220060
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.2285144542
Short name T683
Test name
Test status
Simulation time 5852443456 ps
CPU time 11.1 seconds
Started Jun 13 01:02:01 PM PDT 24
Finished Jun 13 01:02:14 PM PDT 24
Peak memory 199320 kb
Host smart-cd5925a0-00ef-4ce4-8c5a-999937c62294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285144542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.2285144542
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_perf.1271808315
Short name T501
Test name
Test status
Simulation time 12264315666 ps
CPU time 378.72 seconds
Started Jun 13 01:02:02 PM PDT 24
Finished Jun 13 01:08:22 PM PDT 24
Peak memory 200704 kb
Host smart-ef4447c9-b21e-4080-8479-139b0876f410
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1271808315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.1271808315
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.2091634119
Short name T729
Test name
Test status
Simulation time 2020588661 ps
CPU time 9.82 seconds
Started Jun 13 01:01:55 PM PDT 24
Finished Jun 13 01:02:07 PM PDT 24
Peak memory 199708 kb
Host smart-e314bae2-0273-41af-ba8a-15ec06309eab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2091634119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.2091634119
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.3169074160
Short name T927
Test name
Test status
Simulation time 75484612426 ps
CPU time 106.54 seconds
Started Jun 13 01:02:02 PM PDT 24
Finished Jun 13 01:03:49 PM PDT 24
Peak memory 200720 kb
Host smart-3b5abfd4-76a5-40f9-94b8-e255aed90552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169074160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.3169074160
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.1537924739
Short name T589
Test name
Test status
Simulation time 2145034895 ps
CPU time 2.24 seconds
Started Jun 13 01:01:55 PM PDT 24
Finished Jun 13 01:01:57 PM PDT 24
Peak memory 196160 kb
Host smart-64d9927c-47e9-469d-b5f0-d988b6794f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537924739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.1537924739
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.3913062289
Short name T1060
Test name
Test status
Simulation time 314247446 ps
CPU time 1.1 seconds
Started Jun 13 01:01:56 PM PDT 24
Finished Jun 13 01:01:58 PM PDT 24
Peak memory 199404 kb
Host smart-bd760b18-3c06-4abc-b47d-4cd607468928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913062289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.3913062289
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.2745901192
Short name T106
Test name
Test status
Simulation time 1325743018 ps
CPU time 4.34 seconds
Started Jun 13 01:02:01 PM PDT 24
Finished Jun 13 01:02:07 PM PDT 24
Peak memory 199564 kb
Host smart-6b2c8847-5ea0-4c92-aafb-f54f91873374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745901192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.2745901192
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.3137093306
Short name T844
Test name
Test status
Simulation time 110979356178 ps
CPU time 109.52 seconds
Started Jun 13 01:01:55 PM PDT 24
Finished Jun 13 01:03:46 PM PDT 24
Peak memory 200752 kb
Host smart-677b4f5e-8401-4ba1-ad59-16d3c372eec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137093306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.3137093306
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.947753870
Short name T265
Test name
Test status
Simulation time 16860801017 ps
CPU time 14.78 seconds
Started Jun 13 01:39:40 PM PDT 24
Finished Jun 13 01:39:56 PM PDT 24
Peak memory 200808 kb
Host smart-b7672957-6191-4505-bae8-b6bd83796ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947753870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.947753870
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.2091419843
Short name T391
Test name
Test status
Simulation time 14611485393 ps
CPU time 12 seconds
Started Jun 13 01:23:21 PM PDT 24
Finished Jun 13 01:23:35 PM PDT 24
Peak memory 200748 kb
Host smart-33db0ad6-8b50-479a-bebc-b99be97161bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091419843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.2091419843
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.626844636
Short name T215
Test name
Test status
Simulation time 166343501586 ps
CPU time 75.71 seconds
Started Jun 13 01:03:02 PM PDT 24
Finished Jun 13 01:04:18 PM PDT 24
Peak memory 200728 kb
Host smart-d7d196fb-99ab-44ab-9767-eeb791bade4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626844636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.626844636
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.529387736
Short name T911
Test name
Test status
Simulation time 11588517041 ps
CPU time 19.55 seconds
Started Jun 13 01:48:16 PM PDT 24
Finished Jun 13 01:48:36 PM PDT 24
Peak memory 200552 kb
Host smart-d9270d83-3895-495f-8758-cf87755bdff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529387736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.529387736
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.2434779701
Short name T233
Test name
Test status
Simulation time 87312899284 ps
CPU time 159.52 seconds
Started Jun 13 01:35:19 PM PDT 24
Finished Jun 13 01:37:59 PM PDT 24
Peak memory 200820 kb
Host smart-caa52975-029c-469f-84ad-972321f43d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434779701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.2434779701
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.3313765797
Short name T65
Test name
Test status
Simulation time 120160151576 ps
CPU time 50.49 seconds
Started Jun 13 02:02:35 PM PDT 24
Finished Jun 13 02:03:28 PM PDT 24
Peak memory 200388 kb
Host smart-15ff458d-6630-4716-8bd4-3bfea3b7f4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313765797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.3313765797
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.2455702383
Short name T692
Test name
Test status
Simulation time 31082245827 ps
CPU time 43.62 seconds
Started Jun 13 01:03:00 PM PDT 24
Finished Jun 13 01:03:45 PM PDT 24
Peak memory 200724 kb
Host smart-cd530657-6406-44c7-ae49-54f199e2a02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455702383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.2455702383
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.2411207195
Short name T997
Test name
Test status
Simulation time 105231459856 ps
CPU time 148.58 seconds
Started Jun 13 01:46:01 PM PDT 24
Finished Jun 13 01:48:31 PM PDT 24
Peak memory 200820 kb
Host smart-6bf19085-1387-4a9f-9114-5be3eb6abca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411207195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.2411207195
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.2235393329
Short name T965
Test name
Test status
Simulation time 26274989 ps
CPU time 0.57 seconds
Started Jun 13 01:02:13 PM PDT 24
Finished Jun 13 01:02:13 PM PDT 24
Peak memory 196364 kb
Host smart-34abd063-d366-44f1-b088-8999be2f17ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235393329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.2235393329
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.4147711528
Short name T1066
Test name
Test status
Simulation time 8459495958 ps
CPU time 1.94 seconds
Started Jun 13 01:02:04 PM PDT 24
Finished Jun 13 01:02:07 PM PDT 24
Peak memory 199504 kb
Host smart-7e926387-d560-44c9-8511-a47d85a2154d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147711528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.4147711528
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.432968530
Short name T257
Test name
Test status
Simulation time 54646557377 ps
CPU time 38.2 seconds
Started Jun 13 01:02:06 PM PDT 24
Finished Jun 13 01:02:45 PM PDT 24
Peak memory 200788 kb
Host smart-bfac4843-3bd6-48d9-af35-d86ead8e374a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432968530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.432968530
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.1183506553
Short name T670
Test name
Test status
Simulation time 15949391279 ps
CPU time 11.22 seconds
Started Jun 13 01:02:02 PM PDT 24
Finished Jun 13 01:02:14 PM PDT 24
Peak memory 200500 kb
Host smart-2788e318-cc38-4f01-8e7e-6ad23256ff52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183506553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.1183506553
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.1697806258
Short name T1026
Test name
Test status
Simulation time 149637703628 ps
CPU time 63.18 seconds
Started Jun 13 01:02:02 PM PDT 24
Finished Jun 13 01:03:06 PM PDT 24
Peak memory 200740 kb
Host smart-bc73077b-caac-4577-aea1-436cd804c909
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697806258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.1697806258
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.1326729127
Short name T422
Test name
Test status
Simulation time 78738477904 ps
CPU time 112.6 seconds
Started Jun 13 01:02:10 PM PDT 24
Finished Jun 13 01:04:03 PM PDT 24
Peak memory 200724 kb
Host smart-bed7ddb4-4828-4c0a-a373-1c7e8706b765
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1326729127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.1326729127
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.370230030
Short name T1028
Test name
Test status
Simulation time 7333840820 ps
CPU time 2.01 seconds
Started Jun 13 01:02:13 PM PDT 24
Finished Jun 13 01:02:15 PM PDT 24
Peak memory 200056 kb
Host smart-cbe08378-5165-42ac-a97b-673171b7e726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370230030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.370230030
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_perf.1394105248
Short name T243
Test name
Test status
Simulation time 7914218593 ps
CPU time 444.74 seconds
Started Jun 13 01:02:09 PM PDT 24
Finished Jun 13 01:09:34 PM PDT 24
Peak memory 200780 kb
Host smart-eb8140d9-09b9-42f2-9d18-851d0af5fa26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1394105248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.1394105248
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.4027245146
Short name T634
Test name
Test status
Simulation time 6138469734 ps
CPU time 5.38 seconds
Started Jun 13 01:02:06 PM PDT 24
Finished Jun 13 01:02:12 PM PDT 24
Peak memory 199044 kb
Host smart-73dd50b3-a0ad-4e69-8de4-57a8b7d4413c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4027245146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.4027245146
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.3096967921
Short name T816
Test name
Test status
Simulation time 12599577768 ps
CPU time 22.2 seconds
Started Jun 13 01:02:10 PM PDT 24
Finished Jun 13 01:02:33 PM PDT 24
Peak memory 200760 kb
Host smart-76e00721-9fb9-43c5-ba90-fb387059dac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096967921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.3096967921
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.520730877
Short name T757
Test name
Test status
Simulation time 2080613588 ps
CPU time 2.26 seconds
Started Jun 13 01:02:13 PM PDT 24
Finished Jun 13 01:02:17 PM PDT 24
Peak memory 196196 kb
Host smart-25543c2d-b535-41fa-919b-aebee1126693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520730877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.520730877
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.3758878396
Short name T643
Test name
Test status
Simulation time 5476805798 ps
CPU time 12.45 seconds
Started Jun 13 01:02:00 PM PDT 24
Finished Jun 13 01:02:14 PM PDT 24
Peak memory 200564 kb
Host smart-013e5d25-9b00-44f6-947d-44cb0f729a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758878396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.3758878396
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.2386261988
Short name T629
Test name
Test status
Simulation time 1848131586 ps
CPU time 2.12 seconds
Started Jun 13 01:02:11 PM PDT 24
Finished Jun 13 01:02:14 PM PDT 24
Peak memory 199532 kb
Host smart-ecb984cd-7ca4-45a9-a866-7d2e0acd3e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386261988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.2386261988
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.2912430295
Short name T40
Test name
Test status
Simulation time 108012125236 ps
CPU time 107.16 seconds
Started Jun 13 01:02:02 PM PDT 24
Finished Jun 13 01:03:50 PM PDT 24
Peak memory 200832 kb
Host smart-99834e52-256c-41a9-a8f2-1723f9799aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912430295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.2912430295
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.3425117577
Short name T384
Test name
Test status
Simulation time 9253408428 ps
CPU time 24.63 seconds
Started Jun 13 02:19:09 PM PDT 24
Finished Jun 13 02:19:43 PM PDT 24
Peak memory 200808 kb
Host smart-ca31aaba-a823-4742-8a0a-879ff6d2153d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425117577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.3425117577
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.4230372339
Short name T808
Test name
Test status
Simulation time 91243260546 ps
CPU time 26.5 seconds
Started Jun 13 01:03:15 PM PDT 24
Finished Jun 13 01:03:43 PM PDT 24
Peak memory 200528 kb
Host smart-cab0bc41-0056-4edc-bba2-7cf97d48cfb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230372339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.4230372339
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.3918169251
Short name T1094
Test name
Test status
Simulation time 16417292390 ps
CPU time 12.4 seconds
Started Jun 13 01:03:03 PM PDT 24
Finished Jun 13 01:03:16 PM PDT 24
Peak memory 200748 kb
Host smart-00ccec9d-bc98-4933-8f97-408424e912ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918169251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.3918169251
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.457972808
Short name T148
Test name
Test status
Simulation time 14442378040 ps
CPU time 6.42 seconds
Started Jun 13 01:49:05 PM PDT 24
Finished Jun 13 01:49:13 PM PDT 24
Peak memory 200764 kb
Host smart-41455d7e-0c50-4a7c-9541-fc4868138466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457972808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.457972808
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.15376010
Short name T601
Test name
Test status
Simulation time 85594385830 ps
CPU time 20.13 seconds
Started Jun 13 02:12:29 PM PDT 24
Finished Jun 13 02:12:50 PM PDT 24
Peak memory 200788 kb
Host smart-3e5121e5-af6c-4dae-b005-c3c65fd20663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15376010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.15376010
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.3645220167
Short name T507
Test name
Test status
Simulation time 53490680571 ps
CPU time 75.71 seconds
Started Jun 13 01:03:01 PM PDT 24
Finished Jun 13 01:04:17 PM PDT 24
Peak memory 200720 kb
Host smart-701de912-ce7e-43e2-87d5-43fdb7442f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645220167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.3645220167
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.821646872
Short name T780
Test name
Test status
Simulation time 94991534611 ps
CPU time 38.25 seconds
Started Jun 13 02:21:27 PM PDT 24
Finished Jun 13 02:22:06 PM PDT 24
Peak memory 200836 kb
Host smart-8dc323de-8a6b-4923-979d-20a80c956f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821646872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.821646872
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.3964323598
Short name T208
Test name
Test status
Simulation time 315144046811 ps
CPU time 27.61 seconds
Started Jun 13 02:16:32 PM PDT 24
Finished Jun 13 02:17:05 PM PDT 24
Peak memory 200768 kb
Host smart-af55931d-129e-4359-80fb-cd838f0b0eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964323598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.3964323598
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.3868963360
Short name T526
Test name
Test status
Simulation time 51577397606 ps
CPU time 13.47 seconds
Started Jun 13 01:03:01 PM PDT 24
Finished Jun 13 01:03:15 PM PDT 24
Peak memory 200740 kb
Host smart-2e34ae49-a5b6-47cf-aacc-d6f5c957aaea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868963360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.3868963360
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.2773125838
Short name T504
Test name
Test status
Simulation time 46451439 ps
CPU time 0.57 seconds
Started Jun 13 01:02:10 PM PDT 24
Finished Jun 13 01:02:11 PM PDT 24
Peak memory 195744 kb
Host smart-a2bf4dad-2df0-4d2a-a4c1-97a3737de231
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773125838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.2773125838
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.4182781445
Short name T890
Test name
Test status
Simulation time 141908171565 ps
CPU time 37.59 seconds
Started Jun 13 01:02:11 PM PDT 24
Finished Jun 13 01:02:49 PM PDT 24
Peak memory 200760 kb
Host smart-293f647b-7468-4c30-a2e0-459ba9acec53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182781445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.4182781445
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.4185614643
Short name T1014
Test name
Test status
Simulation time 24285926148 ps
CPU time 22.88 seconds
Started Jun 13 01:02:11 PM PDT 24
Finished Jun 13 01:02:34 PM PDT 24
Peak memory 200772 kb
Host smart-4b7dec0a-abb4-431f-9c73-b3e3d88564d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185614643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.4185614643
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.156758435
Short name T628
Test name
Test status
Simulation time 34989147307 ps
CPU time 14.41 seconds
Started Jun 13 01:02:12 PM PDT 24
Finished Jun 13 01:02:27 PM PDT 24
Peak memory 200532 kb
Host smart-23817c58-aa2d-496b-ba40-ae2e70fb1e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156758435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.156758435
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.3572533003
Short name T475
Test name
Test status
Simulation time 3637661361 ps
CPU time 5.18 seconds
Started Jun 13 01:02:08 PM PDT 24
Finished Jun 13 01:02:14 PM PDT 24
Peak memory 200664 kb
Host smart-f305b340-c700-47a2-b66b-9256362b66f0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572533003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.3572533003
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.2365150412
Short name T578
Test name
Test status
Simulation time 206063933082 ps
CPU time 220.45 seconds
Started Jun 13 01:02:10 PM PDT 24
Finished Jun 13 01:05:52 PM PDT 24
Peak memory 200816 kb
Host smart-31d88a3a-27a0-4c63-ae77-24648047c96b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2365150412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.2365150412
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.854533081
Short name T777
Test name
Test status
Simulation time 4031393833 ps
CPU time 3.08 seconds
Started Jun 13 01:02:09 PM PDT 24
Finished Jun 13 01:02:13 PM PDT 24
Peak memory 199376 kb
Host smart-828393d1-58aa-4ffe-840f-35916e410918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854533081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.854533081
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_perf.1405715589
Short name T600
Test name
Test status
Simulation time 13376350060 ps
CPU time 654.85 seconds
Started Jun 13 01:02:08 PM PDT 24
Finished Jun 13 01:13:04 PM PDT 24
Peak memory 200680 kb
Host smart-7d81f1df-cb07-42e9-955d-a699e36cb8b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1405715589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.1405715589
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.3299749781
Short name T899
Test name
Test status
Simulation time 4548964473 ps
CPU time 8.66 seconds
Started Jun 13 01:02:10 PM PDT 24
Finished Jun 13 01:02:20 PM PDT 24
Peak memory 199588 kb
Host smart-9883c96c-1107-4b53-8238-b62f723220ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3299749781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.3299749781
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.2823973753
Short name T948
Test name
Test status
Simulation time 31256647741 ps
CPU time 50.83 seconds
Started Jun 13 01:02:10 PM PDT 24
Finished Jun 13 01:03:02 PM PDT 24
Peak memory 200496 kb
Host smart-ad401dea-bc9a-4c87-a7a5-f49694d98670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823973753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.2823973753
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.1399307826
Short name T973
Test name
Test status
Simulation time 2071799953 ps
CPU time 3.87 seconds
Started Jun 13 01:02:08 PM PDT 24
Finished Jun 13 01:02:12 PM PDT 24
Peak memory 196196 kb
Host smart-695db060-44d9-498b-b88b-d4e52b2060e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399307826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.1399307826
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.1006753361
Short name T847
Test name
Test status
Simulation time 834019594 ps
CPU time 1.1 seconds
Started Jun 13 01:02:08 PM PDT 24
Finished Jun 13 01:02:09 PM PDT 24
Peak memory 199852 kb
Host smart-55e1025a-50ba-4286-beef-44f80086aefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006753361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.1006753361
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.777458428
Short name T1024
Test name
Test status
Simulation time 216664001564 ps
CPU time 746.21 seconds
Started Jun 13 01:02:14 PM PDT 24
Finished Jun 13 01:14:41 PM PDT 24
Peak memory 225400 kb
Host smart-be7891af-1ce2-479f-b879-b5b84bdd083e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777458428 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.777458428
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.1480224398
Short name T378
Test name
Test status
Simulation time 577272325 ps
CPU time 2.04 seconds
Started Jun 13 01:02:09 PM PDT 24
Finished Jun 13 01:02:12 PM PDT 24
Peak memory 199056 kb
Host smart-d135473a-2ad6-4200-a6b0-acb53221d131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480224398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.1480224398
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.2893829112
Short name T295
Test name
Test status
Simulation time 163265575048 ps
CPU time 79.66 seconds
Started Jun 13 01:02:09 PM PDT 24
Finished Jun 13 01:03:29 PM PDT 24
Peak memory 200672 kb
Host smart-50463ba5-45c7-48c2-aeb9-5d5b3d2578e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893829112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.2893829112
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.2063663661
Short name T996
Test name
Test status
Simulation time 49521577275 ps
CPU time 63.53 seconds
Started Jun 13 02:11:49 PM PDT 24
Finished Jun 13 02:12:54 PM PDT 24
Peak memory 200792 kb
Host smart-656d23ee-294a-428a-8556-0bf0f776ca0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063663661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.2063663661
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.1621116935
Short name T225
Test name
Test status
Simulation time 31618962053 ps
CPU time 42.04 seconds
Started Jun 13 02:23:40 PM PDT 24
Finished Jun 13 02:24:22 PM PDT 24
Peak memory 200848 kb
Host smart-22fdb888-37f3-4f70-8669-c4a34a48794a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621116935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.1621116935
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.2742897571
Short name T402
Test name
Test status
Simulation time 32570018276 ps
CPU time 25.25 seconds
Started Jun 13 01:31:40 PM PDT 24
Finished Jun 13 01:32:07 PM PDT 24
Peak memory 200784 kb
Host smart-316bd6df-7da4-49af-acc0-bdfab9322064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742897571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.2742897571
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.859015194
Short name T196
Test name
Test status
Simulation time 172435101122 ps
CPU time 17.94 seconds
Started Jun 13 01:54:49 PM PDT 24
Finished Jun 13 01:55:12 PM PDT 24
Peak memory 200864 kb
Host smart-915d8b27-effe-4c24-9c24-8fe308ecb7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859015194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.859015194
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.3599362468
Short name T212
Test name
Test status
Simulation time 39051912826 ps
CPU time 84.13 seconds
Started Jun 13 01:48:23 PM PDT 24
Finished Jun 13 01:49:49 PM PDT 24
Peak memory 200836 kb
Host smart-03074446-a7c7-4d2d-9fa9-453ec6534331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599362468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.3599362468
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.1941623496
Short name T612
Test name
Test status
Simulation time 23078852966 ps
CPU time 8.69 seconds
Started Jun 13 02:20:53 PM PDT 24
Finished Jun 13 02:21:02 PM PDT 24
Peak memory 200820 kb
Host smart-4b652229-04b3-48f2-865f-37caaeb4129e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941623496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.1941623496
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.2268931135
Short name T227
Test name
Test status
Simulation time 41747032149 ps
CPU time 35.33 seconds
Started Jun 13 01:03:00 PM PDT 24
Finished Jun 13 01:03:36 PM PDT 24
Peak memory 200664 kb
Host smart-3dcabeca-8008-4421-b210-62591903d761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268931135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.2268931135
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.2652024746
Short name T199
Test name
Test status
Simulation time 38485535371 ps
CPU time 17.04 seconds
Started Jun 13 02:08:19 PM PDT 24
Finished Jun 13 02:08:37 PM PDT 24
Peak memory 200744 kb
Host smart-2f969397-a42f-4245-9b82-46055f1096df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652024746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.2652024746
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.1669652421
Short name T449
Test name
Test status
Simulation time 114396226785 ps
CPU time 47.1 seconds
Started Jun 13 01:30:58 PM PDT 24
Finished Jun 13 01:31:46 PM PDT 24
Peak memory 200812 kb
Host smart-fa2183b0-3cb6-40f4-b790-11a44cec99c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669652421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.1669652421
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.3482239476
Short name T46
Test name
Test status
Simulation time 26351665 ps
CPU time 0.54 seconds
Started Jun 13 01:02:19 PM PDT 24
Finished Jun 13 01:02:20 PM PDT 24
Peak memory 196360 kb
Host smart-695cf1fd-3ffe-472b-8327-2232617e92d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482239476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.3482239476
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.381484847
Short name T688
Test name
Test status
Simulation time 30432585991 ps
CPU time 29.94 seconds
Started Jun 13 01:02:18 PM PDT 24
Finished Jun 13 01:02:48 PM PDT 24
Peak memory 200672 kb
Host smart-29c750eb-e241-410f-9712-62c081fdbfac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381484847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.381484847
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.3497973956
Short name T303
Test name
Test status
Simulation time 24962622100 ps
CPU time 58.67 seconds
Started Jun 13 01:02:15 PM PDT 24
Finished Jun 13 01:03:15 PM PDT 24
Peak memory 200712 kb
Host smart-c1d449c0-9432-4839-8561-69b84d769965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497973956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.3497973956
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.740178887
Short name T204
Test name
Test status
Simulation time 29243540359 ps
CPU time 71.94 seconds
Started Jun 13 01:02:15 PM PDT 24
Finished Jun 13 01:03:27 PM PDT 24
Peak memory 200708 kb
Host smart-288ee480-1bc9-4530-a81a-f4afe13e8529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740178887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.740178887
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.3411786961
Short name T515
Test name
Test status
Simulation time 32970516795 ps
CPU time 16.6 seconds
Started Jun 13 01:02:14 PM PDT 24
Finished Jun 13 01:02:31 PM PDT 24
Peak memory 200732 kb
Host smart-b8b95e19-7b05-4e09-88c1-cbac39d30ee2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411786961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.3411786961
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.2706490503
Short name T709
Test name
Test status
Simulation time 189875468761 ps
CPU time 351.28 seconds
Started Jun 13 01:02:16 PM PDT 24
Finished Jun 13 01:08:08 PM PDT 24
Peak memory 200800 kb
Host smart-6caa563d-1155-4628-9ad7-e02217e692f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2706490503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.2706490503
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.58023068
Short name T851
Test name
Test status
Simulation time 273885769 ps
CPU time 0.9 seconds
Started Jun 13 01:02:17 PM PDT 24
Finished Jun 13 01:02:18 PM PDT 24
Peak memory 197940 kb
Host smart-74e15ed5-8d1b-47c6-9987-2cc161872f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58023068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.58023068
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_perf.3792982912
Short name T658
Test name
Test status
Simulation time 17926650689 ps
CPU time 257 seconds
Started Jun 13 01:02:20 PM PDT 24
Finished Jun 13 01:06:37 PM PDT 24
Peak memory 200708 kb
Host smart-7844fdc4-de38-46da-a9c7-204f54010d38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3792982912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.3792982912
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.1052731476
Short name T854
Test name
Test status
Simulation time 7353140510 ps
CPU time 33.17 seconds
Started Jun 13 01:02:14 PM PDT 24
Finished Jun 13 01:02:48 PM PDT 24
Peak memory 198872 kb
Host smart-d5d8e575-2836-4489-ae77-fdb2c67f2646
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1052731476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.1052731476
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.2675852668
Short name T769
Test name
Test status
Simulation time 43680098785 ps
CPU time 14.49 seconds
Started Jun 13 01:02:17 PM PDT 24
Finished Jun 13 01:02:31 PM PDT 24
Peak memory 199188 kb
Host smart-3a449f75-74b3-420d-8f02-70d890b0d79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675852668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.2675852668
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.286307647
Short name T365
Test name
Test status
Simulation time 3177386678 ps
CPU time 1.65 seconds
Started Jun 13 01:02:18 PM PDT 24
Finished Jun 13 01:02:20 PM PDT 24
Peak memory 196644 kb
Host smart-572fe00c-d6c5-4fb9-a86d-e5dfc95e3b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286307647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.286307647
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.4280002194
Short name T258
Test name
Test status
Simulation time 5760802101 ps
CPU time 23.18 seconds
Started Jun 13 01:02:13 PM PDT 24
Finished Jun 13 01:02:36 PM PDT 24
Peak memory 200804 kb
Host smart-e16e7c7d-6fa7-45b7-985b-2b8143b3475a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280002194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.4280002194
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.135298947
Short name T989
Test name
Test status
Simulation time 505739848135 ps
CPU time 2172.66 seconds
Started Jun 13 01:02:15 PM PDT 24
Finished Jun 13 01:38:29 PM PDT 24
Peak memory 200776 kb
Host smart-76cecf9c-7d56-42bc-9097-c36d95be3a7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135298947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.135298947
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.1145975077
Short name T1002
Test name
Test status
Simulation time 449297386 ps
CPU time 2.04 seconds
Started Jun 13 01:02:15 PM PDT 24
Finished Jun 13 01:02:18 PM PDT 24
Peak memory 200008 kb
Host smart-9c50c6f0-b272-47d9-9137-a3f260934119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145975077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.1145975077
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.1925600340
Short name T317
Test name
Test status
Simulation time 91192189657 ps
CPU time 189.9 seconds
Started Jun 13 01:02:19 PM PDT 24
Finished Jun 13 01:05:30 PM PDT 24
Peak memory 200812 kb
Host smart-b6171d59-9b77-4300-950a-060e8f5b4c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925600340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.1925600340
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.868431069
Short name T770
Test name
Test status
Simulation time 129757556786 ps
CPU time 148.35 seconds
Started Jun 13 01:37:32 PM PDT 24
Finished Jun 13 01:40:02 PM PDT 24
Peak memory 200688 kb
Host smart-151cd029-fd4c-4db9-917c-0cb53d86be0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868431069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.868431069
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.2930100012
Short name T586
Test name
Test status
Simulation time 13964454598 ps
CPU time 23.34 seconds
Started Jun 13 01:45:45 PM PDT 24
Finished Jun 13 01:46:10 PM PDT 24
Peak memory 200788 kb
Host smart-7cb274e6-36c4-49c9-a9ef-d477c3998d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930100012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.2930100012
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.3251205593
Short name T386
Test name
Test status
Simulation time 115517421812 ps
CPU time 86.74 seconds
Started Jun 13 01:30:35 PM PDT 24
Finished Jun 13 01:32:03 PM PDT 24
Peak memory 200740 kb
Host smart-1e791c22-1de6-45ed-9ae9-50888b725da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251205593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.3251205593
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.3507930693
Short name T1057
Test name
Test status
Simulation time 47353316611 ps
CPU time 63.46 seconds
Started Jun 13 02:47:21 PM PDT 24
Finished Jun 13 02:48:27 PM PDT 24
Peak memory 200772 kb
Host smart-913641d6-5e94-43d6-af7f-7ec0635401b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507930693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.3507930693
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.588507984
Short name T725
Test name
Test status
Simulation time 31109665941 ps
CPU time 16.41 seconds
Started Jun 13 01:03:04 PM PDT 24
Finished Jun 13 01:03:21 PM PDT 24
Peak memory 200612 kb
Host smart-44898e68-c8fd-4ab6-bd8d-dfc9a702e2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588507984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.588507984
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.956669086
Short name T336
Test name
Test status
Simulation time 30528045657 ps
CPU time 63.69 seconds
Started Jun 13 01:03:03 PM PDT 24
Finished Jun 13 01:04:07 PM PDT 24
Peak memory 200648 kb
Host smart-f439e5bc-e36b-485b-8e6b-dee8ee787c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956669086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.956669086
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.1259892427
Short name T239
Test name
Test status
Simulation time 47667373035 ps
CPU time 40.79 seconds
Started Jun 13 02:17:32 PM PDT 24
Finished Jun 13 02:18:16 PM PDT 24
Peak memory 200480 kb
Host smart-ea85882a-3a53-47bb-aa95-4fd9b2f3599b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259892427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.1259892427
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.225107099
Short name T583
Test name
Test status
Simulation time 42054892 ps
CPU time 0.51 seconds
Started Jun 13 01:00:45 PM PDT 24
Finished Jun 13 01:00:46 PM PDT 24
Peak memory 196072 kb
Host smart-bae87553-75d0-4a92-b416-3cc889814c5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225107099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.225107099
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.2684593482
Short name T3
Test name
Test status
Simulation time 84295684532 ps
CPU time 74.09 seconds
Started Jun 13 01:00:41 PM PDT 24
Finished Jun 13 01:01:56 PM PDT 24
Peak memory 200728 kb
Host smart-19039b3c-2eb9-452e-a874-44f230537a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684593482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.2684593482
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.1495778292
Short name T134
Test name
Test status
Simulation time 153707418422 ps
CPU time 119.61 seconds
Started Jun 13 01:00:42 PM PDT 24
Finished Jun 13 01:02:42 PM PDT 24
Peak memory 200732 kb
Host smart-2c4526c7-03df-4896-acfd-ca340d0bd585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495778292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.1495778292
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_intr.3237474300
Short name T893
Test name
Test status
Simulation time 52300005975 ps
CPU time 68.66 seconds
Started Jun 13 01:00:41 PM PDT 24
Finished Jun 13 01:01:50 PM PDT 24
Peak memory 199848 kb
Host smart-33aca4e8-a68f-45ad-a44a-74652fc8a3a4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237474300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.3237474300
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.3045471770
Short name T676
Test name
Test status
Simulation time 177777680633 ps
CPU time 592.14 seconds
Started Jun 13 01:00:46 PM PDT 24
Finished Jun 13 01:10:39 PM PDT 24
Peak memory 200708 kb
Host smart-77688072-2a93-4190-a2ec-c7aa79d39d05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3045471770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.3045471770
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.1498276527
Short name T1091
Test name
Test status
Simulation time 1609924689 ps
CPU time 1.41 seconds
Started Jun 13 01:00:42 PM PDT 24
Finished Jun 13 01:00:44 PM PDT 24
Peak memory 196812 kb
Host smart-bf45aedd-ac84-4dd0-890c-3a6279056394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498276527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.1498276527
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_perf.818828926
Short name T982
Test name
Test status
Simulation time 11322564130 ps
CPU time 157.34 seconds
Started Jun 13 01:00:46 PM PDT 24
Finished Jun 13 01:03:23 PM PDT 24
Peak memory 200772 kb
Host smart-4175535a-0521-4eda-91cd-8b613ad6813d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=818828926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.818828926
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.2348403129
Short name T555
Test name
Test status
Simulation time 2966023846 ps
CPU time 5.46 seconds
Started Jun 13 01:00:44 PM PDT 24
Finished Jun 13 01:00:50 PM PDT 24
Peak memory 198976 kb
Host smart-7159cecd-6b9d-4fcd-9492-1742687c1172
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2348403129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.2348403129
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.2618579376
Short name T1040
Test name
Test status
Simulation time 242089068653 ps
CPU time 73.95 seconds
Started Jun 13 01:00:41 PM PDT 24
Finished Jun 13 01:01:56 PM PDT 24
Peak memory 200808 kb
Host smart-7d458e29-6374-40d7-8dc2-008105b8be46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618579376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.2618579376
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.4061570591
Short name T749
Test name
Test status
Simulation time 29433855017 ps
CPU time 4.14 seconds
Started Jun 13 01:00:46 PM PDT 24
Finished Jun 13 01:00:51 PM PDT 24
Peak memory 196772 kb
Host smart-f2cfa6d3-d702-4abd-a991-3524175326aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061570591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.4061570591
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.3349782704
Short name T99
Test name
Test status
Simulation time 178746767 ps
CPU time 0.76 seconds
Started Jun 13 01:00:40 PM PDT 24
Finished Jun 13 01:00:41 PM PDT 24
Peak memory 219168 kb
Host smart-64931872-3451-4c29-9ac2-645e6bf7ccb2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349782704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.3349782704
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.1627027667
Short name T915
Test name
Test status
Simulation time 504019454 ps
CPU time 1.76 seconds
Started Jun 13 01:00:44 PM PDT 24
Finished Jun 13 01:00:47 PM PDT 24
Peak memory 199108 kb
Host smart-da1e8a0d-9e2f-4687-a845-5973074e39fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627027667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.1627027667
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.820156602
Short name T767
Test name
Test status
Simulation time 61677214231 ps
CPU time 231.94 seconds
Started Jun 13 01:00:41 PM PDT 24
Finished Jun 13 01:04:34 PM PDT 24
Peak memory 200948 kb
Host smart-aaad0d44-a411-408e-8be8-cae19c91a9f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820156602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.820156602
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.91734611
Short name T282
Test name
Test status
Simulation time 43386271732 ps
CPU time 348.64 seconds
Started Jun 13 01:00:46 PM PDT 24
Finished Jun 13 01:06:35 PM PDT 24
Peak memory 208960 kb
Host smart-5c64d37c-b3c4-45d5-b721-67880c9df9d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91734611 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.91734611
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.1759811339
Short name T318
Test name
Test status
Simulation time 1846460016 ps
CPU time 2.06 seconds
Started Jun 13 01:00:47 PM PDT 24
Finished Jun 13 01:00:50 PM PDT 24
Peak memory 198860 kb
Host smart-869b0e28-68c4-4ccc-bc88-ec385b07dc3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759811339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.1759811339
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.1264568780
Short name T699
Test name
Test status
Simulation time 27411913632 ps
CPU time 113.32 seconds
Started Jun 13 01:00:40 PM PDT 24
Finished Jun 13 01:02:34 PM PDT 24
Peak memory 200712 kb
Host smart-5a54d929-209c-4f3b-927c-33b29cadc056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264568780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.1264568780
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.3773728362
Short name T613
Test name
Test status
Simulation time 37560747 ps
CPU time 0.62 seconds
Started Jun 13 01:02:23 PM PDT 24
Finished Jun 13 01:02:24 PM PDT 24
Peak memory 196376 kb
Host smart-423684ff-80e8-46b4-bfd1-8218df0fb1de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773728362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.3773728362
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.3206004251
Short name T595
Test name
Test status
Simulation time 31025582926 ps
CPU time 50.92 seconds
Started Jun 13 01:02:26 PM PDT 24
Finished Jun 13 01:03:17 PM PDT 24
Peak memory 200720 kb
Host smart-e0281ed7-5749-487a-8658-379f1ee40f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206004251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.3206004251
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.1387790007
Short name T144
Test name
Test status
Simulation time 151607609335 ps
CPU time 39.21 seconds
Started Jun 13 01:02:29 PM PDT 24
Finished Jun 13 01:03:08 PM PDT 24
Peak memory 200648 kb
Host smart-d9caa554-7ef4-4066-a204-8a3607cd879a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387790007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.1387790007
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.477141299
Short name T830
Test name
Test status
Simulation time 10348182356 ps
CPU time 19.25 seconds
Started Jun 13 01:02:21 PM PDT 24
Finished Jun 13 01:02:41 PM PDT 24
Peak memory 200724 kb
Host smart-1d9d9c27-2f75-4c0f-be54-1de02ef2a3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477141299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.477141299
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.2243057641
Short name T385
Test name
Test status
Simulation time 97652128009 ps
CPU time 8.44 seconds
Started Jun 13 01:02:29 PM PDT 24
Finished Jun 13 01:02:38 PM PDT 24
Peak memory 196768 kb
Host smart-fc551055-8dcf-4050-8bb4-0d067fab81ef
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243057641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.2243057641
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.3296045054
Short name T1046
Test name
Test status
Simulation time 121474218414 ps
CPU time 668.93 seconds
Started Jun 13 01:02:29 PM PDT 24
Finished Jun 13 01:13:39 PM PDT 24
Peak memory 200632 kb
Host smart-3a780254-0728-4dea-86d9-23b8a5796936
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3296045054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.3296045054
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.4204206621
Short name T576
Test name
Test status
Simulation time 6000514077 ps
CPU time 3.61 seconds
Started Jun 13 01:02:23 PM PDT 24
Finished Jun 13 01:02:27 PM PDT 24
Peak memory 199764 kb
Host smart-96598ad7-3a36-4fee-99d2-7f8385a17a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204206621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.4204206621
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_perf.3185267721
Short name T313
Test name
Test status
Simulation time 23139986089 ps
CPU time 1263.11 seconds
Started Jun 13 01:02:20 PM PDT 24
Finished Jun 13 01:23:23 PM PDT 24
Peak memory 200648 kb
Host smart-83db212d-d79a-4283-9c2f-7cef140bd8b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3185267721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.3185267721
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.787182362
Short name T339
Test name
Test status
Simulation time 6437709119 ps
CPU time 12.43 seconds
Started Jun 13 01:02:29 PM PDT 24
Finished Jun 13 01:02:42 PM PDT 24
Peak memory 199456 kb
Host smart-5b5f524f-b990-4e10-82fe-de2723decc3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=787182362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.787182362
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.2181129017
Short name T162
Test name
Test status
Simulation time 43160157388 ps
CPU time 20.42 seconds
Started Jun 13 01:02:23 PM PDT 24
Finished Jun 13 01:02:44 PM PDT 24
Peak memory 200812 kb
Host smart-ecb60d6c-07b0-4eaf-b875-79917b7398d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181129017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.2181129017
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.2825665103
Short name T974
Test name
Test status
Simulation time 719791831 ps
CPU time 1.24 seconds
Started Jun 13 01:02:21 PM PDT 24
Finished Jun 13 01:02:23 PM PDT 24
Peak memory 196172 kb
Host smart-ab873d72-723e-4d7b-9abc-b2a1b0222d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825665103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.2825665103
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.3387805556
Short name T413
Test name
Test status
Simulation time 450069441 ps
CPU time 1.25 seconds
Started Jun 13 01:02:14 PM PDT 24
Finished Jun 13 01:02:16 PM PDT 24
Peak memory 200644 kb
Host smart-67545ae1-55e4-40e2-8074-7c1db4940873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387805556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.3387805556
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.3637434151
Short name T814
Test name
Test status
Simulation time 32566192281 ps
CPU time 181.68 seconds
Started Jun 13 01:02:22 PM PDT 24
Finished Jun 13 01:05:24 PM PDT 24
Peak memory 216744 kb
Host smart-8cfc59a4-df83-48bc-8c19-216b41cb1ea0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637434151 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.3637434151
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.3448537463
Short name T1044
Test name
Test status
Simulation time 406190011 ps
CPU time 1.49 seconds
Started Jun 13 01:02:29 PM PDT 24
Finished Jun 13 01:02:31 PM PDT 24
Peak memory 199628 kb
Host smart-0242d72b-9952-4bfd-b3c2-b9a892874173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448537463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.3448537463
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.3464853131
Short name T296
Test name
Test status
Simulation time 77081387219 ps
CPU time 131.82 seconds
Started Jun 13 01:02:30 PM PDT 24
Finished Jun 13 01:04:42 PM PDT 24
Peak memory 200656 kb
Host smart-3af1119a-501a-4bc5-b3a8-14f20518effa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464853131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.3464853131
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.1345942994
Short name T21
Test name
Test status
Simulation time 19171287 ps
CPU time 0.56 seconds
Started Jun 13 01:23:12 PM PDT 24
Finished Jun 13 01:23:13 PM PDT 24
Peak memory 196120 kb
Host smart-f61dd028-000a-4b10-8f55-833a60032fb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345942994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.1345942994
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.1419235821
Short name T772
Test name
Test status
Simulation time 210739773411 ps
CPU time 227.9 seconds
Started Jun 13 01:02:21 PM PDT 24
Finished Jun 13 01:06:09 PM PDT 24
Peak memory 200796 kb
Host smart-5a79b946-ec5d-49e1-8171-55b6fae0ef05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419235821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.1419235821
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.1137955880
Short name T1056
Test name
Test status
Simulation time 249007514982 ps
CPU time 23.54 seconds
Started Jun 13 01:02:23 PM PDT 24
Finished Jun 13 01:02:46 PM PDT 24
Peak memory 200728 kb
Host smart-f59756cb-7ae3-48f9-9c50-143354457d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137955880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.1137955880
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.2512114347
Short name T102
Test name
Test status
Simulation time 143854254580 ps
CPU time 72.6 seconds
Started Jun 13 01:02:26 PM PDT 24
Finished Jun 13 01:03:39 PM PDT 24
Peak memory 200784 kb
Host smart-c5789130-4a59-45a1-a25a-8fc7e25a3bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512114347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.2512114347
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.1062641224
Short name T763
Test name
Test status
Simulation time 384567440556 ps
CPU time 127.3 seconds
Started Jun 13 01:21:51 PM PDT 24
Finished Jun 13 01:23:58 PM PDT 24
Peak memory 199216 kb
Host smart-675b9f0b-6c5c-4170-b293-a0d27090dfcb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062641224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.1062641224
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.1102875234
Short name T728
Test name
Test status
Simulation time 94987895195 ps
CPU time 280.89 seconds
Started Jun 13 01:24:51 PM PDT 24
Finished Jun 13 01:29:33 PM PDT 24
Peak memory 200772 kb
Host smart-18348fc2-1d51-4a9e-926e-a9c1528a4b6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1102875234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.1102875234
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.1126520163
Short name T510
Test name
Test status
Simulation time 10275334862 ps
CPU time 26.52 seconds
Started Jun 13 01:08:57 PM PDT 24
Finished Jun 13 01:09:24 PM PDT 24
Peak memory 200656 kb
Host smart-b44292d4-127e-4b4f-a11e-aec2b537b259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126520163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.1126520163
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_perf.3075733662
Short name T651
Test name
Test status
Simulation time 10408260583 ps
CPU time 160.15 seconds
Started Jun 13 01:31:34 PM PDT 24
Finished Jun 13 01:34:16 PM PDT 24
Peak memory 200736 kb
Host smart-3018a060-aaec-4074-8648-210b6d4eda2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3075733662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.3075733662
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.1132738134
Short name T1068
Test name
Test status
Simulation time 6884068235 ps
CPU time 16.4 seconds
Started Jun 13 01:02:21 PM PDT 24
Finished Jun 13 01:02:38 PM PDT 24
Peak memory 199892 kb
Host smart-a4e6c978-c225-4db7-9d66-5dba639fa387
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1132738134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.1132738134
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.3991768170
Short name T1077
Test name
Test status
Simulation time 143305669027 ps
CPU time 53.22 seconds
Started Jun 13 01:02:29 PM PDT 24
Finished Jun 13 01:03:22 PM PDT 24
Peak memory 200588 kb
Host smart-e0a660ed-01ad-4ddd-b52f-abdc5619c55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991768170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.3991768170
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.523804524
Short name T470
Test name
Test status
Simulation time 4170283215 ps
CPU time 6.35 seconds
Started Jun 13 01:04:56 PM PDT 24
Finished Jun 13 01:05:03 PM PDT 24
Peak memory 197064 kb
Host smart-9178ebcd-b4cd-4a65-af5e-9d361e4be842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523804524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.523804524
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.2535406971
Short name T267
Test name
Test status
Simulation time 289274960 ps
CPU time 1.38 seconds
Started Jun 13 01:02:22 PM PDT 24
Finished Jun 13 01:02:24 PM PDT 24
Peak memory 199132 kb
Host smart-cf0d38e1-c6d8-4589-bbf1-a7a959eefe2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535406971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.2535406971
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.2688817478
Short name T231
Test name
Test status
Simulation time 283174677215 ps
CPU time 103.57 seconds
Started Jun 13 01:02:29 PM PDT 24
Finished Jun 13 01:04:14 PM PDT 24
Peak memory 200796 kb
Host smart-8a4f2ff2-c138-435c-b4cd-bd93667ab01d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688817478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.2688817478
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.359354905
Short name T930
Test name
Test status
Simulation time 3797873553 ps
CPU time 46.59 seconds
Started Jun 13 01:02:30 PM PDT 24
Finished Jun 13 01:03:17 PM PDT 24
Peak memory 216436 kb
Host smart-d5833a5f-f63f-4686-9f58-59ab2f5ba476
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359354905 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.359354905
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.2039522898
Short name T933
Test name
Test status
Simulation time 7286311633 ps
CPU time 13.1 seconds
Started Jun 13 01:42:21 PM PDT 24
Finished Jun 13 01:42:36 PM PDT 24
Peak memory 200260 kb
Host smart-18503b10-4326-4ac9-b4e4-963c37803219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039522898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.2039522898
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.458099743
Short name T992
Test name
Test status
Simulation time 133349380007 ps
CPU time 84.95 seconds
Started Jun 13 01:02:21 PM PDT 24
Finished Jun 13 01:03:46 PM PDT 24
Peak memory 200784 kb
Host smart-7a373e42-87ab-4b56-bb78-644814e4885e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458099743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.458099743
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.778015550
Short name T388
Test name
Test status
Simulation time 12721202 ps
CPU time 0.59 seconds
Started Jun 13 02:03:01 PM PDT 24
Finished Jun 13 02:03:03 PM PDT 24
Peak memory 195776 kb
Host smart-8d503bba-760b-4977-84ce-22a9fb232a7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778015550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.778015550
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.1928815160
Short name T1048
Test name
Test status
Simulation time 28841212245 ps
CPU time 48.8 seconds
Started Jun 13 01:32:51 PM PDT 24
Finished Jun 13 01:33:41 PM PDT 24
Peak memory 200840 kb
Host smart-82c9f95a-47e7-4f02-9ef3-4097c55361b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928815160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.1928815160
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.2572156329
Short name T940
Test name
Test status
Simulation time 217854151134 ps
CPU time 30.81 seconds
Started Jun 13 01:44:40 PM PDT 24
Finished Jun 13 01:45:11 PM PDT 24
Peak memory 200796 kb
Host smart-d78265f8-388a-4792-a475-7a552d0ed84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572156329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.2572156329
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.2710388088
Short name T599
Test name
Test status
Simulation time 17653500102 ps
CPU time 27.65 seconds
Started Jun 13 01:14:06 PM PDT 24
Finished Jun 13 01:14:34 PM PDT 24
Peak memory 200672 kb
Host smart-e796ec7c-804c-43d0-9b22-b5aa0cb09d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710388088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.2710388088
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.2759341347
Short name T314
Test name
Test status
Simulation time 54346472721 ps
CPU time 40.22 seconds
Started Jun 13 01:16:15 PM PDT 24
Finished Jun 13 01:16:56 PM PDT 24
Peak memory 200588 kb
Host smart-bbdb52a0-f525-4c59-8ddf-b5ec6f6b8369
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759341347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.2759341347
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.2169485721
Short name T476
Test name
Test status
Simulation time 119747699043 ps
CPU time 391.33 seconds
Started Jun 13 01:02:26 PM PDT 24
Finished Jun 13 01:08:58 PM PDT 24
Peak memory 200836 kb
Host smart-f302c6ff-c140-4bf3-9a97-366fd95a6072
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2169485721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.2169485721
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.2449624475
Short name T917
Test name
Test status
Simulation time 3544105947 ps
CPU time 3.45 seconds
Started Jun 13 01:34:00 PM PDT 24
Finished Jun 13 01:34:05 PM PDT 24
Peak memory 199244 kb
Host smart-d0dc8360-7c68-4ddd-a6f6-fadc9c99ec82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449624475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.2449624475
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_perf.496770317
Short name T35
Test name
Test status
Simulation time 16784328344 ps
CPU time 519.4 seconds
Started Jun 13 01:02:26 PM PDT 24
Finished Jun 13 01:11:05 PM PDT 24
Peak memory 200600 kb
Host smart-e54b3b55-9dd8-47c8-b10d-c852ee9ff00b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=496770317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.496770317
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.2683924480
Short name T639
Test name
Test status
Simulation time 4238459091 ps
CPU time 9.57 seconds
Started Jun 13 01:31:47 PM PDT 24
Finished Jun 13 01:31:58 PM PDT 24
Peak memory 199008 kb
Host smart-a984515a-d866-4f46-a71b-7985cf14d45e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2683924480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.2683924480
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.402410500
Short name T164
Test name
Test status
Simulation time 141436125375 ps
CPU time 57.96 seconds
Started Jun 13 01:02:27 PM PDT 24
Finished Jun 13 01:03:25 PM PDT 24
Peak memory 200744 kb
Host smart-6cae07ca-b3bb-4789-b04a-ce4eab6b683a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402410500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.402410500
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.2189522489
Short name T1031
Test name
Test status
Simulation time 4795534248 ps
CPU time 8.6 seconds
Started Jun 13 01:58:43 PM PDT 24
Finished Jun 13 01:58:53 PM PDT 24
Peak memory 196944 kb
Host smart-db8781c4-8e63-4b96-aa68-1c3530d83ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189522489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.2189522489
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.4268815545
Short name T43
Test name
Test status
Simulation time 900169741 ps
CPU time 2.41 seconds
Started Jun 13 01:41:14 PM PDT 24
Finished Jun 13 01:41:18 PM PDT 24
Peak memory 200468 kb
Host smart-37bc3b8d-6a56-4d2b-9785-f96c1ff7e446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268815545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.4268815545
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.630698587
Short name T434
Test name
Test status
Simulation time 123446135562 ps
CPU time 135.92 seconds
Started Jun 13 01:03:42 PM PDT 24
Finished Jun 13 01:05:59 PM PDT 24
Peak memory 200652 kb
Host smart-02ced02d-b238-4156-9558-d36ad5ee69f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630698587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.630698587
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.841770441
Short name T671
Test name
Test status
Simulation time 7347344758 ps
CPU time 11.65 seconds
Started Jun 13 01:02:28 PM PDT 24
Finished Jun 13 01:02:40 PM PDT 24
Peak memory 200792 kb
Host smart-4a65a4d1-344b-4a55-b83b-36cb3fd6c5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841770441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.841770441
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.1547375491
Short name T41
Test name
Test status
Simulation time 41976098998 ps
CPU time 15.26 seconds
Started Jun 13 01:40:56 PM PDT 24
Finished Jun 13 01:41:13 PM PDT 24
Peak memory 200208 kb
Host smart-44b3ff86-9af0-48b9-9739-49ec50422dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547375491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.1547375491
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.793758804
Short name T451
Test name
Test status
Simulation time 10466369 ps
CPU time 0.55 seconds
Started Jun 13 01:26:48 PM PDT 24
Finished Jun 13 01:26:50 PM PDT 24
Peak memory 195088 kb
Host smart-252057f1-ef79-4cce-b9f2-71c950b44f0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793758804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.793758804
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.3098192249
Short name T143
Test name
Test status
Simulation time 132122213047 ps
CPU time 43.84 seconds
Started Jun 13 01:11:14 PM PDT 24
Finished Jun 13 01:11:59 PM PDT 24
Peak memory 200748 kb
Host smart-fd05160e-61e5-40f2-8e91-3597329e0d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098192249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.3098192249
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.844172045
Short name T1001
Test name
Test status
Simulation time 20399464025 ps
CPU time 38.96 seconds
Started Jun 13 01:02:26 PM PDT 24
Finished Jun 13 01:03:05 PM PDT 24
Peak memory 200808 kb
Host smart-2acb69b0-ca05-451f-af52-ba2008cb8c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844172045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.844172045
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.1257594734
Short name T939
Test name
Test status
Simulation time 15826720749 ps
CPU time 7.79 seconds
Started Jun 13 01:12:18 PM PDT 24
Finished Jun 13 01:12:26 PM PDT 24
Peak memory 200736 kb
Host smart-cf0beacd-84ee-42ed-964e-dec4fd99a1e6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257594734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.1257594734
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.2665708911
Short name T719
Test name
Test status
Simulation time 139049572253 ps
CPU time 466.27 seconds
Started Jun 13 01:21:51 PM PDT 24
Finished Jun 13 01:29:37 PM PDT 24
Peak memory 200824 kb
Host smart-f7bacc5c-29f7-4788-99c8-c5baca591c9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2665708911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.2665708911
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.2824713275
Short name T696
Test name
Test status
Simulation time 9538770765 ps
CPU time 19.06 seconds
Started Jun 13 01:59:42 PM PDT 24
Finished Jun 13 02:00:03 PM PDT 24
Peak memory 200728 kb
Host smart-39a3d4ea-b053-4ac4-af0f-b11125678999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824713275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.2824713275
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_perf.1750386687
Short name T994
Test name
Test status
Simulation time 18153182662 ps
CPU time 450.13 seconds
Started Jun 13 01:06:25 PM PDT 24
Finished Jun 13 01:13:57 PM PDT 24
Peak memory 201004 kb
Host smart-41971c8f-b592-4e41-bc9c-d15f379e13c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1750386687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.1750386687
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.297343972
Short name T689
Test name
Test status
Simulation time 5344006900 ps
CPU time 21.03 seconds
Started Jun 13 02:12:19 PM PDT 24
Finished Jun 13 02:12:40 PM PDT 24
Peak memory 198996 kb
Host smart-f6f33bef-ee35-4f63-8e77-d9985c7b4ee3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=297343972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.297343972
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.1347664565
Short name T834
Test name
Test status
Simulation time 169514514224 ps
CPU time 431.28 seconds
Started Jun 13 01:19:42 PM PDT 24
Finished Jun 13 01:26:54 PM PDT 24
Peak memory 200812 kb
Host smart-e236ff17-2d08-4204-9dda-e2a9e56f9be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347664565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.1347664565
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.1869222741
Short name T371
Test name
Test status
Simulation time 4758622303 ps
CPU time 2.09 seconds
Started Jun 13 01:04:26 PM PDT 24
Finished Jun 13 01:04:29 PM PDT 24
Peak memory 197060 kb
Host smart-ee0e817f-6094-4a8d-8b6b-b7b150616613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869222741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.1869222741
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.2710766346
Short name T474
Test name
Test status
Simulation time 780305077 ps
CPU time 1.28 seconds
Started Jun 13 01:14:43 PM PDT 24
Finished Jun 13 01:14:45 PM PDT 24
Peak memory 200720 kb
Host smart-6915beb3-a0f4-4670-9337-46714c23c732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710766346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.2710766346
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.1207804363
Short name T945
Test name
Test status
Simulation time 2409073095 ps
CPU time 2.11 seconds
Started Jun 13 01:02:28 PM PDT 24
Finished Jun 13 01:02:30 PM PDT 24
Peak memory 199696 kb
Host smart-df2d8bfc-b095-4ab8-9b74-4dcb19780929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207804363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.1207804363
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.2140355482
Short name T409
Test name
Test status
Simulation time 31867325459 ps
CPU time 12.6 seconds
Started Jun 13 01:39:01 PM PDT 24
Finished Jun 13 01:39:15 PM PDT 24
Peak memory 200628 kb
Host smart-06abfb32-c192-40fb-8041-120271aec604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140355482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.2140355482
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.4257060986
Short name T652
Test name
Test status
Simulation time 12653659 ps
CPU time 0.55 seconds
Started Jun 13 02:06:06 PM PDT 24
Finished Jun 13 02:06:07 PM PDT 24
Peak memory 196148 kb
Host smart-8fc305ff-5559-4129-9b9e-027aa05aa241
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257060986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.4257060986
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.3360571044
Short name T405
Test name
Test status
Simulation time 49113969169 ps
CPU time 21.23 seconds
Started Jun 13 02:17:18 PM PDT 24
Finished Jun 13 02:17:43 PM PDT 24
Peak memory 200768 kb
Host smart-6d9fc577-3095-4d5a-83ce-7f8e3c24fa02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360571044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.3360571044
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.3851176478
Short name T1051
Test name
Test status
Simulation time 93473225391 ps
CPU time 24.85 seconds
Started Jun 13 01:59:10 PM PDT 24
Finished Jun 13 01:59:36 PM PDT 24
Peak memory 200492 kb
Host smart-bea8cddb-5a22-4eae-844f-edb27b1f52d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851176478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.3851176478
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.2445983220
Short name T450
Test name
Test status
Simulation time 9280043637 ps
CPU time 15.07 seconds
Started Jun 13 01:02:26 PM PDT 24
Finished Jun 13 01:02:42 PM PDT 24
Peak memory 200776 kb
Host smart-3137f518-1fb4-4432-acdf-8f1e992a2ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445983220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.2445983220
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.283121193
Short name T322
Test name
Test status
Simulation time 236055885464 ps
CPU time 359.53 seconds
Started Jun 13 01:02:32 PM PDT 24
Finished Jun 13 01:08:32 PM PDT 24
Peak memory 197604 kb
Host smart-4d60052d-885c-49f1-8414-8b8d66cd69d5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283121193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.283121193
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.677874609
Short name T408
Test name
Test status
Simulation time 88240744254 ps
CPU time 411.52 seconds
Started Jun 13 02:10:49 PM PDT 24
Finished Jun 13 02:17:41 PM PDT 24
Peak memory 200820 kb
Host smart-d5118568-a893-4101-9d78-20cce8cdaa88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=677874609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.677874609
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.2258489636
Short name T387
Test name
Test status
Simulation time 8516148925 ps
CPU time 17.19 seconds
Started Jun 13 02:35:01 PM PDT 24
Finished Jun 13 02:35:19 PM PDT 24
Peak memory 199628 kb
Host smart-fd90f1c0-23d2-4b1e-aa6f-c1b774c989c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258489636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.2258489636
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_perf.2292896782
Short name T964
Test name
Test status
Simulation time 7530180542 ps
CPU time 116.07 seconds
Started Jun 13 01:02:27 PM PDT 24
Finished Jun 13 01:04:24 PM PDT 24
Peak memory 200696 kb
Host smart-f9bc9ceb-aa60-4283-baa3-1cfddd2ec7d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2292896782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.2292896782
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.1530215859
Short name T1088
Test name
Test status
Simulation time 4757825283 ps
CPU time 43.47 seconds
Started Jun 13 02:30:00 PM PDT 24
Finished Jun 13 02:30:44 PM PDT 24
Peak memory 199152 kb
Host smart-610dfc8d-04c6-48dc-8daf-06b0ec40c15e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1530215859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.1530215859
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.2053409016
Short name T273
Test name
Test status
Simulation time 117771289353 ps
CPU time 50.52 seconds
Started Jun 13 01:55:36 PM PDT 24
Finished Jun 13 01:56:28 PM PDT 24
Peak memory 200788 kb
Host smart-db096d09-d256-461f-b09a-6331c9b45f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053409016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.2053409016
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.685879971
Short name T289
Test name
Test status
Simulation time 2823527143 ps
CPU time 4.23 seconds
Started Jun 13 01:58:55 PM PDT 24
Finished Jun 13 01:59:01 PM PDT 24
Peak memory 197356 kb
Host smart-7a64833d-1dbf-4bc3-a900-ed876270d91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685879971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.685879971
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.3658341034
Short name T829
Test name
Test status
Simulation time 666355938 ps
CPU time 3.51 seconds
Started Jun 13 01:38:44 PM PDT 24
Finished Jun 13 01:38:48 PM PDT 24
Peak memory 200616 kb
Host smart-660e227d-eeea-4f8c-bbab-b5be80529405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658341034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.3658341034
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.283169975
Short name T862
Test name
Test status
Simulation time 280397941081 ps
CPU time 949.81 seconds
Started Jun 13 02:00:38 PM PDT 24
Finished Jun 13 02:16:30 PM PDT 24
Peak memory 229932 kb
Host smart-3e6eb880-d661-430b-9488-2e96d63ac6be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283169975 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.283169975
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.2860776355
Short name T400
Test name
Test status
Simulation time 600180458 ps
CPU time 1.84 seconds
Started Jun 13 01:02:30 PM PDT 24
Finished Jun 13 01:02:32 PM PDT 24
Peak memory 199816 kb
Host smart-bcdebea5-11b9-4115-b636-242b02a6ecc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860776355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.2860776355
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.3887634461
Short name T694
Test name
Test status
Simulation time 4575820005 ps
CPU time 8.68 seconds
Started Jun 13 01:02:29 PM PDT 24
Finished Jun 13 01:02:38 PM PDT 24
Peak memory 200832 kb
Host smart-62abee85-4685-47be-b2d2-e5ff44e9a041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887634461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.3887634461
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.3144154856
Short name T490
Test name
Test status
Simulation time 12528067 ps
CPU time 0.57 seconds
Started Jun 13 01:29:59 PM PDT 24
Finished Jun 13 01:30:00 PM PDT 24
Peak memory 195392 kb
Host smart-c877f80e-1bdf-4e5d-b5e0-033bf9e19080
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144154856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.3144154856
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.877724686
Short name T381
Test name
Test status
Simulation time 113907722075 ps
CPU time 314.13 seconds
Started Jun 13 01:02:29 PM PDT 24
Finished Jun 13 01:07:44 PM PDT 24
Peak memory 200680 kb
Host smart-639462df-0294-4a6f-9b6c-a3c1c88d9551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877724686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.877724686
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.2204732750
Short name T448
Test name
Test status
Simulation time 28706057487 ps
CPU time 32.05 seconds
Started Jun 13 02:48:30 PM PDT 24
Finished Jun 13 02:49:18 PM PDT 24
Peak memory 200564 kb
Host smart-76752e28-89a5-49a0-9e10-626c1d920305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204732750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.2204732750
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.4238316633
Short name T527
Test name
Test status
Simulation time 155790708290 ps
CPU time 68.36 seconds
Started Jun 13 01:02:26 PM PDT 24
Finished Jun 13 01:03:35 PM PDT 24
Peak memory 200704 kb
Host smart-26347523-b800-45e9-9603-147ee5cd41d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238316633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.4238316633
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.1486046182
Short name T672
Test name
Test status
Simulation time 40851348725 ps
CPU time 20.7 seconds
Started Jun 13 01:22:39 PM PDT 24
Finished Jun 13 01:23:01 PM PDT 24
Peak memory 200584 kb
Host smart-dffefa98-d1db-40a4-b1fb-5154b64ed003
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486046182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.1486046182
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.3665136549
Short name T924
Test name
Test status
Simulation time 83638922004 ps
CPU time 607.13 seconds
Started Jun 13 01:02:28 PM PDT 24
Finished Jun 13 01:12:36 PM PDT 24
Peak memory 200724 kb
Host smart-a43e3cbf-66bd-409d-97f9-2d97f24e92b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3665136549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.3665136549
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.432238535
Short name T328
Test name
Test status
Simulation time 8445081268 ps
CPU time 9.51 seconds
Started Jun 13 01:19:53 PM PDT 24
Finished Jun 13 01:20:03 PM PDT 24
Peak memory 200428 kb
Host smart-b3a79645-2e83-4f69-a853-4fa505e8d6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432238535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.432238535
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.1242778371
Short name T656
Test name
Test status
Simulation time 23908686057 ps
CPU time 34.47 seconds
Started Jun 13 02:32:02 PM PDT 24
Finished Jun 13 02:32:42 PM PDT 24
Peak memory 200860 kb
Host smart-0f1b6004-6374-4e49-8049-c2b8e9efb31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242778371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.1242778371
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.3988230216
Short name T593
Test name
Test status
Simulation time 32871957664 ps
CPU time 1669.99 seconds
Started Jun 13 01:34:34 PM PDT 24
Finished Jun 13 02:02:25 PM PDT 24
Peak memory 200804 kb
Host smart-07ccacb8-cf1c-40fb-a1e2-9797a597612a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3988230216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.3988230216
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.1525354241
Short name T537
Test name
Test status
Simulation time 1496674420 ps
CPU time 3.37 seconds
Started Jun 13 01:25:19 PM PDT 24
Finished Jun 13 01:25:23 PM PDT 24
Peak memory 198832 kb
Host smart-733ab56a-1f63-48ab-9caf-781e3cb77d20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1525354241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.1525354241
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.2188836204
Short name T458
Test name
Test status
Simulation time 87298900206 ps
CPU time 35.24 seconds
Started Jun 13 01:59:18 PM PDT 24
Finished Jun 13 01:59:55 PM PDT 24
Peak memory 200804 kb
Host smart-ab18c4df-68bd-4fdb-b67a-d8de0e3991e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188836204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.2188836204
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.2526908891
Short name T644
Test name
Test status
Simulation time 2100144902 ps
CPU time 3.87 seconds
Started Jun 13 01:27:52 PM PDT 24
Finished Jun 13 01:27:57 PM PDT 24
Peak memory 196424 kb
Host smart-7125b86d-5b02-4a37-a541-4bd2f4dd1727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526908891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.2526908891
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.2348389877
Short name T279
Test name
Test status
Simulation time 492551018 ps
CPU time 1.27 seconds
Started Jun 13 02:33:36 PM PDT 24
Finished Jun 13 02:33:39 PM PDT 24
Peak memory 200708 kb
Host smart-230d9c33-d3e3-4ccc-9c9e-4ee50cea3730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348389877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.2348389877
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.2632978800
Short name T806
Test name
Test status
Simulation time 165451745151 ps
CPU time 263.62 seconds
Started Jun 13 01:50:27 PM PDT 24
Finished Jun 13 01:54:51 PM PDT 24
Peak memory 200848 kb
Host smart-ec1cf5bb-b71f-4e00-8fc7-402f0b7539ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632978800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.2632978800
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.1596231828
Short name T347
Test name
Test status
Simulation time 1264811540 ps
CPU time 3.98 seconds
Started Jun 13 02:33:01 PM PDT 24
Finished Jun 13 02:33:06 PM PDT 24
Peak memory 200236 kb
Host smart-9e9da796-9cc8-429b-a2ea-0092630ea9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596231828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.1596231828
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.3906505722
Short name T791
Test name
Test status
Simulation time 60397119496 ps
CPU time 35.16 seconds
Started Jun 13 01:47:33 PM PDT 24
Finished Jun 13 01:48:09 PM PDT 24
Peak memory 200860 kb
Host smart-b766640f-5772-40a7-b45b-fd5b022b3cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906505722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.3906505722
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.1554716955
Short name T956
Test name
Test status
Simulation time 23708667 ps
CPU time 0.57 seconds
Started Jun 13 01:05:58 PM PDT 24
Finished Jun 13 01:05:59 PM PDT 24
Peak memory 196312 kb
Host smart-83d05050-3e94-4382-b0c4-a91284dcc6f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554716955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.1554716955
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.1300461781
Short name T1050
Test name
Test status
Simulation time 59136260311 ps
CPU time 18.38 seconds
Started Jun 13 01:55:07 PM PDT 24
Finished Jun 13 01:55:26 PM PDT 24
Peak memory 200848 kb
Host smart-4f43ce76-bc18-4151-ac0b-f584cda09045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300461781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.1300461781
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.2408749606
Short name T887
Test name
Test status
Simulation time 17380951794 ps
CPU time 28.3 seconds
Started Jun 13 01:51:16 PM PDT 24
Finished Jun 13 01:51:45 PM PDT 24
Peak memory 200516 kb
Host smart-b84f2aa3-7f7e-47c2-94c8-9cc3c3982e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408749606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.2408749606
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.2195050677
Short name T695
Test name
Test status
Simulation time 24499013897 ps
CPU time 36.54 seconds
Started Jun 13 01:34:08 PM PDT 24
Finished Jun 13 01:34:46 PM PDT 24
Peak memory 200792 kb
Host smart-c9873b2c-e917-44be-9b69-84e7acd64282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195050677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.2195050677
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.1368119377
Short name T401
Test name
Test status
Simulation time 294390328049 ps
CPU time 390.3 seconds
Started Jun 13 01:27:24 PM PDT 24
Finished Jun 13 01:33:56 PM PDT 24
Peak memory 200768 kb
Host smart-3fc3f38c-3162-451b-bfcb-34aee27d906c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368119377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.1368119377
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.4210228452
Short name T362
Test name
Test status
Simulation time 58735027808 ps
CPU time 336.93 seconds
Started Jun 13 01:02:26 PM PDT 24
Finished Jun 13 01:08:04 PM PDT 24
Peak memory 200784 kb
Host smart-b55f7af9-b371-49fe-86ac-804083bd5ed3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4210228452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.4210228452
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.576842446
Short name T1015
Test name
Test status
Simulation time 1226753085 ps
CPU time 1.2 seconds
Started Jun 13 01:40:42 PM PDT 24
Finished Jun 13 01:40:44 PM PDT 24
Peak memory 196400 kb
Host smart-141d3516-45cb-4698-8cd9-8727c8f0077e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576842446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.576842446
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.2251035130
Short name T616
Test name
Test status
Simulation time 50308271320 ps
CPU time 81.27 seconds
Started Jun 13 02:06:17 PM PDT 24
Finished Jun 13 02:07:39 PM PDT 24
Peak memory 200788 kb
Host smart-16caab3a-2d7a-43cd-9bc4-05a4615850e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251035130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.2251035130
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.405838410
Short name T988
Test name
Test status
Simulation time 7545257013 ps
CPU time 459.85 seconds
Started Jun 13 02:43:06 PM PDT 24
Finished Jun 13 02:50:49 PM PDT 24
Peak memory 200856 kb
Host smart-8e9b3ece-0424-4d20-a5cd-307b57369b92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=405838410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.405838410
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.3386500382
Short name T812
Test name
Test status
Simulation time 3570018241 ps
CPU time 14.29 seconds
Started Jun 13 02:08:54 PM PDT 24
Finished Jun 13 02:09:08 PM PDT 24
Peak memory 200004 kb
Host smart-e3caffe2-f318-49c2-8077-ce1ae58cacd7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3386500382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.3386500382
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.3582712109
Short name T720
Test name
Test status
Simulation time 203410953813 ps
CPU time 78.57 seconds
Started Jun 13 01:24:48 PM PDT 24
Finished Jun 13 01:26:08 PM PDT 24
Peak memory 200836 kb
Host smart-6f068ac9-de8c-4f7f-b708-e271d8089359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582712109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.3582712109
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.3526505782
Short name T739
Test name
Test status
Simulation time 3880410129 ps
CPU time 2.29 seconds
Started Jun 13 01:50:39 PM PDT 24
Finished Jun 13 01:50:43 PM PDT 24
Peak memory 196896 kb
Host smart-0fc025f0-ab1c-41b2-9339-9cecf8a33c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526505782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.3526505782
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.2124818962
Short name T647
Test name
Test status
Simulation time 155793744 ps
CPU time 0.83 seconds
Started Jun 13 01:29:26 PM PDT 24
Finished Jun 13 01:29:28 PM PDT 24
Peak memory 198496 kb
Host smart-4a64f602-7158-403b-9c24-7a3affe71d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124818962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.2124818962
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.515515161
Short name T832
Test name
Test status
Simulation time 259869639044 ps
CPU time 703.15 seconds
Started Jun 13 02:04:01 PM PDT 24
Finished Jun 13 02:15:45 PM PDT 24
Peak memory 200772 kb
Host smart-bfd06367-3e23-4af3-b36e-2a0249bf2247
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515515161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.515515161
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.2281862731
Short name T623
Test name
Test status
Simulation time 1426062962 ps
CPU time 5.42 seconds
Started Jun 13 01:02:29 PM PDT 24
Finished Jun 13 01:02:36 PM PDT 24
Peak memory 200172 kb
Host smart-1a7ef7f0-5e17-479e-add1-7216dffed461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281862731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.2281862731
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.2191760697
Short name T766
Test name
Test status
Simulation time 49683100429 ps
CPU time 78.48 seconds
Started Jun 13 01:04:56 PM PDT 24
Finished Jun 13 01:06:15 PM PDT 24
Peak memory 200624 kb
Host smart-cf196cc9-0704-4d5f-b85a-49bf69789dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191760697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.2191760697
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.1778263886
Short name T718
Test name
Test status
Simulation time 15016407 ps
CPU time 0.58 seconds
Started Jun 13 01:57:29 PM PDT 24
Finished Jun 13 01:57:31 PM PDT 24
Peak memory 196384 kb
Host smart-9e9ff613-ec25-482e-ab2d-239e78265740
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778263886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.1778263886
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.865203449
Short name T888
Test name
Test status
Simulation time 132312421362 ps
CPU time 316.06 seconds
Started Jun 13 01:07:27 PM PDT 24
Finished Jun 13 01:12:45 PM PDT 24
Peak memory 200804 kb
Host smart-1f5f7c76-0e48-4bb0-b2c6-9199c286540b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865203449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.865203449
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.2635442290
Short name T957
Test name
Test status
Simulation time 31538819321 ps
CPU time 12.69 seconds
Started Jun 13 01:20:04 PM PDT 24
Finished Jun 13 01:20:18 PM PDT 24
Peak memory 200796 kb
Host smart-4b9b087e-4c4c-43bf-a523-1a0c5acb30b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635442290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.2635442290
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.2174786781
Short name T1053
Test name
Test status
Simulation time 95491370814 ps
CPU time 168.15 seconds
Started Jun 13 02:20:06 PM PDT 24
Finished Jun 13 02:23:02 PM PDT 24
Peak memory 200824 kb
Host smart-2a23f577-5981-4419-bf64-9fb501306ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174786781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.2174786781
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.2319688144
Short name T423
Test name
Test status
Simulation time 52105044692 ps
CPU time 71.17 seconds
Started Jun 13 02:39:38 PM PDT 24
Finished Jun 13 02:40:56 PM PDT 24
Peak memory 200812 kb
Host smart-c21c1f77-d373-4727-b052-b41c39deec33
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319688144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.2319688144
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.1778053258
Short name T479
Test name
Test status
Simulation time 103739532703 ps
CPU time 734.13 seconds
Started Jun 13 01:02:35 PM PDT 24
Finished Jun 13 01:14:50 PM PDT 24
Peak memory 200808 kb
Host smart-f66cf304-73ce-4d10-9706-142817950446
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1778053258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.1778053258
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.3439390200
Short name T18
Test name
Test status
Simulation time 8282133957 ps
CPU time 7.63 seconds
Started Jun 13 01:57:33 PM PDT 24
Finished Jun 13 01:57:42 PM PDT 24
Peak memory 199936 kb
Host smart-c1987fdf-3416-4379-836c-b7cb696be509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439390200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.3439390200
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_perf.3841782772
Short name T1033
Test name
Test status
Simulation time 9045439408 ps
CPU time 553.11 seconds
Started Jun 13 01:49:01 PM PDT 24
Finished Jun 13 01:58:16 PM PDT 24
Peak memory 200792 kb
Host smart-649390c8-9afb-4a0c-81f1-1b553e810a07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3841782772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.3841782772
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.2374282318
Short name T755
Test name
Test status
Simulation time 2341367740 ps
CPU time 3.13 seconds
Started Jun 13 01:02:30 PM PDT 24
Finished Jun 13 01:02:34 PM PDT 24
Peak memory 198868 kb
Host smart-3cd32852-b24f-4765-9268-70eae2e1fbec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2374282318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.2374282318
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.3767100021
Short name T368
Test name
Test status
Simulation time 27321414383 ps
CPU time 48.22 seconds
Started Jun 13 01:02:41 PM PDT 24
Finished Jun 13 01:03:30 PM PDT 24
Peak memory 200644 kb
Host smart-35122f14-a702-4559-b4ac-673964dceb32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767100021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.3767100021
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.1471230335
Short name T884
Test name
Test status
Simulation time 42943422936 ps
CPU time 24.53 seconds
Started Jun 13 01:02:36 PM PDT 24
Finished Jun 13 01:03:01 PM PDT 24
Peak memory 196896 kb
Host smart-19ecaa80-c9d8-47e7-88f4-ac62fe2385d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471230335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.1471230335
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.2074162130
Short name T818
Test name
Test status
Simulation time 547377588 ps
CPU time 3.52 seconds
Started Jun 13 01:13:36 PM PDT 24
Finished Jun 13 01:13:40 PM PDT 24
Peak memory 200572 kb
Host smart-560ad9f2-5c26-4a02-b54b-57c89c55838e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074162130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.2074162130
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.3535450528
Short name T50
Test name
Test status
Simulation time 162480908059 ps
CPU time 1582.77 seconds
Started Jun 13 02:02:28 PM PDT 24
Finished Jun 13 02:28:52 PM PDT 24
Peak memory 233688 kb
Host smart-146a1f80-3b1c-4d10-bfdd-57e674686078
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535450528 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.3535450528
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.3856915577
Short name T361
Test name
Test status
Simulation time 2369481947 ps
CPU time 2.03 seconds
Started Jun 13 02:11:47 PM PDT 24
Finished Jun 13 02:11:49 PM PDT 24
Peak memory 200612 kb
Host smart-4d859d79-b52f-4655-bd47-d7d64a906a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856915577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.3856915577
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.507489388
Short name T631
Test name
Test status
Simulation time 35031502729 ps
CPU time 51.14 seconds
Started Jun 13 01:21:14 PM PDT 24
Finished Jun 13 01:22:07 PM PDT 24
Peak memory 200724 kb
Host smart-653a6641-6b5c-4e23-a447-88627d648e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507489388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.507489388
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.2694827058
Short name T397
Test name
Test status
Simulation time 13970008 ps
CPU time 0.56 seconds
Started Jun 13 01:02:38 PM PDT 24
Finished Jun 13 01:02:39 PM PDT 24
Peak memory 196056 kb
Host smart-abddd484-306e-4ecd-b251-e8f13ec58435
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694827058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.2694827058
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.1606014890
Short name T678
Test name
Test status
Simulation time 40928515891 ps
CPU time 18.91 seconds
Started Jun 13 02:22:28 PM PDT 24
Finished Jun 13 02:22:48 PM PDT 24
Peak memory 200840 kb
Host smart-fb591f2b-08c1-45c1-bc72-514d2cb7aa96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606014890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.1606014890
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.1381944435
Short name T429
Test name
Test status
Simulation time 68420910595 ps
CPU time 7.38 seconds
Started Jun 13 01:28:04 PM PDT 24
Finished Jun 13 01:28:13 PM PDT 24
Peak memory 200784 kb
Host smart-9e9d9d78-1d5e-4cf2-a39a-8acf01658de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381944435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.1381944435
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.2881505359
Short name T219
Test name
Test status
Simulation time 20766110427 ps
CPU time 16.48 seconds
Started Jun 13 01:39:36 PM PDT 24
Finished Jun 13 01:39:53 PM PDT 24
Peak memory 200828 kb
Host smart-26d29190-fcb7-49b9-8640-26181ecdec1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881505359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.2881505359
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.1512479723
Short name T416
Test name
Test status
Simulation time 289601291067 ps
CPU time 295.7 seconds
Started Jun 13 01:02:35 PM PDT 24
Finished Jun 13 01:07:32 PM PDT 24
Peak memory 197760 kb
Host smart-23500d40-f9d8-4f37-b307-25559fd8f50b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512479723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.1512479723
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.3713132909
Short name T473
Test name
Test status
Simulation time 171362929718 ps
CPU time 1801.85 seconds
Started Jun 13 01:41:20 PM PDT 24
Finished Jun 13 02:11:24 PM PDT 24
Peak memory 200752 kb
Host smart-17317b9b-5c39-47da-b16f-080194530df8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3713132909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.3713132909
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.2023301148
Short name T721
Test name
Test status
Simulation time 6696860101 ps
CPU time 12.26 seconds
Started Jun 13 01:27:31 PM PDT 24
Finished Jun 13 01:27:44 PM PDT 24
Peak memory 198496 kb
Host smart-b44b211a-816b-489c-a2f0-be990e645ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023301148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.2023301148
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_perf.2554872963
Short name T242
Test name
Test status
Simulation time 4962526583 ps
CPU time 62.62 seconds
Started Jun 13 01:14:00 PM PDT 24
Finished Jun 13 01:15:03 PM PDT 24
Peak memory 200816 kb
Host smart-4534c787-ae9c-4011-8d13-69439be165a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2554872963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.2554872963
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.1911429047
Short name T622
Test name
Test status
Simulation time 5774382714 ps
CPU time 20.69 seconds
Started Jun 13 01:52:25 PM PDT 24
Finished Jun 13 01:52:47 PM PDT 24
Peak memory 199704 kb
Host smart-8552e836-240d-4e0c-90be-0c9723ba45ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1911429047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.1911429047
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.2793579811
Short name T602
Test name
Test status
Simulation time 119506800063 ps
CPU time 168.31 seconds
Started Jun 13 01:02:34 PM PDT 24
Finished Jun 13 01:05:23 PM PDT 24
Peak memory 200588 kb
Host smart-cbab21f1-1e67-4883-b935-cbe0c789ee3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793579811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.2793579811
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.3511823684
Short name T636
Test name
Test status
Simulation time 29234655782 ps
CPU time 11.1 seconds
Started Jun 13 01:21:05 PM PDT 24
Finished Jun 13 01:21:17 PM PDT 24
Peak memory 197052 kb
Host smart-9be8c1c7-1de7-49aa-94fb-84683445128c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511823684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.3511823684
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.2778536889
Short name T1013
Test name
Test status
Simulation time 11037895445 ps
CPU time 27.17 seconds
Started Jun 13 01:41:04 PM PDT 24
Finished Jun 13 01:41:33 PM PDT 24
Peak memory 200808 kb
Host smart-eef40887-a443-4b68-a409-bbfab8651e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778536889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.2778536889
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.1320040440
Short name T1011
Test name
Test status
Simulation time 435691593876 ps
CPU time 824.7 seconds
Started Jun 13 01:48:41 PM PDT 24
Finished Jun 13 02:02:27 PM PDT 24
Peak memory 225412 kb
Host smart-1690c2a9-a70c-4cb7-bd5b-2f718202210e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320040440 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.1320040440
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.3729626678
Short name T717
Test name
Test status
Simulation time 953620806 ps
CPU time 3.91 seconds
Started Jun 13 01:27:31 PM PDT 24
Finished Jun 13 01:27:36 PM PDT 24
Peak memory 200272 kb
Host smart-043fe4d8-917a-4c32-ba3d-e27893756129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729626678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.3729626678
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_alert_test.1020534365
Short name T358
Test name
Test status
Simulation time 16877366 ps
CPU time 0.58 seconds
Started Jun 13 01:02:36 PM PDT 24
Finished Jun 13 01:02:37 PM PDT 24
Peak memory 196060 kb
Host smart-6d4ce1f4-5441-4e6b-a00d-1648f61c6ee4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020534365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.1020534365
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.1900735759
Short name T175
Test name
Test status
Simulation time 56257628382 ps
CPU time 26.93 seconds
Started Jun 13 01:02:34 PM PDT 24
Finished Jun 13 01:03:02 PM PDT 24
Peak memory 200740 kb
Host smart-b758aabd-0bd0-41a0-9536-6d68df383c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900735759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.1900735759
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.2556329920
Short name T45
Test name
Test status
Simulation time 8821959890 ps
CPU time 13.2 seconds
Started Jun 13 01:19:28 PM PDT 24
Finished Jun 13 01:19:42 PM PDT 24
Peak memory 200272 kb
Host smart-0ff92eaa-c9d7-41ae-8814-3bc1c584e5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556329920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.2556329920
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.773270686
Short name T180
Test name
Test status
Simulation time 38463872421 ps
CPU time 30.32 seconds
Started Jun 13 02:51:26 PM PDT 24
Finished Jun 13 02:52:06 PM PDT 24
Peak memory 200804 kb
Host smart-6162017c-84c5-4620-af25-9b48e07653b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773270686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.773270686
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.3133006431
Short name T853
Test name
Test status
Simulation time 52686198380 ps
CPU time 46.29 seconds
Started Jun 13 01:44:37 PM PDT 24
Finished Jun 13 01:45:24 PM PDT 24
Peak memory 200504 kb
Host smart-9d602df2-f3ee-47c4-9714-af3ac5af5006
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133006431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.3133006431
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.1718888380
Short name T1064
Test name
Test status
Simulation time 167631021483 ps
CPU time 1315.58 seconds
Started Jun 13 01:02:34 PM PDT 24
Finished Jun 13 01:24:30 PM PDT 24
Peak memory 200692 kb
Host smart-ea1b3ecc-c1ce-4d75-b0c5-e1d817ba120d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1718888380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.1718888380
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.3169000909
Short name T529
Test name
Test status
Simulation time 2614780278 ps
CPU time 2.75 seconds
Started Jun 13 01:56:30 PM PDT 24
Finished Jun 13 01:56:36 PM PDT 24
Peak memory 197132 kb
Host smart-ada86a6b-dcdb-42f7-95da-5cc52800d15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169000909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.3169000909
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.1514432649
Short name T740
Test name
Test status
Simulation time 28474683927 ps
CPU time 10.17 seconds
Started Jun 13 01:35:33 PM PDT 24
Finished Jun 13 01:35:44 PM PDT 24
Peak memory 200576 kb
Host smart-f252451c-d4f8-4420-9aff-3587d85394ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514432649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.1514432649
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.3409205872
Short name T252
Test name
Test status
Simulation time 17071325545 ps
CPU time 189.13 seconds
Started Jun 13 01:02:36 PM PDT 24
Finished Jun 13 01:05:46 PM PDT 24
Peak memory 200788 kb
Host smart-9b8a446b-e1c6-44f3-8d1b-ab9c173bec59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3409205872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.3409205872
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.3409185322
Short name T398
Test name
Test status
Simulation time 7270997684 ps
CPU time 9.83 seconds
Started Jun 13 02:19:14 PM PDT 24
Finished Jun 13 02:19:32 PM PDT 24
Peak memory 198984 kb
Host smart-d41bc04b-16f7-422c-a917-e48177ddb6c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3409185322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.3409185322
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.1164435790
Short name T747
Test name
Test status
Simulation time 117061512515 ps
CPU time 164.39 seconds
Started Jun 13 01:51:54 PM PDT 24
Finished Jun 13 01:54:39 PM PDT 24
Peak memory 200804 kb
Host smart-ec0c3f4b-a92d-41b3-b88a-a0c3bf04591f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164435790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.1164435790
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.2875197938
Short name T1058
Test name
Test status
Simulation time 34174993948 ps
CPU time 55.14 seconds
Started Jun 13 01:53:58 PM PDT 24
Finished Jun 13 01:54:55 PM PDT 24
Peak memory 197120 kb
Host smart-c3cee26f-f122-4d25-9ae2-535cec199bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875197938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.2875197938
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.1185711629
Short name T849
Test name
Test status
Simulation time 319370529 ps
CPU time 1.31 seconds
Started Jun 13 01:17:19 PM PDT 24
Finished Jun 13 01:17:21 PM PDT 24
Peak memory 200652 kb
Host smart-3702caaa-2ca6-48bd-81c1-0ad279413c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185711629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.1185711629
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.2038511819
Short name T459
Test name
Test status
Simulation time 1071601523 ps
CPU time 1.92 seconds
Started Jun 13 02:39:49 PM PDT 24
Finished Jun 13 02:39:59 PM PDT 24
Peak memory 199452 kb
Host smart-419a2443-822a-4741-a6e3-0a4132b9d688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038511819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.2038511819
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.608609604
Short name T892
Test name
Test status
Simulation time 46038831321 ps
CPU time 21.53 seconds
Started Jun 13 01:36:20 PM PDT 24
Finished Jun 13 01:36:42 PM PDT 24
Peak memory 200784 kb
Host smart-03051e51-fab3-4247-bff1-bf17a8b7def4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608609604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.608609604
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.2653189890
Short name T635
Test name
Test status
Simulation time 21885348 ps
CPU time 0.57 seconds
Started Jun 13 01:00:51 PM PDT 24
Finished Jun 13 01:00:53 PM PDT 24
Peak memory 196096 kb
Host smart-0e09d960-abc1-4f0f-a9d5-2edcfd4c154a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653189890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.2653189890
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.4133505966
Short name T975
Test name
Test status
Simulation time 37424361737 ps
CPU time 49.44 seconds
Started Jun 13 01:00:45 PM PDT 24
Finished Jun 13 01:01:35 PM PDT 24
Peak memory 200612 kb
Host smart-abfbf06d-ba20-4f06-81c4-b2c5e4eefa93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133505966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.4133505966
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.3881720025
Short name T309
Test name
Test status
Simulation time 14951927250 ps
CPU time 6.67 seconds
Started Jun 13 01:00:44 PM PDT 24
Finished Jun 13 01:00:51 PM PDT 24
Peak memory 199424 kb
Host smart-0a773da5-8afc-4548-9d3a-3d6ee347d4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881720025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.3881720025
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.493540368
Short name T427
Test name
Test status
Simulation time 96092973350 ps
CPU time 27.68 seconds
Started Jun 13 01:00:40 PM PDT 24
Finished Jun 13 01:01:09 PM PDT 24
Peak memory 200724 kb
Host smart-6ffe2f7c-04d1-402a-8718-93fc44df79e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493540368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.493540368
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.2064998206
Short name T1089
Test name
Test status
Simulation time 160902489257 ps
CPU time 68.14 seconds
Started Jun 13 01:00:41 PM PDT 24
Finished Jun 13 01:01:50 PM PDT 24
Peak memory 199852 kb
Host smart-da948190-f304-42d3-bb8a-5124c6ad9c90
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064998206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.2064998206
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.3467588871
Short name T548
Test name
Test status
Simulation time 161169385866 ps
CPU time 621.87 seconds
Started Jun 13 01:00:41 PM PDT 24
Finished Jun 13 01:11:04 PM PDT 24
Peak memory 200796 kb
Host smart-17cbcc18-8165-49ee-a420-1774daa538a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3467588871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.3467588871
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.1456922248
Short name T343
Test name
Test status
Simulation time 6425748712 ps
CPU time 6.68 seconds
Started Jun 13 01:00:43 PM PDT 24
Finished Jun 13 01:00:50 PM PDT 24
Peak memory 199916 kb
Host smart-d57ec3bb-a326-44c5-a9c9-87ab5662d513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456922248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.1456922248
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_perf.7538825
Short name T993
Test name
Test status
Simulation time 27411929090 ps
CPU time 340.7 seconds
Started Jun 13 01:00:42 PM PDT 24
Finished Jun 13 01:06:24 PM PDT 24
Peak memory 200760 kb
Host smart-b9fce6d0-3264-42bd-a983-04f3fc9ccdf1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=7538825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.7538825
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.4069265678
Short name T569
Test name
Test status
Simulation time 3087620195 ps
CPU time 6.25 seconds
Started Jun 13 01:00:41 PM PDT 24
Finished Jun 13 01:00:49 PM PDT 24
Peak memory 199164 kb
Host smart-606bda9d-799f-4781-9db3-bd749604c860
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4069265678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.4069265678
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.3573303769
Short name T1052
Test name
Test status
Simulation time 25305642466 ps
CPU time 41.59 seconds
Started Jun 13 01:00:46 PM PDT 24
Finished Jun 13 01:01:28 PM PDT 24
Peak memory 200784 kb
Host smart-f8857a7d-4f7f-45e8-a196-d1e478a2de40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573303769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.3573303769
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.3568916933
Short name T463
Test name
Test status
Simulation time 2866134092 ps
CPU time 2.38 seconds
Started Jun 13 01:00:43 PM PDT 24
Finished Jun 13 01:00:46 PM PDT 24
Peak memory 196788 kb
Host smart-09ad1c86-6931-48ab-b70f-dd70347492ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568916933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.3568916933
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.1099920166
Short name T22
Test name
Test status
Simulation time 534416125 ps
CPU time 0.81 seconds
Started Jun 13 01:00:53 PM PDT 24
Finished Jun 13 01:00:57 PM PDT 24
Peak memory 219232 kb
Host smart-4cac9426-460b-43ad-932c-dd4efb428971
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099920166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.1099920166
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.3979826903
Short name T707
Test name
Test status
Simulation time 285685073 ps
CPU time 1.75 seconds
Started Jun 13 01:00:41 PM PDT 24
Finished Jun 13 01:00:44 PM PDT 24
Peak memory 200500 kb
Host smart-98a0e863-db53-4d7e-b190-0a6df0dd9b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979826903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.3979826903
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.533866058
Short name T686
Test name
Test status
Simulation time 75753380132 ps
CPU time 472.78 seconds
Started Jun 13 01:00:42 PM PDT 24
Finished Jun 13 01:08:36 PM PDT 24
Peak memory 217228 kb
Host smart-462546be-ea32-4971-9405-09090e9e0af9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533866058 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.533866058
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.1345905001
Short name T941
Test name
Test status
Simulation time 664036146 ps
CPU time 2.37 seconds
Started Jun 13 01:00:45 PM PDT 24
Finished Jun 13 01:00:48 PM PDT 24
Peak memory 199228 kb
Host smart-d6f38fae-fe3b-4504-9608-b114dc19528c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345905001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.1345905001
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.1110966276
Short name T44
Test name
Test status
Simulation time 23900339767 ps
CPU time 9.37 seconds
Started Jun 13 01:00:46 PM PDT 24
Finished Jun 13 01:00:56 PM PDT 24
Peak memory 200384 kb
Host smart-051d1974-396e-409e-aae8-32cd0c0dacad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110966276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.1110966276
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.4141128698
Short name T1049
Test name
Test status
Simulation time 14009270 ps
CPU time 0.59 seconds
Started Jun 13 01:17:55 PM PDT 24
Finished Jun 13 01:17:56 PM PDT 24
Peak memory 196428 kb
Host smart-fa3877c3-6976-4ec9-9e7c-c2d558484598
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141128698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.4141128698
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.3912613605
Short name T943
Test name
Test status
Simulation time 33457432375 ps
CPU time 62.91 seconds
Started Jun 13 01:49:55 PM PDT 24
Finished Jun 13 01:51:00 PM PDT 24
Peak memory 200808 kb
Host smart-18ef166f-97bf-4535-a155-c94d1b4bfc1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912613605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.3912613605
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.1090037013
Short name T891
Test name
Test status
Simulation time 34745674578 ps
CPU time 66.75 seconds
Started Jun 13 01:02:35 PM PDT 24
Finished Jun 13 01:03:43 PM PDT 24
Peak memory 200880 kb
Host smart-dac8d323-df73-4f6d-8592-8a0af17e1f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090037013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.1090037013
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.1706680118
Short name T292
Test name
Test status
Simulation time 18942548750 ps
CPU time 32.26 seconds
Started Jun 13 01:02:37 PM PDT 24
Finished Jun 13 01:03:10 PM PDT 24
Peak memory 200720 kb
Host smart-91dbfc46-06e4-442f-a534-94ed2adb9761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706680118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.1706680118
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.3766303763
Short name T677
Test name
Test status
Simulation time 13372516345 ps
CPU time 27.27 seconds
Started Jun 13 01:44:04 PM PDT 24
Finished Jun 13 01:44:33 PM PDT 24
Peak memory 200880 kb
Host smart-9d142f24-aa34-4c8e-9138-24fd6f85e081
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766303763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.3766303763
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.2481205389
Short name T748
Test name
Test status
Simulation time 127787406714 ps
CPU time 801.52 seconds
Started Jun 13 01:02:37 PM PDT 24
Finished Jun 13 01:15:59 PM PDT 24
Peak memory 200764 kb
Host smart-86077d68-eb2d-4c1b-88eb-ea13787e5269
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2481205389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.2481205389
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.1296377194
Short name T630
Test name
Test status
Simulation time 4261606147 ps
CPU time 8.1 seconds
Started Jun 13 01:02:36 PM PDT 24
Finished Jun 13 01:02:45 PM PDT 24
Peak memory 200080 kb
Host smart-de9f67a0-f304-4efe-9c57-c0af54daaca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296377194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.1296377194
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_perf.4071018421
Short name T454
Test name
Test status
Simulation time 5505688363 ps
CPU time 321.67 seconds
Started Jun 13 02:18:10 PM PDT 24
Finished Jun 13 02:23:40 PM PDT 24
Peak memory 200752 kb
Host smart-3de9f016-8420-4305-adf4-166132d0763e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4071018421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.4071018421
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.2433380905
Short name T797
Test name
Test status
Simulation time 5855551907 ps
CPU time 52.83 seconds
Started Jun 13 01:50:53 PM PDT 24
Finished Jun 13 01:51:48 PM PDT 24
Peak memory 199056 kb
Host smart-242ebc98-e29d-43f6-b3d1-d4da111cec2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2433380905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.2433380905
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.102263084
Short name T469
Test name
Test status
Simulation time 53608865824 ps
CPU time 44.93 seconds
Started Jun 13 01:02:35 PM PDT 24
Finished Jun 13 01:03:20 PM PDT 24
Peak memory 200584 kb
Host smart-3955a75e-1386-42d4-ad7d-ec4c6d56428b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102263084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.102263084
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.447915783
Short name T787
Test name
Test status
Simulation time 33273786711 ps
CPU time 56.24 seconds
Started Jun 13 01:02:35 PM PDT 24
Finished Jun 13 01:03:32 PM PDT 24
Peak memory 196592 kb
Host smart-c861f44b-7e10-4360-8585-d834d528783a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447915783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.447915783
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.1067516866
Short name T467
Test name
Test status
Simulation time 269188180 ps
CPU time 1.9 seconds
Started Jun 13 01:48:31 PM PDT 24
Finished Jun 13 01:48:33 PM PDT 24
Peak memory 199572 kb
Host smart-3083a661-f572-43e3-b3c1-4b6661122201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067516866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.1067516866
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.105942187
Short name T471
Test name
Test status
Simulation time 1142137728 ps
CPU time 3.4 seconds
Started Jun 13 02:08:13 PM PDT 24
Finished Jun 13 02:08:18 PM PDT 24
Peak memory 199548 kb
Host smart-b629b853-2ebc-4a15-b5a1-3ff9137d0eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105942187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.105942187
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.663774764
Short name T485
Test name
Test status
Simulation time 10232956333 ps
CPU time 8.25 seconds
Started Jun 13 02:26:16 PM PDT 24
Finished Jun 13 02:26:25 PM PDT 24
Peak memory 197480 kb
Host smart-d94a8c25-d226-4959-a03c-085c0b5bd412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663774764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.663774764
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.2811846575
Short name T546
Test name
Test status
Simulation time 34209051 ps
CPU time 0.57 seconds
Started Jun 13 01:26:14 PM PDT 24
Finished Jun 13 01:26:15 PM PDT 24
Peak memory 196352 kb
Host smart-16b8eae0-ec3e-46b3-b6f2-b5f582e060b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811846575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.2811846575
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.13082338
Short name T665
Test name
Test status
Simulation time 76872141748 ps
CPU time 180.07 seconds
Started Jun 13 01:06:57 PM PDT 24
Finished Jun 13 01:10:00 PM PDT 24
Peak memory 200692 kb
Host smart-2ad504a7-a000-4055-a608-f0b716e4f768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13082338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.13082338
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.4169634772
Short name T693
Test name
Test status
Simulation time 132491688619 ps
CPU time 16.55 seconds
Started Jun 13 02:28:36 PM PDT 24
Finished Jun 13 02:28:54 PM PDT 24
Peak memory 200784 kb
Host smart-01167d60-b6b5-4eaa-ac22-73e39179aed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169634772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.4169634772
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.1215465905
Short name T928
Test name
Test status
Simulation time 64256956690 ps
CPU time 27.36 seconds
Started Jun 13 01:34:14 PM PDT 24
Finished Jun 13 01:34:42 PM PDT 24
Peak memory 200824 kb
Host smart-11c21015-4c24-492c-a635-4a8471143e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215465905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.1215465905
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.1634036792
Short name T908
Test name
Test status
Simulation time 37616850356 ps
CPU time 17.13 seconds
Started Jun 13 01:21:31 PM PDT 24
Finished Jun 13 01:21:49 PM PDT 24
Peak memory 200684 kb
Host smart-0c3d15f7-6fd4-4139-b7b9-c30f7f204a19
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634036792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.1634036792
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_loopback.633011537
Short name T350
Test name
Test status
Simulation time 3799584908 ps
CPU time 2.87 seconds
Started Jun 13 01:42:21 PM PDT 24
Finished Jun 13 01:42:25 PM PDT 24
Peak memory 197252 kb
Host smart-3965789c-894a-4fbf-adf9-872d042599c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633011537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.633011537
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_perf.2740417745
Short name T744
Test name
Test status
Simulation time 3334523018 ps
CPU time 202.06 seconds
Started Jun 13 01:51:24 PM PDT 24
Finished Jun 13 01:54:48 PM PDT 24
Peak memory 200760 kb
Host smart-1e79f147-cbce-44a7-9cd3-66be02a66fa6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2740417745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.2740417745
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.2280138987
Short name T15
Test name
Test status
Simulation time 5427414073 ps
CPU time 13.33 seconds
Started Jun 13 01:16:32 PM PDT 24
Finished Jun 13 01:16:46 PM PDT 24
Peak memory 199020 kb
Host smart-0327fcd4-501a-493c-b6ae-e64f712654a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2280138987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.2280138987
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.787946833
Short name T789
Test name
Test status
Simulation time 36945215758 ps
CPU time 17.35 seconds
Started Jun 13 01:02:35 PM PDT 24
Finished Jun 13 01:02:53 PM PDT 24
Peak memory 200828 kb
Host smart-7b96cb8b-3da7-4929-9cec-eacdd9806195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787946833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.787946833
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.1359504114
Short name T986
Test name
Test status
Simulation time 1848948334 ps
CPU time 3.25 seconds
Started Jun 13 01:45:05 PM PDT 24
Finished Jun 13 01:45:09 PM PDT 24
Peak memory 196192 kb
Host smart-73340e6c-3d26-4744-a18e-8589b7ea9e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359504114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.1359504114
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.3264357687
Short name T525
Test name
Test status
Simulation time 270423429 ps
CPU time 2.39 seconds
Started Jun 13 02:00:15 PM PDT 24
Finished Jun 13 02:00:19 PM PDT 24
Peak memory 200428 kb
Host smart-f5346fca-6a17-456e-b2b7-3d4c877fab06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264357687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.3264357687
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.2203271165
Short name T480
Test name
Test status
Simulation time 137359079279 ps
CPU time 683.25 seconds
Started Jun 13 01:19:05 PM PDT 24
Finished Jun 13 01:30:31 PM PDT 24
Peak memory 200776 kb
Host smart-444d1ce5-0617-43a4-80a8-f3318fbd7e4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203271165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.2203271165
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.3522419575
Short name T523
Test name
Test status
Simulation time 7510740887 ps
CPU time 8.18 seconds
Started Jun 13 01:02:35 PM PDT 24
Finished Jun 13 01:02:44 PM PDT 24
Peak memory 200652 kb
Host smart-4d934cdf-38a0-4395-881a-f0a45f6e7c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522419575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.3522419575
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.369377130
Short name T969
Test name
Test status
Simulation time 31023753286 ps
CPU time 14.73 seconds
Started Jun 13 01:22:46 PM PDT 24
Finished Jun 13 01:23:01 PM PDT 24
Peak memory 200844 kb
Host smart-cef177ab-d33e-4f7c-b52e-12ffed98564e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369377130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.369377130
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.2588102388
Short name T447
Test name
Test status
Simulation time 16954360 ps
CPU time 0.62 seconds
Started Jun 13 01:56:39 PM PDT 24
Finished Jun 13 01:56:42 PM PDT 24
Peak memory 196412 kb
Host smart-1d4b237f-43a8-4375-82fc-150e26b81229
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588102388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.2588102388
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.2065046648
Short name T300
Test name
Test status
Simulation time 68107250031 ps
CPU time 45.61 seconds
Started Jun 13 01:15:33 PM PDT 24
Finished Jun 13 01:16:19 PM PDT 24
Peak memory 200800 kb
Host smart-9aed206a-c60d-41ab-a700-88ffa4fb69cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065046648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.2065046648
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.3883276324
Short name T329
Test name
Test status
Simulation time 85288296066 ps
CPU time 63.86 seconds
Started Jun 13 01:17:40 PM PDT 24
Finished Jun 13 01:18:44 PM PDT 24
Peak memory 200656 kb
Host smart-8a3344f7-6448-4197-b025-ed39c3516e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883276324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.3883276324
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.3910602343
Short name T549
Test name
Test status
Simulation time 209990630446 ps
CPU time 36.44 seconds
Started Jun 13 01:24:51 PM PDT 24
Finished Jun 13 01:25:29 PM PDT 24
Peak memory 200808 kb
Host smart-db5b941f-81e4-49be-9da4-984ffa6cfd25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910602343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.3910602343
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.1385126638
Short name T675
Test name
Test status
Simulation time 33251311650 ps
CPU time 18.83 seconds
Started Jun 13 01:41:34 PM PDT 24
Finished Jun 13 01:41:54 PM PDT 24
Peak memory 200728 kb
Host smart-fd515bcd-098d-4cfd-b69d-343e8e03c4f8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385126638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.1385126638
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.575364264
Short name T369
Test name
Test status
Simulation time 278889047803 ps
CPU time 443.25 seconds
Started Jun 13 01:55:13 PM PDT 24
Finished Jun 13 02:02:37 PM PDT 24
Peak memory 200840 kb
Host smart-9762644d-daa5-4c8e-8bb1-abc5936af291
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=575364264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.575364264
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.1257734044
Short name T406
Test name
Test status
Simulation time 1859659765 ps
CPU time 1.37 seconds
Started Jun 13 01:33:48 PM PDT 24
Finished Jun 13 01:33:50 PM PDT 24
Peak memory 196200 kb
Host smart-1e986cfe-c57c-47e1-999a-d4b246c78b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257734044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.1257734044
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_perf.2725926071
Short name T456
Test name
Test status
Simulation time 26004355217 ps
CPU time 265.6 seconds
Started Jun 13 02:10:13 PM PDT 24
Finished Jun 13 02:14:40 PM PDT 24
Peak memory 201000 kb
Host smart-0a58d09a-6446-4376-a896-fe64bcdb96e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2725926071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.2725926071
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.2661422044
Short name T552
Test name
Test status
Simulation time 3275439101 ps
CPU time 10.56 seconds
Started Jun 13 01:58:28 PM PDT 24
Finished Jun 13 01:58:40 PM PDT 24
Peak memory 198940 kb
Host smart-23971f35-e58e-4f4b-8c62-d41640574717
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2661422044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.2661422044
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.1194008401
Short name T522
Test name
Test status
Simulation time 70490683343 ps
CPU time 28.79 seconds
Started Jun 13 01:02:41 PM PDT 24
Finished Jun 13 01:03:11 PM PDT 24
Peak memory 200676 kb
Host smart-b8b93771-1f89-4d37-959b-5837e5cddbcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194008401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.1194008401
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.2859199435
Short name T316
Test name
Test status
Simulation time 35357469878 ps
CPU time 44.81 seconds
Started Jun 13 02:06:17 PM PDT 24
Finished Jun 13 02:07:03 PM PDT 24
Peak memory 196916 kb
Host smart-c4623f73-d07f-41a6-b767-db50bfcc5988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859199435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.2859199435
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.2938535115
Short name T998
Test name
Test status
Simulation time 861250819 ps
CPU time 2.28 seconds
Started Jun 13 01:08:05 PM PDT 24
Finished Jun 13 01:08:08 PM PDT 24
Peak memory 199364 kb
Host smart-6d5b3440-284e-402b-9809-a52db2e6de3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938535115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.2938535115
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.62889937
Short name T949
Test name
Test status
Simulation time 16216766055 ps
CPU time 14.23 seconds
Started Jun 13 01:16:50 PM PDT 24
Finished Jun 13 01:17:05 PM PDT 24
Peak memory 200800 kb
Host smart-3bc5fd9f-c9c6-4f3b-8bd7-72a88dee0c6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62889937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.62889937
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.2264284097
Short name T591
Test name
Test status
Simulation time 1147896661 ps
CPU time 3.3 seconds
Started Jun 13 01:02:34 PM PDT 24
Finished Jun 13 01:02:38 PM PDT 24
Peak memory 200580 kb
Host smart-664fcac3-b12a-488c-8abb-9e2d85ac1378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264284097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.2264284097
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.2846800881
Short name T843
Test name
Test status
Simulation time 48928787148 ps
CPU time 19.33 seconds
Started Jun 13 01:11:32 PM PDT 24
Finished Jun 13 01:11:52 PM PDT 24
Peak memory 200780 kb
Host smart-22b1b384-0217-4a04-861f-c793076a1e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846800881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.2846800881
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.2071109356
Short name T19
Test name
Test status
Simulation time 13357228 ps
CPU time 0.58 seconds
Started Jun 13 01:06:05 PM PDT 24
Finished Jun 13 01:06:07 PM PDT 24
Peak memory 196064 kb
Host smart-de6245ea-5efd-498b-9ad9-31de1d6a44f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071109356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.2071109356
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.3754945426
Short name T559
Test name
Test status
Simulation time 70472879396 ps
CPU time 34.18 seconds
Started Jun 13 01:52:10 PM PDT 24
Finished Jun 13 01:52:46 PM PDT 24
Peak memory 200816 kb
Host smart-d9fc781a-ae46-4eb6-814a-cfdfa9c637fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754945426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.3754945426
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.3307106570
Short name T359
Test name
Test status
Simulation time 42417393819 ps
CPU time 13.81 seconds
Started Jun 13 01:02:39 PM PDT 24
Finished Jun 13 01:02:53 PM PDT 24
Peak memory 200772 kb
Host smart-1bd4c456-3964-4d68-9b1c-23f567f8845b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307106570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.3307106570
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.1452077415
Short name T752
Test name
Test status
Simulation time 77095711605 ps
CPU time 16.65 seconds
Started Jun 13 01:39:40 PM PDT 24
Finished Jun 13 01:39:57 PM PDT 24
Peak memory 200644 kb
Host smart-a8fb2778-dc64-49d7-9263-a9f640c43348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452077415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.1452077415
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.3573426715
Short name T726
Test name
Test status
Simulation time 478262141701 ps
CPU time 357.84 seconds
Started Jun 13 02:38:09 PM PDT 24
Finished Jun 13 02:44:08 PM PDT 24
Peak memory 200184 kb
Host smart-bb0a0db5-7462-4838-9449-b3829ab60053
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573426715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.3573426715
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.3045296827
Short name T1047
Test name
Test status
Simulation time 137777314955 ps
CPU time 968.28 seconds
Started Jun 13 01:02:41 PM PDT 24
Finished Jun 13 01:18:50 PM PDT 24
Peak memory 200676 kb
Host smart-3139f56e-aaa5-494c-92b5-075ba7bdf293
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3045296827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.3045296827
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.3900926142
Short name T921
Test name
Test status
Simulation time 5902486293 ps
CPU time 2.49 seconds
Started Jun 13 02:01:20 PM PDT 24
Finished Jun 13 02:01:24 PM PDT 24
Peak memory 199164 kb
Host smart-dd2c8f09-3557-4449-b6a9-a849726748f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900926142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.3900926142
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_perf.915691227
Short name T516
Test name
Test status
Simulation time 15469915048 ps
CPU time 168.98 seconds
Started Jun 13 01:02:42 PM PDT 24
Finished Jun 13 01:05:32 PM PDT 24
Peak memory 200764 kb
Host smart-1946104e-c94e-41bb-a449-a0f2462a31ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=915691227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.915691227
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.504018110
Short name T980
Test name
Test status
Simulation time 6324696252 ps
CPU time 50.03 seconds
Started Jun 13 02:39:39 PM PDT 24
Finished Jun 13 02:40:36 PM PDT 24
Peak memory 199768 kb
Host smart-32684121-cf8c-4926-8a13-86f364e95ae7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=504018110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.504018110
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.3329560175
Short name T815
Test name
Test status
Simulation time 3917023334 ps
CPU time 6.82 seconds
Started Jun 13 01:30:08 PM PDT 24
Finished Jun 13 01:30:16 PM PDT 24
Peak memory 197340 kb
Host smart-4a1e8648-d925-4690-b547-bc454c99d5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329560175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.3329560175
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.1335789210
Short name T1070
Test name
Test status
Simulation time 626417155 ps
CPU time 2.21 seconds
Started Jun 13 01:02:41 PM PDT 24
Finished Jun 13 01:02:44 PM PDT 24
Peak memory 199044 kb
Host smart-5a19a9ea-a0b8-4887-9682-dcd187335462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335789210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.1335789210
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.2398265554
Short name T163
Test name
Test status
Simulation time 658997979243 ps
CPU time 193.14 seconds
Started Jun 13 01:02:41 PM PDT 24
Finished Jun 13 01:05:56 PM PDT 24
Peak memory 200760 kb
Host smart-cd391126-4e9d-4a58-8bd9-caf84b826339
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398265554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.2398265554
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.1169008277
Short name T226
Test name
Test status
Simulation time 182607648713 ps
CPU time 664.11 seconds
Started Jun 13 01:16:01 PM PDT 24
Finished Jun 13 01:27:05 PM PDT 24
Peak memory 215744 kb
Host smart-b179ef67-4295-492e-adde-a7cc020ebc8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169008277 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.1169008277
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.133257419
Short name T811
Test name
Test status
Simulation time 4278877172 ps
CPU time 1.73 seconds
Started Jun 13 01:18:46 PM PDT 24
Finished Jun 13 01:18:48 PM PDT 24
Peak memory 200024 kb
Host smart-03120e5d-b610-43a8-b4ee-a0d79dfe4da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133257419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.133257419
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.3198323401
Short name T685
Test name
Test status
Simulation time 9583577215 ps
CPU time 14.7 seconds
Started Jun 13 01:23:21 PM PDT 24
Finished Jun 13 01:23:38 PM PDT 24
Peak memory 200848 kb
Host smart-497adfc8-156a-4355-ba67-8e4adcd31ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198323401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.3198323401
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.1999398671
Short name T544
Test name
Test status
Simulation time 20960687 ps
CPU time 0.52 seconds
Started Jun 13 01:02:43 PM PDT 24
Finished Jun 13 01:02:44 PM PDT 24
Peak memory 196088 kb
Host smart-1b16afbf-3c0f-4ff3-82c9-3be644c09122
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999398671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.1999398671
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.912428126
Short name T584
Test name
Test status
Simulation time 19940088534 ps
CPU time 38.35 seconds
Started Jun 13 02:11:48 PM PDT 24
Finished Jun 13 02:12:27 PM PDT 24
Peak memory 200780 kb
Host smart-79a9522d-de72-4ae8-ae5c-b89727056874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912428126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.912428126
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.2457156248
Short name T914
Test name
Test status
Simulation time 26459834482 ps
CPU time 39.06 seconds
Started Jun 13 02:20:19 PM PDT 24
Finished Jun 13 02:21:10 PM PDT 24
Peak memory 200796 kb
Host smart-3fc014d4-2918-42b2-9d12-246a33336a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457156248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.2457156248
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.4019282315
Short name T312
Test name
Test status
Simulation time 90273343957 ps
CPU time 428.78 seconds
Started Jun 13 01:56:42 PM PDT 24
Finished Jun 13 02:03:53 PM PDT 24
Peak memory 200844 kb
Host smart-91d45389-73cf-4e2d-912c-22a8b8ebac44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019282315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.4019282315
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.2612664157
Short name T2
Test name
Test status
Simulation time 73244306464 ps
CPU time 103.49 seconds
Started Jun 13 02:17:58 PM PDT 24
Finished Jun 13 02:19:48 PM PDT 24
Peak memory 200760 kb
Host smart-062dc49d-dcd4-49e8-a1a1-51d306ce53d5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612664157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.2612664157
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.4261855576
Short name T967
Test name
Test status
Simulation time 148484814117 ps
CPU time 425.3 seconds
Started Jun 13 01:43:46 PM PDT 24
Finished Jun 13 01:50:53 PM PDT 24
Peak memory 200764 kb
Host smart-b742c9ea-cf39-4d22-a1c4-4aa1706041d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4261855576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.4261855576
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.1132074539
Short name T344
Test name
Test status
Simulation time 4980444739 ps
CPU time 11.46 seconds
Started Jun 13 01:24:46 PM PDT 24
Finished Jun 13 01:24:58 PM PDT 24
Peak memory 200728 kb
Host smart-7ba977e3-bb0c-49bb-87e8-48eee652adce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132074539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.1132074539
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_perf.3598126510
Short name T34
Test name
Test status
Simulation time 4497283467 ps
CPU time 257.78 seconds
Started Jun 13 01:55:39 PM PDT 24
Finished Jun 13 01:59:58 PM PDT 24
Peak memory 200852 kb
Host smart-317ce4fb-e7b7-4f2e-813c-18f6c54360ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3598126510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.3598126510
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.3322092458
Short name T1087
Test name
Test status
Simulation time 6509385735 ps
CPU time 23.46 seconds
Started Jun 13 02:04:33 PM PDT 24
Finished Jun 13 02:04:58 PM PDT 24
Peak memory 199008 kb
Host smart-7adfccab-f0d0-45c9-b529-71273e9f6857
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3322092458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.3322092458
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.3849442964
Short name T509
Test name
Test status
Simulation time 20583535531 ps
CPU time 40.83 seconds
Started Jun 13 01:02:42 PM PDT 24
Finished Jun 13 01:03:24 PM PDT 24
Peak memory 200684 kb
Host smart-5783e674-885e-4448-997c-d5e15414cc09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849442964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.3849442964
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.3107228348
Short name T983
Test name
Test status
Simulation time 4608580500 ps
CPU time 7.14 seconds
Started Jun 13 01:57:17 PM PDT 24
Finished Jun 13 01:57:27 PM PDT 24
Peak memory 196884 kb
Host smart-3f355c39-d6b6-4a98-99e3-d2bad52887ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107228348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.3107228348
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.1645165625
Short name T783
Test name
Test status
Simulation time 447161195 ps
CPU time 1.77 seconds
Started Jun 13 01:02:41 PM PDT 24
Finished Jun 13 01:02:44 PM PDT 24
Peak memory 198984 kb
Host smart-8dd84f58-1cc8-4b26-8006-98c257ad0f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645165625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.1645165625
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.405691815
Short name T799
Test name
Test status
Simulation time 219028603229 ps
CPU time 1630.09 seconds
Started Jun 13 01:02:43 PM PDT 24
Finished Jun 13 01:29:54 PM PDT 24
Peak memory 200708 kb
Host smart-2fb5aa61-504a-489f-8ad5-7b9a437ff369
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405691815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.405691815
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.3876665782
Short name T788
Test name
Test status
Simulation time 36555756409 ps
CPU time 183.35 seconds
Started Jun 13 01:41:36 PM PDT 24
Finished Jun 13 01:44:40 PM PDT 24
Peak memory 217280 kb
Host smart-35d7fcaa-a6d8-4301-8d5c-ada36eafe19f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876665782 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.3876665782
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.2715330890
Short name T528
Test name
Test status
Simulation time 1263067177 ps
CPU time 3.1 seconds
Started Jun 13 01:10:17 PM PDT 24
Finished Jun 13 01:10:21 PM PDT 24
Peak memory 199052 kb
Host smart-c6abb212-84a5-45aa-b6ab-9080ec89e5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715330890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.2715330890
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.13849587
Short name T396
Test name
Test status
Simulation time 100570189077 ps
CPU time 46.47 seconds
Started Jun 13 01:43:06 PM PDT 24
Finished Jun 13 01:43:53 PM PDT 24
Peak memory 200764 kb
Host smart-af770dc5-62ab-45be-8bb9-dd1cec5e9510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13849587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.13849587
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.3272804568
Short name T346
Test name
Test status
Simulation time 48360706 ps
CPU time 0.59 seconds
Started Jun 13 01:48:01 PM PDT 24
Finished Jun 13 01:48:02 PM PDT 24
Peak memory 196148 kb
Host smart-51bb0fbb-55a8-4e04-9128-c01bbc9d6692
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272804568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.3272804568
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.4220985042
Short name T608
Test name
Test status
Simulation time 44617393804 ps
CPU time 16.87 seconds
Started Jun 13 02:35:20 PM PDT 24
Finished Jun 13 02:35:37 PM PDT 24
Peak memory 200768 kb
Host smart-464b2461-8068-4e3f-8dbc-e0ac59608b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220985042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.4220985042
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.3288077680
Short name T715
Test name
Test status
Simulation time 120868381283 ps
CPU time 177.73 seconds
Started Jun 13 01:39:13 PM PDT 24
Finished Jun 13 01:42:11 PM PDT 24
Peak memory 200756 kb
Host smart-fe3c9dee-9c2e-44cc-be15-60916beccd8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288077680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.3288077680
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.2027560796
Short name T617
Test name
Test status
Simulation time 106384756295 ps
CPU time 42.72 seconds
Started Jun 13 01:02:43 PM PDT 24
Finished Jun 13 01:03:26 PM PDT 24
Peak memory 200680 kb
Host smart-669527b9-392a-46c9-8159-df043d4489df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027560796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.2027560796
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.2786431726
Short name T321
Test name
Test status
Simulation time 115147850569 ps
CPU time 43.58 seconds
Started Jun 13 01:16:08 PM PDT 24
Finished Jun 13 01:16:52 PM PDT 24
Peak memory 196852 kb
Host smart-0eaf781c-d2aa-4b2e-bfc0-f6b1b778960a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786431726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.2786431726
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.236279945
Short name T1098
Test name
Test status
Simulation time 105257293545 ps
CPU time 689.21 seconds
Started Jun 13 01:16:24 PM PDT 24
Finished Jun 13 01:27:54 PM PDT 24
Peak memory 200824 kb
Host smart-0e04832d-6224-4cb0-8a12-0e87b81b24ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=236279945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.236279945
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.1385640222
Short name T519
Test name
Test status
Simulation time 2015209486 ps
CPU time 1.32 seconds
Started Jun 13 01:42:34 PM PDT 24
Finished Jun 13 01:42:36 PM PDT 24
Peak memory 197804 kb
Host smart-0f329695-0e46-472f-8efa-4d2bb156b79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385640222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.1385640222
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_perf.4108502036
Short name T596
Test name
Test status
Simulation time 12857445635 ps
CPU time 795.62 seconds
Started Jun 13 01:30:37 PM PDT 24
Finished Jun 13 01:43:54 PM PDT 24
Peak memory 200788 kb
Host smart-8ade751a-1c5c-4192-a594-855184694f9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4108502036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.4108502036
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.1731450155
Short name T610
Test name
Test status
Simulation time 4445374966 ps
CPU time 29.82 seconds
Started Jun 13 01:14:04 PM PDT 24
Finished Jun 13 01:14:35 PM PDT 24
Peak memory 199716 kb
Host smart-6a668146-6b91-4adf-ba89-b5f552e1bd30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1731450155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.1731450155
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.3477969857
Short name T167
Test name
Test status
Simulation time 33766781793 ps
CPU time 15.76 seconds
Started Jun 13 02:23:52 PM PDT 24
Finished Jun 13 02:24:08 PM PDT 24
Peak memory 200840 kb
Host smart-5d2ecb07-9674-4aba-82fa-3cfa01739d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477969857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.3477969857
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.592687207
Short name T1010
Test name
Test status
Simulation time 3061500344 ps
CPU time 4.44 seconds
Started Jun 13 02:04:55 PM PDT 24
Finished Jun 13 02:05:00 PM PDT 24
Peak memory 196700 kb
Host smart-dc2c6637-cf97-4d22-be83-20d6fa23b007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592687207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.592687207
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.3668771831
Short name T276
Test name
Test status
Simulation time 926616465 ps
CPU time 3.38 seconds
Started Jun 13 01:46:32 PM PDT 24
Finished Jun 13 01:46:36 PM PDT 24
Peak memory 200476 kb
Host smart-bc3ac943-47fb-49aa-b8fd-388595a9a204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668771831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.3668771831
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.3781746723
Short name T418
Test name
Test status
Simulation time 831420886 ps
CPU time 2.36 seconds
Started Jun 13 02:16:25 PM PDT 24
Finished Jun 13 02:16:32 PM PDT 24
Peak memory 200636 kb
Host smart-01d4d76a-420d-43ea-90cc-a4a3e6c43216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781746723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.3781746723
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.1253705425
Short name T627
Test name
Test status
Simulation time 52888779726 ps
CPU time 42 seconds
Started Jun 13 01:02:43 PM PDT 24
Finished Jun 13 01:03:26 PM PDT 24
Peak memory 200688 kb
Host smart-3f876015-dc3c-44b7-940f-4b8d81622e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253705425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.1253705425
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.254545326
Short name T345
Test name
Test status
Simulation time 13919130 ps
CPU time 0.56 seconds
Started Jun 13 01:02:41 PM PDT 24
Finished Jun 13 01:02:42 PM PDT 24
Peak memory 195524 kb
Host smart-0a785507-f306-4162-984c-5b6c5ccedef6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254545326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.254545326
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.3023151385
Short name T598
Test name
Test status
Simulation time 61663858951 ps
CPU time 88.6 seconds
Started Jun 13 02:47:42 PM PDT 24
Finished Jun 13 02:49:24 PM PDT 24
Peak memory 200424 kb
Host smart-4dc54e92-451c-4430-b31c-3478576af93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023151385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.3023151385
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.2992088525
Short name T1016
Test name
Test status
Simulation time 31998739375 ps
CPU time 56.09 seconds
Started Jun 13 01:47:24 PM PDT 24
Finished Jun 13 01:48:21 PM PDT 24
Peak memory 200644 kb
Host smart-d5a0889a-e5a9-4463-900b-b1fe0429b9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992088525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.2992088525
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_intr.2027671233
Short name T909
Test name
Test status
Simulation time 13905192723 ps
CPU time 13.97 seconds
Started Jun 13 01:25:25 PM PDT 24
Finished Jun 13 01:25:40 PM PDT 24
Peak memory 200728 kb
Host smart-d1e68741-69dc-4e0b-9115-c51418a35f66
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027671233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.2027671233
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.2563811309
Short name T540
Test name
Test status
Simulation time 92613315838 ps
CPU time 322.95 seconds
Started Jun 13 02:09:20 PM PDT 24
Finished Jun 13 02:14:45 PM PDT 24
Peak memory 200840 kb
Host smart-6c440f20-c369-460d-96e1-0547acdd0c1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2563811309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.2563811309
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.2534512680
Short name T104
Test name
Test status
Simulation time 3548657189 ps
CPU time 3.62 seconds
Started Jun 13 01:41:14 PM PDT 24
Finished Jun 13 01:41:20 PM PDT 24
Peak memory 199844 kb
Host smart-bc2ff0ea-1f9b-452c-a26d-c72e0bbe633b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534512680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.2534512680
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_perf.1558828184
Short name T669
Test name
Test status
Simulation time 15403156550 ps
CPU time 880.94 seconds
Started Jun 13 01:20:43 PM PDT 24
Finished Jun 13 01:35:26 PM PDT 24
Peak memory 200816 kb
Host smart-75ea8c1b-d970-4309-89b7-cb70c871c650
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1558828184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.1558828184
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.3826480888
Short name T985
Test name
Test status
Simulation time 2217715544 ps
CPU time 3.64 seconds
Started Jun 13 01:48:28 PM PDT 24
Finished Jun 13 01:48:32 PM PDT 24
Peak memory 199004 kb
Host smart-7ae0cdcd-c09c-418d-bd12-0c11763aa2c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3826480888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.3826480888
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.4183575176
Short name T562
Test name
Test status
Simulation time 57144526479 ps
CPU time 35.09 seconds
Started Jun 13 01:02:44 PM PDT 24
Finished Jun 13 01:03:20 PM PDT 24
Peak memory 200772 kb
Host smart-a06ad2ed-86b2-4788-aeb7-61b766f106f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183575176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.4183575176
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.2886996382
Short name T723
Test name
Test status
Simulation time 3442610561 ps
CPU time 1.97 seconds
Started Jun 13 02:16:04 PM PDT 24
Finished Jun 13 02:16:08 PM PDT 24
Peak memory 196856 kb
Host smart-89af7dc1-6167-44f3-90cf-cb71982a1d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886996382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.2886996382
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.3688714222
Short name T1018
Test name
Test status
Simulation time 462681608 ps
CPU time 2.24 seconds
Started Jun 13 01:58:49 PM PDT 24
Finished Jun 13 01:58:53 PM PDT 24
Peak memory 199144 kb
Host smart-5217db50-0170-43d2-897f-067169077f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688714222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.3688714222
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.885236288
Short name T565
Test name
Test status
Simulation time 280717613307 ps
CPU time 289.57 seconds
Started Jun 13 01:02:40 PM PDT 24
Finished Jun 13 01:07:30 PM PDT 24
Peak memory 200744 kb
Host smart-326caa89-f992-4fb9-88ce-38835824777e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885236288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.885236288
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.1968362974
Short name T399
Test name
Test status
Simulation time 1014175017 ps
CPU time 2.82 seconds
Started Jun 13 01:21:38 PM PDT 24
Finished Jun 13 01:21:41 PM PDT 24
Peak memory 199048 kb
Host smart-3461c684-f1ca-45c3-9c69-de1e94ca190f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968362974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.1968362974
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.1292929053
Short name T432
Test name
Test status
Simulation time 10500631400 ps
CPU time 12.9 seconds
Started Jun 13 02:30:17 PM PDT 24
Finished Jun 13 02:30:30 PM PDT 24
Peak memory 200048 kb
Host smart-fa2a4ab0-a5c2-4080-bdd2-bf0b760b2a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292929053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.1292929053
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.870803428
Short name T942
Test name
Test status
Simulation time 14650349 ps
CPU time 0.55 seconds
Started Jun 13 01:14:27 PM PDT 24
Finished Jun 13 01:14:29 PM PDT 24
Peak memory 195624 kb
Host smart-3960b986-ec32-41a0-8897-e7778e8a62f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870803428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.870803428
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.1384438395
Short name T554
Test name
Test status
Simulation time 252910122645 ps
CPU time 67.89 seconds
Started Jun 13 01:54:13 PM PDT 24
Finished Jun 13 01:55:23 PM PDT 24
Peak memory 200796 kb
Host smart-9cdba20c-6315-4526-8057-68d2f4d81520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384438395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.1384438395
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.1140508681
Short name T151
Test name
Test status
Simulation time 52089163351 ps
CPU time 83.32 seconds
Started Jun 13 01:22:07 PM PDT 24
Finished Jun 13 01:23:31 PM PDT 24
Peak memory 200764 kb
Host smart-d557d1f7-55a6-42b9-9314-08291abb3d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140508681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.1140508681
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.4170969056
Short name T202
Test name
Test status
Simulation time 45134024632 ps
CPU time 20.75 seconds
Started Jun 13 01:02:43 PM PDT 24
Finished Jun 13 01:03:05 PM PDT 24
Peak memory 200692 kb
Host smart-3a93ab43-0cab-477d-8e73-14fa3aebff6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170969056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.4170969056
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.3107549926
Short name T1045
Test name
Test status
Simulation time 4427312807 ps
CPU time 5.24 seconds
Started Jun 13 01:02:42 PM PDT 24
Finished Jun 13 01:02:48 PM PDT 24
Peak memory 200708 kb
Host smart-39074008-81bd-4b9b-92c4-95d354220e0d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107549926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.3107549926
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.2860105197
Short name T900
Test name
Test status
Simulation time 58841675958 ps
CPU time 622.24 seconds
Started Jun 13 01:20:00 PM PDT 24
Finished Jun 13 01:30:23 PM PDT 24
Peak memory 200852 kb
Host smart-9d4b9ca9-04fd-4a13-a337-1a2e6b78c76d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2860105197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.2860105197
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.685039136
Short name T867
Test name
Test status
Simulation time 6470679817 ps
CPU time 10.12 seconds
Started Jun 13 02:05:46 PM PDT 24
Finished Jun 13 02:05:59 PM PDT 24
Peak memory 199896 kb
Host smart-2ce25968-ae98-4a50-827c-02bfa62bbcef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685039136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.685039136
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_perf.710113185
Short name T625
Test name
Test status
Simulation time 14431815434 ps
CPU time 189.69 seconds
Started Jun 13 01:02:43 PM PDT 24
Finished Jun 13 01:05:53 PM PDT 24
Peak memory 200788 kb
Host smart-c795b554-1f10-448e-b4ec-8db1419afaba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=710113185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.710113185
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.2199794786
Short name T831
Test name
Test status
Simulation time 4268021777 ps
CPU time 41.26 seconds
Started Jun 13 01:02:43 PM PDT 24
Finished Jun 13 01:03:25 PM PDT 24
Peak memory 199168 kb
Host smart-e82925e5-c01d-4185-9d07-3fb1ccab52b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2199794786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.2199794786
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.3387996529
Short name T946
Test name
Test status
Simulation time 5860326814 ps
CPU time 2.11 seconds
Started Jun 13 01:19:28 PM PDT 24
Finished Jun 13 01:19:31 PM PDT 24
Peak memory 196984 kb
Host smart-24ad3af2-0df2-44a6-928e-dc66de778933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387996529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.3387996529
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.890898277
Short name T557
Test name
Test status
Simulation time 118777786 ps
CPU time 0.95 seconds
Started Jun 13 01:32:53 PM PDT 24
Finished Jun 13 01:32:54 PM PDT 24
Peak memory 198956 kb
Host smart-2d00c2aa-82e3-4059-b2b1-c744e0bb56e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890898277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.890898277
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.313106899
Short name T1063
Test name
Test status
Simulation time 118584044784 ps
CPU time 135.24 seconds
Started Jun 13 01:02:43 PM PDT 24
Finished Jun 13 01:05:00 PM PDT 24
Peak memory 200736 kb
Host smart-cdc710cc-21e7-4c62-aef9-e3d7ca672899
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313106899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.313106899
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.1345955035
Short name T920
Test name
Test status
Simulation time 849028904 ps
CPU time 2.05 seconds
Started Jun 13 02:33:19 PM PDT 24
Finished Jun 13 02:33:23 PM PDT 24
Peak memory 200416 kb
Host smart-9b8f8d74-5649-409e-9fea-673a4472f95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345955035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.1345955035
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.1671549011
Short name T978
Test name
Test status
Simulation time 34865897517 ps
CPU time 31.02 seconds
Started Jun 13 01:10:56 PM PDT 24
Finished Jun 13 01:11:31 PM PDT 24
Peak memory 200820 kb
Host smart-5f2bc579-d071-4fef-a1a9-c379d398026d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671549011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.1671549011
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.3427539102
Short name T1082
Test name
Test status
Simulation time 10666915 ps
CPU time 0.57 seconds
Started Jun 13 01:20:27 PM PDT 24
Finished Jun 13 01:20:28 PM PDT 24
Peak memory 195752 kb
Host smart-b365de46-3ca2-4b03-9527-0a7e21784244
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427539102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.3427539102
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.2015901745
Short name T713
Test name
Test status
Simulation time 84436597546 ps
CPU time 35.79 seconds
Started Jun 13 01:36:36 PM PDT 24
Finished Jun 13 01:37:12 PM PDT 24
Peak memory 200828 kb
Host smart-3bbc5d2b-0e31-4271-a1ff-fafff845fb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015901745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.2015901745
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.2612102872
Short name T1076
Test name
Test status
Simulation time 39239580494 ps
CPU time 36.82 seconds
Started Jun 13 01:02:43 PM PDT 24
Finished Jun 13 01:03:21 PM PDT 24
Peak memory 200620 kb
Host smart-b9de6add-16c2-4d8b-99a6-a1e9bdfe73dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612102872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.2612102872
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.1191421180
Short name T860
Test name
Test status
Simulation time 111878543538 ps
CPU time 125.16 seconds
Started Jun 13 02:19:51 PM PDT 24
Finished Jun 13 02:22:02 PM PDT 24
Peak memory 200764 kb
Host smart-ce6dd511-b949-4305-a7ec-69bdd5ffef30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191421180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.1191421180
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.515967246
Short name T394
Test name
Test status
Simulation time 18394710731 ps
CPU time 8.23 seconds
Started Jun 13 02:02:07 PM PDT 24
Finished Jun 13 02:02:16 PM PDT 24
Peak memory 199028 kb
Host smart-1479af24-8c1b-4231-bbb0-25ffcf49dc60
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515967246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.515967246
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.3088077905
Short name T732
Test name
Test status
Simulation time 116710167746 ps
CPU time 720.1 seconds
Started Jun 13 01:02:41 PM PDT 24
Finished Jun 13 01:14:43 PM PDT 24
Peak memory 200756 kb
Host smart-101b249b-2978-42ca-b3c6-85a62f5b5f1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3088077905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.3088077905
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.2828678443
Short name T341
Test name
Test status
Simulation time 3338187820 ps
CPU time 5.76 seconds
Started Jun 13 01:02:44 PM PDT 24
Finished Jun 13 01:02:51 PM PDT 24
Peak memory 198108 kb
Host smart-2a9fadba-788f-427b-a92c-47f1ddc1db7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828678443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.2828678443
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_perf.2559903518
Short name T968
Test name
Test status
Simulation time 13395976520 ps
CPU time 671.46 seconds
Started Jun 13 02:08:15 PM PDT 24
Finished Jun 13 02:19:28 PM PDT 24
Peak memory 200776 kb
Host smart-35d8e0f4-67f6-42d2-8354-a9b8ab41ec0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2559903518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.2559903518
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.751369766
Short name T768
Test name
Test status
Simulation time 5746140696 ps
CPU time 23.8 seconds
Started Jun 13 01:02:43 PM PDT 24
Finished Jun 13 01:03:07 PM PDT 24
Peak memory 199928 kb
Host smart-35c7b182-a66f-45ac-bc7d-7cfc8f44ea4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=751369766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.751369766
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.1546968934
Short name T137
Test name
Test status
Simulation time 53594936625 ps
CPU time 26 seconds
Started Jun 13 01:02:41 PM PDT 24
Finished Jun 13 01:03:08 PM PDT 24
Peak memory 200844 kb
Host smart-7e1ef829-c78c-403b-91fb-33b0ba189f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546968934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.1546968934
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.3808229251
Short name T774
Test name
Test status
Simulation time 48981210214 ps
CPU time 70.2 seconds
Started Jun 13 01:02:44 PM PDT 24
Finished Jun 13 01:03:55 PM PDT 24
Peak memory 196644 kb
Host smart-59f51308-4dd1-4c27-8cb1-009e84d49c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808229251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.3808229251
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.769259714
Short name T353
Test name
Test status
Simulation time 647224842 ps
CPU time 3.38 seconds
Started Jun 13 01:09:06 PM PDT 24
Finished Jun 13 01:09:10 PM PDT 24
Peak memory 200688 kb
Host smart-83e3e4ce-bc33-45e4-a385-36fd4d113b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769259714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.769259714
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.2431923225
Short name T938
Test name
Test status
Simulation time 220253087041 ps
CPU time 111.01 seconds
Started Jun 13 01:54:37 PM PDT 24
Finished Jun 13 01:56:34 PM PDT 24
Peak memory 200832 kb
Host smart-2e623613-34ff-41a4-993c-eb03f8c1d01e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431923225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.2431923225
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.1796868608
Short name T550
Test name
Test status
Simulation time 1848761011 ps
CPU time 3.46 seconds
Started Jun 13 02:31:12 PM PDT 24
Finished Jun 13 02:31:18 PM PDT 24
Peak memory 199136 kb
Host smart-2d7ed831-09b5-4157-8173-e7b6bcd47960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796868608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.1796868608
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.949098639
Short name T304
Test name
Test status
Simulation time 171752524915 ps
CPU time 109.82 seconds
Started Jun 13 01:02:41 PM PDT 24
Finished Jun 13 01:04:32 PM PDT 24
Peak memory 200748 kb
Host smart-477ca987-9912-4bca-8a15-814afdce1f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949098639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.949098639
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.2705700907
Short name T438
Test name
Test status
Simulation time 13091955 ps
CPU time 0.59 seconds
Started Jun 13 01:04:09 PM PDT 24
Finished Jun 13 01:04:11 PM PDT 24
Peak memory 196376 kb
Host smart-8a571342-c63d-41c6-ac93-36897fa2976b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705700907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.2705700907
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.3649230690
Short name T990
Test name
Test status
Simulation time 149799686943 ps
CPU time 109.99 seconds
Started Jun 13 02:00:06 PM PDT 24
Finished Jun 13 02:01:58 PM PDT 24
Peak memory 200840 kb
Host smart-b0bc58bf-70ac-4562-823e-c96b969ef885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649230690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.3649230690
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.1480538543
Short name T453
Test name
Test status
Simulation time 21703208668 ps
CPU time 10.51 seconds
Started Jun 13 01:18:55 PM PDT 24
Finished Jun 13 01:19:06 PM PDT 24
Peak memory 200256 kb
Host smart-facb4d06-c273-493f-92a1-9f85f40025f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480538543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.1480538543
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.1803286538
Short name T835
Test name
Test status
Simulation time 26446776809 ps
CPU time 29.94 seconds
Started Jun 13 01:07:27 PM PDT 24
Finished Jun 13 01:07:58 PM PDT 24
Peak memory 200824 kb
Host smart-f3476208-6b99-4b28-abb0-baa46857b0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803286538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.1803286538
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.3045891927
Short name T496
Test name
Test status
Simulation time 55976239617 ps
CPU time 27.1 seconds
Started Jun 13 01:02:48 PM PDT 24
Finished Jun 13 01:03:16 PM PDT 24
Peak memory 200796 kb
Host smart-1a597e2e-aab6-41a1-aa51-5b811f3fe6f5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045891927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.3045891927
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.4121892745
Short name T415
Test name
Test status
Simulation time 92703252807 ps
CPU time 821.86 seconds
Started Jun 13 01:29:13 PM PDT 24
Finished Jun 13 01:42:56 PM PDT 24
Peak memory 200820 kb
Host smart-9793cb3b-5d96-400e-8dc5-4f0bebefe3d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4121892745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.4121892745
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.1920203898
Short name T445
Test name
Test status
Simulation time 13617984699 ps
CPU time 23.12 seconds
Started Jun 13 01:27:20 PM PDT 24
Finished Jun 13 01:27:43 PM PDT 24
Peak memory 200824 kb
Host smart-c0f8d497-9a36-415c-bbc6-5b20983c425d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920203898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.1920203898
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.4018419616
Short name T663
Test name
Test status
Simulation time 57206919626 ps
CPU time 105.14 seconds
Started Jun 13 01:17:41 PM PDT 24
Finished Jun 13 01:19:26 PM PDT 24
Peak memory 200844 kb
Host smart-4c80b245-9d8d-4c98-96b7-dcef1ce32a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018419616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.4018419616
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.2842165899
Short name T902
Test name
Test status
Simulation time 20784446480 ps
CPU time 1202.26 seconds
Started Jun 13 01:05:08 PM PDT 24
Finished Jun 13 01:25:14 PM PDT 24
Peak memory 200728 kb
Host smart-bd730083-fe64-4646-970a-a0d3be3aa7e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2842165899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.2842165899
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.523828910
Short name T682
Test name
Test status
Simulation time 2326069057 ps
CPU time 6.72 seconds
Started Jun 13 01:03:43 PM PDT 24
Finished Jun 13 01:03:50 PM PDT 24
Peak memory 199200 kb
Host smart-403e165f-175f-41c2-9287-005297d08813
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=523828910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.523828910
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.1238619083
Short name T261
Test name
Test status
Simulation time 143904189183 ps
CPU time 217.64 seconds
Started Jun 13 01:02:50 PM PDT 24
Finished Jun 13 01:06:28 PM PDT 24
Peak memory 200804 kb
Host smart-c1e0bc90-a9d0-45da-9351-d4265fbc3130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238619083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.1238619083
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.1613541756
Short name T566
Test name
Test status
Simulation time 4629988686 ps
CPU time 1.1 seconds
Started Jun 13 01:02:50 PM PDT 24
Finished Jun 13 01:02:52 PM PDT 24
Peak memory 196868 kb
Host smart-d3fa574b-20a6-47b0-9ceb-87c9fbf1a454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613541756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.1613541756
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.2075310745
Short name T828
Test name
Test status
Simulation time 907703563 ps
CPU time 1.83 seconds
Started Jun 13 01:28:27 PM PDT 24
Finished Jun 13 01:28:29 PM PDT 24
Peak memory 199336 kb
Host smart-2f499b45-52b8-4d79-a33b-651420a1dfb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075310745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.2075310745
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.2330703557
Short name T149
Test name
Test status
Simulation time 44097094995 ps
CPU time 139.82 seconds
Started Jun 13 01:23:01 PM PDT 24
Finished Jun 13 01:25:22 PM PDT 24
Peak memory 200748 kb
Host smart-7a0c738d-7f35-4d98-9bfb-362be2707d6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330703557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.2330703557
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.456475887
Short name T487
Test name
Test status
Simulation time 209683476856 ps
CPU time 535.01 seconds
Started Jun 13 01:02:48 PM PDT 24
Finished Jun 13 01:11:43 PM PDT 24
Peak memory 217192 kb
Host smart-035664a8-3f86-4ca9-be2f-7d63696dd979
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456475887 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.456475887
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.1785764687
Short name T108
Test name
Test status
Simulation time 1311628624 ps
CPU time 1.54 seconds
Started Jun 13 01:02:50 PM PDT 24
Finished Jun 13 01:02:53 PM PDT 24
Peak memory 199248 kb
Host smart-d988f2e3-fc05-4fc0-ba46-f580cd22f3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785764687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.1785764687
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.3470318002
Short name T935
Test name
Test status
Simulation time 98866643506 ps
CPU time 42.93 seconds
Started Jun 13 01:02:50 PM PDT 24
Finished Jun 13 01:03:34 PM PDT 24
Peak memory 200780 kb
Host smart-44008f02-88b5-403e-b06b-8856b8fdad39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470318002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.3470318002
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.3379116253
Short name T786
Test name
Test status
Simulation time 43769824 ps
CPU time 0.56 seconds
Started Jun 13 01:00:53 PM PDT 24
Finished Jun 13 01:00:56 PM PDT 24
Peak memory 196072 kb
Host smart-80df8980-a043-4d2d-a5dd-9671daf5f3c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379116253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.3379116253
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.12614300
Short name T585
Test name
Test status
Simulation time 59481653652 ps
CPU time 51.76 seconds
Started Jun 13 01:00:54 PM PDT 24
Finished Jun 13 01:01:48 PM PDT 24
Peak memory 200728 kb
Host smart-4202759d-9f95-4c51-a0d6-8650b0a7ad2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12614300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.12614300
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.4263813330
Short name T700
Test name
Test status
Simulation time 146523015169 ps
CPU time 222.01 seconds
Started Jun 13 01:00:51 PM PDT 24
Finished Jun 13 01:04:35 PM PDT 24
Peak memory 200696 kb
Host smart-ca846b91-2765-4fda-aaee-243d6edb619b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263813330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.4263813330
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.3016572212
Short name T210
Test name
Test status
Simulation time 55119384443 ps
CPU time 55.54 seconds
Started Jun 13 01:01:01 PM PDT 24
Finished Jun 13 01:01:57 PM PDT 24
Peak memory 200736 kb
Host smart-e9775fd2-9b28-4c42-992f-5c234f1e76f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016572212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.3016572212
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.16224506
Short name T754
Test name
Test status
Simulation time 34998975201 ps
CPU time 65.93 seconds
Started Jun 13 01:00:53 PM PDT 24
Finished Jun 13 01:02:02 PM PDT 24
Peak memory 200768 kb
Host smart-62f45a78-7932-444c-a33a-1b429e19de3e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16224506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.16224506
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.4062782523
Short name T1093
Test name
Test status
Simulation time 27250234664 ps
CPU time 78.22 seconds
Started Jun 13 01:00:51 PM PDT 24
Finished Jun 13 01:02:11 PM PDT 24
Peak memory 200724 kb
Host smart-d9f9adb7-96e4-41e4-853f-b31a34b75cba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4062782523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.4062782523
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.4204557004
Short name T1017
Test name
Test status
Simulation time 1372711095 ps
CPU time 2.74 seconds
Started Jun 13 01:00:53 PM PDT 24
Finished Jun 13 01:00:58 PM PDT 24
Peak memory 196368 kb
Host smart-e02f954b-fd9c-4a46-9abb-ad27440cf023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204557004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.4204557004
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.126984429
Short name T320
Test name
Test status
Simulation time 43975224146 ps
CPU time 11.09 seconds
Started Jun 13 01:00:54 PM PDT 24
Finished Jun 13 01:01:08 PM PDT 24
Peak memory 198516 kb
Host smart-c4e1d0b9-ac2f-410c-ad22-495c11838f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126984429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.126984429
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.140531758
Short name T269
Test name
Test status
Simulation time 27140693930 ps
CPU time 1369.37 seconds
Started Jun 13 01:00:51 PM PDT 24
Finished Jun 13 01:23:42 PM PDT 24
Peak memory 200736 kb
Host smart-770ffbc8-50d1-461f-b556-76bbc2b240cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=140531758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.140531758
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.2208592292
Short name T904
Test name
Test status
Simulation time 4817790259 ps
CPU time 21.47 seconds
Started Jun 13 01:00:50 PM PDT 24
Finished Jun 13 01:01:12 PM PDT 24
Peak memory 199860 kb
Host smart-11a9b146-af2c-4018-9a42-6532b39e2188
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2208592292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.2208592292
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.1443502801
Short name T1007
Test name
Test status
Simulation time 236690625590 ps
CPU time 130.25 seconds
Started Jun 13 01:00:53 PM PDT 24
Finished Jun 13 01:03:06 PM PDT 24
Peak memory 200740 kb
Host smart-ff774482-d7f7-421d-a8be-2a32a65f0793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443502801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.1443502801
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.1936655721
Short name T801
Test name
Test status
Simulation time 5919080580 ps
CPU time 8.58 seconds
Started Jun 13 01:00:53 PM PDT 24
Finished Jun 13 01:01:04 PM PDT 24
Peak memory 196856 kb
Host smart-77938e9e-3db3-4fb9-8f3d-1e082ff257a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936655721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.1936655721
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.3840193383
Short name T775
Test name
Test status
Simulation time 477642177 ps
CPU time 1.66 seconds
Started Jun 13 01:00:52 PM PDT 24
Finished Jun 13 01:00:56 PM PDT 24
Peak memory 199488 kb
Host smart-fc4306cd-271c-4c44-bc11-8a0354873d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840193383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.3840193383
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.2697974207
Short name T932
Test name
Test status
Simulation time 36243488411 ps
CPU time 66.48 seconds
Started Jun 13 01:00:52 PM PDT 24
Finished Jun 13 01:02:00 PM PDT 24
Peak memory 200800 kb
Host smart-2ee077fd-6d8d-42ac-ba74-71acd3566382
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697974207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.2697974207
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.828727447
Short name T785
Test name
Test status
Simulation time 1031929493 ps
CPU time 3.59 seconds
Started Jun 13 01:00:49 PM PDT 24
Finished Jun 13 01:00:54 PM PDT 24
Peak memory 199584 kb
Host smart-49e3748b-a984-4933-bea8-c1c01ce1c27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828727447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.828727447
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.3476456878
Short name T961
Test name
Test status
Simulation time 224971140947 ps
CPU time 88.66 seconds
Started Jun 13 01:00:49 PM PDT 24
Finished Jun 13 01:02:19 PM PDT 24
Peak memory 200820 kb
Host smart-ef26f869-8555-4d34-b4af-a1ce8334ce96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476456878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.3476456878
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.1485927450
Short name T545
Test name
Test status
Simulation time 41621512289 ps
CPU time 17.71 seconds
Started Jun 13 01:27:34 PM PDT 24
Finished Jun 13 01:27:54 PM PDT 24
Peak memory 200800 kb
Host smart-b385730a-63b3-4cc7-b454-7eb2cfa9a2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485927450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.1485927450
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.3037567529
Short name T1075
Test name
Test status
Simulation time 49106616273 ps
CPU time 596.17 seconds
Started Jun 13 01:02:50 PM PDT 24
Finished Jun 13 01:12:47 PM PDT 24
Peak memory 217212 kb
Host smart-b9830bf6-563b-4fa6-bbf2-85e0e9a73250
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037567529 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.3037567529
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.231867299
Short name T444
Test name
Test status
Simulation time 125236824898 ps
CPU time 210.81 seconds
Started Jun 13 02:03:13 PM PDT 24
Finished Jun 13 02:06:46 PM PDT 24
Peak memory 200840 kb
Host smart-8d6e4b90-210b-4e5f-92f4-a263ad479baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231867299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.231867299
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.3313155528
Short name T741
Test name
Test status
Simulation time 4658619693 ps
CPU time 52 seconds
Started Jun 13 01:28:39 PM PDT 24
Finished Jun 13 01:29:32 PM PDT 24
Peak memory 212016 kb
Host smart-e4f71aa5-3504-422d-b41b-31c58a828b91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313155528 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.3313155528
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.2052164672
Short name T372
Test name
Test status
Simulation time 107686280856 ps
CPU time 54.39 seconds
Started Jun 13 01:27:02 PM PDT 24
Finished Jun 13 01:27:56 PM PDT 24
Peak memory 200864 kb
Host smart-de29494b-dd29-432a-b85b-3d70ae1fe002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052164672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.2052164672
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.989152542
Short name T28
Test name
Test status
Simulation time 94411189133 ps
CPU time 110.6 seconds
Started Jun 13 01:16:15 PM PDT 24
Finished Jun 13 01:18:07 PM PDT 24
Peak memory 209064 kb
Host smart-7db090cc-6107-4dd3-a8bb-aa80c2834479
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989152542 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.989152542
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.916074443
Short name T255
Test name
Test status
Simulation time 56967650680 ps
CPU time 10.83 seconds
Started Jun 13 02:46:05 PM PDT 24
Finished Jun 13 02:46:26 PM PDT 24
Peak memory 200752 kb
Host smart-95328db6-1390-4381-a874-04c4a451bf72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916074443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.916074443
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.1023020482
Short name T886
Test name
Test status
Simulation time 57165791525 ps
CPU time 662.85 seconds
Started Jun 13 01:02:48 PM PDT 24
Finished Jun 13 01:13:52 PM PDT 24
Peak memory 217280 kb
Host smart-ccaf2cde-50b2-45db-ae00-33ccebbbb641
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023020482 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.1023020482
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.422351290
Short name T272
Test name
Test status
Simulation time 49334973524 ps
CPU time 68.97 seconds
Started Jun 13 02:36:10 PM PDT 24
Finished Jun 13 02:37:24 PM PDT 24
Peak memory 200848 kb
Host smart-75d60b2f-3d5f-42da-9b85-eed3852af74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422351290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.422351290
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.3140256989
Short name T845
Test name
Test status
Simulation time 34419167933 ps
CPU time 133.55 seconds
Started Jun 13 02:05:42 PM PDT 24
Finished Jun 13 02:07:59 PM PDT 24
Peak memory 216456 kb
Host smart-bbf86a51-215d-462a-940c-5a2c88761830
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140256989 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.3140256989
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.964913552
Short name T648
Test name
Test status
Simulation time 32556561164 ps
CPU time 49.85 seconds
Started Jun 13 01:58:36 PM PDT 24
Finished Jun 13 01:59:27 PM PDT 24
Peak memory 200844 kb
Host smart-714e72d4-7afc-45e7-83ff-5c33ab5b5c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964913552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.964913552
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.2402865250
Short name T508
Test name
Test status
Simulation time 49475523200 ps
CPU time 200.6 seconds
Started Jun 13 02:00:33 PM PDT 24
Finished Jun 13 02:03:55 PM PDT 24
Peak memory 216328 kb
Host smart-e5563ce3-8495-4f40-b6d0-4c969067892b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402865250 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.2402865250
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.652012652
Short name T916
Test name
Test status
Simulation time 146235866367 ps
CPU time 354.19 seconds
Started Jun 13 01:33:46 PM PDT 24
Finished Jun 13 01:39:41 PM PDT 24
Peak memory 200808 kb
Host smart-450eef80-20d7-432c-a8c4-8aa5b499ece3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652012652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.652012652
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.982035965
Short name T919
Test name
Test status
Simulation time 189461706885 ps
CPU time 562.11 seconds
Started Jun 13 02:05:07 PM PDT 24
Finished Jun 13 02:14:30 PM PDT 24
Peak memory 217292 kb
Host smart-66f7b2a3-b7eb-4a9d-a1f0-ace8a73e36f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982035965 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.982035965
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.1161798508
Short name T863
Test name
Test status
Simulation time 5964627656 ps
CPU time 9.95 seconds
Started Jun 13 02:18:24 PM PDT 24
Finished Jun 13 02:18:41 PM PDT 24
Peak memory 200732 kb
Host smart-75002d93-a929-40af-9b79-6af2b8c99fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161798508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.1161798508
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.3681128871
Short name T218
Test name
Test status
Simulation time 129943364615 ps
CPU time 97.01 seconds
Started Jun 13 01:02:51 PM PDT 24
Finished Jun 13 01:04:28 PM PDT 24
Peak memory 201016 kb
Host smart-9cd278bd-613a-4bb1-a26f-9a40f38e67a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681128871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.3681128871
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.3221137365
Short name T30
Test name
Test status
Simulation time 46874823734 ps
CPU time 268.77 seconds
Started Jun 13 01:56:46 PM PDT 24
Finished Jun 13 02:01:16 PM PDT 24
Peak memory 217188 kb
Host smart-1f317f70-ba17-4c0c-be23-436b134219cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221137365 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.3221137365
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.1774651679
Short name T650
Test name
Test status
Simulation time 13309680 ps
CPU time 0.56 seconds
Started Jun 13 01:00:51 PM PDT 24
Finished Jun 13 01:00:54 PM PDT 24
Peak memory 196036 kb
Host smart-c4647a6b-9506-4c5c-8e19-c7793f4974ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774651679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.1774651679
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.1640873620
Short name T113
Test name
Test status
Simulation time 38116636675 ps
CPU time 54.17 seconds
Started Jun 13 01:01:01 PM PDT 24
Finished Jun 13 01:01:57 PM PDT 24
Peak memory 200772 kb
Host smart-8b0dfd53-782c-4c0c-9dfb-cbcd4b527e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640873620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.1640873620
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.1607988868
Short name T876
Test name
Test status
Simulation time 162586081287 ps
CPU time 67.53 seconds
Started Jun 13 01:00:52 PM PDT 24
Finished Jun 13 01:02:02 PM PDT 24
Peak memory 200768 kb
Host smart-bdc733fa-f243-4f3a-bf32-514bdcdb8fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607988868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.1607988868
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_intr.1778616068
Short name T530
Test name
Test status
Simulation time 11706690989 ps
CPU time 17.4 seconds
Started Jun 13 01:00:51 PM PDT 24
Finished Jun 13 01:01:10 PM PDT 24
Peak memory 200704 kb
Host smart-aeb367ee-f8dc-459b-91f2-409fa93c0aa9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778616068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.1778616068
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.3261262086
Short name T880
Test name
Test status
Simulation time 75566706245 ps
CPU time 266.2 seconds
Started Jun 13 01:00:52 PM PDT 24
Finished Jun 13 01:05:20 PM PDT 24
Peak memory 200744 kb
Host smart-0ba1dce4-f8da-4a65-a228-b336232d7e4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3261262086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.3261262086
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.1211489485
Short name T708
Test name
Test status
Simulation time 502906987 ps
CPU time 0.85 seconds
Started Jun 13 01:01:01 PM PDT 24
Finished Jun 13 01:01:02 PM PDT 24
Peak memory 196708 kb
Host smart-232119fb-9773-4ed0-a0a3-86052123bf51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211489485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.1211489485
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_perf.3488730350
Short name T364
Test name
Test status
Simulation time 20033223974 ps
CPU time 166.29 seconds
Started Jun 13 01:00:49 PM PDT 24
Finished Jun 13 01:03:35 PM PDT 24
Peak memory 200812 kb
Host smart-f61347e5-fae4-4025-999d-72f4b0215c14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3488730350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.3488730350
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.3240732407
Short name T342
Test name
Test status
Simulation time 6939582437 ps
CPU time 32.14 seconds
Started Jun 13 01:00:54 PM PDT 24
Finished Jun 13 01:01:28 PM PDT 24
Peak memory 199140 kb
Host smart-5a7257ae-6658-46b7-af0b-933b21ed240d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3240732407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.3240732407
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.1654543343
Short name T873
Test name
Test status
Simulation time 98299960662 ps
CPU time 124.67 seconds
Started Jun 13 01:00:52 PM PDT 24
Finished Jun 13 01:02:59 PM PDT 24
Peak memory 200736 kb
Host smart-bd0f35aa-530d-4514-abfe-d4a43848ae8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654543343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.1654543343
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.1988949492
Short name T380
Test name
Test status
Simulation time 3103313645 ps
CPU time 3.24 seconds
Started Jun 13 01:00:50 PM PDT 24
Finished Jun 13 01:00:54 PM PDT 24
Peak memory 196752 kb
Host smart-d191755b-2927-4323-8710-6ee1793e2048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988949492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.1988949492
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.902721247
Short name T858
Test name
Test status
Simulation time 278093529 ps
CPU time 1.15 seconds
Started Jun 13 01:00:49 PM PDT 24
Finished Jun 13 01:00:51 PM PDT 24
Peak memory 199016 kb
Host smart-ce5ff4d8-6320-41b6-80df-1f759c87d3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902721247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.902721247
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.2431941181
Short name T813
Test name
Test status
Simulation time 93656262251 ps
CPU time 147.24 seconds
Started Jun 13 01:00:52 PM PDT 24
Finished Jun 13 01:03:21 PM PDT 24
Peak memory 200752 kb
Host smart-090c73ae-75fb-47d4-800d-39c3ffc69738
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431941181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.2431941181
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.2302016641
Short name T277
Test name
Test status
Simulation time 1052138297 ps
CPU time 3.89 seconds
Started Jun 13 01:00:51 PM PDT 24
Finished Jun 13 01:00:56 PM PDT 24
Peak memory 199596 kb
Host smart-7d26f7dc-1e3a-4d66-b772-4cbd883555e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302016641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.2302016641
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.1359235060
Short name T1073
Test name
Test status
Simulation time 116851228401 ps
CPU time 19.52 seconds
Started Jun 13 01:00:51 PM PDT 24
Finished Jun 13 01:01:12 PM PDT 24
Peak memory 200760 kb
Host smart-32dc4708-7ae4-4e45-bbfc-6f35d84011ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359235060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.1359235060
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.3650263647
Short name T160
Test name
Test status
Simulation time 188352241239 ps
CPU time 30.96 seconds
Started Jun 13 01:02:48 PM PDT 24
Finished Jun 13 01:03:20 PM PDT 24
Peak memory 200688 kb
Host smart-dba8c3b6-a622-48e9-846b-6beff2aaaded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650263647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.3650263647
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.1348462239
Short name T1067
Test name
Test status
Simulation time 172810078743 ps
CPU time 577.19 seconds
Started Jun 13 01:19:07 PM PDT 24
Finished Jun 13 01:28:46 PM PDT 24
Peak memory 217208 kb
Host smart-e771245f-f8f8-4db9-886b-941d7f432be9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348462239 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.1348462239
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.2545570694
Short name T684
Test name
Test status
Simulation time 84560237006 ps
CPU time 175.59 seconds
Started Jun 13 02:10:33 PM PDT 24
Finished Jun 13 02:13:29 PM PDT 24
Peak memory 200836 kb
Host smart-d51fc12e-d07f-461b-b927-5c70f6343768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545570694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.2545570694
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.1371528322
Short name T981
Test name
Test status
Simulation time 102145788842 ps
CPU time 681.33 seconds
Started Jun 13 01:11:15 PM PDT 24
Finished Jun 13 01:22:37 PM PDT 24
Peak memory 217244 kb
Host smart-35db2c74-0d08-40e0-b953-e981b4e136f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371528322 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.1371528322
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.1091533987
Short name T690
Test name
Test status
Simulation time 69935600143 ps
CPU time 9.02 seconds
Started Jun 13 02:08:38 PM PDT 24
Finished Jun 13 02:08:48 PM PDT 24
Peak memory 200548 kb
Host smart-2112ea01-0f17-40d3-abe4-24eb40d94246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091533987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.1091533987
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.1132698268
Short name T839
Test name
Test status
Simulation time 60156435596 ps
CPU time 159.76 seconds
Started Jun 13 01:40:47 PM PDT 24
Finished Jun 13 01:43:27 PM PDT 24
Peak memory 216588 kb
Host smart-671d6ff7-6b50-4802-a96c-96420d1e0a17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132698268 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.1132698268
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.3015083707
Short name T680
Test name
Test status
Simulation time 8461947067 ps
CPU time 13.94 seconds
Started Jun 13 01:46:49 PM PDT 24
Finished Jun 13 01:47:04 PM PDT 24
Peak memory 200784 kb
Host smart-a8491530-2967-4c93-b083-52ffcfab7163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015083707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.3015083707
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.4043427890
Short name T52
Test name
Test status
Simulation time 324236999947 ps
CPU time 705.82 seconds
Started Jun 13 01:02:51 PM PDT 24
Finished Jun 13 01:14:37 PM PDT 24
Peak memory 217448 kb
Host smart-bbd0e943-02f0-4889-a6bb-a99e88a33d13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043427890 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.4043427890
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.362989422
Short name T285
Test name
Test status
Simulation time 145752403891 ps
CPU time 108.97 seconds
Started Jun 13 01:02:50 PM PDT 24
Finished Jun 13 01:04:39 PM PDT 24
Peak memory 200748 kb
Host smart-577ad89d-7c35-4dbc-a8a1-5312dc04a3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362989422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.362989422
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.2623324096
Short name T477
Test name
Test status
Simulation time 170238034904 ps
CPU time 36.2 seconds
Started Jun 13 01:02:50 PM PDT 24
Finished Jun 13 01:03:27 PM PDT 24
Peak memory 200744 kb
Host smart-9d5ac19e-da41-4cc4-8541-d5051d4de780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623324096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.2623324096
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.3223903327
Short name T802
Test name
Test status
Simulation time 31487700386 ps
CPU time 445.18 seconds
Started Jun 13 01:46:37 PM PDT 24
Finished Jun 13 01:54:03 PM PDT 24
Peak memory 217296 kb
Host smart-b8005bb8-a7ba-4cc6-b8ca-6ae594e3a3ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223903327 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.3223903327
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.1873858411
Short name T32
Test name
Test status
Simulation time 34022726706 ps
CPU time 55.8 seconds
Started Jun 13 01:22:08 PM PDT 24
Finished Jun 13 01:23:04 PM PDT 24
Peak memory 200820 kb
Host smart-694ade17-d8dc-4db4-a2e1-82b4b5ca6d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873858411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.1873858411
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.3411256844
Short name T326
Test name
Test status
Simulation time 27684298027 ps
CPU time 189.54 seconds
Started Jun 13 01:29:26 PM PDT 24
Finished Jun 13 01:32:37 PM PDT 24
Peak memory 217240 kb
Host smart-217050e1-a0c0-4c2e-a985-e932b5fdbb8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411256844 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.3411256844
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.928254339
Short name T203
Test name
Test status
Simulation time 7305992773 ps
CPU time 13.13 seconds
Started Jun 13 02:14:51 PM PDT 24
Finished Jun 13 02:15:05 PM PDT 24
Peak memory 200592 kb
Host smart-540cb315-f071-4fac-aecc-1479d4ac95a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928254339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.928254339
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.2177659767
Short name T861
Test name
Test status
Simulation time 130166413551 ps
CPU time 1170.26 seconds
Started Jun 13 02:07:21 PM PDT 24
Finished Jun 13 02:26:53 PM PDT 24
Peak memory 217264 kb
Host smart-ca3edf30-e295-4905-8a9e-2335716e1ac4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177659767 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.2177659767
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.3169044363
Short name T506
Test name
Test status
Simulation time 9716256421 ps
CPU time 13.8 seconds
Started Jun 13 01:02:48 PM PDT 24
Finished Jun 13 01:03:03 PM PDT 24
Peak memory 199788 kb
Host smart-b9b3272a-e10f-42e2-b521-499e9fc0cabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169044363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.3169044363
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.237415400
Short name T101
Test name
Test status
Simulation time 53588135 ps
CPU time 0.56 seconds
Started Jun 13 01:01:04 PM PDT 24
Finished Jun 13 01:01:05 PM PDT 24
Peak memory 195984 kb
Host smart-d509e254-b714-4016-8265-d368464e3572
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237415400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.237415400
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.1255815174
Short name T297
Test name
Test status
Simulation time 20247014549 ps
CPU time 28.88 seconds
Started Jun 13 01:00:48 PM PDT 24
Finished Jun 13 01:01:17 PM PDT 24
Peak memory 200780 kb
Host smart-eb1ee4ff-45ec-4960-b860-6674a0ede598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255815174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.1255815174
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.493950160
Short name T987
Test name
Test status
Simulation time 54324073380 ps
CPU time 22.27 seconds
Started Jun 13 01:00:51 PM PDT 24
Finished Jun 13 01:01:15 PM PDT 24
Peak memory 200800 kb
Host smart-0672a962-ad71-478e-a8fd-2cd86a3c66b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493950160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.493950160
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.3413464494
Short name T1034
Test name
Test status
Simulation time 45107964671 ps
CPU time 15.88 seconds
Started Jun 13 01:01:00 PM PDT 24
Finished Jun 13 01:01:17 PM PDT 24
Peak memory 200488 kb
Host smart-d90ee5ab-6e27-4bca-82e1-72c9ea191638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413464494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.3413464494
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.2796210588
Short name T13
Test name
Test status
Simulation time 15521392249 ps
CPU time 21.32 seconds
Started Jun 13 01:00:52 PM PDT 24
Finished Jun 13 01:01:16 PM PDT 24
Peak memory 200788 kb
Host smart-03a01309-cc82-472f-8287-8a6d58c7df17
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796210588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.2796210588
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.332702315
Short name T67
Test name
Test status
Simulation time 164933677059 ps
CPU time 106.37 seconds
Started Jun 13 01:00:52 PM PDT 24
Finished Jun 13 01:02:41 PM PDT 24
Peak memory 200676 kb
Host smart-7738729c-485f-402c-9227-09bc49611b0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=332702315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.332702315
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.1089901608
Short name T714
Test name
Test status
Simulation time 10287492979 ps
CPU time 21.92 seconds
Started Jun 13 01:00:52 PM PDT 24
Finished Jun 13 01:01:16 PM PDT 24
Peak memory 200352 kb
Host smart-512e73ce-5ff9-471c-a200-a2b93bcb2c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089901608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.1089901608
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_perf.2158105424
Short name T414
Test name
Test status
Simulation time 26067654935 ps
CPU time 183.3 seconds
Started Jun 13 01:00:48 PM PDT 24
Finished Jun 13 01:03:52 PM PDT 24
Peak memory 200680 kb
Host smart-cfad0e9f-1ae1-4361-a42a-acb074fd9c40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2158105424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.2158105424
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.1699356414
Short name T881
Test name
Test status
Simulation time 1605130258 ps
CPU time 2.54 seconds
Started Jun 13 01:00:54 PM PDT 24
Finished Jun 13 01:00:59 PM PDT 24
Peak memory 198892 kb
Host smart-44c970c8-3df2-47c7-ada7-2ac31452cb82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1699356414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.1699356414
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.3338605380
Short name T37
Test name
Test status
Simulation time 28480695513 ps
CPU time 30.49 seconds
Started Jun 13 01:01:02 PM PDT 24
Finished Jun 13 01:01:33 PM PDT 24
Peak memory 200668 kb
Host smart-c481eaed-fe40-4317-a718-324245a0bafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338605380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.3338605380
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.2113946520
Short name T491
Test name
Test status
Simulation time 4241759573 ps
CPU time 2.18 seconds
Started Jun 13 01:00:53 PM PDT 24
Finished Jun 13 01:00:57 PM PDT 24
Peak memory 197076 kb
Host smart-7c695f72-fa71-44d5-a724-5fb73fd8b253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113946520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.2113946520
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.772206579
Short name T607
Test name
Test status
Simulation time 5780494858 ps
CPU time 6.67 seconds
Started Jun 13 01:00:52 PM PDT 24
Finished Jun 13 01:01:00 PM PDT 24
Peak memory 200680 kb
Host smart-f0bcd2b1-9a8f-4cf8-b00d-50f84e5e2f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772206579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.772206579
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.4032952961
Short name T68
Test name
Test status
Simulation time 61860973169 ps
CPU time 1475.53 seconds
Started Jun 13 01:00:55 PM PDT 24
Finished Jun 13 01:25:33 PM PDT 24
Peak memory 217156 kb
Host smart-2588c3c5-700f-4e18-985d-d2f296973999
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032952961 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.4032952961
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.3318649850
Short name T389
Test name
Test status
Simulation time 490796128 ps
CPU time 1.2 seconds
Started Jun 13 01:00:49 PM PDT 24
Finished Jun 13 01:00:52 PM PDT 24
Peak memory 197760 kb
Host smart-faa50935-cafd-4dd8-85ac-4ba765d7d829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318649850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.3318649850
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.2939244710
Short name T419
Test name
Test status
Simulation time 32426617854 ps
CPU time 48.76 seconds
Started Jun 13 01:00:53 PM PDT 24
Finished Jun 13 01:01:44 PM PDT 24
Peak memory 200772 kb
Host smart-6a702f86-0c53-430a-b5e5-b31d521e493b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939244710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.2939244710
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.14584889
Short name T114
Test name
Test status
Simulation time 130783697004 ps
CPU time 55.08 seconds
Started Jun 13 01:02:49 PM PDT 24
Finished Jun 13 01:03:45 PM PDT 24
Peak memory 200632 kb
Host smart-c113343a-9116-4248-834c-3758c003af41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14584889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.14584889
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.3569254080
Short name T443
Test name
Test status
Simulation time 60846010592 ps
CPU time 644.31 seconds
Started Jun 13 01:32:01 PM PDT 24
Finished Jun 13 01:42:46 PM PDT 24
Peak memory 217244 kb
Host smart-f87a0ee6-6618-4f55-86e1-46fbc8439b2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569254080 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.3569254080
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.4104752506
Short name T959
Test name
Test status
Simulation time 27560911257 ps
CPU time 33.39 seconds
Started Jun 13 01:14:16 PM PDT 24
Finished Jun 13 01:14:51 PM PDT 24
Peak memory 200776 kb
Host smart-044528e8-9b22-4589-8433-83db65733316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104752506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.4104752506
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.3640229537
Short name T86
Test name
Test status
Simulation time 136556905702 ps
CPU time 57.96 seconds
Started Jun 13 01:51:59 PM PDT 24
Finished Jun 13 01:52:58 PM PDT 24
Peak memory 200788 kb
Host smart-5664559c-14e7-406f-a531-a5888cf2c781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640229537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.3640229537
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.724222756
Short name T1000
Test name
Test status
Simulation time 101799513002 ps
CPU time 848.23 seconds
Started Jun 13 01:25:36 PM PDT 24
Finished Jun 13 01:39:46 PM PDT 24
Peak memory 215544 kb
Host smart-7413e4dc-b9ec-429a-b545-b2dbd86c72aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724222756 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.724222756
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.3480075358
Short name T655
Test name
Test status
Simulation time 137641350828 ps
CPU time 23.94 seconds
Started Jun 13 01:58:39 PM PDT 24
Finished Jun 13 01:59:04 PM PDT 24
Peak memory 200776 kb
Host smart-528b7127-489a-4971-b7d9-2e812ca0c26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480075358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.3480075358
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.1018204377
Short name T435
Test name
Test status
Simulation time 45289162480 ps
CPU time 34.14 seconds
Started Jun 13 01:15:26 PM PDT 24
Finished Jun 13 01:16:01 PM PDT 24
Peak memory 200824 kb
Host smart-35b9483c-88c8-4339-a770-1424e2dd1121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018204377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.1018204377
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.2173608861
Short name T54
Test name
Test status
Simulation time 259415369897 ps
CPU time 1003.87 seconds
Started Jun 13 02:10:08 PM PDT 24
Finished Jun 13 02:26:54 PM PDT 24
Peak memory 225508 kb
Host smart-1fb301dd-99a1-46e0-a98b-3cf37b6967db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173608861 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.2173608861
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.3056138252
Short name T531
Test name
Test status
Simulation time 541241852797 ps
CPU time 898.12 seconds
Started Jun 13 01:12:31 PM PDT 24
Finished Jun 13 01:27:29 PM PDT 24
Peak memory 217288 kb
Host smart-1ec21eb3-161e-427f-b39e-0d84c10f359f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056138252 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.3056138252
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.1650577007
Short name T872
Test name
Test status
Simulation time 34395107128 ps
CPU time 43 seconds
Started Jun 13 01:17:13 PM PDT 24
Finished Jun 13 01:17:57 PM PDT 24
Peak memory 200836 kb
Host smart-7a80c00b-2ff5-43be-88c2-abe805a8b662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650577007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.1650577007
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.565322889
Short name T182
Test name
Test status
Simulation time 22644947785 ps
CPU time 17.58 seconds
Started Jun 13 02:16:24 PM PDT 24
Finished Jun 13 02:16:46 PM PDT 24
Peak memory 200852 kb
Host smart-45f5274c-d3ef-4fb3-9c88-38cba679810f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565322889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.565322889
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.3952661126
Short name T850
Test name
Test status
Simulation time 72522843572 ps
CPU time 111.17 seconds
Started Jun 13 01:02:51 PM PDT 24
Finished Jun 13 01:04:43 PM PDT 24
Peak memory 200748 kb
Host smart-24b01267-6905-43b8-aaea-06a65c8fd727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952661126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.3952661126
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.2901700975
Short name T621
Test name
Test status
Simulation time 45463090988 ps
CPU time 174.04 seconds
Started Jun 13 02:07:25 PM PDT 24
Finished Jun 13 02:10:20 PM PDT 24
Peak memory 217248 kb
Host smart-84bc2adb-4074-4a8d-b53c-2d870fec5ff4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901700975 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.2901700975
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.4288451924
Short name T36
Test name
Test status
Simulation time 4628562635 ps
CPU time 7.91 seconds
Started Jun 13 02:10:16 PM PDT 24
Finished Jun 13 02:10:26 PM PDT 24
Peak memory 200760 kb
Host smart-445092b6-3710-4172-ace6-3d4af948772b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288451924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.4288451924
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.198217726
Short name T905
Test name
Test status
Simulation time 38574921 ps
CPU time 0.57 seconds
Started Jun 13 01:00:54 PM PDT 24
Finished Jun 13 01:00:57 PM PDT 24
Peak memory 196052 kb
Host smart-eb358c31-b10b-4ffa-81bf-687ac0be6082
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198217726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.198217726
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.828001376
Short name T293
Test name
Test status
Simulation time 29242374732 ps
CPU time 13.41 seconds
Started Jun 13 01:00:53 PM PDT 24
Finished Jun 13 01:01:09 PM PDT 24
Peak memory 198924 kb
Host smart-f3ffe800-4537-4975-98f0-40bb8a2d84e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828001376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.828001376
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.1403430493
Short name T374
Test name
Test status
Simulation time 12580549730 ps
CPU time 5.27 seconds
Started Jun 13 01:00:55 PM PDT 24
Finished Jun 13 01:01:03 PM PDT 24
Peak memory 199168 kb
Host smart-a62821c3-5d00-4992-8d58-159f4ee196cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403430493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.1403430493
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.1255795539
Short name T894
Test name
Test status
Simulation time 57492475370 ps
CPU time 168.02 seconds
Started Jun 13 01:00:53 PM PDT 24
Finished Jun 13 01:03:43 PM PDT 24
Peak memory 200720 kb
Host smart-18b26ecd-9268-4c8a-9e67-9d5902486c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255795539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.1255795539
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.980144782
Short name T619
Test name
Test status
Simulation time 24104139621 ps
CPU time 22.74 seconds
Started Jun 13 01:00:55 PM PDT 24
Finished Jun 13 01:01:20 PM PDT 24
Peak memory 200776 kb
Host smart-2871a19b-cee3-453e-9ced-16704a698732
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980144782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.980144782
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.4040771996
Short name T626
Test name
Test status
Simulation time 79738337707 ps
CPU time 399.87 seconds
Started Jun 13 01:00:54 PM PDT 24
Finished Jun 13 01:07:36 PM PDT 24
Peak memory 200820 kb
Host smart-1712238d-c6b8-4dd3-8c88-ad856854451e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4040771996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.4040771996
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.1578792298
Short name T896
Test name
Test status
Simulation time 5512031909 ps
CPU time 9.53 seconds
Started Jun 13 01:00:53 PM PDT 24
Finished Jun 13 01:01:04 PM PDT 24
Peak memory 199604 kb
Host smart-e9e30c10-b744-43c0-a3a3-6314a37b8454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578792298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.1578792298
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_perf.3694877475
Short name T703
Test name
Test status
Simulation time 13613594679 ps
CPU time 83.29 seconds
Started Jun 13 01:00:52 PM PDT 24
Finished Jun 13 01:02:18 PM PDT 24
Peak memory 200756 kb
Host smart-341c82be-0280-4c3a-a8cc-e4dbbc537b96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3694877475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.3694877475
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.238866864
Short name T573
Test name
Test status
Simulation time 6537987282 ps
CPU time 8.14 seconds
Started Jun 13 01:00:55 PM PDT 24
Finished Jun 13 01:01:05 PM PDT 24
Peak memory 199008 kb
Host smart-528221e8-64aa-4b27-99ff-f7a30807675f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=238866864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.238866864
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.1658346693
Short name T156
Test name
Test status
Simulation time 27924265596 ps
CPU time 8.8 seconds
Started Jun 13 01:00:57 PM PDT 24
Finished Jun 13 01:01:07 PM PDT 24
Peak memory 200356 kb
Host smart-1cd5fbed-b180-4079-acad-6ea5a5383168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658346693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.1658346693
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.2766495301
Short name T7
Test name
Test status
Simulation time 3625340220 ps
CPU time 1.29 seconds
Started Jun 13 01:00:53 PM PDT 24
Finished Jun 13 01:00:57 PM PDT 24
Peak memory 196808 kb
Host smart-15f8da28-6ed7-4368-95a5-f578b4250e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766495301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.2766495301
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.3937111032
Short name T841
Test name
Test status
Simulation time 5546002340 ps
CPU time 33.95 seconds
Started Jun 13 01:00:53 PM PDT 24
Finished Jun 13 01:01:29 PM PDT 24
Peak memory 200776 kb
Host smart-3046ebc4-63bf-4d8f-9b8e-e10f4888ba10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937111032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.3937111032
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.836686557
Short name T999
Test name
Test status
Simulation time 364533740108 ps
CPU time 220.88 seconds
Started Jun 13 01:01:11 PM PDT 24
Finished Jun 13 01:04:52 PM PDT 24
Peak memory 200664 kb
Host smart-fcefc509-0b5a-4248-882f-7d56d404cd2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836686557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.836686557
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.1240445187
Short name T412
Test name
Test status
Simulation time 46292682874 ps
CPU time 278.99 seconds
Started Jun 13 01:00:55 PM PDT 24
Finished Jun 13 01:05:36 PM PDT 24
Peak memory 208968 kb
Host smart-e1558af8-23f5-4703-a496-d237d98780e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240445187 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.1240445187
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.1960930696
Short name T572
Test name
Test status
Simulation time 992610550 ps
CPU time 2.18 seconds
Started Jun 13 01:01:02 PM PDT 24
Finished Jun 13 01:01:05 PM PDT 24
Peak memory 199640 kb
Host smart-89fd601e-f476-4aaa-a50b-c1e43a53ee54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960930696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.1960930696
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.1069563922
Short name T245
Test name
Test status
Simulation time 90541314177 ps
CPU time 114.74 seconds
Started Jun 13 01:01:11 PM PDT 24
Finished Jun 13 01:03:06 PM PDT 24
Peak memory 200652 kb
Host smart-42784ad4-d26e-434d-9b47-e56ef087ffd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069563922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.1069563922
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.3575323957
Short name T681
Test name
Test status
Simulation time 49391699054 ps
CPU time 17.49 seconds
Started Jun 13 01:17:45 PM PDT 24
Finished Jun 13 01:18:03 PM PDT 24
Peak memory 200836 kb
Host smart-9f54456c-1ef1-4023-aa16-61385bc00186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575323957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.3575323957
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.2319130444
Short name T194
Test name
Test status
Simulation time 94680698173 ps
CPU time 47.94 seconds
Started Jun 13 01:39:57 PM PDT 24
Finished Jun 13 01:40:46 PM PDT 24
Peak memory 200768 kb
Host smart-fd7474f0-ef81-4d42-b8f7-b746951848e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319130444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.2319130444
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.3846364372
Short name T426
Test name
Test status
Simulation time 14913178611 ps
CPU time 144.67 seconds
Started Jun 13 02:08:52 PM PDT 24
Finished Jun 13 02:11:18 PM PDT 24
Peak memory 208980 kb
Host smart-5e48be28-3522-478f-adc4-5ed4f2527966
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846364372 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.3846364372
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.1996539175
Short name T960
Test name
Test status
Simulation time 17064116680 ps
CPU time 25.15 seconds
Started Jun 13 02:17:55 PM PDT 24
Finished Jun 13 02:18:26 PM PDT 24
Peak memory 200796 kb
Host smart-709ad0a1-9d51-4bd0-9895-cc597b3a8322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996539175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.1996539175
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.1158350426
Short name T147
Test name
Test status
Simulation time 29179451738 ps
CPU time 14.62 seconds
Started Jun 13 01:38:56 PM PDT 24
Finished Jun 13 01:39:12 PM PDT 24
Peak memory 200780 kb
Host smart-3e0f0b6f-54df-4c23-8640-de34c8cfb5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158350426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.1158350426
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.1293023888
Short name T161
Test name
Test status
Simulation time 348970844858 ps
CPU time 410.29 seconds
Started Jun 13 01:22:27 PM PDT 24
Finished Jun 13 01:29:18 PM PDT 24
Peak memory 217228 kb
Host smart-8edf8183-50ce-4df3-acc8-3af240e0210e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293023888 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.1293023888
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.3575129281
Short name T129
Test name
Test status
Simulation time 23522923291 ps
CPU time 34.97 seconds
Started Jun 13 01:10:54 PM PDT 24
Finished Jun 13 01:11:33 PM PDT 24
Peak memory 200720 kb
Host smart-029edbb3-da10-4181-89b7-8904480836d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575129281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.3575129281
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.4055915984
Short name T181
Test name
Test status
Simulation time 105713330581 ps
CPU time 46.25 seconds
Started Jun 13 01:02:50 PM PDT 24
Finished Jun 13 01:03:37 PM PDT 24
Peak memory 200756 kb
Host smart-ad06cfbb-68f6-4502-accb-be8948cf003e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055915984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.4055915984
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.2958372755
Short name T794
Test name
Test status
Simulation time 139875881945 ps
CPU time 747.64 seconds
Started Jun 13 01:55:40 PM PDT 24
Finished Jun 13 02:08:09 PM PDT 24
Peak memory 225872 kb
Host smart-8d06dc84-04ed-4af0-8a1b-31f1016b2147
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958372755 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.2958372755
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.2020924339
Short name T738
Test name
Test status
Simulation time 62937969820 ps
CPU time 102.24 seconds
Started Jun 13 02:04:18 PM PDT 24
Finished Jun 13 02:06:02 PM PDT 24
Peak memory 200736 kb
Host smart-4c846965-c2fd-47cb-a1c1-f2f2d5120d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020924339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.2020924339
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.1084993476
Short name T51
Test name
Test status
Simulation time 259631039598 ps
CPU time 1349.09 seconds
Started Jun 13 01:02:48 PM PDT 24
Finished Jun 13 01:25:18 PM PDT 24
Peak memory 225460 kb
Host smart-4d8d7b27-996c-4a74-88ad-b9bbec40ed3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084993476 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.1084993476
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.2805469565
Short name T411
Test name
Test status
Simulation time 156919186796 ps
CPU time 254.17 seconds
Started Jun 13 02:36:39 PM PDT 24
Finished Jun 13 02:40:55 PM PDT 24
Peak memory 200844 kb
Host smart-1f377211-7d52-4979-a0bf-9ab1d6229005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805469565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.2805469565
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.1836848675
Short name T587
Test name
Test status
Simulation time 73873519702 ps
CPU time 199.05 seconds
Started Jun 13 01:26:15 PM PDT 24
Finished Jun 13 01:29:35 PM PDT 24
Peak memory 200836 kb
Host smart-f4d20815-a869-4bce-96aa-9b65f99bff0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836848675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.1836848675
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.3867720666
Short name T1065
Test name
Test status
Simulation time 16905290908 ps
CPU time 16.88 seconds
Started Jun 13 02:56:09 PM PDT 24
Finished Jun 13 02:56:27 PM PDT 24
Peak memory 200864 kb
Host smart-8214dd6b-c311-418f-9dba-2f4f4320cd95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867720666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.3867720666
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.837161123
Short name T498
Test name
Test status
Simulation time 16841078192 ps
CPU time 333.35 seconds
Started Jun 13 01:02:49 PM PDT 24
Finished Jun 13 01:08:23 PM PDT 24
Peak memory 209092 kb
Host smart-68dbc7cf-185f-41da-9c6f-fc7fb484a985
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837161123 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.837161123
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.1203488067
Short name T355
Test name
Test status
Simulation time 12583382 ps
CPU time 0.55 seconds
Started Jun 13 01:00:53 PM PDT 24
Finished Jun 13 01:00:56 PM PDT 24
Peak memory 196364 kb
Host smart-75a7770f-6ed7-44da-8aff-e81b1bbcd52d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203488067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.1203488067
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.151932521
Short name T1004
Test name
Test status
Simulation time 39502007104 ps
CPU time 13.4 seconds
Started Jun 13 01:00:56 PM PDT 24
Finished Jun 13 01:01:11 PM PDT 24
Peak memory 200464 kb
Host smart-76f3cb35-63e9-47a3-ae66-b32531e39a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151932521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.151932521
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.2125663100
Short name T736
Test name
Test status
Simulation time 22362870077 ps
CPU time 17.83 seconds
Started Jun 13 01:00:54 PM PDT 24
Finished Jun 13 01:01:14 PM PDT 24
Peak memory 199688 kb
Host smart-faa7a9b3-9684-4038-b445-d20203233a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125663100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.2125663100
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.3663322175
Short name T879
Test name
Test status
Simulation time 16637488278 ps
CPU time 15.39 seconds
Started Jun 13 01:00:54 PM PDT 24
Finished Jun 13 01:01:12 PM PDT 24
Peak memory 200656 kb
Host smart-b277e48a-d5a9-4a65-8f91-6304d82d334d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663322175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.3663322175
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.389525123
Short name T1019
Test name
Test status
Simulation time 4580753528 ps
CPU time 7 seconds
Started Jun 13 01:00:54 PM PDT 24
Finished Jun 13 01:01:03 PM PDT 24
Peak memory 196692 kb
Host smart-18ae2854-2353-4698-9465-5b2058c66e35
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389525123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.389525123
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.2683931654
Short name T743
Test name
Test status
Simulation time 187073767733 ps
CPU time 804.36 seconds
Started Jun 13 01:00:58 PM PDT 24
Finished Jun 13 01:14:23 PM PDT 24
Peak memory 200776 kb
Host smart-8c372f96-e625-4d9f-852b-3fc506efe513
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2683931654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.2683931654
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.4190776479
Short name T649
Test name
Test status
Simulation time 7119455574 ps
CPU time 7.44 seconds
Started Jun 13 01:01:05 PM PDT 24
Finished Jun 13 01:01:13 PM PDT 24
Peak memory 199408 kb
Host smart-7696842c-cd61-48db-8b44-2d5c5d86da00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190776479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.4190776479
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_perf.55295083
Short name T551
Test name
Test status
Simulation time 3650246129 ps
CPU time 220.36 seconds
Started Jun 13 01:01:11 PM PDT 24
Finished Jun 13 01:04:52 PM PDT 24
Peak memory 200572 kb
Host smart-27d8bc3f-aa7c-4bf5-97e0-ee8905a386cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=55295083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.55295083
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.934111461
Short name T377
Test name
Test status
Simulation time 3063813145 ps
CPU time 22.29 seconds
Started Jun 13 01:00:57 PM PDT 24
Finished Jun 13 01:01:20 PM PDT 24
Peak memory 198868 kb
Host smart-cb93524c-6b8c-4512-8470-cb6b6fb8e47c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=934111461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.934111461
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.1251348269
Short name T85
Test name
Test status
Simulation time 17010428372 ps
CPU time 31.34 seconds
Started Jun 13 01:00:57 PM PDT 24
Finished Jun 13 01:01:29 PM PDT 24
Peak memory 200784 kb
Host smart-cdc96904-0189-4fb3-8ae0-677eb39caab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251348269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.1251348269
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.1386868780
Short name T882
Test name
Test status
Simulation time 45551433261 ps
CPU time 31.97 seconds
Started Jun 13 01:00:57 PM PDT 24
Finished Jun 13 01:01:30 PM PDT 24
Peak memory 196780 kb
Host smart-ee343a2c-91a9-4f24-8a44-42c158788836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386868780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.1386868780
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.1126187244
Short name T294
Test name
Test status
Simulation time 278220695 ps
CPU time 1.23 seconds
Started Jun 13 01:00:55 PM PDT 24
Finished Jun 13 01:00:59 PM PDT 24
Peak memory 200296 kb
Host smart-7fea0ec0-330d-41fa-855f-127aa2f2dd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126187244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.1126187244
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.210265390
Short name T822
Test name
Test status
Simulation time 82006597226 ps
CPU time 287.39 seconds
Started Jun 13 01:00:54 PM PDT 24
Finished Jun 13 01:05:43 PM PDT 24
Peak memory 217172 kb
Host smart-2898b2f0-9da8-4876-8beb-375c4c6edbc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210265390 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.210265390
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.3353773536
Short name T489
Test name
Test status
Simulation time 321094070 ps
CPU time 1.2 seconds
Started Jun 13 01:01:04 PM PDT 24
Finished Jun 13 01:01:07 PM PDT 24
Peak memory 198432 kb
Host smart-3d100161-8f3a-4247-b48a-8f7672731e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353773536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.3353773536
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.3256535175
Short name T283
Test name
Test status
Simulation time 58365934763 ps
CPU time 156.31 seconds
Started Jun 13 01:00:56 PM PDT 24
Finished Jun 13 01:03:34 PM PDT 24
Peak memory 200584 kb
Host smart-898996e3-a1b1-466a-8ed0-21f628fd705b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256535175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.3256535175
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.1025696083
Short name T638
Test name
Test status
Simulation time 36430539998 ps
CPU time 24.47 seconds
Started Jun 13 01:02:50 PM PDT 24
Finished Jun 13 01:03:15 PM PDT 24
Peak memory 200764 kb
Host smart-92fd48f4-a0f4-43c9-8c20-362642b3f0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025696083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.1025696083
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.1728856181
Short name T205
Test name
Test status
Simulation time 61717685019 ps
CPU time 161.77 seconds
Started Jun 13 02:03:41 PM PDT 24
Finished Jun 13 02:06:24 PM PDT 24
Peak memory 200856 kb
Host smart-5006e396-f64e-4cf8-af1e-da4d6d9f6ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728856181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.1728856181
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.3199996470
Short name T84
Test name
Test status
Simulation time 6891520904 ps
CPU time 11.56 seconds
Started Jun 13 01:03:02 PM PDT 24
Finished Jun 13 01:03:14 PM PDT 24
Peak memory 200616 kb
Host smart-9b2db81d-dac8-4efe-a1a5-aabb4ca8e7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199996470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.3199996470
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.1935699928
Short name T1027
Test name
Test status
Simulation time 746971199829 ps
CPU time 971.18 seconds
Started Jun 13 02:05:40 PM PDT 24
Finished Jun 13 02:21:55 PM PDT 24
Peak memory 225520 kb
Host smart-26ff19fd-7416-4d5c-8d9a-93ff6d4fbfcc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935699928 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.1935699928
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.622805708
Short name T819
Test name
Test status
Simulation time 274500089673 ps
CPU time 27.29 seconds
Started Jun 13 02:22:03 PM PDT 24
Finished Jun 13 02:22:31 PM PDT 24
Peak memory 200868 kb
Host smart-3919e757-c391-4a5c-8aff-0291094daa44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622805708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.622805708
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.1252834486
Short name T183
Test name
Test status
Simulation time 32812583990 ps
CPU time 29.03 seconds
Started Jun 13 02:42:31 PM PDT 24
Finished Jun 13 02:43:08 PM PDT 24
Peak memory 200856 kb
Host smart-fa4b736e-afe7-4a27-b7ae-6c1829fe5fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252834486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.1252834486
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.960521098
Short name T27
Test name
Test status
Simulation time 26064720501 ps
CPU time 491.93 seconds
Started Jun 13 01:22:07 PM PDT 24
Finished Jun 13 01:30:20 PM PDT 24
Peak memory 209952 kb
Host smart-1cc7419e-f69f-4779-ae18-af474c19d04b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960521098 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.960521098
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.1487976734
Short name T238
Test name
Test status
Simulation time 80699097001 ps
CPU time 127.15 seconds
Started Jun 13 02:11:13 PM PDT 24
Finished Jun 13 02:13:21 PM PDT 24
Peak memory 200860 kb
Host smart-2baadd06-35ae-4d28-a6b0-f4c6f58d406f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487976734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.1487976734
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.1431192277
Short name T53
Test name
Test status
Simulation time 99716583625 ps
CPU time 596.45 seconds
Started Jun 13 01:18:30 PM PDT 24
Finished Jun 13 01:28:26 PM PDT 24
Peak memory 217252 kb
Host smart-8838948b-62bd-4ef3-9284-8cffed24bf67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431192277 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.1431192277
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.67509019
Short name T577
Test name
Test status
Simulation time 48659591499 ps
CPU time 110.78 seconds
Started Jun 13 02:00:40 PM PDT 24
Finished Jun 13 02:02:32 PM PDT 24
Peak memory 200740 kb
Host smart-527c36e1-41cc-4df9-84ff-206fc53ee0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67509019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.67509019
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.72366747
Short name T922
Test name
Test status
Simulation time 46085656079 ps
CPU time 21.18 seconds
Started Jun 13 01:02:47 PM PDT 24
Finished Jun 13 01:03:08 PM PDT 24
Peak memory 200704 kb
Host smart-4f818ea7-13c0-45de-88d4-673e81324d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72366747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.72366747
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.1304124217
Short name T1071
Test name
Test status
Simulation time 20472005860 ps
CPU time 32.22 seconds
Started Jun 13 02:57:08 PM PDT 24
Finished Jun 13 02:57:41 PM PDT 24
Peak memory 200800 kb
Host smart-fb8e9a2a-4040-4d44-8bce-f0ed4c9564a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304124217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.1304124217
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.3734088317
Short name T327
Test name
Test status
Simulation time 81771647873 ps
CPU time 945.89 seconds
Started Jun 13 02:20:05 PM PDT 24
Finished Jun 13 02:35:58 PM PDT 24
Peak memory 225424 kb
Host smart-99e5de58-a31f-4e0f-a583-38b4eff366c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734088317 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.3734088317
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.501201973
Short name T360
Test name
Test status
Simulation time 57518592212 ps
CPU time 32.79 seconds
Started Jun 13 01:02:50 PM PDT 24
Finished Jun 13 01:03:24 PM PDT 24
Peak memory 200740 kb
Host smart-fb43ce77-bc04-4262-a33a-683d3da33a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501201973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.501201973
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.3940272172
Short name T325
Test name
Test status
Simulation time 53314659631 ps
CPU time 568.26 seconds
Started Jun 13 01:02:50 PM PDT 24
Finished Jun 13 01:12:18 PM PDT 24
Peak memory 211776 kb
Host smart-04243da5-7650-45b9-a711-494f8c2e544f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940272172 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.3940272172
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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