Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	106648	1			T1	1		T2	1		T3	45
all_values[1]	106648	1			T1	1		T2	1		T3	45
all_values[2]	106648	1			T1	1		T2	1		T3	45
all_values[3]	106648	1			T1	1		T2	1		T3	45
all_values[4]	106648	1			T1	1		T2	1		T3	45
all_values[5]	106648	1			T1	1		T2	1		T3	45
all_values[6]	106648	1			T1	1		T2	1		T3	45
all_values[7]	106648	1			T1	1		T2	1		T3	45
all_values[8]	106648	1			T1	1		T2	1		T3	45

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

486297

1

T1

5

T2

4

T3

252

auto[1]

473535

1

T1

4

T2

5

T3

153

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

875342

1

T1

7

T2

7

T3

355

auto[1]

84490

1

T1

2

T2

2

T3

50

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	33426	1			T3	19		T4	5		T5	95
all_values[0]	auto[0]	auto[1]	23424	1			T1	1		T2	1		T5	31
all_values[0]	auto[1]	auto[0]	30565	1			T3	9		T5	93		T8	350
all_values[0]	auto[1]	auto[1]	19233	1			T3	17		T4	3		T5	255
all_values[1]	auto[0]	auto[0]	53685	1			T3	31		T5	227		T6	2
all_values[1]	auto[0]	auto[1]	1569	1			T3	12		T10	1		T13	11
all_values[1]	auto[1]	auto[0]	49862	1			T1	1		T2	1		T3	2
all_values[1]	auto[1]	auto[1]	1532	1			T4	1		T53	1		T15	2
all_values[2]	auto[0]	auto[0]	51580	1			T1	1		T2	1		T3	23
all_values[2]	auto[0]	auto[1]	2422	1			T3	3		T5	4		T6	1
all_values[2]	auto[1]	auto[0]	50389	1			T3	16		T4	6		T5	137
all_values[2]	auto[1]	auto[1]	2257	1			T3	3		T4	2		T5	1
all_values[3]	auto[0]	auto[0]	53322	1			T1	1		T3	4		T4	5
all_values[3]	auto[0]	auto[1]	256	1			T96	2		T56	1		T16	1
all_values[3]	auto[1]	auto[0]	52747	1			T2	1		T3	41		T4	3
all_values[3]	auto[1]	auto[1]	323	1			T12	1		T14	1		T15	2
all_values[4]	auto[0]	auto[0]	54640	1			T1	1		T3	41		T4	3
all_values[4]	auto[0]	auto[1]	328	1			T16	4		T18	4		T97	5
all_values[4]	auto[1]	auto[0]	51300	1			T2	1		T3	4		T4	5
all_values[4]	auto[1]	auto[1]	380	1			T16	14		T17	5		T94	2
all_values[5]	auto[0]	auto[0]	52736	1			T2	1		T3	43		T4	8
all_values[5]	auto[0]	auto[1]	168	1			T16	2		T95	2		T41	5
all_values[5]	auto[1]	auto[0]	53556	1			T1	1		T3	2		T5	235
all_values[5]	auto[1]	auto[1]	188	1			T94	2		T41	3		T65	2
all_values[6]	auto[0]	auto[0]	55918	1			T3	26		T5	17		T6	2
all_values[6]	auto[0]	auto[1]	154	1			T94	1		T41	4		T46	1
all_values[6]	auto[1]	auto[0]	50424	1			T1	1		T2	1		T3	19
all_values[6]	auto[1]	auto[1]	152	1			T94	1		T41	1		T46	3
all_values[7]	auto[0]	auto[0]	49001	1			T1	1		T2	1		T3	28
all_values[7]	auto[0]	auto[1]	348	1			T16	1		T17	4		T138	2
all_values[7]	auto[1]	auto[0]	56982	1			T3	17		T4	3		T5	149
all_values[7]	auto[1]	auto[1]	317	1			T20	3		T16	5		T21	4
all_values[8]	auto[0]	auto[0]	39305	1			T3	9		T5	185		T8	422
all_values[8]	auto[0]	auto[1]	14015	1			T3	13		T4	3		T5	134
all_values[8]	auto[1]	auto[0]	35904	1			T3	21		T4	5		T5	32
all_values[8]	auto[1]	auto[1]	17424	1			T1	1		T2	1		T3	2