Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2334

1

T1

1

T2

1

T3

1

auto[UartRx]

2334

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4183	1			T1	2		T2	2		T3	2
values[1]	34	1			T27	1		T41	1		T65	1
values[2]	52	1			T16	1		T27	1		T28	1
values[3]	57	1			T16	1		T27	1		T40	1
values[4]	41	1			T40	1		T42	1		T43	2
values[5]	41	1			T16	1		T27	1		T40	1
values[6]	46	1			T27	1		T41	1		T46	1
values[7]	40	1			T16	1		T41	1		T43	2
values[8]	38	1			T16	2		T41	1		T42	1
values[9]	68	1			T16	2		T27	1		T28	3
values[10]	47	1			T27	1		T40	1		T41	2

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2157	1			T1	1		T2	1		T3	1
auto[UartTx]	values[1]	10	1			T149	1		T318	1		T319	1
auto[UartTx]	values[2]	19	1			T41	1		T44	1		T127	1
auto[UartTx]	values[3]	21	1			T27	1		T126	1		T129	1
auto[UartTx]	values[4]	12	1			T320	2		T208	1		T321	1
auto[UartTx]	values[5]	14	1			T40	1		T41	1		T43	1
auto[UartTx]	values[6]	19	1			T27	1		T65	1		T118	1
auto[UartTx]	values[7]	18	1			T43	2		T46	2		T65	2
auto[UartTx]	values[8]	12	1			T16	1		T41	1		T42	1
auto[UartTx]	values[9]	29	1			T16	1		T28	1		T43	1
auto[UartTx]	values[10]	16	1			T41	1		T42	1		T149	1
auto[UartRx]	values[0]	2026	1			T1	1		T2	1		T3	1
auto[UartRx]	values[1]	24	1			T27	1		T41	1		T65	1
auto[UartRx]	values[2]	33	1			T16	1		T27	1		T28	1
auto[UartRx]	values[3]	36	1			T16	1		T40	1		T41	1
auto[UartRx]	values[4]	29	1			T40	1		T42	1		T43	2
auto[UartRx]	values[5]	27	1			T16	1		T27	1		T41	1
auto[UartRx]	values[6]	27	1			T41	1		T46	1		T65	1
auto[UartRx]	values[7]	22	1			T16	1		T41	1		T46	1
auto[UartRx]	values[8]	26	1			T16	1		T45	1		T65	1
auto[UartRx]	values[9]	39	1			T16	1		T27	1		T28	2
auto[UartRx]	values[10]	31	1			T27	1		T40	1		T41	1