Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1973	1			T1	9		T2	12		T9	1
auto[BaudRate115200]	1649	1			T1	6		T2	3		T3	2
auto[BaudRate230400]	1668	1			T1	3		T2	9		T3	1
auto[BaudRate128Kbps]	1741	1			T1	3		T3	2		T5	2
auto[BaudRate256Kbps]	1824	1			T1	3		T2	3		T3	1
auto[BaudRate1Mbps]	1747	1			T2	9		T3	2		T4	3
auto[BaudRate1p5Mbps]	1251	1			T1	3		T3	2		T5	2

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1293	1			T5	8		T11	4		T276	3
freqs[25]	886	1			T15	6		T96	9		T17	3
freqs[48]	852	1			T277	3		T322	2		T147	8
freqs[50]	599	1			T123	5		T278	6		T16	73
freqs[100]	1025	1			T93	6		T53	8		T56	9

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	226	1			T55	1		T51	2		T97	1
auto[BaudRate9600]	freqs[25]	174	1			T15	1		T96	1		T272	1
auto[BaudRate9600]	freqs[48]	124	1			T277	1		T147	2		T61	1
auto[BaudRate9600]	freqs[50]	110	1			T123	2		T16	16		T48	2
auto[BaudRate9600]	freqs[100]	114	1			T56	1		T47	1		T137	1
auto[BaudRate115200]	freqs[24]	162	1			T5	1		T55	1		T261	1
auto[BaudRate115200]	freqs[25]	128	1			T15	1		T17	2		T272	1
auto[BaudRate115200]	freqs[48]	128	1			T61	3		T323	3		T127	13
auto[BaudRate115200]	freqs[50]	60	1			T123	2		T278	1		T16	7
auto[BaudRate115200]	freqs[100]	166	1			T53	2		T56	2		T47	2
auto[BaudRate230400]	freqs[24]	192	1			T5	1		T276	1		T261	1
auto[BaudRate230400]	freqs[25]	118	1			T15	1		T96	1		T17	1
auto[BaudRate230400]	freqs[48]	92	1			T277	1		T322	2		T147	2
auto[BaudRate230400]	freqs[50]	82	1			T123	1		T16	9		T50	1
auto[BaudRate230400]	freqs[100]	134	1			T93	1		T56	1		T47	1
auto[BaudRate128Kbps]	freqs[24]	200	1			T5	2		T11	1		T276	2
auto[BaudRate128Kbps]	freqs[25]	113	1			T15	2		T316	1		T41	7
auto[BaudRate128Kbps]	freqs[48]	125	1			T323	2		T127	27		T131	1
auto[BaudRate128Kbps]	freqs[50]	78	1			T16	4		T48	1		T191	1
auto[BaudRate128Kbps]	freqs[100]	145	1			T93	1		T53	3		T56	2
auto[BaudRate256Kbps]	freqs[24]	187	1			T5	1		T11	1		T51	1
auto[BaudRate256Kbps]	freqs[25]	130	1			T15	1		T96	3		T248	5
auto[BaudRate256Kbps]	freqs[48]	125	1			T147	2		T323	1		T127	17
auto[BaudRate256Kbps]	freqs[50]	81	1			T16	10		T48	1		T50	1
auto[BaudRate256Kbps]	freqs[100]	143	1			T93	2		T56	1		T47	2
auto[BaudRate1Mbps]	freqs[24]	206	1			T5	1		T55	3		T51	1
auto[BaudRate1Mbps]	freqs[25]	139	1			T96	3		T248	3		T275	2
auto[BaudRate1Mbps]	freqs[48]	140	1			T147	1		T61	3		T323	2
auto[BaudRate1Mbps]	freqs[50]	84	1			T278	2		T16	12		T48	3
auto[BaudRate1Mbps]	freqs[100]	166	1			T93	2		T53	1		T21	2
auto[BaudRate1p5Mbps]	freqs[25]	84	1			T96	1		T275	3		T316	1
auto[BaudRate1p5Mbps]	freqs[48]	118	1			T277	1		T147	1		T61	1
auto[BaudRate1p5Mbps]	freqs[50]	104	1			T278	3		T16	15		T48	2
auto[BaudRate1p5Mbps]	freqs[100]	157	1			T53	2		T56	2		T47	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded