Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.91	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	12	118	90.77

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	12	118	90.77	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	30865134	1			T1	5		T2	7		T3	65
all_levels[1]	202109	1			T3	4		T5	175		T8	52
all_levels[2]	2210	1			T3	4		T9	1		T12	1
all_levels[3]	976	1			T3	3		T11	1		T12	4
all_levels[4]	658	1			T3	3		T10	1		T11	2
all_levels[5]	499	1			T3	1		T9	2		T39	1
all_levels[6]	393	1			T9	2		T12	1		T39	2
all_levels[7]	320	1			T3	1		T14	1		T96	1
all_levels[8]	281	1			T3	1		T19	1		T51	4
all_levels[9]	268	1			T3	2		T12	2		T15	1
all_levels[10]	241	1			T3	2		T15	1		T123	1
all_levels[11]	186	1			T3	1		T10	1		T13	1
all_levels[12]	146	1			T10	1		T20	1		T52	1
all_levels[13]	147	1			T3	1		T56	1		T20	1
all_levels[14]	141	1			T3	1		T13	1		T20	2
all_levels[15]	102	1			T3	1		T39	1		T47	3
all_levels[16]	103	1			T3	1		T135	1		T136	2
all_levels[17]	94	1			T10	1		T13	1		T47	1
all_levels[18]	85	1			T3	1		T123	1		T137	2
all_levels[19]	94	1			T3	2		T47	1		T138	1
all_levels[20]	72	1			T15	1		T51	1		T52	1
all_levels[21]	67	1			T20	1		T136	1		T47	1
all_levels[22]	61	1			T55	1		T52	1		T139	2
all_levels[23]	71	1			T3	1		T14	1		T47	1
all_levels[24]	47	1			T20	1		T52	1		T140	1
all_levels[25]	58	1			T3	1		T14	3		T141	1
all_levels[26]	57	1			T3	1		T14	1		T19	1
all_levels[27]	40	1			T140	2		T142	1		T124	1
all_levels[28]	54	1			T3	1		T139	1		T143	1
all_levels[29]	42	1			T4	3		T41	1		T144	1
all_levels[30]	32	1			T3	1		T141	1		T145	1
all_levels[31]	46	1			T55	2		T136	1		T146	1
all_levels[32]	38	1			T13	1		T20	1		T47	1
all_levels[33]	31	1			T55	1		T141	1		T142	2
all_levels[34]	19	1			T124	1		T147	1		T148	1
all_levels[35]	20	1			T47	1		T143	1		T59	2
all_levels[36]	12	1			T41	1		T149	1		T150	1
all_levels[37]	19	1			T151	1		T141	1		T152	1
all_levels[38]	19	1			T47	1		T52	1		T153	1
all_levels[39]	28	1			T124	1		T143	1		T66	1
all_levels[40]	17	1			T154	2		T145	1		T155	2
all_levels[41]	16	1			T41	1		T156	5		T129	1
all_levels[42]	20	1			T10	2		T157	1		T155	1
all_levels[43]	23	1			T151	1		T158	1		T159	1
all_levels[44]	8	1			T55	1		T151	1		T160	1
all_levels[45]	15	1			T161	1		T126	1		T162	1
all_levels[46]	13	1			T48	1		T124	1		T163	1
all_levels[47]	13	1			T3	1		T19	2		T164	1
all_levels[48]	22	1			T55	1		T145	1		T117	1
all_levels[49]	9	1			T154	1		T165	1		T143	1
all_levels[50]	17	1			T164	2		T166	2		T163	1
all_levels[51]	8	1			T3	1		T40	1		T167	1
all_levels[52]	13	1			T163	1		T131	1		T168	1
all_levels[53]	11	1			T124	1		T169	1		T170	1
all_levels[54]	13	1			T169	1		T148	1		T171	1
all_levels[55]	8	1			T15	1		T58	1		T172	1
all_levels[56]	3	1			T173	1		T174	1		T175	1
all_levels[57]	7	1			T48	1		T176	2		T155	1
all_levels[58]	13	1			T21	1		T155	1		T131	1
all_levels[59]	8	1			T13	1		T165	1		T144	1
all_levels[60]	10	1			T166	1		T177	1		T178	1
all_levels[61]	7	1			T179	1		T180	1		T181	1
all_levels[62]	3	1			T182	1		T183	1		T184	1
all_levels[63]	15	1			T55	1		T185	1		T186	4
all_levels[64]	123	1			T13	4		T15	2		T56	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31071094

1

T3

101

T4

13

T5

175299

auto[1]

4341

1

T1

5

T2

7

T4

4

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	12	118	90.77	12

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[20]]	[auto[1]]	0	1	1
[all_levels[34]]	[auto[1]]	0	1	1
[all_levels[36] , all_levels[37] , all_levels[38]]	[auto[1]]	--	--	3
[all_levels[44]]	[auto[1]]	0	1	1
[all_levels[51]]	[auto[1]]	0	1	1
[all_levels[53]]	[auto[1]]	0	1	1
[all_levels[55] , all_levels[56]]	[auto[1]]	--	--	2
[all_levels[59]]	[auto[1]]	0	1	1
[all_levels[62]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	30861257	1			T3	65		T4	12		T5	175124
all_levels[0]	auto[1]	3877	1			T1	5		T2	7		T4	2
all_levels[1]	auto[0]	202031	1			T3	4		T5	175		T8	52
all_levels[1]	auto[1]	78	1			T146	1		T48	2		T51	2
all_levels[2]	auto[0]	2189	1			T3	4		T9	1		T12	1
all_levels[2]	auto[1]	21	1			T47	1		T187	2		T41	2
all_levels[3]	auto[0]	952	1			T3	3		T11	1		T12	2
all_levels[3]	auto[1]	24	1			T12	2		T139	1		T153	1
all_levels[4]	auto[0]	645	1			T3	3		T10	1		T11	2
all_levels[4]	auto[1]	13	1			T94	1		T188	1		T189	1
all_levels[5]	auto[0]	485	1			T3	1		T9	2		T39	1
all_levels[5]	auto[1]	14	1			T137	1		T190	1		T161	1
all_levels[6]	auto[0]	367	1			T9	2		T12	1		T39	1
all_levels[6]	auto[1]	26	1			T39	1		T191	1		T192	1
all_levels[7]	auto[0]	295	1			T3	1		T14	1		T96	1
all_levels[7]	auto[1]	25	1			T193	3		T136	1		T194	2
all_levels[8]	auto[0]	271	1			T3	1		T19	1		T51	4
all_levels[8]	auto[1]	10	1			T195	1		T196	3		T197	1
all_levels[9]	auto[0]	249	1			T3	2		T12	1		T15	1
all_levels[9]	auto[1]	19	1			T12	1		T146	2		T130	1
all_levels[10]	auto[0]	217	1			T3	2		T15	1		T123	1
all_levels[10]	auto[1]	24	1			T61	3		T195	2		T188	1
all_levels[11]	auto[0]	176	1			T3	1		T10	1		T13	1
all_levels[11]	auto[1]	10	1			T39	1		T198	2		T199	1
all_levels[12]	auto[0]	144	1			T10	1		T20	1		T52	1
all_levels[12]	auto[1]	2	1			T200	1		T201	1		-	-
all_levels[13]	auto[0]	138	1			T3	1		T56	1		T20	1
all_levels[13]	auto[1]	9	1			T124	1		T157	1		T189	1
all_levels[14]	auto[0]	132	1			T3	1		T13	1		T20	2
all_levels[14]	auto[1]	9	1			T166	1		T202	1		T203	1
all_levels[15]	auto[0]	96	1			T3	1		T39	1		T47	3
all_levels[15]	auto[1]	6	1			T204	3		T128	1		T205	1
all_levels[16]	auto[0]	97	1			T3	1		T135	1		T136	1
all_levels[16]	auto[1]	6	1			T136	1		T139	1		T185	1
all_levels[17]	auto[0]	81	1			T10	1		T13	1		T47	1
all_levels[17]	auto[1]	13	1			T206	1		T207	1		T208	1
all_levels[18]	auto[0]	73	1			T3	1		T123	1		T137	1
all_levels[18]	auto[1]	12	1			T137	1		T209	2		T210	1
all_levels[19]	auto[0]	87	1			T3	2		T47	1		T138	1
all_levels[19]	auto[1]	7	1			T211	1		T212	1		T213	1
all_levels[20]	auto[0]	72	1			T15	1		T51	1		T52	1
all_levels[21]	auto[0]	61	1			T20	1		T136	1		T47	1
all_levels[21]	auto[1]	6	1			T210	1		T214	5		-	-
all_levels[22]	auto[0]	53	1			T55	1		T52	1		T139	1
all_levels[22]	auto[1]	8	1			T139	1		T202	1		T211	1
all_levels[23]	auto[0]	64	1			T3	1		T14	1		T47	1
all_levels[23]	auto[1]	7	1			T142	1		T215	1		T216	1
all_levels[24]	auto[0]	45	1			T20	1		T52	1		T140	1
all_levels[24]	auto[1]	2	1			T217	2		-	-		-	-
all_levels[25]	auto[0]	51	1			T3	1		T14	1		T141	1
all_levels[25]	auto[1]	7	1			T14	2		T140	1		T215	1
all_levels[26]	auto[0]	51	1			T3	1		T14	1		T19	1
all_levels[26]	auto[1]	6	1			T147	1		T165	1		T155	1
all_levels[27]	auto[0]	37	1			T140	2		T142	1		T124	1
all_levels[27]	auto[1]	3	1			T218	1		T216	2		-	-
all_levels[28]	auto[0]	45	1			T3	1		T139	1		T143	1
all_levels[28]	auto[1]	9	1			T219	2		T220	2		T221	3
all_levels[29]	auto[0]	37	1			T4	1		T41	1		T144	1
all_levels[29]	auto[1]	5	1			T4	2		T200	2		T203	1
all_levels[30]	auto[0]	30	1			T3	1		T141	1		T145	1
all_levels[30]	auto[1]	2	1			T129	1		T222	1		-	-
all_levels[31]	auto[0]	41	1			T55	1		T136	1		T146	1
all_levels[31]	auto[1]	5	1			T55	1		T211	1		T223	1
all_levels[32]	auto[0]	31	1			T13	1		T20	1		T47	1
all_levels[32]	auto[1]	7	1			T206	2		T224	1		T225	2
all_levels[33]	auto[0]	29	1			T55	1		T141	1		T142	2
all_levels[33]	auto[1]	2	1			T226	2		-	-		-	-
all_levels[34]	auto[0]	19	1			T124	1		T147	1		T148	1
all_levels[35]	auto[0]	18	1			T47	1		T143	1		T59	2
all_levels[35]	auto[1]	2	1			T227	1		T228	1		-	-
all_levels[36]	auto[0]	12	1			T41	1		T149	1		T150	1
all_levels[37]	auto[0]	19	1			T151	1		T141	1		T152	1
all_levels[38]	auto[0]	19	1			T47	1		T52	1		T153	1
all_levels[39]	auto[0]	27	1			T124	1		T143	1		T66	1
all_levels[39]	auto[1]	1	1			T229	1		-	-		-	-
all_levels[40]	auto[0]	16	1			T154	1		T145	1		T155	2
all_levels[40]	auto[1]	1	1			T154	1		-	-		-	-
all_levels[41]	auto[0]	11	1			T41	1		T156	1		T129	1
all_levels[41]	auto[1]	5	1			T156	4		T230	1		-	-
all_levels[42]	auto[0]	15	1			T10	1		T157	1		T155	1
all_levels[42]	auto[1]	5	1			T10	1		T231	2		T232	2
all_levels[43]	auto[0]	22	1			T151	1		T158	1		T159	1
all_levels[43]	auto[1]	1	1			T233	1		-	-		-	-
all_levels[44]	auto[0]	8	1			T55	1		T151	1		T160	1
all_levels[45]	auto[0]	14	1			T161	1		T126	1		T162	1
all_levels[45]	auto[1]	1	1			T234	1		-	-		-	-
all_levels[46]	auto[0]	12	1			T48	1		T124	1		T163	1
all_levels[46]	auto[1]	1	1			T235	1		-	-		-	-
all_levels[47]	auto[0]	11	1			T3	1		T19	1		T164	1
all_levels[47]	auto[1]	2	1			T19	1		T228	1		-	-
all_levels[48]	auto[0]	20	1			T55	1		T145	1		T117	1
all_levels[48]	auto[1]	2	1			T66	1		T236	1		-	-
all_levels[49]	auto[0]	8	1			T154	1		T165	1		T143	1
all_levels[49]	auto[1]	1	1			T237	1		-	-		-	-
all_levels[50]	auto[0]	14	1			T164	1		T166	1		T163	1
all_levels[50]	auto[1]	3	1			T164	1		T166	1		T238	1
all_levels[51]	auto[0]	8	1			T3	1		T40	1		T167	1
all_levels[52]	auto[0]	12	1			T163	1		T131	1		T168	1
all_levels[52]	auto[1]	1	1			T239	1		-	-		-	-
all_levels[53]	auto[0]	11	1			T124	1		T169	1		T170	1
all_levels[54]	auto[0]	9	1			T169	1		T148	1		T171	1
all_levels[54]	auto[1]	4	1			T240	1		T241	3		-	-
all_levels[55]	auto[0]	8	1			T15	1		T58	1		T172	1
all_levels[56]	auto[0]	3	1			T173	1		T174	1		T175	1
all_levels[57]	auto[0]	6	1			T48	1		T176	1		T155	1
all_levels[57]	auto[1]	1	1			T176	1		-	-		-	-
all_levels[58]	auto[0]	11	1			T21	1		T155	1		T131	1
all_levels[58]	auto[1]	2	1			T71	2		-	-		-	-
all_levels[59]	auto[0]	8	1			T13	1		T165	1		T144	1
all_levels[60]	auto[0]	6	1			T166	1		T177	1		T178	1
all_levels[60]	auto[1]	4	1			T242	4		-	-		-	-
all_levels[61]	auto[0]	5	1			T179	1		T180	1		T181	1
all_levels[61]	auto[1]	2	1			T234	2		-	-		-	-
all_levels[62]	auto[0]	3	1			T182	1		T183	1		T184	1
all_levels[63]	auto[0]	8	1			T55	1		T185	1		T186	1
all_levels[63]	auto[1]	7	1			T186	3		T243	1		T244	3
all_levels[64]	auto[0]	102	1			T13	4		T15	2		T56	1
all_levels[64]	auto[1]	21	1			T165	3		T245	1		T163	2