Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	106648	1			T1	1		T2	1		T3	45
all_pins[1]	106648	1			T1	1		T2	1		T3	45
all_pins[2]	106648	1			T1	1		T2	1		T3	45
all_pins[3]	106648	1			T1	1		T2	1		T3	45
all_pins[4]	106648	1			T1	1		T2	1		T3	45
all_pins[5]	106648	1			T1	1		T2	1		T3	45
all_pins[6]	106648	1			T1	1		T2	1		T3	45
all_pins[7]	106648	1			T1	1		T2	1		T3	45
all_pins[8]	106648	1			T1	1		T2	1		T3	45

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	917111	1			T1	8		T2	8		T3	383
values[0x1]	42721	1			T1	1		T2	1		T3	22
transitions[0x0=>0x1]	34433	1			T3	20		T4	6		T5	258
transitions[0x1=>0x0]	34239	1			T1	1		T2	1		T3	19

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	87334	1			T1	1		T2	1		T3	28
all_pins[0]	values[0x1]	19314	1			T3	17		T4	3		T5	255
all_pins[0]	transitions[0x0=>0x1]	18940	1			T3	17		T4	3		T5	255
all_pins[0]	transitions[0x1=>0x0]	1156	1			T4	1		T53	1		T15	2
all_pins[1]	values[0x0]	105118	1			T1	1		T2	1		T3	45
all_pins[1]	values[0x1]	1530	1			T4	1		T53	1		T15	2
all_pins[1]	transitions[0x0=>0x1]	1431	1			T4	1		T53	1		T15	2
all_pins[1]	transitions[0x1=>0x0]	2206	1			T3	3		T4	2		T5	1
all_pins[2]	values[0x0]	104343	1			T1	1		T2	1		T3	42
all_pins[2]	values[0x1]	2305	1			T3	3		T4	2		T5	1
all_pins[2]	transitions[0x0=>0x1]	2224	1			T3	3		T4	2		T5	1
all_pins[2]	transitions[0x1=>0x0]	242	1			T12	1		T15	2		T56	1
all_pins[3]	values[0x0]	106325	1			T1	1		T2	1		T3	45
all_pins[3]	values[0x1]	323	1			T12	1		T14	1		T15	2
all_pins[3]	transitions[0x0=>0x1]	262	1			T12	1		T14	1		T15	2
all_pins[3]	transitions[0x1=>0x0]	319	1			T16	14		T17	5		T94	1
all_pins[4]	values[0x0]	106268	1			T1	1		T2	1		T3	45
all_pins[4]	values[0x1]	380	1			T16	14		T17	5		T94	2
all_pins[4]	transitions[0x0=>0x1]	303	1			T16	12		T17	4		T94	2
all_pins[4]	transitions[0x1=>0x0]	146	1			T18	1		T94	2		T41	1
all_pins[5]	values[0x0]	106425	1			T1	1		T2	1		T3	45
all_pins[5]	values[0x1]	223	1			T16	2		T17	1		T18	1
all_pins[5]	transitions[0x0=>0x1]	179	1			T16	2		T17	1		T18	1
all_pins[5]	transitions[0x1=>0x0]	763	1			T13	7		T19	18		T55	2
all_pins[6]	values[0x0]	105841	1			T1	1		T2	1		T3	45
all_pins[6]	values[0x1]	807	1			T13	7		T19	18		T55	2
all_pins[6]	transitions[0x0=>0x1]	762	1			T13	7		T19	18		T55	2
all_pins[6]	transitions[0x1=>0x0]	272	1			T20	3		T16	5		T138	7
all_pins[7]	values[0x0]	106331	1			T1	1		T2	1		T3	45
all_pins[7]	values[0x1]	317	1			T20	3		T16	5		T21	4
all_pins[7]	transitions[0x0=>0x1]	188	1			T20	3		T16	1		T21	4
all_pins[7]	transitions[0x1=>0x0]	17393	1			T1	1		T2	1		T3	2
all_pins[8]	values[0x0]	89126	1			T3	43		T4	8		T5	351
all_pins[8]	values[0x1]	17522	1			T1	1		T2	1		T3	2
all_pins[8]	transitions[0x0=>0x1]	10144	1			T5	2		T9	1		T12	2
all_pins[8]	transitions[0x1=>0x0]	11742	1			T3	14		T4	2		T5	134