Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	7691478	1			T3	20		T4	8		T5	110429
all_levels[1]	1777068	1			T3	10		T5	15107		T8	343860
all_levels[2]	590787	1			T3	3		T5	861		T8	175322
all_levels[3]	226266	1			T3	1		T4	1		T5	859
all_levels[4]	346009	1			T3	2		T4	3		T5	852
all_levels[5]	250908	1			T3	3		T5	851		T8	4288
all_levels[6]	206980	1			T5	861		T8	4296		T29	990
all_levels[7]	193633	1			T3	4		T5	861		T8	4297
all_levels[8]	257469	1			T5	862		T8	4290		T10	4
all_levels[9]	225783	1			T5	860		T8	4272		T29	1064
all_levels[10]	239332	1			T5	862		T8	4299		T11	4
all_levels[11]	323249	1			T5	856		T8	4308		T9	2
all_levels[12]	666619	1			T3	1		T5	859		T8	4280
all_levels[13]	681529	1			T5	861		T8	4132		T29	1065
all_levels[14]	282270	1			T4	3		T5	861		T8	4295
all_levels[15]	353153	1			T5	857		T8	4279		T29	1063
all_levels[16]	241968	1			T5	869		T8	4295		T9	1
all_levels[17]	231409	1			T4	2		T5	854		T8	4282
all_levels[18]	471362	1			T5	861		T8	4297		T29	1065
all_levels[19]	185124	1			T5	861		T8	4277		T9	3
all_levels[20]	243887	1			T5	861		T8	4298		T9	2
all_levels[21]	211995	1			T3	2		T5	861		T8	4265
all_levels[22]	179916	1			T5	852		T8	4255		T29	1058
all_levels[23]	236995	1			T5	853		T8	4294		T29	1061
all_levels[24]	637365	1			T3	2		T5	861		T8	4293
all_levels[25]	406444	1			T3	4		T5	856		T8	4265
all_levels[26]	305170	1			T3	6		T5	862		T8	4297
all_levels[27]	228276	1			T3	4		T5	859		T8	4274
all_levels[28]	175529	1			T3	1		T5	846		T8	4237
all_levels[29]	160977	1			T3	2		T5	864		T8	4294
all_levels[30]	161999	1			T3	4		T5	865		T8	4296
all_levels[31]	609003	1			T3	4		T5	3243		T8	9352
all_levels[32]	12075162	1			T3	28		T5	21612		T8	34731

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31071094

1

T3

101

T4

13

T5

175299

auto[1]

4020

1

T4

4

T8

1

T10

7

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	7689112	1			T3	20		T4	7		T5	110429
all_levels[0]	auto[1]	2366	1			T4	1		T10	2		T12	4
all_levels[1]	auto[0]	1776788	1			T3	10		T5	15107		T8	343860
all_levels[1]	auto[1]	280	1			T56	1		T135	2		T136	1
all_levels[2]	auto[0]	590764	1			T3	3		T5	861		T8	175321
all_levels[2]	auto[1]	23	1			T8	1		T135	1		T146	2
all_levels[3]	auto[0]	226125	1			T3	1		T4	1		T5	859
all_levels[3]	auto[1]	141	1			T16	21		T17	4		T204	3
all_levels[4]	auto[0]	345982	1			T3	2		T4	3		T5	852
all_levels[4]	auto[1]	27	1			T288	2		T147	3		T165	1
all_levels[5]	auto[0]	250873	1			T3	3		T5	851		T8	4288
all_levels[5]	auto[1]	35	1			T12	1		T278	2		T246	2
all_levels[6]	auto[0]	206952	1			T5	861		T8	4296		T29	990
all_levels[6]	auto[1]	28	1			T176	1		T128	1		T325	2
all_levels[7]	auto[0]	193564	1			T3	4		T5	861		T8	4297
all_levels[7]	auto[1]	69	1			T14	3		T269	2		T28	5
all_levels[8]	auto[0]	257440	1			T5	862		T8	4290		T10	2
all_levels[8]	auto[1]	29	1			T10	2		T139	1		T164	1
all_levels[9]	auto[0]	225771	1			T5	860		T8	4272		T29	1064
all_levels[9]	auto[1]	12	1			T270	1		T190	2		T182	1
all_levels[10]	auto[0]	239308	1			T5	862		T8	4299		T11	4
all_levels[10]	auto[1]	24	1			T15	1		T47	1		T191	2
all_levels[11]	auto[0]	323239	1			T5	856		T8	4308		T9	2
all_levels[11]	auto[1]	10	1			T56	1		T288	1		T326	1
all_levels[12]	auto[0]	666593	1			T3	1		T5	859		T8	4280
all_levels[12]	auto[1]	26	1			T191	1		T156	5		T327	1
all_levels[13]	auto[0]	681513	1			T5	861		T8	4132		T29	1065
all_levels[13]	auto[1]	16	1			T153	2		T58	1		T328	2
all_levels[14]	auto[0]	282235	1			T4	1		T5	861		T8	4295
all_levels[14]	auto[1]	35	1			T4	2		T47	1		T268	2
all_levels[15]	auto[0]	353054	1			T5	857		T8	4279		T29	1063
all_levels[15]	auto[1]	99	1			T39	2		T17	9		T329	2
all_levels[16]	auto[0]	241940	1			T5	869		T8	4295		T9	1
all_levels[16]	auto[1]	28	1			T154	4		T195	1		T313	1
all_levels[17]	auto[0]	231386	1			T4	1		T5	854		T8	4282
all_levels[17]	auto[1]	23	1			T4	1		T51	1		T329	2
all_levels[18]	auto[0]	471334	1			T5	861		T8	4297		T29	1065
all_levels[18]	auto[1]	28	1			T96	4		T94	1		T128	1
all_levels[19]	auto[0]	185106	1			T5	861		T8	4277		T9	3
all_levels[19]	auto[1]	18	1			T146	1		T48	1		T151	2
all_levels[20]	auto[0]	243862	1			T5	861		T8	4298		T9	2
all_levels[20]	auto[1]	25	1			T185	1		T264	1		T57	1
all_levels[21]	auto[0]	211973	1			T3	2		T5	861		T8	4265
all_levels[21]	auto[1]	22	1			T16	3		T155	2		T305	3
all_levels[22]	auto[0]	179902	1			T5	852		T8	4255		T29	1058
all_levels[22]	auto[1]	14	1			T249	1		T164	1		T166	1
all_levels[23]	auto[0]	236967	1			T5	853		T8	4294		T29	1061
all_levels[23]	auto[1]	28	1			T155	1		T64	1		T330	1
all_levels[24]	auto[0]	637347	1			T3	2		T5	861		T8	4293
all_levels[24]	auto[1]	18	1			T147	1		T331	2		T149	1
all_levels[25]	auto[0]	406429	1			T3	4		T5	856		T8	4265
all_levels[25]	auto[1]	15	1			T197	1		T332	1		T333	2
all_levels[26]	auto[0]	305154	1			T3	6		T5	862		T8	4297
all_levels[26]	auto[1]	16	1			T19	2		T137	1		T288	1
all_levels[27]	auto[0]	228264	1			T3	4		T5	859		T8	4274
all_levels[27]	auto[1]	12	1			T187	1		T165	1		T334	1
all_levels[28]	auto[0]	175508	1			T3	1		T5	846		T8	4237
all_levels[28]	auto[1]	21	1			T55	2		T252	2		T335	1
all_levels[29]	auto[0]	160961	1			T3	2		T5	864		T8	4294
all_levels[29]	auto[1]	16	1			T165	2		T188	1		T336	1
all_levels[30]	auto[0]	161986	1			T3	4		T5	865		T8	4296
all_levels[30]	auto[1]	13	1			T56	1		T94	1		T258	1
all_levels[31]	auto[0]	608980	1			T3	4		T5	3243		T8	9352
all_levels[31]	auto[1]	23	1			T268	4		T218	1		T337	1
all_levels[32]	auto[0]	12074682	1			T3	28		T5	21612		T8	34731
all_levels[32]	auto[1]	480	1			T10	3		T12	1		T29	1