Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	731	1			T16	4		T94	7		T95	4
all_values[1]	731	1			T16	4		T94	7		T95	4
all_values[2]	731	1			T16	4		T94	7		T95	4
all_values[3]	731	1			T16	4		T94	7		T95	4
all_values[4]	731	1			T16	4		T94	7		T95	4
all_values[5]	731	1			T16	4		T94	7		T95	4
all_values[6]	731	1			T16	4		T94	7		T95	4
all_values[7]	731	1			T16	4		T94	7		T95	4
all_values[8]	731	1			T16	4		T94	7		T95	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3501

1

T16

27

T94

32

T95

15

auto[1]

3078

1

T16

9

T94

31

T95

21

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2171

1

T16

16

T94

25

T95

12

auto[1]

4408

1

T16

20

T94

38

T95

24

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3838

1

T16

25

T94

43

T95

22

auto[1]

2741

1

T16

11

T94

20

T95

14

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	227	1			T16	1		T94	4		T95	1
all_values[0]	auto[0]	auto[1]	auto[1]	182	1			T16	1		T94	1		T95	2
all_values[0]	auto[1]	auto[0]	auto[1]	179	1			T16	2		T94	2		T41	1
all_values[0]	auto[1]	auto[1]	auto[1]	143	1			T95	1		T41	2		T42	2
all_values[1]	auto[0]	auto[0]	auto[0]	236	1			T16	3		T94	1		T95	2
all_values[1]	auto[0]	auto[1]	auto[0]	201	1			T94	5		T95	2		T42	3
all_values[1]	auto[1]	auto[0]	auto[1]	165	1			T16	1		T94	1		T41	5
all_values[1]	auto[1]	auto[1]	auto[1]	129	1			T42	1		T46	4		T127	1
all_values[2]	auto[0]	auto[0]	auto[0]	152	1			T16	1		T94	3		T41	1
all_values[2]	auto[0]	auto[0]	auto[1]	63	1			T16	1		T94	2		T41	1
all_values[2]	auto[0]	auto[1]	auto[0]	125	1			T16	1		T41	2		T46	1
all_values[2]	auto[0]	auto[1]	auto[1]	77	1			T95	2		T41	4		T128	2
all_values[2]	auto[1]	auto[0]	auto[1]	157	1			T16	1		T94	1		T95	1
all_values[2]	auto[1]	auto[1]	auto[1]	157	1			T94	1		T95	1		T41	2
all_values[3]	auto[0]	auto[0]	auto[0]	152	1			T94	2		T41	7		T42	1
all_values[3]	auto[0]	auto[0]	auto[1]	66	1			T16	1		T94	1		T41	2
all_values[3]	auto[0]	auto[1]	auto[0]	118	1			T16	1		T94	1		T41	2
all_values[3]	auto[0]	auto[1]	auto[1]	85	1			T95	1		T46	3		T127	1
all_values[3]	auto[1]	auto[0]	auto[1]	160	1			T94	2		T95	1		T41	3
all_values[3]	auto[1]	auto[1]	auto[1]	150	1			T16	2		T94	1		T95	2
all_values[4]	auto[0]	auto[0]	auto[0]	170	1			T16	2		T94	1		T41	4
all_values[4]	auto[0]	auto[0]	auto[1]	66	1			T65	2		T128	1		T127	1
all_values[4]	auto[0]	auto[1]	auto[0]	121	1			T16	2		T94	3		T95	2
all_values[4]	auto[0]	auto[1]	auto[1]	73	1			T94	1		T95	1		T41	1
all_values[4]	auto[1]	auto[0]	auto[1]	152	1			T41	4		T46	1		T65	1
all_values[4]	auto[1]	auto[1]	auto[1]	149	1			T94	2		T95	1		T41	3
all_values[5]	auto[0]	auto[0]	auto[0]	155	1			T16	1		T94	3		T95	1
all_values[5]	auto[0]	auto[0]	auto[1]	78	1			T16	1		T95	1		T41	2
all_values[5]	auto[0]	auto[1]	auto[0]	117	1			T94	2		T41	1		T46	1
all_values[5]	auto[0]	auto[1]	auto[1]	77	1			T65	1		T129	2		T119	1
all_values[5]	auto[1]	auto[0]	auto[1]	151	1			T16	2		T95	2		T41	4
all_values[5]	auto[1]	auto[1]	auto[1]	153	1			T94	2		T41	4		T46	1
all_values[6]	auto[0]	auto[0]	auto[0]	174	1			T16	3		T94	1		T95	1
all_values[6]	auto[0]	auto[0]	auto[1]	64	1			T41	1		T128	1		T127	1
all_values[6]	auto[0]	auto[1]	auto[0]	156	1			T16	1		T94	3		T95	3
all_values[6]	auto[0]	auto[1]	auto[1]	63	1			T46	2		T129	1		T130	1
all_values[6]	auto[1]	auto[0]	auto[1]	144	1			T94	2		T41	3		T46	2
all_values[6]	auto[1]	auto[1]	auto[1]	130	1			T94	1		T41	1		T42	1
all_values[7]	auto[0]	auto[0]	auto[0]	175	1			T16	1		T95	1		T41	4
all_values[7]	auto[0]	auto[0]	auto[1]	61	1			T16	1		T94	2		T95	1
all_values[7]	auto[0]	auto[1]	auto[0]	119	1			T46	3		T127	4		T131	3
all_values[7]	auto[0]	auto[1]	auto[1]	73	1			T16	1		T94	3		T41	1
all_values[7]	auto[1]	auto[0]	auto[1]	161	1			T16	1		T94	1		T95	1
all_values[7]	auto[1]	auto[1]	auto[1]	142	1			T94	1		T95	1		T41	5
all_values[8]	auto[0]	auto[0]	auto[1]	230	1			T16	2		T94	3		T95	1
all_values[8]	auto[0]	auto[1]	auto[1]	182	1			T94	1		T41	5		T42	1
all_values[8]	auto[1]	auto[0]	auto[1]	163	1			T16	2		T95	1		T41	3
all_values[8]	auto[1]	auto[1]	auto[1]	156	1			T94	3		T95	2		T41	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal