Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.10 99.10 97.65 100.00 98.38 100.00 99.50


Total test records in report: 1236
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T1033 /workspace/coverage/default/44.uart_perf.3240874899 Jun 21 04:46:29 PM PDT 24 Jun 21 04:47:01 PM PDT 24 8862560207 ps
T1034 /workspace/coverage/default/229.uart_fifo_reset.1151294651 Jun 21 04:47:30 PM PDT 24 Jun 21 04:48:07 PM PDT 24 21638712598 ps
T1035 /workspace/coverage/default/0.uart_perf.722775495 Jun 21 04:44:19 PM PDT 24 Jun 21 04:57:04 PM PDT 24 17686877632 ps
T1036 /workspace/coverage/default/26.uart_rx_parity_err.3651585186 Jun 21 04:45:57 PM PDT 24 Jun 21 04:47:30 PM PDT 24 115085340475 ps
T1037 /workspace/coverage/default/115.uart_fifo_reset.22347683 Jun 21 04:47:28 PM PDT 24 Jun 21 04:48:52 PM PDT 24 326866841805 ps
T1038 /workspace/coverage/default/12.uart_loopback.2989492746 Jun 21 04:44:52 PM PDT 24 Jun 21 04:45:01 PM PDT 24 10403002787 ps
T1039 /workspace/coverage/default/37.uart_rx_start_bit_filter.4095280951 Jun 21 04:46:05 PM PDT 24 Jun 21 04:46:15 PM PDT 24 3364156811 ps
T1040 /workspace/coverage/default/39.uart_smoke.1722728169 Jun 21 04:46:08 PM PDT 24 Jun 21 04:46:16 PM PDT 24 585531713 ps
T1041 /workspace/coverage/default/13.uart_tx_rx.1096036120 Jun 21 04:44:50 PM PDT 24 Jun 21 04:46:17 PM PDT 24 74550156349 ps
T1042 /workspace/coverage/default/32.uart_rx_oversample.3202136887 Jun 21 04:46:04 PM PDT 24 Jun 21 04:47:06 PM PDT 24 6286994297 ps
T234 /workspace/coverage/default/175.uart_fifo_reset.3076583035 Jun 21 04:47:26 PM PDT 24 Jun 21 04:48:28 PM PDT 24 203879839287 ps
T1043 /workspace/coverage/default/11.uart_fifo_full.3208543046 Jun 21 04:44:54 PM PDT 24 Jun 21 04:45:28 PM PDT 24 310660621839 ps
T1044 /workspace/coverage/default/4.uart_intr.3209260976 Jun 21 04:44:29 PM PDT 24 Jun 21 04:44:43 PM PDT 24 13263076755 ps
T1045 /workspace/coverage/default/32.uart_smoke.3178439723 Jun 21 04:45:56 PM PDT 24 Jun 21 04:46:03 PM PDT 24 430132857 ps
T1046 /workspace/coverage/default/247.uart_fifo_reset.4139843449 Jun 21 04:47:37 PM PDT 24 Jun 21 04:48:10 PM PDT 24 71166111237 ps
T1047 /workspace/coverage/default/236.uart_fifo_reset.3181140386 Jun 21 04:47:28 PM PDT 24 Jun 21 04:48:52 PM PDT 24 58773937354 ps
T1048 /workspace/coverage/default/116.uart_fifo_reset.1137267048 Jun 21 04:47:25 PM PDT 24 Jun 21 04:47:42 PM PDT 24 4582336390 ps
T1049 /workspace/coverage/default/17.uart_perf.2780709057 Jun 21 04:45:03 PM PDT 24 Jun 21 04:47:58 PM PDT 24 22032892663 ps
T1050 /workspace/coverage/default/19.uart_fifo_overflow.2404369885 Jun 21 04:45:11 PM PDT 24 Jun 21 04:46:21 PM PDT 24 93509387278 ps
T1051 /workspace/coverage/default/49.uart_rx_start_bit_filter.4247376403 Jun 21 04:47:24 PM PDT 24 Jun 21 04:47:37 PM PDT 24 30674191794 ps
T1052 /workspace/coverage/default/37.uart_tx_rx.1956443202 Jun 21 04:46:01 PM PDT 24 Jun 21 04:46:27 PM PDT 24 61203942730 ps
T1053 /workspace/coverage/default/22.uart_stress_all.2339367401 Jun 21 04:45:40 PM PDT 24 Jun 21 04:54:50 PM PDT 24 126274806222 ps
T1054 /workspace/coverage/default/8.uart_stress_all_with_rand_reset.1563096002 Jun 21 04:44:39 PM PDT 24 Jun 21 04:48:25 PM PDT 24 199817177782 ps
T1055 /workspace/coverage/default/18.uart_perf.1148830890 Jun 21 04:45:08 PM PDT 24 Jun 21 04:48:47 PM PDT 24 19382264930 ps
T1056 /workspace/coverage/default/165.uart_fifo_reset.1053950982 Jun 21 04:47:28 PM PDT 24 Jun 21 04:51:42 PM PDT 24 87916413705 ps
T1057 /workspace/coverage/default/22.uart_rx_parity_err.2451288273 Jun 21 04:45:12 PM PDT 24 Jun 21 04:48:48 PM PDT 24 109312714528 ps
T1058 /workspace/coverage/default/40.uart_tx_rx.1190742828 Jun 21 04:46:11 PM PDT 24 Jun 21 04:46:39 PM PDT 24 61003707208 ps
T1059 /workspace/coverage/default/43.uart_fifo_full.2618947501 Jun 21 04:46:31 PM PDT 24 Jun 21 04:48:38 PM PDT 24 153121278140 ps
T1060 /workspace/coverage/default/25.uart_rx_parity_err.2975574249 Jun 21 04:45:42 PM PDT 24 Jun 21 04:47:55 PM PDT 24 141988522998 ps
T1061 /workspace/coverage/default/37.uart_smoke.116927448 Jun 21 04:45:58 PM PDT 24 Jun 21 04:46:05 PM PDT 24 681201040 ps
T1062 /workspace/coverage/default/81.uart_stress_all_with_rand_reset.3029266627 Jun 21 04:47:27 PM PDT 24 Jun 21 04:50:55 PM PDT 24 72479299481 ps
T1063 /workspace/coverage/default/9.uart_alert_test.3791359587 Jun 21 04:45:00 PM PDT 24 Jun 21 04:45:03 PM PDT 24 13220371 ps
T1064 /workspace/coverage/default/83.uart_fifo_reset.3112437307 Jun 21 04:47:28 PM PDT 24 Jun 21 04:50:05 PM PDT 24 152954968146 ps
T184 /workspace/coverage/default/40.uart_rx_parity_err.1401046868 Jun 21 04:46:06 PM PDT 24 Jun 21 04:47:11 PM PDT 24 36790505868 ps
T1065 /workspace/coverage/default/16.uart_alert_test.13569441 Jun 21 04:45:07 PM PDT 24 Jun 21 04:45:09 PM PDT 24 81282041 ps
T1066 /workspace/coverage/default/189.uart_fifo_reset.2695574111 Jun 21 04:47:21 PM PDT 24 Jun 21 04:48:42 PM PDT 24 199470632932 ps
T1067 /workspace/coverage/default/11.uart_fifo_overflow.3834577936 Jun 21 04:44:43 PM PDT 24 Jun 21 04:44:55 PM PDT 24 104726997952 ps
T1068 /workspace/coverage/default/49.uart_rx_oversample.977408228 Jun 21 04:47:14 PM PDT 24 Jun 21 04:47:38 PM PDT 24 5405227146 ps
T1069 /workspace/coverage/default/3.uart_tx_rx.580629760 Jun 21 04:44:14 PM PDT 24 Jun 21 04:44:54 PM PDT 24 25854993508 ps
T1070 /workspace/coverage/default/88.uart_fifo_reset.3985424302 Jun 21 04:47:29 PM PDT 24 Jun 21 04:50:33 PM PDT 24 109480487828 ps
T1071 /workspace/coverage/default/112.uart_fifo_reset.160146967 Jun 21 04:47:29 PM PDT 24 Jun 21 04:49:34 PM PDT 24 195285348368 ps
T1072 /workspace/coverage/default/18.uart_rx_start_bit_filter.4207680619 Jun 21 04:45:15 PM PDT 24 Jun 21 04:45:28 PM PDT 24 46918385299 ps
T1073 /workspace/coverage/default/262.uart_fifo_reset.855934478 Jun 21 04:47:45 PM PDT 24 Jun 21 04:48:04 PM PDT 24 20316741819 ps
T1074 /workspace/coverage/default/10.uart_intr.3320322129 Jun 21 04:44:43 PM PDT 24 Jun 21 04:45:12 PM PDT 24 29304806489 ps
T1075 /workspace/coverage/default/60.uart_stress_all_with_rand_reset.726425682 Jun 21 04:47:14 PM PDT 24 Jun 21 04:50:34 PM PDT 24 43718205155 ps
T1076 /workspace/coverage/default/28.uart_perf.503917167 Jun 21 04:45:57 PM PDT 24 Jun 21 04:53:47 PM PDT 24 16891140595 ps
T1077 /workspace/coverage/default/14.uart_tx_rx.3500389723 Jun 21 04:44:56 PM PDT 24 Jun 21 04:45:11 PM PDT 24 7611062897 ps
T1078 /workspace/coverage/default/289.uart_fifo_reset.2789606027 Jun 21 04:47:59 PM PDT 24 Jun 21 04:48:08 PM PDT 24 17616421925 ps
T1079 /workspace/coverage/default/41.uart_fifo_overflow.975197203 Jun 21 04:46:12 PM PDT 24 Jun 21 04:46:53 PM PDT 24 71604157905 ps
T1080 /workspace/coverage/default/5.uart_fifo_overflow.461466479 Jun 21 04:44:27 PM PDT 24 Jun 21 04:45:11 PM PDT 24 54203469877 ps
T1081 /workspace/coverage/default/7.uart_fifo_full.3534080774 Jun 21 04:44:30 PM PDT 24 Jun 21 04:47:19 PM PDT 24 116270874262 ps
T1082 /workspace/coverage/default/9.uart_rx_parity_err.24159181 Jun 21 04:44:41 PM PDT 24 Jun 21 04:45:02 PM PDT 24 28986953538 ps
T1083 /workspace/coverage/default/14.uart_perf.40578590 Jun 21 04:44:59 PM PDT 24 Jun 21 05:06:52 PM PDT 24 21522603653 ps
T1084 /workspace/coverage/default/71.uart_stress_all_with_rand_reset.3587451605 Jun 21 04:47:22 PM PDT 24 Jun 21 05:04:44 PM PDT 24 81703228708 ps
T1085 /workspace/coverage/default/6.uart_fifo_full.123041195 Jun 21 04:44:50 PM PDT 24 Jun 21 04:46:10 PM PDT 24 69305135787 ps
T1086 /workspace/coverage/default/272.uart_fifo_reset.2285675113 Jun 21 04:47:58 PM PDT 24 Jun 21 04:48:13 PM PDT 24 61464658652 ps
T1087 /workspace/coverage/default/60.uart_fifo_reset.576279727 Jun 21 04:47:20 PM PDT 24 Jun 21 04:48:02 PM PDT 24 106010676773 ps
T1088 /workspace/coverage/default/256.uart_fifo_reset.3912894582 Jun 21 04:47:48 PM PDT 24 Jun 21 04:49:01 PM PDT 24 163330486215 ps
T1089 /workspace/coverage/default/30.uart_rx_start_bit_filter.3884797564 Jun 21 04:46:05 PM PDT 24 Jun 21 04:46:17 PM PDT 24 7248366525 ps
T1090 /workspace/coverage/default/15.uart_long_xfer_wo_dly.2119133589 Jun 21 04:45:03 PM PDT 24 Jun 21 05:08:03 PM PDT 24 129927197133 ps
T1091 /workspace/coverage/default/29.uart_rx_parity_err.1763946917 Jun 21 04:45:55 PM PDT 24 Jun 21 04:47:30 PM PDT 24 46457087707 ps
T1092 /workspace/coverage/default/34.uart_long_xfer_wo_dly.3646111232 Jun 21 04:46:06 PM PDT 24 Jun 21 04:56:31 PM PDT 24 88010517355 ps
T1093 /workspace/coverage/default/37.uart_fifo_full.2960915941 Jun 21 04:45:59 PM PDT 24 Jun 21 04:47:15 PM PDT 24 40842674431 ps
T1094 /workspace/coverage/default/66.uart_fifo_reset.1976985808 Jun 21 04:47:28 PM PDT 24 Jun 21 04:47:47 PM PDT 24 41345491512 ps
T1095 /workspace/coverage/default/17.uart_tx_rx.3562813997 Jun 21 04:45:03 PM PDT 24 Jun 21 04:45:38 PM PDT 24 19080869208 ps
T1096 /workspace/coverage/default/46.uart_long_xfer_wo_dly.3085527938 Jun 21 04:47:05 PM PDT 24 Jun 21 04:49:13 PM PDT 24 197329810235 ps
T1097 /workspace/coverage/default/39.uart_rx_start_bit_filter.1415522542 Jun 21 04:46:14 PM PDT 24 Jun 21 04:46:30 PM PDT 24 46828248063 ps
T1098 /workspace/coverage/default/14.uart_rx_parity_err.2252289240 Jun 21 04:45:10 PM PDT 24 Jun 21 04:47:40 PM PDT 24 84458186606 ps
T1099 /workspace/coverage/default/271.uart_fifo_reset.2990158360 Jun 21 04:47:57 PM PDT 24 Jun 21 04:49:14 PM PDT 24 156637933672 ps
T1100 /workspace/coverage/default/12.uart_alert_test.2857593548 Jun 21 04:44:50 PM PDT 24 Jun 21 04:44:55 PM PDT 24 15992790 ps
T1101 /workspace/coverage/default/26.uart_intr.3831745350 Jun 21 04:45:53 PM PDT 24 Jun 21 04:46:03 PM PDT 24 19773919749 ps
T1102 /workspace/coverage/cover_reg_top/0.uart_tl_errors.3385711412 Jun 21 04:42:59 PM PDT 24 Jun 21 04:43:07 PM PDT 24 82773445 ps
T82 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3968629985 Jun 21 04:43:07 PM PDT 24 Jun 21 04:43:11 PM PDT 24 58420760 ps
T1103 /workspace/coverage/cover_reg_top/31.uart_intr_test.2955773923 Jun 21 04:43:26 PM PDT 24 Jun 21 04:43:33 PM PDT 24 10940716 ps
T1104 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.333891747 Jun 21 04:43:04 PM PDT 24 Jun 21 04:43:07 PM PDT 24 40643860 ps
T1105 /workspace/coverage/cover_reg_top/48.uart_intr_test.4196038117 Jun 21 04:43:16 PM PDT 24 Jun 21 04:43:20 PM PDT 24 18865453 ps
T83 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2719966311 Jun 21 04:43:20 PM PDT 24 Jun 21 04:43:25 PM PDT 24 49914515 ps
T1106 /workspace/coverage/cover_reg_top/22.uart_intr_test.2299984888 Jun 21 04:43:20 PM PDT 24 Jun 21 04:43:24 PM PDT 24 13276871 ps
T1107 /workspace/coverage/cover_reg_top/19.uart_tl_errors.1367991804 Jun 21 04:43:27 PM PDT 24 Jun 21 04:43:34 PM PDT 24 126477865 ps
T1108 /workspace/coverage/cover_reg_top/36.uart_intr_test.1128582414 Jun 21 04:43:25 PM PDT 24 Jun 21 04:43:31 PM PDT 24 49626339 ps
T1109 /workspace/coverage/cover_reg_top/20.uart_intr_test.384034759 Jun 21 04:43:16 PM PDT 24 Jun 21 04:43:21 PM PDT 24 11556130 ps
T1110 /workspace/coverage/cover_reg_top/18.uart_intr_test.323971872 Jun 21 04:43:05 PM PDT 24 Jun 21 04:43:07 PM PDT 24 36304864 ps
T1111 /workspace/coverage/cover_reg_top/43.uart_intr_test.3302839853 Jun 21 04:43:07 PM PDT 24 Jun 21 04:43:10 PM PDT 24 11849628 ps
T1112 /workspace/coverage/cover_reg_top/23.uart_intr_test.3669781817 Jun 21 04:43:18 PM PDT 24 Jun 21 04:43:22 PM PDT 24 15876811 ps
T1113 /workspace/coverage/cover_reg_top/30.uart_intr_test.1913801492 Jun 21 04:43:07 PM PDT 24 Jun 21 04:43:11 PM PDT 24 22283080 ps
T84 /workspace/coverage/cover_reg_top/18.uart_csr_rw.741408537 Jun 21 04:43:14 PM PDT 24 Jun 21 04:43:19 PM PDT 24 24664168 ps
T85 /workspace/coverage/cover_reg_top/4.uart_csr_rw.1283230949 Jun 21 04:42:50 PM PDT 24 Jun 21 04:42:53 PM PDT 24 40030300 ps
T1114 /workspace/coverage/cover_reg_top/12.uart_intr_test.4107114813 Jun 21 04:43:17 PM PDT 24 Jun 21 04:43:21 PM PDT 24 12666179 ps
T1115 /workspace/coverage/cover_reg_top/7.uart_intr_test.2469543005 Jun 21 04:42:50 PM PDT 24 Jun 21 04:42:53 PM PDT 24 76174970 ps
T1116 /workspace/coverage/cover_reg_top/8.uart_intr_test.742987708 Jun 21 04:42:58 PM PDT 24 Jun 21 04:43:00 PM PDT 24 32922394 ps
T98 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1302790765 Jun 21 04:43:05 PM PDT 24 Jun 21 04:43:09 PM PDT 24 314593314 ps
T1117 /workspace/coverage/cover_reg_top/34.uart_intr_test.707783146 Jun 21 04:43:13 PM PDT 24 Jun 21 04:43:18 PM PDT 24 17995197 ps
T1118 /workspace/coverage/cover_reg_top/44.uart_intr_test.71483556 Jun 21 04:43:10 PM PDT 24 Jun 21 04:43:14 PM PDT 24 42966886 ps
T74 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2756661598 Jun 21 04:42:48 PM PDT 24 Jun 21 04:42:52 PM PDT 24 314319144 ps
T1119 /workspace/coverage/cover_reg_top/6.uart_tl_errors.2297007272 Jun 21 04:42:46 PM PDT 24 Jun 21 04:42:51 PM PDT 24 46173674 ps
T99 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3593204255 Jun 21 04:43:15 PM PDT 24 Jun 21 04:43:21 PM PDT 24 626534607 ps
T100 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1106534018 Jun 21 04:43:04 PM PDT 24 Jun 21 04:43:07 PM PDT 24 68039782 ps
T86 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3181465827 Jun 21 04:43:10 PM PDT 24 Jun 21 04:43:15 PM PDT 24 65074881 ps
T87 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.1020376029 Jun 21 04:42:59 PM PDT 24 Jun 21 04:43:03 PM PDT 24 20170235 ps
T1120 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.465597650 Jun 21 04:43:00 PM PDT 24 Jun 21 04:43:03 PM PDT 24 135874803 ps
T1121 /workspace/coverage/cover_reg_top/49.uart_intr_test.3433889169 Jun 21 04:43:05 PM PDT 24 Jun 21 04:43:08 PM PDT 24 13000528 ps
T102 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.3725608934 Jun 21 04:42:33 PM PDT 24 Jun 21 04:42:35 PM PDT 24 188918549 ps
T88 /workspace/coverage/cover_reg_top/15.uart_csr_rw.402645798 Jun 21 04:43:13 PM PDT 24 Jun 21 04:43:18 PM PDT 24 18833077 ps
T89 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.2035092078 Jun 21 04:42:57 PM PDT 24 Jun 21 04:42:59 PM PDT 24 73202204 ps
T1122 /workspace/coverage/cover_reg_top/18.uart_tl_errors.1495873094 Jun 21 04:43:16 PM PDT 24 Jun 21 04:43:22 PM PDT 24 93983450 ps
T90 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2202639457 Jun 21 04:43:19 PM PDT 24 Jun 21 04:43:23 PM PDT 24 67090318 ps
T1123 /workspace/coverage/cover_reg_top/28.uart_intr_test.3762457245 Jun 21 04:43:07 PM PDT 24 Jun 21 04:43:11 PM PDT 24 20200707 ps
T1124 /workspace/coverage/cover_reg_top/1.uart_intr_test.3249370012 Jun 21 04:42:56 PM PDT 24 Jun 21 04:42:57 PM PDT 24 17524403 ps
T1125 /workspace/coverage/cover_reg_top/15.uart_intr_test.3483323246 Jun 21 04:43:04 PM PDT 24 Jun 21 04:43:07 PM PDT 24 11806531 ps
T1126 /workspace/coverage/cover_reg_top/39.uart_intr_test.2106234096 Jun 21 04:43:29 PM PDT 24 Jun 21 04:43:34 PM PDT 24 14717598 ps
T91 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3283129995 Jun 21 04:42:43 PM PDT 24 Jun 21 04:42:45 PM PDT 24 52865166 ps
T79 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.151599670 Jun 21 04:42:47 PM PDT 24 Jun 21 04:42:50 PM PDT 24 15185332 ps
T1127 /workspace/coverage/cover_reg_top/3.uart_intr_test.1343244439 Jun 21 04:42:51 PM PDT 24 Jun 21 04:42:54 PM PDT 24 14460621 ps
T1128 /workspace/coverage/cover_reg_top/17.uart_intr_test.3179897538 Jun 21 04:43:24 PM PDT 24 Jun 21 04:43:29 PM PDT 24 41441617 ps
T1129 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2524631909 Jun 21 04:42:37 PM PDT 24 Jun 21 04:42:39 PM PDT 24 22043070 ps
T1130 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.3399861881 Jun 21 04:43:15 PM PDT 24 Jun 21 04:43:20 PM PDT 24 284360163 ps
T1131 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3813314335 Jun 21 04:43:07 PM PDT 24 Jun 21 04:43:11 PM PDT 24 88251940 ps
T1132 /workspace/coverage/cover_reg_top/7.uart_tl_errors.983050275 Jun 21 04:42:52 PM PDT 24 Jun 21 04:42:56 PM PDT 24 110639632 ps
T1133 /workspace/coverage/cover_reg_top/5.uart_csr_rw.234357233 Jun 21 04:42:44 PM PDT 24 Jun 21 04:42:46 PM PDT 24 41292387 ps
T1134 /workspace/coverage/cover_reg_top/17.uart_csr_rw.857770873 Jun 21 04:43:05 PM PDT 24 Jun 21 04:43:07 PM PDT 24 29898512 ps
T1135 /workspace/coverage/cover_reg_top/33.uart_intr_test.22741742 Jun 21 04:43:26 PM PDT 24 Jun 21 04:43:32 PM PDT 24 195076907 ps
T1136 /workspace/coverage/cover_reg_top/5.uart_intr_test.275518066 Jun 21 04:42:59 PM PDT 24 Jun 21 04:43:02 PM PDT 24 16864428 ps
T1137 /workspace/coverage/cover_reg_top/12.uart_tl_errors.100750649 Jun 21 04:43:15 PM PDT 24 Jun 21 04:43:22 PM PDT 24 49961621 ps
T1138 /workspace/coverage/cover_reg_top/16.uart_intr_test.751557994 Jun 21 04:43:20 PM PDT 24 Jun 21 04:43:25 PM PDT 24 13214724 ps
T1139 /workspace/coverage/cover_reg_top/32.uart_intr_test.4024158914 Jun 21 04:43:14 PM PDT 24 Jun 21 04:43:19 PM PDT 24 13559959 ps
T1140 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3815390916 Jun 21 04:43:07 PM PDT 24 Jun 21 04:43:11 PM PDT 24 79608463 ps
T105 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1169609337 Jun 21 04:42:53 PM PDT 24 Jun 21 04:42:56 PM PDT 24 42622557 ps
T106 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.1219132597 Jun 21 04:43:09 PM PDT 24 Jun 21 04:43:14 PM PDT 24 291910634 ps
T1141 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3265050854 Jun 21 04:43:01 PM PDT 24 Jun 21 04:43:05 PM PDT 24 280785418 ps
T1142 /workspace/coverage/cover_reg_top/4.uart_tl_errors.2812183465 Jun 21 04:42:42 PM PDT 24 Jun 21 04:42:46 PM PDT 24 328317693 ps
T1143 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.4287620538 Jun 21 04:42:33 PM PDT 24 Jun 21 04:42:36 PM PDT 24 63143133 ps
T1144 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.757581278 Jun 21 04:43:08 PM PDT 24 Jun 21 04:43:12 PM PDT 24 94675685 ps
T103 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.3887937776 Jun 21 04:43:01 PM PDT 24 Jun 21 04:43:04 PM PDT 24 95143871 ps
T75 /workspace/coverage/cover_reg_top/0.uart_csr_rw.1540648621 Jun 21 04:42:27 PM PDT 24 Jun 21 04:42:29 PM PDT 24 29788005 ps
T101 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3161986526 Jun 21 04:43:00 PM PDT 24 Jun 21 04:43:04 PM PDT 24 53943264 ps
T1145 /workspace/coverage/cover_reg_top/3.uart_tl_errors.3757372732 Jun 21 04:42:49 PM PDT 24 Jun 21 04:42:53 PM PDT 24 24701682 ps
T1146 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.1575309307 Jun 21 04:42:54 PM PDT 24 Jun 21 04:43:01 PM PDT 24 69640330 ps
T1147 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.194123734 Jun 21 04:42:59 PM PDT 24 Jun 21 04:43:02 PM PDT 24 20408446 ps
T1148 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.2182321908 Jun 21 04:43:16 PM PDT 24 Jun 21 04:43:21 PM PDT 24 57990011 ps
T1149 /workspace/coverage/cover_reg_top/2.uart_intr_test.981914427 Jun 21 04:42:58 PM PDT 24 Jun 21 04:43:00 PM PDT 24 15660786 ps
T1150 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.814928331 Jun 21 04:42:56 PM PDT 24 Jun 21 04:42:58 PM PDT 24 25713097 ps
T76 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2904708842 Jun 21 04:42:35 PM PDT 24 Jun 21 04:42:37 PM PDT 24 63152931 ps
T132 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.3733891043 Jun 21 04:43:09 PM PDT 24 Jun 21 04:43:13 PM PDT 24 49168538 ps
T1151 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3145757779 Jun 21 04:43:14 PM PDT 24 Jun 21 04:43:20 PM PDT 24 139904421 ps
T1152 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3707296965 Jun 21 04:43:07 PM PDT 24 Jun 21 04:43:11 PM PDT 24 23792354 ps
T1153 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.1508506995 Jun 21 04:43:06 PM PDT 24 Jun 21 04:43:16 PM PDT 24 1043175414 ps
T80 /workspace/coverage/cover_reg_top/2.uart_csr_rw.4267680257 Jun 21 04:42:42 PM PDT 24 Jun 21 04:42:43 PM PDT 24 125669582 ps
T1154 /workspace/coverage/cover_reg_top/10.uart_tl_errors.911911175 Jun 21 04:42:49 PM PDT 24 Jun 21 04:42:53 PM PDT 24 105930177 ps
T1155 /workspace/coverage/cover_reg_top/19.uart_intr_test.3722685470 Jun 21 04:43:05 PM PDT 24 Jun 21 04:43:08 PM PDT 24 63880600 ps
T81 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.970512482 Jun 21 04:42:55 PM PDT 24 Jun 21 04:42:57 PM PDT 24 59874840 ps
T1156 /workspace/coverage/cover_reg_top/9.uart_csr_rw.1309182147 Jun 21 04:43:08 PM PDT 24 Jun 21 04:43:12 PM PDT 24 53402766 ps
T1157 /workspace/coverage/cover_reg_top/45.uart_intr_test.562024199 Jun 21 04:43:10 PM PDT 24 Jun 21 04:43:14 PM PDT 24 14722349 ps
T1158 /workspace/coverage/cover_reg_top/8.uart_csr_rw.2476884962 Jun 21 04:42:54 PM PDT 24 Jun 21 04:43:01 PM PDT 24 13793194 ps
T1159 /workspace/coverage/cover_reg_top/40.uart_intr_test.2922199075 Jun 21 04:43:14 PM PDT 24 Jun 21 04:43:19 PM PDT 24 33953389 ps
T134 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2103431363 Jun 21 04:42:58 PM PDT 24 Jun 21 04:43:00 PM PDT 24 323191691 ps
T1160 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.3093149257 Jun 21 04:43:23 PM PDT 24 Jun 21 04:43:29 PM PDT 24 36638601 ps
T1161 /workspace/coverage/cover_reg_top/26.uart_intr_test.16319368 Jun 21 04:43:07 PM PDT 24 Jun 21 04:43:10 PM PDT 24 20248723 ps
T1162 /workspace/coverage/cover_reg_top/13.uart_csr_rw.1013260248 Jun 21 04:43:10 PM PDT 24 Jun 21 04:43:14 PM PDT 24 42024690 ps
T104 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.2975439195 Jun 21 04:42:49 PM PDT 24 Jun 21 04:42:53 PM PDT 24 96401788 ps
T77 /workspace/coverage/cover_reg_top/14.uart_csr_rw.1592788896 Jun 21 04:43:15 PM PDT 24 Jun 21 04:43:20 PM PDT 24 57789227 ps
T1163 /workspace/coverage/cover_reg_top/2.uart_tl_errors.3047346263 Jun 21 04:42:47 PM PDT 24 Jun 21 04:42:50 PM PDT 24 423205403 ps
T1164 /workspace/coverage/cover_reg_top/13.uart_intr_test.1429377661 Jun 21 04:43:01 PM PDT 24 Jun 21 04:43:04 PM PDT 24 112335777 ps
T1165 /workspace/coverage/cover_reg_top/14.uart_tl_errors.3113148227 Jun 21 04:43:00 PM PDT 24 Jun 21 04:43:04 PM PDT 24 184735715 ps
T1166 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.62489683 Jun 21 04:43:24 PM PDT 24 Jun 21 04:43:30 PM PDT 24 33205266 ps
T1167 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2611638868 Jun 21 04:42:41 PM PDT 24 Jun 21 04:42:43 PM PDT 24 38278389 ps
T1168 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.2940708710 Jun 21 04:42:33 PM PDT 24 Jun 21 04:42:36 PM PDT 24 91851331 ps
T1169 /workspace/coverage/cover_reg_top/1.uart_tl_errors.2563246747 Jun 21 04:42:57 PM PDT 24 Jun 21 04:43:00 PM PDT 24 82567145 ps
T1170 /workspace/coverage/cover_reg_top/16.uart_csr_rw.3821264363 Jun 21 04:43:08 PM PDT 24 Jun 21 04:43:11 PM PDT 24 23273582 ps
T1171 /workspace/coverage/cover_reg_top/6.uart_csr_rw.3434032064 Jun 21 04:43:10 PM PDT 24 Jun 21 04:43:15 PM PDT 24 22309440 ps
T1172 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.2749666578 Jun 21 04:43:05 PM PDT 24 Jun 21 04:43:08 PM PDT 24 153665415 ps
T1173 /workspace/coverage/cover_reg_top/14.uart_intr_test.3084474173 Jun 21 04:42:59 PM PDT 24 Jun 21 04:43:01 PM PDT 24 37566043 ps
T1174 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.4260139579 Jun 21 04:42:52 PM PDT 24 Jun 21 04:42:57 PM PDT 24 1036330875 ps
T1175 /workspace/coverage/cover_reg_top/5.uart_tl_errors.703733613 Jun 21 04:42:58 PM PDT 24 Jun 21 04:43:00 PM PDT 24 22519413 ps
T1176 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1931461425 Jun 21 04:43:12 PM PDT 24 Jun 21 04:43:17 PM PDT 24 20341872 ps
T1177 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2879112077 Jun 21 04:42:38 PM PDT 24 Jun 21 04:42:40 PM PDT 24 23594241 ps
T1178 /workspace/coverage/cover_reg_top/38.uart_intr_test.1855800789 Jun 21 04:43:07 PM PDT 24 Jun 21 04:43:10 PM PDT 24 44580160 ps
T1179 /workspace/coverage/cover_reg_top/19.uart_csr_rw.1467148500 Jun 21 04:43:01 PM PDT 24 Jun 21 04:43:04 PM PDT 24 14190308 ps
T1180 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.674908469 Jun 21 04:42:33 PM PDT 24 Jun 21 04:42:35 PM PDT 24 22102795 ps
T133 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3163706959 Jun 21 04:42:49 PM PDT 24 Jun 21 04:42:53 PM PDT 24 83851789 ps
T1181 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.654842258 Jun 21 04:42:48 PM PDT 24 Jun 21 04:42:53 PM PDT 24 342037113 ps
T1182 /workspace/coverage/cover_reg_top/17.uart_tl_errors.2995259633 Jun 21 04:43:17 PM PDT 24 Jun 21 04:43:22 PM PDT 24 37787306 ps
T1183 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3463478280 Jun 21 04:43:18 PM PDT 24 Jun 21 04:43:23 PM PDT 24 163851091 ps
T1184 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.1537257126 Jun 21 04:43:17 PM PDT 24 Jun 21 04:43:22 PM PDT 24 23166745 ps
T1185 /workspace/coverage/cover_reg_top/11.uart_intr_test.559903143 Jun 21 04:43:03 PM PDT 24 Jun 21 04:43:06 PM PDT 24 30815661 ps
T1186 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3901699006 Jun 21 04:42:59 PM PDT 24 Jun 21 04:43:02 PM PDT 24 31563032 ps
T1187 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1924346105 Jun 21 04:42:34 PM PDT 24 Jun 21 04:42:37 PM PDT 24 1594725783 ps
T1188 /workspace/coverage/cover_reg_top/47.uart_intr_test.650508701 Jun 21 04:43:24 PM PDT 24 Jun 21 04:43:29 PM PDT 24 17941823 ps
T1189 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.3059420651 Jun 21 04:43:11 PM PDT 24 Jun 21 04:43:15 PM PDT 24 135035117 ps
T1190 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.2084682267 Jun 21 04:43:17 PM PDT 24 Jun 21 04:43:22 PM PDT 24 12982729 ps
T1191 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3192749613 Jun 21 04:43:14 PM PDT 24 Jun 21 04:43:20 PM PDT 24 71092620 ps
T1192 /workspace/coverage/cover_reg_top/4.uart_intr_test.62006702 Jun 21 04:43:16 PM PDT 24 Jun 21 04:43:21 PM PDT 24 14772131 ps
T1193 /workspace/coverage/cover_reg_top/9.uart_tl_errors.2574609513 Jun 21 04:42:39 PM PDT 24 Jun 21 04:42:41 PM PDT 24 215033481 ps
T1194 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1847798066 Jun 21 04:43:01 PM PDT 24 Jun 21 04:43:04 PM PDT 24 108618804 ps
T1195 /workspace/coverage/cover_reg_top/6.uart_intr_test.3351933092 Jun 21 04:43:20 PM PDT 24 Jun 21 04:43:24 PM PDT 24 50417587 ps
T1196 /workspace/coverage/cover_reg_top/11.uart_tl_errors.912936278 Jun 21 04:43:20 PM PDT 24 Jun 21 04:43:26 PM PDT 24 314330157 ps
T1197 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1752796858 Jun 21 04:43:12 PM PDT 24 Jun 21 04:43:18 PM PDT 24 498743177 ps
T1198 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2306428531 Jun 21 04:42:52 PM PDT 24 Jun 21 04:42:55 PM PDT 24 137266195 ps
T1199 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.3718965672 Jun 21 04:43:18 PM PDT 24 Jun 21 04:43:23 PM PDT 24 68065047 ps
T1200 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2141210936 Jun 21 04:42:44 PM PDT 24 Jun 21 04:42:46 PM PDT 24 88734802 ps
T1201 /workspace/coverage/cover_reg_top/21.uart_intr_test.3136830623 Jun 21 04:43:07 PM PDT 24 Jun 21 04:43:10 PM PDT 24 37317447 ps
T1202 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1235783350 Jun 21 04:42:51 PM PDT 24 Jun 21 04:42:55 PM PDT 24 140189902 ps
T1203 /workspace/coverage/cover_reg_top/29.uart_intr_test.1934341784 Jun 21 04:43:20 PM PDT 24 Jun 21 04:43:24 PM PDT 24 43937541 ps
T1204 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.1444339717 Jun 21 04:42:56 PM PDT 24 Jun 21 04:42:58 PM PDT 24 13710810 ps
T1205 /workspace/coverage/cover_reg_top/35.uart_intr_test.1653917587 Jun 21 04:42:59 PM PDT 24 Jun 21 04:43:02 PM PDT 24 37271917 ps
T1206 /workspace/coverage/cover_reg_top/3.uart_csr_rw.666737116 Jun 21 04:42:54 PM PDT 24 Jun 21 04:42:56 PM PDT 24 17187395 ps
T1207 /workspace/coverage/cover_reg_top/16.uart_tl_errors.872563667 Jun 21 04:43:07 PM PDT 24 Jun 21 04:43:11 PM PDT 24 60809076 ps
T1208 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1008478836 Jun 21 04:42:34 PM PDT 24 Jun 21 04:42:36 PM PDT 24 17871213 ps
T1209 /workspace/coverage/cover_reg_top/10.uart_intr_test.563432597 Jun 21 04:43:21 PM PDT 24 Jun 21 04:43:25 PM PDT 24 20305587 ps
T1210 /workspace/coverage/cover_reg_top/15.uart_tl_errors.73807998 Jun 21 04:43:09 PM PDT 24 Jun 21 04:43:13 PM PDT 24 54561200 ps
T1211 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3201124387 Jun 21 04:42:52 PM PDT 24 Jun 21 04:42:55 PM PDT 24 49657796 ps
T1212 /workspace/coverage/cover_reg_top/9.uart_intr_test.2633506411 Jun 21 04:42:45 PM PDT 24 Jun 21 04:42:48 PM PDT 24 28474340 ps
T1213 /workspace/coverage/cover_reg_top/11.uart_csr_rw.64286333 Jun 21 04:43:12 PM PDT 24 Jun 21 04:43:18 PM PDT 24 12632648 ps
T1214 /workspace/coverage/cover_reg_top/10.uart_csr_rw.2426796001 Jun 21 04:43:14 PM PDT 24 Jun 21 04:43:19 PM PDT 24 10702546 ps
T1215 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.180373837 Jun 21 04:43:08 PM PDT 24 Jun 21 04:43:13 PM PDT 24 121471450 ps
T1216 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.3043620177 Jun 21 04:43:17 PM PDT 24 Jun 21 04:43:22 PM PDT 24 67370927 ps
T1217 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.328249926 Jun 21 04:42:27 PM PDT 24 Jun 21 04:42:29 PM PDT 24 90293406 ps
T1218 /workspace/coverage/cover_reg_top/13.uart_tl_errors.1409121930 Jun 21 04:42:58 PM PDT 24 Jun 21 04:43:01 PM PDT 24 447190605 ps
T1219 /workspace/coverage/cover_reg_top/7.uart_csr_rw.1558292263 Jun 21 04:42:47 PM PDT 24 Jun 21 04:42:50 PM PDT 24 16146975 ps
T1220 /workspace/coverage/cover_reg_top/46.uart_intr_test.2567914645 Jun 21 04:43:24 PM PDT 24 Jun 21 04:43:30 PM PDT 24 30972646 ps
T1221 /workspace/coverage/cover_reg_top/25.uart_intr_test.946672344 Jun 21 04:43:24 PM PDT 24 Jun 21 04:43:30 PM PDT 24 13425308 ps
T1222 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.555051728 Jun 21 04:42:45 PM PDT 24 Jun 21 04:42:49 PM PDT 24 15854602 ps
T1223 /workspace/coverage/cover_reg_top/24.uart_intr_test.659485492 Jun 21 04:43:17 PM PDT 24 Jun 21 04:43:21 PM PDT 24 28055114 ps
T1224 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.3670101389 Jun 21 04:43:37 PM PDT 24 Jun 21 04:43:39 PM PDT 24 235708399 ps
T1225 /workspace/coverage/cover_reg_top/42.uart_intr_test.158942077 Jun 21 04:43:15 PM PDT 24 Jun 21 04:43:20 PM PDT 24 16828305 ps
T1226 /workspace/coverage/cover_reg_top/27.uart_intr_test.3407485298 Jun 21 04:43:25 PM PDT 24 Jun 21 04:43:31 PM PDT 24 11740381 ps
T1227 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.996858878 Jun 21 04:43:08 PM PDT 24 Jun 21 04:43:12 PM PDT 24 28929056 ps
T1228 /workspace/coverage/cover_reg_top/37.uart_intr_test.3604288124 Jun 21 04:43:08 PM PDT 24 Jun 21 04:43:12 PM PDT 24 13483529 ps
T1229 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.739610028 Jun 21 04:43:11 PM PDT 24 Jun 21 04:43:16 PM PDT 24 43097948 ps
T1230 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2574713510 Jun 21 04:42:59 PM PDT 24 Jun 21 04:43:02 PM PDT 24 42849166 ps
T1231 /workspace/coverage/cover_reg_top/41.uart_intr_test.4071437177 Jun 21 04:43:27 PM PDT 24 Jun 21 04:43:33 PM PDT 24 16945531 ps
T1232 /workspace/coverage/cover_reg_top/0.uart_intr_test.3603615820 Jun 21 04:42:45 PM PDT 24 Jun 21 04:42:49 PM PDT 24 143832791 ps
T78 /workspace/coverage/cover_reg_top/1.uart_csr_rw.3697250200 Jun 21 04:42:52 PM PDT 24 Jun 21 04:42:54 PM PDT 24 37747517 ps
T1233 /workspace/coverage/cover_reg_top/12.uart_csr_rw.2660198068 Jun 21 04:43:06 PM PDT 24 Jun 21 04:43:10 PM PDT 24 21900493 ps
T1234 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.4172752114 Jun 21 04:42:57 PM PDT 24 Jun 21 04:43:00 PM PDT 24 224389691 ps
T1235 /workspace/coverage/cover_reg_top/8.uart_tl_errors.2250935858 Jun 21 04:42:49 PM PDT 24 Jun 21 04:42:54 PM PDT 24 163135298 ps
T1236 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3253881130 Jun 21 04:43:15 PM PDT 24 Jun 21 04:43:21 PM PDT 24 107996574 ps

Test location /workspace/coverage/default/51.uart_fifo_reset.4280154504
Short name T4
Test name
Test status
Simulation time 21413913284 ps
CPU time 14.6 seconds
Started Jun 21 04:47:20 PM PDT 24
Finished Jun 21 04:47:36 PM PDT 24
Peak memory 200672 kb
Host smart-625e05e0-af02-447f-9e82-453251d6359d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280154504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.4280154504
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.303263818
Short name T16
Test name
Test status
Simulation time 106695039577 ps
CPU time 633.21 seconds
Started Jun 21 04:47:15 PM PDT 24
Finished Jun 21 04:57:50 PM PDT 24
Peak memory 217108 kb
Host smart-e0e7953b-e857-4aea-a99e-1089391471d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303263818 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.303263818
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_stress_all.3063296219
Short name T249
Test name
Test status
Simulation time 247499198965 ps
CPU time 855.34 seconds
Started Jun 21 04:47:17 PM PDT 24
Finished Jun 21 05:01:34 PM PDT 24
Peak memory 200660 kb
Host smart-a49f7a8d-fcb6-451b-a0a0-b6d6985e758f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063296219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.3063296219
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.563834233
Short name T41
Test name
Test status
Simulation time 224682323361 ps
CPU time 1059.78 seconds
Started Jun 21 04:47:14 PM PDT 24
Finished Jun 21 05:04:56 PM PDT 24
Peak memory 227232 kb
Host smart-ad8a2769-b08d-49fc-af0c-5560954c6eac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563834233 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.563834233
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.1458412748
Short name T3
Test name
Test status
Simulation time 31551910285 ps
CPU time 56.57 seconds
Started Jun 21 04:45:09 PM PDT 24
Finished Jun 21 04:46:06 PM PDT 24
Peak memory 200684 kb
Host smart-53c0b21d-e144-482e-b528-2abf592b9a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458412748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.1458412748
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_stress_all.160151549
Short name T94
Test name
Test status
Simulation time 145022925574 ps
CPU time 433.88 seconds
Started Jun 21 04:47:04 PM PDT 24
Finished Jun 21 04:54:19 PM PDT 24
Peak memory 200604 kb
Host smart-2f6d9230-f255-4632-a840-2974390eec5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160151549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.160151549
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_fifo_full.2475334244
Short name T13
Test name
Test status
Simulation time 120087199134 ps
CPU time 50.21 seconds
Started Jun 21 04:44:13 PM PDT 24
Finished Jun 21 04:45:06 PM PDT 24
Peak memory 200592 kb
Host smart-3677bdab-267a-4875-b813-56b8b61407bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475334244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.2475334244
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_perf.1347678171
Short name T250
Test name
Test status
Simulation time 28007155897 ps
CPU time 1429.36 seconds
Started Jun 21 04:44:48 PM PDT 24
Finished Jun 21 05:08:41 PM PDT 24
Peak memory 200652 kb
Host smart-a52a186d-df55-4be8-9c4a-c35971e4bb28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1347678171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.1347678171
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.3238350415
Short name T65
Test name
Test status
Simulation time 75180069264 ps
CPU time 1174.52 seconds
Started Jun 21 04:47:21 PM PDT 24
Finished Jun 21 05:07:00 PM PDT 24
Peak memory 225856 kb
Host smart-97609718-2b0a-42bc-9c33-fd052ba50be9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238350415 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.3238350415
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_stress_all.1800406183
Short name T33
Test name
Test status
Simulation time 185660009952 ps
CPU time 89.02 seconds
Started Jun 21 04:45:10 PM PDT 24
Finished Jun 21 04:46:41 PM PDT 24
Peak memory 200528 kb
Host smart-02abd2a8-a9f9-48a8-8c88-2cd86c8285d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800406183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.1800406183
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.632181433
Short name T190
Test name
Test status
Simulation time 290617807120 ps
CPU time 137.82 seconds
Started Jun 21 04:44:21 PM PDT 24
Finished Jun 21 04:46:44 PM PDT 24
Peak memory 200388 kb
Host smart-e1f1a842-ac02-4d1e-91a0-1c95a61d520a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632181433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.632181433
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.1445816779
Short name T54
Test name
Test status
Simulation time 94124116317 ps
CPU time 601.54 seconds
Started Jun 21 04:47:16 PM PDT 24
Finished Jun 21 04:57:19 PM PDT 24
Peak memory 200552 kb
Host smart-74dd6942-dc05-46ca-85c5-ecd02337aab0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1445816779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.1445816779
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1106534018
Short name T100
Test name
Test status
Simulation time 68039782 ps
CPU time 1.33 seconds
Started Jun 21 04:43:04 PM PDT 24
Finished Jun 21 04:43:07 PM PDT 24
Peak memory 199248 kb
Host smart-fb0b041a-f1f4-4c47-b4e0-7decc1f20565
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106534018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.1106534018
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/default/17.uart_stress_all.3280313528
Short name T131
Test name
Test status
Simulation time 209786995523 ps
CPU time 230.48 seconds
Started Jun 21 04:45:03 PM PDT 24
Finished Jun 21 04:48:56 PM PDT 24
Peak memory 200592 kb
Host smart-3ad57a55-cdc4-49d9-aa94-4915d925f383
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280313528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.3280313528
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_alert_test.3713869779
Short name T358
Test name
Test status
Simulation time 50702004 ps
CPU time 0.58 seconds
Started Jun 21 04:44:10 PM PDT 24
Finished Jun 21 04:44:13 PM PDT 24
Peak memory 195976 kb
Host smart-675eac57-2c14-4c50-8f98-40b9ec5660be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713869779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.3713869779
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_stress_all.887432668
Short name T137
Test name
Test status
Simulation time 147360223197 ps
CPU time 1035.42 seconds
Started Jun 21 04:45:15 PM PDT 24
Finished Jun 21 05:02:32 PM PDT 24
Peak memory 200604 kb
Host smart-2f27010b-444a-4591-b822-1716a7ff7589
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887432668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.887432668
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.156452664
Short name T55
Test name
Test status
Simulation time 153440294159 ps
CPU time 119.17 seconds
Started Jun 21 04:47:43 PM PDT 24
Finished Jun 21 04:49:44 PM PDT 24
Peak memory 200644 kb
Host smart-38a6b5c3-8e32-42a1-ac91-5946a69a3b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156452664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.156452664
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_stress_all.2395925495
Short name T163
Test name
Test status
Simulation time 436392099089 ps
CPU time 142.39 seconds
Started Jun 21 04:46:12 PM PDT 24
Finished Jun 21 04:48:40 PM PDT 24
Peak memory 200612 kb
Host smart-b5baa242-d69e-4792-a552-64a804ac2f9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395925495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.2395925495
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.4104953587
Short name T164
Test name
Test status
Simulation time 89663814643 ps
CPU time 36.45 seconds
Started Jun 21 04:47:44 PM PDT 24
Finished Jun 21 04:48:22 PM PDT 24
Peak memory 200600 kb
Host smart-10902ce9-5142-46f6-a504-0a4367759f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104953587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.4104953587
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.3239390163
Short name T129
Test name
Test status
Simulation time 353400002689 ps
CPU time 1493.59 seconds
Started Jun 21 04:47:23 PM PDT 24
Finished Jun 21 05:12:22 PM PDT 24
Peak memory 225252 kb
Host smart-0169d944-a1e9-416a-b9d1-42ee3a32b1bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239390163 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.3239390163
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_sec_cm.2087295267
Short name T108
Test name
Test status
Simulation time 237891886 ps
CPU time 0.84 seconds
Started Jun 21 04:44:19 PM PDT 24
Finished Jun 21 04:44:25 PM PDT 24
Peak memory 218568 kb
Host smart-c0c24bb8-ccb2-41c3-80b3-7c0a8e8e8438
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087295267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.2087295267
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.2423600591
Short name T279
Test name
Test status
Simulation time 155948393523 ps
CPU time 237.51 seconds
Started Jun 21 04:45:40 PM PDT 24
Finished Jun 21 04:49:39 PM PDT 24
Peak memory 200296 kb
Host smart-7c8bd357-044d-4ee2-8313-df873335759c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423600591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.2423600591
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.2383355556
Short name T195
Test name
Test status
Simulation time 145533320806 ps
CPU time 245.03 seconds
Started Jun 21 04:47:22 PM PDT 24
Finished Jun 21 04:51:32 PM PDT 24
Peak memory 200536 kb
Host smart-33366bbb-cf36-4783-9997-5d5d2d2ac771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383355556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.2383355556
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.1047991891
Short name T130
Test name
Test status
Simulation time 203317570054 ps
CPU time 723.12 seconds
Started Jun 21 04:47:19 PM PDT 24
Finished Jun 21 04:59:25 PM PDT 24
Peak memory 208876 kb
Host smart-a986f571-82c0-4b2f-adb6-4ff00466f678
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047991891 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.1047991891
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.2503147264
Short name T155
Test name
Test status
Simulation time 67335475141 ps
CPU time 117.62 seconds
Started Jun 21 04:47:29 PM PDT 24
Finished Jun 21 04:49:36 PM PDT 24
Peak memory 200636 kb
Host smart-1fccb144-9b28-4c49-9f60-3ede9a8a9f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503147264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.2503147264
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.1424306740
Short name T17
Test name
Test status
Simulation time 75725275505 ps
CPU time 30.8 seconds
Started Jun 21 04:45:57 PM PDT 24
Finished Jun 21 04:46:32 PM PDT 24
Peak memory 200632 kb
Host smart-ec5bc653-d4db-46cc-b54d-77369ffb46d7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424306740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.1424306740
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.3932444228
Short name T293
Test name
Test status
Simulation time 135291939660 ps
CPU time 47.43 seconds
Started Jun 21 04:46:09 PM PDT 24
Finished Jun 21 04:47:03 PM PDT 24
Peak memory 200628 kb
Host smart-b6df95e7-37bf-48e8-a445-42fe21b687a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932444228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.3932444228
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.1790088077
Short name T124
Test name
Test status
Simulation time 32747918675 ps
CPU time 48.58 seconds
Started Jun 21 04:47:22 PM PDT 24
Finished Jun 21 04:48:16 PM PDT 24
Peak memory 200560 kb
Host smart-2aa67673-40fb-42d2-9197-dab2165ab497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790088077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.1790088077
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.1540648621
Short name T75
Test name
Test status
Simulation time 29788005 ps
CPU time 0.61 seconds
Started Jun 21 04:42:27 PM PDT 24
Finished Jun 21 04:42:29 PM PDT 24
Peak memory 194552 kb
Host smart-b9b1e25a-cffc-41bb-93cb-b613e78bff3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540648621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.1540648621
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3181465827
Short name T86
Test name
Test status
Simulation time 65074881 ps
CPU time 0.75 seconds
Started Jun 21 04:43:10 PM PDT 24
Finished Jun 21 04:43:15 PM PDT 24
Peak memory 196960 kb
Host smart-de1c19c2-dc1b-4dec-b603-dfea637152a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181465827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.3181465827
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.uart_tx_rx.991839788
Short name T413
Test name
Test status
Simulation time 211959282999 ps
CPU time 85.28 seconds
Started Jun 21 04:44:17 PM PDT 24
Finished Jun 21 04:45:47 PM PDT 24
Peak memory 198964 kb
Host smart-2029f9ad-a5ee-421c-984b-1c9c1ae91da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991839788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.991839788
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.1039670867
Short name T219
Test name
Test status
Simulation time 32298276581 ps
CPU time 57.63 seconds
Started Jun 21 04:47:29 PM PDT 24
Finished Jun 21 04:48:36 PM PDT 24
Peak memory 200520 kb
Host smart-b8dafdf3-dbae-41dc-b3c8-95c7d9e7ce1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039670867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.1039670867
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.2049231216
Short name T48
Test name
Test status
Simulation time 92854963927 ps
CPU time 79.41 seconds
Started Jun 21 04:47:28 PM PDT 24
Finished Jun 21 04:48:57 PM PDT 24
Peak memory 200788 kb
Host smart-54b4f835-0bbc-418f-9df9-4d3db4e43d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049231216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.2049231216
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.1199835130
Short name T123
Test name
Test status
Simulation time 138132364627 ps
CPU time 102.98 seconds
Started Jun 21 04:47:24 PM PDT 24
Finished Jun 21 04:49:14 PM PDT 24
Peak memory 200624 kb
Host smart-8334c32b-3e1d-42aa-9149-c88cef3b1f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199835130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.1199835130
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.613492162
Short name T194
Test name
Test status
Simulation time 153011701457 ps
CPU time 217.63 seconds
Started Jun 21 04:47:58 PM PDT 24
Finished Jun 21 04:51:37 PM PDT 24
Peak memory 200420 kb
Host smart-e6ca16fa-b47f-4cc7-b739-aebae66605a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613492162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.613492162
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.345187523
Short name T39
Test name
Test status
Simulation time 14757034357 ps
CPU time 11.41 seconds
Started Jun 21 04:47:59 PM PDT 24
Finished Jun 21 04:48:12 PM PDT 24
Peak memory 200624 kb
Host smart-8fe2ef2f-0ab2-4b36-97c3-52a606cad51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345187523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.345187523
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2103431363
Short name T134
Test name
Test status
Simulation time 323191691 ps
CPU time 1.35 seconds
Started Jun 21 04:42:58 PM PDT 24
Finished Jun 21 04:43:00 PM PDT 24
Peak memory 199224 kb
Host smart-44aa6818-3527-4cb6-b455-39b4da117f8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103431363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.2103431363
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/default/48.uart_fifo_full.2156302481
Short name T152
Test name
Test status
Simulation time 26252186879 ps
CPU time 42.77 seconds
Started Jun 21 04:47:04 PM PDT 24
Finished Jun 21 04:47:48 PM PDT 24
Peak memory 200624 kb
Host smart-61d5078a-ecd9-4381-97ba-6b3aed76a16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156302481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.2156302481
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.721702403
Short name T208
Test name
Test status
Simulation time 894280765820 ps
CPU time 669.44 seconds
Started Jun 21 04:47:24 PM PDT 24
Finished Jun 21 04:58:40 PM PDT 24
Peak memory 226820 kb
Host smart-87e7f68b-b794-42d3-a689-62f2e23bf7d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721702403 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.721702403
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.1129225710
Short name T47
Test name
Test status
Simulation time 25396561132 ps
CPU time 39.17 seconds
Started Jun 21 04:47:59 PM PDT 24
Finished Jun 21 04:48:39 PM PDT 24
Peak memory 200644 kb
Host smart-30b8e34d-07ea-414a-b57e-7afac5fea5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129225710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.1129225710
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.2543784913
Short name T148
Test name
Test status
Simulation time 125332805793 ps
CPU time 179.81 seconds
Started Jun 21 04:45:55 PM PDT 24
Finished Jun 21 04:48:59 PM PDT 24
Peak memory 200592 kb
Host smart-9f852cd1-f5bd-4d6d-b03c-d7e9ff033482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543784913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.2543784913
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.946488540
Short name T149
Test name
Test status
Simulation time 377409968655 ps
CPU time 1187.67 seconds
Started Jun 21 04:46:04 PM PDT 24
Finished Jun 21 05:05:59 PM PDT 24
Peak memory 225260 kb
Host smart-20e5925f-a9e7-4528-a1eb-36b6920e75bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946488540 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.946488540
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.3076583035
Short name T234
Test name
Test status
Simulation time 203879839287 ps
CPU time 53.24 seconds
Started Jun 21 04:47:26 PM PDT 24
Finished Jun 21 04:48:28 PM PDT 24
Peak memory 200292 kb
Host smart-fb999f57-f382-47e8-bfd0-ae8a2b8da6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076583035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.3076583035
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_stress_all.2704092618
Short name T281
Test name
Test status
Simulation time 584647838189 ps
CPU time 119.2 seconds
Started Jun 21 04:46:15 PM PDT 24
Finished Jun 21 04:48:19 PM PDT 24
Peak memory 200660 kb
Host smart-38c63c4f-44e7-471b-94b1-1f97ddc0c92b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704092618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.2704092618
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.1527229054
Short name T61
Test name
Test status
Simulation time 42619101391 ps
CPU time 33.85 seconds
Started Jun 21 04:47:22 PM PDT 24
Finished Jun 21 04:48:01 PM PDT 24
Peak memory 200584 kb
Host smart-a65c5e8e-74e6-4786-8653-d7c82a1d13a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527229054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.1527229054
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.1463584862
Short name T40
Test name
Test status
Simulation time 39249171499 ps
CPU time 512.03 seconds
Started Jun 21 04:47:30 PM PDT 24
Finished Jun 21 04:56:11 PM PDT 24
Peak memory 217044 kb
Host smart-85c46cc7-e305-4e8a-bf9b-d4ae4a2e3182
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463584862 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.1463584862
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.3604397553
Short name T478
Test name
Test status
Simulation time 38579182590 ps
CPU time 268.26 seconds
Started Jun 21 04:44:26 PM PDT 24
Finished Jun 21 04:48:57 PM PDT 24
Peak memory 200528 kb
Host smart-5b81f1a3-a8ab-4bc5-a3f6-7ec308a53dd3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3604397553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.3604397553
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.1865935385
Short name T173
Test name
Test status
Simulation time 99806489193 ps
CPU time 41.28 seconds
Started Jun 21 04:44:49 PM PDT 24
Finished Jun 21 04:45:34 PM PDT 24
Peak memory 200572 kb
Host smart-9f00aa62-6948-49c6-a6aa-ed3e6004edf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865935385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.1865935385
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.3872222121
Short name T253
Test name
Test status
Simulation time 291117957366 ps
CPU time 148.38 seconds
Started Jun 21 04:44:56 PM PDT 24
Finished Jun 21 04:47:27 PM PDT 24
Peak memory 200608 kb
Host smart-2a422a0c-ecce-4f5d-ba82-6ef606da7735
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3872222121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.3872222121
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.4230890695
Short name T242
Test name
Test status
Simulation time 157313834144 ps
CPU time 23.58 seconds
Started Jun 21 04:47:32 PM PDT 24
Finished Jun 21 04:48:03 PM PDT 24
Peak memory 200468 kb
Host smart-f8222fe0-8b38-4cdb-8943-588f5a4a6286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230890695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.4230890695
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.2679598205
Short name T187
Test name
Test status
Simulation time 120523688473 ps
CPU time 89.29 seconds
Started Jun 21 04:47:25 PM PDT 24
Finished Jun 21 04:49:02 PM PDT 24
Peak memory 200704 kb
Host smart-be8a79ea-b548-4d72-ac08-2ae21f15e004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679598205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.2679598205
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.2845514272
Short name T229
Test name
Test status
Simulation time 55165505680 ps
CPU time 22.65 seconds
Started Jun 21 04:45:42 PM PDT 24
Finished Jun 21 04:46:06 PM PDT 24
Peak memory 200600 kb
Host smart-42fdcaf3-0ed9-4480-8810-66cf1bad080d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845514272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.2845514272
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.4209587700
Short name T214
Test name
Test status
Simulation time 373435239070 ps
CPU time 1120.92 seconds
Started Jun 21 04:45:46 PM PDT 24
Finished Jun 21 05:04:28 PM PDT 24
Peak memory 225348 kb
Host smart-0ad10dfe-6fcf-4ca0-ae52-6733f92fcef0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209587700 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.4209587700
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.963613303
Short name T217
Test name
Test status
Simulation time 146798257418 ps
CPU time 277.15 seconds
Started Jun 21 04:47:28 PM PDT 24
Finished Jun 21 04:52:14 PM PDT 24
Peak memory 200624 kb
Host smart-6071b14e-bf78-48e7-aea6-44d5ab9cfd09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963613303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.963613303
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.29413507
Short name T325
Test name
Test status
Simulation time 41562273402 ps
CPU time 32.64 seconds
Started Jun 21 04:47:22 PM PDT 24
Finished Jun 21 04:48:00 PM PDT 24
Peak memory 200480 kb
Host smart-e2130c48-7300-4fe2-bc2f-81354f22f80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29413507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.29413507
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.2207446596
Short name T176
Test name
Test status
Simulation time 30489824505 ps
CPU time 10.71 seconds
Started Jun 21 04:47:28 PM PDT 24
Finished Jun 21 04:47:47 PM PDT 24
Peak memory 200624 kb
Host smart-9c09ba4d-cae7-4f38-a3f4-d126c40c7f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207446596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.2207446596
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.3526190663
Short name T183
Test name
Test status
Simulation time 66559216708 ps
CPU time 28.74 seconds
Started Jun 21 04:44:50 PM PDT 24
Finished Jun 21 04:45:23 PM PDT 24
Peak memory 200632 kb
Host smart-a6e45b7f-6579-43bb-8de4-a87eeba26bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526190663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.3526190663
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.2138372464
Short name T228
Test name
Test status
Simulation time 73577238223 ps
CPU time 53.86 seconds
Started Jun 21 04:47:30 PM PDT 24
Finished Jun 21 04:48:32 PM PDT 24
Peak memory 200576 kb
Host smart-53c27c70-8e9d-464b-90f2-a2e3951e0a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138372464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.2138372464
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.2058759824
Short name T66
Test name
Test status
Simulation time 43658301439 ps
CPU time 137.2 seconds
Started Jun 21 04:47:07 PM PDT 24
Finished Jun 21 04:49:28 PM PDT 24
Peak memory 208904 kb
Host smart-2f687815-9a4f-471f-bca3-0f17aac34860
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058759824 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.2058759824
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.562464498
Short name T237
Test name
Test status
Simulation time 284591657682 ps
CPU time 1116.71 seconds
Started Jun 21 04:47:22 PM PDT 24
Finished Jun 21 05:06:03 PM PDT 24
Peak memory 217028 kb
Host smart-05f5e6ef-5524-4b48-8246-d36740894fc8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562464498 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.562464498
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.1219132597
Short name T106
Test name
Test status
Simulation time 291910634 ps
CPU time 1.23 seconds
Started Jun 21 04:43:09 PM PDT 24
Finished Jun 21 04:43:14 PM PDT 24
Peak memory 198928 kb
Host smart-24afd98b-7b57-4c23-aab3-f6d015bd6ce6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219132597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.1219132597
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.84123302
Short name T140
Test name
Test status
Simulation time 153671760815 ps
CPU time 262.49 seconds
Started Jun 21 04:47:25 PM PDT 24
Finished Jun 21 04:51:55 PM PDT 24
Peak memory 200628 kb
Host smart-9dd65900-a55f-4804-8e2d-11adc7d8c527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84123302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.84123302
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.2767232449
Short name T226
Test name
Test status
Simulation time 123363465801 ps
CPU time 90.25 seconds
Started Jun 21 04:47:24 PM PDT 24
Finished Jun 21 04:49:01 PM PDT 24
Peak memory 200596 kb
Host smart-7e9db5b5-9f05-4a1c-882f-2f1f3c3d2121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767232449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.2767232449
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.2401019778
Short name T204
Test name
Test status
Simulation time 8429438723 ps
CPU time 12.98 seconds
Started Jun 21 04:47:29 PM PDT 24
Finished Jun 21 04:47:52 PM PDT 24
Peak memory 200564 kb
Host smart-290b32c5-f3db-421c-94cf-068ce71375b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401019778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.2401019778
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.1049736515
Short name T56
Test name
Test status
Simulation time 99041774418 ps
CPU time 141.02 seconds
Started Jun 21 04:47:27 PM PDT 24
Finished Jun 21 04:49:57 PM PDT 24
Peak memory 200636 kb
Host smart-d49403da-621d-49b5-ae07-f031fd80e199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049736515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.1049736515
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.1908698816
Short name T216
Test name
Test status
Simulation time 123498037856 ps
CPU time 275.82 seconds
Started Jun 21 04:47:24 PM PDT 24
Finished Jun 21 04:52:06 PM PDT 24
Peak memory 200620 kb
Host smart-f6509f14-bfb9-4377-bffb-0f9667d2b49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908698816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.1908698816
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.144093549
Short name T336
Test name
Test status
Simulation time 86145025599 ps
CPU time 42.17 seconds
Started Jun 21 04:47:24 PM PDT 24
Finished Jun 21 04:48:13 PM PDT 24
Peak memory 200688 kb
Host smart-ee7f90a3-0688-4518-b698-c2aad1717d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144093549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.144093549
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.3654931088
Short name T239
Test name
Test status
Simulation time 36667719680 ps
CPU time 18.27 seconds
Started Jun 21 04:47:24 PM PDT 24
Finished Jun 21 04:47:49 PM PDT 24
Peak memory 200476 kb
Host smart-0475cb9c-7e75-4b45-a779-a1810f08df5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654931088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.3654931088
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.2640071896
Short name T240
Test name
Test status
Simulation time 103023685387 ps
CPU time 176.56 seconds
Started Jun 21 04:47:32 PM PDT 24
Finished Jun 21 04:50:36 PM PDT 24
Peak memory 200596 kb
Host smart-581520ce-8de0-4ccc-a0da-4ccadeb13311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640071896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.2640071896
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.775979084
Short name T230
Test name
Test status
Simulation time 69275788944 ps
CPU time 46.16 seconds
Started Jun 21 04:47:33 PM PDT 24
Finished Jun 21 04:48:26 PM PDT 24
Peak memory 200600 kb
Host smart-29588416-0f98-4833-a800-3948976263e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775979084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.775979084
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.3940281430
Short name T206
Test name
Test status
Simulation time 114974580188 ps
CPU time 29.58 seconds
Started Jun 21 04:47:32 PM PDT 24
Finished Jun 21 04:48:09 PM PDT 24
Peak memory 200564 kb
Host smart-a0bf05ca-09f5-4f49-b25c-6d72991302b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940281430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.3940281430
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.1843571515
Short name T232
Test name
Test status
Simulation time 128898180757 ps
CPU time 52.71 seconds
Started Jun 21 04:47:30 PM PDT 24
Finished Jun 21 04:48:31 PM PDT 24
Peak memory 200704 kb
Host smart-e55681bf-b226-4c1c-8c66-888c1eb8356d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843571515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.1843571515
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.3623974667
Short name T244
Test name
Test status
Simulation time 48447032932 ps
CPU time 15.16 seconds
Started Jun 21 04:45:52 PM PDT 24
Finished Jun 21 04:46:08 PM PDT 24
Peak memory 200668 kb
Host smart-bb1a1979-4eb2-4904-80c2-ff5314407e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623974667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.3623974667
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.985247587
Short name T233
Test name
Test status
Simulation time 156043687009 ps
CPU time 216.49 seconds
Started Jun 21 04:47:57 PM PDT 24
Finished Jun 21 04:51:34 PM PDT 24
Peak memory 200600 kb
Host smart-a6bb5b7a-d31c-44ab-bc92-f6f6c89df77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985247587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.985247587
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.3235148796
Short name T235
Test name
Test status
Simulation time 67135236159 ps
CPU time 93.33 seconds
Started Jun 21 04:48:07 PM PDT 24
Finished Jun 21 04:49:41 PM PDT 24
Peak memory 200568 kb
Host smart-2b0cfc56-9fc5-4bde-ac20-3d4d905f52f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235148796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.3235148796
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.3812566289
Short name T201
Test name
Test status
Simulation time 32867940092 ps
CPU time 39.56 seconds
Started Jun 21 04:46:04 PM PDT 24
Finished Jun 21 04:46:50 PM PDT 24
Peak memory 200580 kb
Host smart-f95c09ad-9449-47bb-a8cc-852a652f085e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812566289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.3812566289
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.637196200
Short name T154
Test name
Test status
Simulation time 116155434425 ps
CPU time 20.55 seconds
Started Jun 21 04:47:30 PM PDT 24
Finished Jun 21 04:47:59 PM PDT 24
Peak memory 200428 kb
Host smart-b9e82a6e-aef7-43a0-b2a1-35b858410cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637196200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.637196200
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.163726037
Short name T71
Test name
Test status
Simulation time 183291383821 ps
CPU time 1332.2 seconds
Started Jun 21 04:47:27 PM PDT 24
Finished Jun 21 05:09:47 PM PDT 24
Peak memory 225232 kb
Host smart-529a170e-5365-466d-9e35-1a7fac0591cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163726037 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.163726037
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1008478836
Short name T1208
Test name
Test status
Simulation time 17871213 ps
CPU time 0.73 seconds
Started Jun 21 04:42:34 PM PDT 24
Finished Jun 21 04:42:36 PM PDT 24
Peak memory 196044 kb
Host smart-bfd3bbdd-53e5-483a-8245-6a3ca5885713
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008478836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.1008478836
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.4287620538
Short name T1143
Test name
Test status
Simulation time 63143133 ps
CPU time 1.4 seconds
Started Jun 21 04:42:33 PM PDT 24
Finished Jun 21 04:42:36 PM PDT 24
Peak memory 196964 kb
Host smart-7cdf2d1d-d934-4658-98dc-26713297f563
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287620538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.4287620538
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.328249926
Short name T1217
Test name
Test status
Simulation time 90293406 ps
CPU time 0.6 seconds
Started Jun 21 04:42:27 PM PDT 24
Finished Jun 21 04:42:29 PM PDT 24
Peak memory 194560 kb
Host smart-e5826ac6-c9a6-49c3-abf8-fc933c1bbfbf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328249926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.328249926
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2141210936
Short name T1200
Test name
Test status
Simulation time 88734802 ps
CPU time 0.79 seconds
Started Jun 21 04:42:44 PM PDT 24
Finished Jun 21 04:42:46 PM PDT 24
Peak memory 198752 kb
Host smart-56ab0f6c-d8a3-4be6-919a-eca5cb4defbe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141210936 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.2141210936
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.3603615820
Short name T1232
Test name
Test status
Simulation time 143832791 ps
CPU time 0.61 seconds
Started Jun 21 04:42:45 PM PDT 24
Finished Jun 21 04:42:49 PM PDT 24
Peak memory 193528 kb
Host smart-323cb904-9ade-4499-af05-f3d03bd497be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603615820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.3603615820
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.3059420651
Short name T1189
Test name
Test status
Simulation time 135035117 ps
CPU time 0.67 seconds
Started Jun 21 04:43:11 PM PDT 24
Finished Jun 21 04:43:15 PM PDT 24
Peak memory 195844 kb
Host smart-c4d58350-1c7e-446d-b2cc-5102d7403663
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059420651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.3059420651
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.3385711412
Short name T1102
Test name
Test status
Simulation time 82773445 ps
CPU time 0.92 seconds
Started Jun 21 04:42:59 PM PDT 24
Finished Jun 21 04:43:07 PM PDT 24
Peak memory 199540 kb
Host smart-2f2375b6-0185-49cc-af23-5f8261e60b3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385711412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.3385711412
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.3725608934
Short name T102
Test name
Test status
Simulation time 188918549 ps
CPU time 0.97 seconds
Started Jun 21 04:42:33 PM PDT 24
Finished Jun 21 04:42:35 PM PDT 24
Peak memory 198960 kb
Host smart-58e2adc0-583a-4c97-b6cf-660fc8f8b5a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725608934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.3725608934
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2879112077
Short name T1177
Test name
Test status
Simulation time 23594241 ps
CPU time 0.69 seconds
Started Jun 21 04:42:38 PM PDT 24
Finished Jun 21 04:42:40 PM PDT 24
Peak memory 195204 kb
Host smart-630473b2-5452-45e9-bf3c-76b2169b38bb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879112077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.2879112077
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2756661598
Short name T74
Test name
Test status
Simulation time 314319144 ps
CPU time 2.31 seconds
Started Jun 21 04:42:48 PM PDT 24
Finished Jun 21 04:42:52 PM PDT 24
Peak memory 197408 kb
Host smart-8cb2d762-4fc4-4215-a780-a4a9453dd4a6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756661598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.2756661598
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.1508506995
Short name T1153
Test name
Test status
Simulation time 1043175414 ps
CPU time 1.29 seconds
Started Jun 21 04:43:06 PM PDT 24
Finished Jun 21 04:43:16 PM PDT 24
Peak memory 195224 kb
Host smart-9b78ad7c-dcb3-4de0-a3b8-2292b3a2d278
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508506995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.1508506995
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.654842258
Short name T1181
Test name
Test status
Simulation time 342037113 ps
CPU time 1.47 seconds
Started Jun 21 04:42:48 PM PDT 24
Finished Jun 21 04:42:53 PM PDT 24
Peak memory 199188 kb
Host smart-eb35d57e-e96d-4b86-b994-e6c3eb16f8a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654842258 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.654842258
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.3697250200
Short name T78
Test name
Test status
Simulation time 37747517 ps
CPU time 0.57 seconds
Started Jun 21 04:42:52 PM PDT 24
Finished Jun 21 04:42:54 PM PDT 24
Peak memory 195220 kb
Host smart-1f6cb5d3-bc8d-4b8c-b1b7-941492aa1533
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697250200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.3697250200
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.3249370012
Short name T1124
Test name
Test status
Simulation time 17524403 ps
CPU time 0.61 seconds
Started Jun 21 04:42:56 PM PDT 24
Finished Jun 21 04:42:57 PM PDT 24
Peak memory 194240 kb
Host smart-261f72b1-3814-42b7-bbb6-2643705d6419
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249370012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.3249370012
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3901699006
Short name T1186
Test name
Test status
Simulation time 31563032 ps
CPU time 0.63 seconds
Started Jun 21 04:42:59 PM PDT 24
Finished Jun 21 04:43:02 PM PDT 24
Peak memory 195472 kb
Host smart-17010677-6fd0-4dbe-a150-09196064d435
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901699006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.3901699006
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.2563246747
Short name T1169
Test name
Test status
Simulation time 82567145 ps
CPU time 1.08 seconds
Started Jun 21 04:42:57 PM PDT 24
Finished Jun 21 04:43:00 PM PDT 24
Peak memory 199844 kb
Host smart-1205ed8f-5971-4404-a270-d05f543df78c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563246747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.2563246747
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3192749613
Short name T1191
Test name
Test status
Simulation time 71092620 ps
CPU time 0.94 seconds
Started Jun 21 04:43:14 PM PDT 24
Finished Jun 21 04:43:20 PM PDT 24
Peak memory 199700 kb
Host smart-a1d9225b-292d-445e-9766-1f2beb0ffcd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192749613 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.3192749613
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.2426796001
Short name T1214
Test name
Test status
Simulation time 10702546 ps
CPU time 0.59 seconds
Started Jun 21 04:43:14 PM PDT 24
Finished Jun 21 04:43:19 PM PDT 24
Peak memory 195236 kb
Host smart-cc002310-5422-4dd6-95a7-5158ddd38c2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426796001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.2426796001
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.563432597
Short name T1209
Test name
Test status
Simulation time 20305587 ps
CPU time 0.56 seconds
Started Jun 21 04:43:21 PM PDT 24
Finished Jun 21 04:43:25 PM PDT 24
Peak memory 194332 kb
Host smart-56af6f16-1ccd-41b5-8e2b-04e40fb63397
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563432597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.563432597
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.2182321908
Short name T1148
Test name
Test status
Simulation time 57990011 ps
CPU time 0.79 seconds
Started Jun 21 04:43:16 PM PDT 24
Finished Jun 21 04:43:21 PM PDT 24
Peak memory 196648 kb
Host smart-f907e0ca-f15d-4d02-b4ef-e0ec0814e43b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182321908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.2182321908
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.911911175
Short name T1154
Test name
Test status
Simulation time 105930177 ps
CPU time 1.27 seconds
Started Jun 21 04:42:49 PM PDT 24
Finished Jun 21 04:42:53 PM PDT 24
Peak memory 199820 kb
Host smart-d8274c9b-2b84-4b3c-a19e-5ec2e548f820
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911911175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.911911175
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3145757779
Short name T1151
Test name
Test status
Simulation time 139904421 ps
CPU time 1.24 seconds
Started Jun 21 04:43:14 PM PDT 24
Finished Jun 21 04:43:20 PM PDT 24
Peak memory 199260 kb
Host smart-aadab4f4-6d78-4015-b64c-5783fb89fd70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145757779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.3145757779
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.62489683
Short name T1166
Test name
Test status
Simulation time 33205266 ps
CPU time 0.87 seconds
Started Jun 21 04:43:24 PM PDT 24
Finished Jun 21 04:43:30 PM PDT 24
Peak memory 199664 kb
Host smart-8bc8d039-5376-460a-9ad1-331159423054
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62489683 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.62489683
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.64286333
Short name T1213
Test name
Test status
Simulation time 12632648 ps
CPU time 0.59 seconds
Started Jun 21 04:43:12 PM PDT 24
Finished Jun 21 04:43:18 PM PDT 24
Peak memory 195224 kb
Host smart-231f542a-f813-498b-864f-09412ae6a861
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64286333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.64286333
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.559903143
Short name T1185
Test name
Test status
Simulation time 30815661 ps
CPU time 0.59 seconds
Started Jun 21 04:43:03 PM PDT 24
Finished Jun 21 04:43:06 PM PDT 24
Peak memory 194268 kb
Host smart-af84d595-67a4-4e72-b53c-37fb2a9c8f15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559903143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.559903143
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.912936278
Short name T1196
Test name
Test status
Simulation time 314330157 ps
CPU time 1.83 seconds
Started Jun 21 04:43:20 PM PDT 24
Finished Jun 21 04:43:26 PM PDT 24
Peak memory 199612 kb
Host smart-a7f59efe-2c53-42d8-bf43-fc926c8c311e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912936278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.912936278
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3265050854
Short name T1141
Test name
Test status
Simulation time 280785418 ps
CPU time 1.39 seconds
Started Jun 21 04:43:01 PM PDT 24
Finished Jun 21 04:43:05 PM PDT 24
Peak memory 199124 kb
Host smart-179ebd25-62f0-4532-a510-8d1882f1006e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265050854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.3265050854
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1752796858
Short name T1197
Test name
Test status
Simulation time 498743177 ps
CPU time 1.35 seconds
Started Jun 21 04:43:12 PM PDT 24
Finished Jun 21 04:43:18 PM PDT 24
Peak memory 199916 kb
Host smart-6896953f-a63f-4753-a1af-fb1b656662c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752796858 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.1752796858
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.2660198068
Short name T1233
Test name
Test status
Simulation time 21900493 ps
CPU time 0.65 seconds
Started Jun 21 04:43:06 PM PDT 24
Finished Jun 21 04:43:10 PM PDT 24
Peak memory 195576 kb
Host smart-fd03d388-2b41-477a-a6c6-e49c81238378
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660198068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.2660198068
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.4107114813
Short name T1114
Test name
Test status
Simulation time 12666179 ps
CPU time 0.55 seconds
Started Jun 21 04:43:17 PM PDT 24
Finished Jun 21 04:43:21 PM PDT 24
Peak memory 194268 kb
Host smart-f6d7592f-6257-4f08-8a8d-ee6b0549810d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107114813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.4107114813
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3707296965
Short name T1152
Test name
Test status
Simulation time 23792354 ps
CPU time 0.67 seconds
Started Jun 21 04:43:07 PM PDT 24
Finished Jun 21 04:43:11 PM PDT 24
Peak memory 196464 kb
Host smart-2ccc7f11-0f9f-4384-b185-1bfa759f0879
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707296965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.3707296965
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.100750649
Short name T1137
Test name
Test status
Simulation time 49961621 ps
CPU time 2.22 seconds
Started Jun 21 04:43:15 PM PDT 24
Finished Jun 21 04:43:22 PM PDT 24
Peak memory 199848 kb
Host smart-24404f3e-93d9-4695-9447-dc19fd2e1450
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100750649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.100750649
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.739610028
Short name T1229
Test name
Test status
Simulation time 43097948 ps
CPU time 0.93 seconds
Started Jun 21 04:43:11 PM PDT 24
Finished Jun 21 04:43:16 PM PDT 24
Peak memory 198568 kb
Host smart-62b297f9-a520-4b37-993d-9e0865edbd46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739610028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.739610028
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1847798066
Short name T1194
Test name
Test status
Simulation time 108618804 ps
CPU time 0.8 seconds
Started Jun 21 04:43:01 PM PDT 24
Finished Jun 21 04:43:04 PM PDT 24
Peak memory 198280 kb
Host smart-a776a6d5-f761-4eeb-9857-55618ef3e919
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847798066 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.1847798066
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.1013260248
Short name T1162
Test name
Test status
Simulation time 42024690 ps
CPU time 0.57 seconds
Started Jun 21 04:43:10 PM PDT 24
Finished Jun 21 04:43:14 PM PDT 24
Peak memory 195228 kb
Host smart-f4064d1d-7202-411f-b92d-1fec13def704
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013260248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.1013260248
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.1429377661
Short name T1164
Test name
Test status
Simulation time 112335777 ps
CPU time 0.6 seconds
Started Jun 21 04:43:01 PM PDT 24
Finished Jun 21 04:43:04 PM PDT 24
Peak memory 194232 kb
Host smart-4e3ecf11-66d9-4659-9531-ebe327d159ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429377661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.1429377661
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.2084682267
Short name T1190
Test name
Test status
Simulation time 12982729 ps
CPU time 0.63 seconds
Started Jun 21 04:43:17 PM PDT 24
Finished Jun 21 04:43:22 PM PDT 24
Peak memory 195324 kb
Host smart-54100a08-c9b2-4339-a5ab-fe9f5c0b9b09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084682267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.2084682267
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.1409121930
Short name T1218
Test name
Test status
Simulation time 447190605 ps
CPU time 1.61 seconds
Started Jun 21 04:42:58 PM PDT 24
Finished Jun 21 04:43:01 PM PDT 24
Peak memory 199820 kb
Host smart-8129d20c-adc5-4190-a35e-ff813e4d9c6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409121930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.1409121930
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3813314335
Short name T1131
Test name
Test status
Simulation time 88251940 ps
CPU time 0.77 seconds
Started Jun 21 04:43:07 PM PDT 24
Finished Jun 21 04:43:11 PM PDT 24
Peak memory 198964 kb
Host smart-27d593e5-f5cf-4adf-9bf2-3a7e3a94f220
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813314335 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.3813314335
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.1592788896
Short name T77
Test name
Test status
Simulation time 57789227 ps
CPU time 0.61 seconds
Started Jun 21 04:43:15 PM PDT 24
Finished Jun 21 04:43:20 PM PDT 24
Peak memory 195316 kb
Host smart-a8fc6814-0658-42b4-87e6-81373329e4af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592788896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.1592788896
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.3084474173
Short name T1173
Test name
Test status
Simulation time 37566043 ps
CPU time 0.56 seconds
Started Jun 21 04:42:59 PM PDT 24
Finished Jun 21 04:43:01 PM PDT 24
Peak memory 194164 kb
Host smart-004f06ba-1b62-45a1-9600-01db9fb61466
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084474173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.3084474173
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3968629985
Short name T82
Test name
Test status
Simulation time 58420760 ps
CPU time 0.63 seconds
Started Jun 21 04:43:07 PM PDT 24
Finished Jun 21 04:43:11 PM PDT 24
Peak memory 195624 kb
Host smart-a201f2b3-9b24-407f-9c73-ea27f5745285
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968629985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.3968629985
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.3113148227
Short name T1165
Test name
Test status
Simulation time 184735715 ps
CPU time 1.81 seconds
Started Jun 21 04:43:00 PM PDT 24
Finished Jun 21 04:43:04 PM PDT 24
Peak memory 199996 kb
Host smart-dee51d5e-66c3-4895-8d2e-dba6f430afc9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113148227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.3113148227
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3161986526
Short name T101
Test name
Test status
Simulation time 53943264 ps
CPU time 1.01 seconds
Started Jun 21 04:43:00 PM PDT 24
Finished Jun 21 04:43:04 PM PDT 24
Peak memory 198872 kb
Host smart-65218909-4e07-4167-948c-d99d8561a696
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161986526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.3161986526
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.180373837
Short name T1215
Test name
Test status
Simulation time 121471450 ps
CPU time 1.48 seconds
Started Jun 21 04:43:08 PM PDT 24
Finished Jun 21 04:43:13 PM PDT 24
Peak memory 199884 kb
Host smart-8867a3c8-9d53-4206-8e8e-9146aba3d0fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180373837 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.180373837
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.402645798
Short name T88
Test name
Test status
Simulation time 18833077 ps
CPU time 0.58 seconds
Started Jun 21 04:43:13 PM PDT 24
Finished Jun 21 04:43:18 PM PDT 24
Peak memory 195296 kb
Host smart-7207a423-5dc2-4ae0-a745-805457af27e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402645798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.402645798
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.3483323246
Short name T1125
Test name
Test status
Simulation time 11806531 ps
CPU time 0.6 seconds
Started Jun 21 04:43:04 PM PDT 24
Finished Jun 21 04:43:07 PM PDT 24
Peak memory 194272 kb
Host smart-9b9fd48a-dbc7-49d0-9c11-d32a560bbca6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483323246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.3483323246
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.3093149257
Short name T1160
Test name
Test status
Simulation time 36638601 ps
CPU time 0.74 seconds
Started Jun 21 04:43:23 PM PDT 24
Finished Jun 21 04:43:29 PM PDT 24
Peak memory 195984 kb
Host smart-8aee751a-1540-4f2f-b55c-ad44db05df37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093149257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.3093149257
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.73807998
Short name T1210
Test name
Test status
Simulation time 54561200 ps
CPU time 1.4 seconds
Started Jun 21 04:43:09 PM PDT 24
Finished Jun 21 04:43:13 PM PDT 24
Peak memory 199824 kb
Host smart-a7eb4759-077f-41af-9dd9-271ade9986ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73807998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.73807998
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1302790765
Short name T98
Test name
Test status
Simulation time 314593314 ps
CPU time 1.33 seconds
Started Jun 21 04:43:05 PM PDT 24
Finished Jun 21 04:43:09 PM PDT 24
Peak memory 199068 kb
Host smart-54504055-68c0-43e6-b9bd-1bf7c2b4e490
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302790765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.1302790765
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.333891747
Short name T1104
Test name
Test status
Simulation time 40643860 ps
CPU time 0.75 seconds
Started Jun 21 04:43:04 PM PDT 24
Finished Jun 21 04:43:07 PM PDT 24
Peak memory 198800 kb
Host smart-746db1b4-f26d-4b19-859f-b5ec6a9d4666
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333891747 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.333891747
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.3821264363
Short name T1170
Test name
Test status
Simulation time 23273582 ps
CPU time 0.59 seconds
Started Jun 21 04:43:08 PM PDT 24
Finished Jun 21 04:43:11 PM PDT 24
Peak memory 195228 kb
Host smart-7589c829-4064-4b1c-919d-c73d80abe8ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821264363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.3821264363
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.751557994
Short name T1138
Test name
Test status
Simulation time 13214724 ps
CPU time 0.54 seconds
Started Jun 21 04:43:20 PM PDT 24
Finished Jun 21 04:43:25 PM PDT 24
Peak memory 194196 kb
Host smart-c0a500cd-1674-4a36-ad7f-1756524d3ad6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751557994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.751557994
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.3399861881
Short name T1130
Test name
Test status
Simulation time 284360163 ps
CPU time 0.72 seconds
Started Jun 21 04:43:15 PM PDT 24
Finished Jun 21 04:43:20 PM PDT 24
Peak memory 195652 kb
Host smart-0f533e6e-2b9a-4b99-9125-7b2d77bbe6d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399861881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.3399861881
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.872563667
Short name T1207
Test name
Test status
Simulation time 60809076 ps
CPU time 1.42 seconds
Started Jun 21 04:43:07 PM PDT 24
Finished Jun 21 04:43:11 PM PDT 24
Peak memory 199848 kb
Host smart-1f745029-7691-4c6a-9774-6af3c8f06c40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872563667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.872563667
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3593204255
Short name T99
Test name
Test status
Simulation time 626534607 ps
CPU time 1.25 seconds
Started Jun 21 04:43:15 PM PDT 24
Finished Jun 21 04:43:21 PM PDT 24
Peak memory 199136 kb
Host smart-410665be-fe31-4157-bf0e-d754fcb83cb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593204255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.3593204255
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.1537257126
Short name T1184
Test name
Test status
Simulation time 23166745 ps
CPU time 1 seconds
Started Jun 21 04:43:17 PM PDT 24
Finished Jun 21 04:43:22 PM PDT 24
Peak memory 199764 kb
Host smart-73a0cb34-632a-4181-8a0c-8835634dcdb8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537257126 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.1537257126
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.857770873
Short name T1134
Test name
Test status
Simulation time 29898512 ps
CPU time 0.59 seconds
Started Jun 21 04:43:05 PM PDT 24
Finished Jun 21 04:43:07 PM PDT 24
Peak memory 195240 kb
Host smart-503704d0-4fdf-4e64-81d3-9c2b32275f79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857770873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.857770873
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.3179897538
Short name T1128
Test name
Test status
Simulation time 41441617 ps
CPU time 0.61 seconds
Started Jun 21 04:43:24 PM PDT 24
Finished Jun 21 04:43:29 PM PDT 24
Peak memory 193600 kb
Host smart-4c92e4b7-3bec-492c-b16b-a458de0cd4ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179897538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.3179897538
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.996858878
Short name T1227
Test name
Test status
Simulation time 28929056 ps
CPU time 0.72 seconds
Started Jun 21 04:43:08 PM PDT 24
Finished Jun 21 04:43:12 PM PDT 24
Peak memory 196868 kb
Host smart-9c28bd75-6a6a-4ac3-867e-2502e98773da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996858878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr
_outstanding.996858878
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.2995259633
Short name T1182
Test name
Test status
Simulation time 37787306 ps
CPU time 0.95 seconds
Started Jun 21 04:43:17 PM PDT 24
Finished Jun 21 04:43:22 PM PDT 24
Peak memory 199668 kb
Host smart-e01cc273-2f99-46d3-a8ab-2fb70ee76f05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995259633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.2995259633
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3463478280
Short name T1183
Test name
Test status
Simulation time 163851091 ps
CPU time 1.24 seconds
Started Jun 21 04:43:18 PM PDT 24
Finished Jun 21 04:43:23 PM PDT 24
Peak memory 199056 kb
Host smart-4790ac27-2a68-498a-bcef-82e1ef2ad208
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463478280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.3463478280
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1931461425
Short name T1176
Test name
Test status
Simulation time 20341872 ps
CPU time 0.96 seconds
Started Jun 21 04:43:12 PM PDT 24
Finished Jun 21 04:43:17 PM PDT 24
Peak memory 199700 kb
Host smart-63c02aac-6c24-4a0e-a78a-99e757d5ca7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931461425 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.1931461425
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.741408537
Short name T84
Test name
Test status
Simulation time 24664168 ps
CPU time 0.59 seconds
Started Jun 21 04:43:14 PM PDT 24
Finished Jun 21 04:43:19 PM PDT 24
Peak memory 195400 kb
Host smart-f8535469-6971-4ab3-9c0f-2477c750f05a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741408537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.741408537
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.323971872
Short name T1110
Test name
Test status
Simulation time 36304864 ps
CPU time 0.57 seconds
Started Jun 21 04:43:05 PM PDT 24
Finished Jun 21 04:43:07 PM PDT 24
Peak memory 194200 kb
Host smart-52cf04c7-e46e-41fc-96d5-f3525d217b47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323971872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.323971872
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2202639457
Short name T90
Test name
Test status
Simulation time 67090318 ps
CPU time 0.68 seconds
Started Jun 21 04:43:19 PM PDT 24
Finished Jun 21 04:43:23 PM PDT 24
Peak memory 195528 kb
Host smart-e9ab7dec-bf62-4287-bfc9-554019658b01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202639457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.2202639457
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.1495873094
Short name T1122
Test name
Test status
Simulation time 93983450 ps
CPU time 1.49 seconds
Started Jun 21 04:43:16 PM PDT 24
Finished Jun 21 04:43:22 PM PDT 24
Peak memory 199164 kb
Host smart-547ee5c7-8add-4539-9502-eba8bf72ca6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495873094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.1495873094
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3815390916
Short name T1140
Test name
Test status
Simulation time 79608463 ps
CPU time 1.14 seconds
Started Jun 21 04:43:07 PM PDT 24
Finished Jun 21 04:43:11 PM PDT 24
Peak memory 199784 kb
Host smart-56a4fd1b-c94f-410f-9d6b-6b7f94ab26f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815390916 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.3815390916
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.1467148500
Short name T1179
Test name
Test status
Simulation time 14190308 ps
CPU time 0.59 seconds
Started Jun 21 04:43:01 PM PDT 24
Finished Jun 21 04:43:04 PM PDT 24
Peak memory 195072 kb
Host smart-f5eb961c-86d4-4ac1-a096-a88b094904ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467148500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.1467148500
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.3722685470
Short name T1155
Test name
Test status
Simulation time 63880600 ps
CPU time 0.58 seconds
Started Jun 21 04:43:05 PM PDT 24
Finished Jun 21 04:43:08 PM PDT 24
Peak memory 194164 kb
Host smart-01fa04da-bd3b-4227-8db7-49a7d4f60f7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722685470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.3722685470
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.3718965672
Short name T1199
Test name
Test status
Simulation time 68065047 ps
CPU time 0.76 seconds
Started Jun 21 04:43:18 PM PDT 24
Finished Jun 21 04:43:23 PM PDT 24
Peak memory 197128 kb
Host smart-08cebfef-9440-4f2d-a61d-cec2cb76c5db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718965672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.3718965672
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.1367991804
Short name T1107
Test name
Test status
Simulation time 126477865 ps
CPU time 1.78 seconds
Started Jun 21 04:43:27 PM PDT 24
Finished Jun 21 04:43:34 PM PDT 24
Peak memory 199812 kb
Host smart-fc34992e-6c1f-496b-8c2e-7f3683002b3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367991804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.1367991804
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.3670101389
Short name T1224
Test name
Test status
Simulation time 235708399 ps
CPU time 0.96 seconds
Started Jun 21 04:43:37 PM PDT 24
Finished Jun 21 04:43:39 PM PDT 24
Peak memory 198824 kb
Host smart-aad904e1-bcda-47f4-a2cb-16ca52b23d4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670101389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.3670101389
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.151599670
Short name T79
Test name
Test status
Simulation time 15185332 ps
CPU time 0.67 seconds
Started Jun 21 04:42:47 PM PDT 24
Finished Jun 21 04:42:50 PM PDT 24
Peak memory 194680 kb
Host smart-2b5c2f98-fa06-402a-8858-bd659886c255
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151599670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.151599670
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.4260139579
Short name T1174
Test name
Test status
Simulation time 1036330875 ps
CPU time 2.59 seconds
Started Jun 21 04:42:52 PM PDT 24
Finished Jun 21 04:42:57 PM PDT 24
Peak memory 197624 kb
Host smart-75befabe-8065-4a08-bd1c-053d99860cff
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260139579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.4260139579
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.1444339717
Short name T1204
Test name
Test status
Simulation time 13710810 ps
CPU time 0.57 seconds
Started Jun 21 04:42:56 PM PDT 24
Finished Jun 21 04:42:58 PM PDT 24
Peak memory 195224 kb
Host smart-3336e6b7-1ea0-4aef-b7eb-891e384ff2a0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444339717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.1444339717
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.194123734
Short name T1147
Test name
Test status
Simulation time 20408446 ps
CPU time 1.06 seconds
Started Jun 21 04:42:59 PM PDT 24
Finished Jun 21 04:43:02 PM PDT 24
Peak memory 199704 kb
Host smart-33bce4ed-6f0a-4ff7-94e0-62c58af4cfe6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194123734 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.194123734
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.4267680257
Short name T80
Test name
Test status
Simulation time 125669582 ps
CPU time 0.66 seconds
Started Jun 21 04:42:42 PM PDT 24
Finished Jun 21 04:42:43 PM PDT 24
Peak memory 194652 kb
Host smart-5615f4b4-00ec-4d52-8a81-4198e70c1ecb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267680257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.4267680257
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.981914427
Short name T1149
Test name
Test status
Simulation time 15660786 ps
CPU time 0.57 seconds
Started Jun 21 04:42:58 PM PDT 24
Finished Jun 21 04:43:00 PM PDT 24
Peak memory 194200 kb
Host smart-408c986d-e006-4ea5-91ea-c7335a292318
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981914427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.981914427
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3283129995
Short name T91
Test name
Test status
Simulation time 52865166 ps
CPU time 0.74 seconds
Started Jun 21 04:42:43 PM PDT 24
Finished Jun 21 04:42:45 PM PDT 24
Peak memory 196780 kb
Host smart-dca900ca-6283-4dc6-92c0-88e704a69693
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283129995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.3283129995
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.3047346263
Short name T1163
Test name
Test status
Simulation time 423205403 ps
CPU time 1.28 seconds
Started Jun 21 04:42:47 PM PDT 24
Finished Jun 21 04:42:50 PM PDT 24
Peak memory 199780 kb
Host smart-7b2a5d50-68ca-4da8-8e90-c508296d2575
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047346263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.3047346263
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1235783350
Short name T1202
Test name
Test status
Simulation time 140189902 ps
CPU time 1.27 seconds
Started Jun 21 04:42:51 PM PDT 24
Finished Jun 21 04:42:55 PM PDT 24
Peak memory 199056 kb
Host smart-5bdcfa2a-6417-4bf4-a5dc-2e422c003f48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235783350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.1235783350
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.384034759
Short name T1109
Test name
Test status
Simulation time 11556130 ps
CPU time 0.56 seconds
Started Jun 21 04:43:16 PM PDT 24
Finished Jun 21 04:43:21 PM PDT 24
Peak memory 194260 kb
Host smart-ab2bbaaf-ec81-429b-95ac-427d295b989e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384034759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.384034759
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.3136830623
Short name T1201
Test name
Test status
Simulation time 37317447 ps
CPU time 0.57 seconds
Started Jun 21 04:43:07 PM PDT 24
Finished Jun 21 04:43:10 PM PDT 24
Peak memory 194228 kb
Host smart-60b8db3f-52d4-4fed-99f7-33d01026eaf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136830623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.3136830623
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.2299984888
Short name T1106
Test name
Test status
Simulation time 13276871 ps
CPU time 0.58 seconds
Started Jun 21 04:43:20 PM PDT 24
Finished Jun 21 04:43:24 PM PDT 24
Peak memory 194316 kb
Host smart-0f94d1ca-4176-40c5-9c41-9a86ea21c864
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299984888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.2299984888
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.3669781817
Short name T1112
Test name
Test status
Simulation time 15876811 ps
CPU time 0.57 seconds
Started Jun 21 04:43:18 PM PDT 24
Finished Jun 21 04:43:22 PM PDT 24
Peak memory 194168 kb
Host smart-f5f1bc52-bd11-4152-95c2-3aac80b0eee2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669781817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.3669781817
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.659485492
Short name T1223
Test name
Test status
Simulation time 28055114 ps
CPU time 0.58 seconds
Started Jun 21 04:43:17 PM PDT 24
Finished Jun 21 04:43:21 PM PDT 24
Peak memory 194208 kb
Host smart-3905d2b2-6fa7-4eca-94bd-84f78b81f4af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659485492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.659485492
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.946672344
Short name T1221
Test name
Test status
Simulation time 13425308 ps
CPU time 0.57 seconds
Started Jun 21 04:43:24 PM PDT 24
Finished Jun 21 04:43:30 PM PDT 24
Peak memory 194240 kb
Host smart-f548abf4-702d-4d3d-8a06-7f08fbaa92bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946672344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.946672344
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.16319368
Short name T1161
Test name
Test status
Simulation time 20248723 ps
CPU time 0.56 seconds
Started Jun 21 04:43:07 PM PDT 24
Finished Jun 21 04:43:10 PM PDT 24
Peak memory 194248 kb
Host smart-296b39fc-84e7-4f8f-a50a-400a774768eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16319368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.16319368
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.3407485298
Short name T1226
Test name
Test status
Simulation time 11740381 ps
CPU time 0.6 seconds
Started Jun 21 04:43:25 PM PDT 24
Finished Jun 21 04:43:31 PM PDT 24
Peak memory 194020 kb
Host smart-8d7afb7c-1845-4bef-ac8c-4c5b826fad50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407485298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.3407485298
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.3762457245
Short name T1123
Test name
Test status
Simulation time 20200707 ps
CPU time 0.58 seconds
Started Jun 21 04:43:07 PM PDT 24
Finished Jun 21 04:43:11 PM PDT 24
Peak memory 194184 kb
Host smart-fb7028a7-97b3-48fc-b006-a722372c0c7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762457245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.3762457245
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.1934341784
Short name T1203
Test name
Test status
Simulation time 43937541 ps
CPU time 0.55 seconds
Started Jun 21 04:43:20 PM PDT 24
Finished Jun 21 04:43:24 PM PDT 24
Peak memory 194264 kb
Host smart-f1c71fde-3a3b-4047-9c92-a014c9f6e9ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934341784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.1934341784
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.814928331
Short name T1150
Test name
Test status
Simulation time 25713097 ps
CPU time 0.68 seconds
Started Jun 21 04:42:56 PM PDT 24
Finished Jun 21 04:42:58 PM PDT 24
Peak memory 195256 kb
Host smart-967a1ea0-a94c-4c34-9ff9-b96b1a9c42fc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814928331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.814928331
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.2940708710
Short name T1168
Test name
Test status
Simulation time 91851331 ps
CPU time 1.51 seconds
Started Jun 21 04:42:33 PM PDT 24
Finished Jun 21 04:42:36 PM PDT 24
Peak memory 197656 kb
Host smart-b618c460-08fe-4a2d-a25e-90002a0bb883
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940708710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.2940708710
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.970512482
Short name T81
Test name
Test status
Simulation time 59874840 ps
CPU time 0.65 seconds
Started Jun 21 04:42:55 PM PDT 24
Finished Jun 21 04:42:57 PM PDT 24
Peak memory 195212 kb
Host smart-425d8de4-78c6-4be1-b824-977a9a8766ed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970512482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.970512482
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.465597650
Short name T1120
Test name
Test status
Simulation time 135874803 ps
CPU time 0.67 seconds
Started Jun 21 04:43:00 PM PDT 24
Finished Jun 21 04:43:03 PM PDT 24
Peak memory 197016 kb
Host smart-3f90807d-46b7-4fdb-9495-f4b01fd9969f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465597650 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.465597650
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.666737116
Short name T1206
Test name
Test status
Simulation time 17187395 ps
CPU time 0.63 seconds
Started Jun 21 04:42:54 PM PDT 24
Finished Jun 21 04:42:56 PM PDT 24
Peak memory 195504 kb
Host smart-28a972ed-54c5-43b9-89af-bb788e26fae1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666737116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.666737116
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.1343244439
Short name T1127
Test name
Test status
Simulation time 14460621 ps
CPU time 0.58 seconds
Started Jun 21 04:42:51 PM PDT 24
Finished Jun 21 04:42:54 PM PDT 24
Peak memory 194220 kb
Host smart-38f250f1-740d-459e-80c2-2fd106ebaea1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343244439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.1343244439
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.1575309307
Short name T1146
Test name
Test status
Simulation time 69640330 ps
CPU time 0.72 seconds
Started Jun 21 04:42:54 PM PDT 24
Finished Jun 21 04:43:01 PM PDT 24
Peak memory 194880 kb
Host smart-42ba613a-271d-4863-a0c2-6cddc847aa48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575309307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.1575309307
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.3757372732
Short name T1145
Test name
Test status
Simulation time 24701682 ps
CPU time 1.08 seconds
Started Jun 21 04:42:49 PM PDT 24
Finished Jun 21 04:42:53 PM PDT 24
Peak memory 199812 kb
Host smart-37370399-3246-4bfd-adec-481c38d6c244
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757372732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.3757372732
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1169609337
Short name T105
Test name
Test status
Simulation time 42622557 ps
CPU time 1 seconds
Started Jun 21 04:42:53 PM PDT 24
Finished Jun 21 04:42:56 PM PDT 24
Peak memory 198712 kb
Host smart-a54fbaff-a1c6-495c-9896-24616481cdfe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169609337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.1169609337
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.1913801492
Short name T1113
Test name
Test status
Simulation time 22283080 ps
CPU time 0.56 seconds
Started Jun 21 04:43:07 PM PDT 24
Finished Jun 21 04:43:11 PM PDT 24
Peak memory 194200 kb
Host smart-591ccb99-1ea9-4062-ad0e-21ccd4ea3054
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913801492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.1913801492
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.2955773923
Short name T1103
Test name
Test status
Simulation time 10940716 ps
CPU time 0.54 seconds
Started Jun 21 04:43:26 PM PDT 24
Finished Jun 21 04:43:33 PM PDT 24
Peak memory 194268 kb
Host smart-cd191593-5785-4148-80cd-76de968b7b51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955773923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.2955773923
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.4024158914
Short name T1139
Test name
Test status
Simulation time 13559959 ps
CPU time 0.58 seconds
Started Jun 21 04:43:14 PM PDT 24
Finished Jun 21 04:43:19 PM PDT 24
Peak memory 194264 kb
Host smart-1b9a75df-fd0c-4717-87d2-d6854417856a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024158914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.4024158914
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.22741742
Short name T1135
Test name
Test status
Simulation time 195076907 ps
CPU time 0.57 seconds
Started Jun 21 04:43:26 PM PDT 24
Finished Jun 21 04:43:32 PM PDT 24
Peak memory 194272 kb
Host smart-2d23ae32-0bfd-4ff3-a0d5-c4c28c5f7ca5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22741742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.22741742
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.707783146
Short name T1117
Test name
Test status
Simulation time 17995197 ps
CPU time 0.59 seconds
Started Jun 21 04:43:13 PM PDT 24
Finished Jun 21 04:43:18 PM PDT 24
Peak memory 194264 kb
Host smart-e53396d9-5d9e-4c77-803a-70c9a8cef584
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707783146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.707783146
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.1653917587
Short name T1205
Test name
Test status
Simulation time 37271917 ps
CPU time 0.55 seconds
Started Jun 21 04:42:59 PM PDT 24
Finished Jun 21 04:43:02 PM PDT 24
Peak memory 194276 kb
Host smart-7ba1e5da-0782-4000-a9af-834faaf2f5fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653917587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.1653917587
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.1128582414
Short name T1108
Test name
Test status
Simulation time 49626339 ps
CPU time 0.53 seconds
Started Jun 21 04:43:25 PM PDT 24
Finished Jun 21 04:43:31 PM PDT 24
Peak memory 194292 kb
Host smart-77a438e1-88c1-4fba-a9da-07adb4c198c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128582414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.1128582414
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.3604288124
Short name T1228
Test name
Test status
Simulation time 13483529 ps
CPU time 0.61 seconds
Started Jun 21 04:43:08 PM PDT 24
Finished Jun 21 04:43:12 PM PDT 24
Peak memory 194380 kb
Host smart-8d949d67-c588-4b7f-9d5f-0300e32e21db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604288124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.3604288124
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.1855800789
Short name T1178
Test name
Test status
Simulation time 44580160 ps
CPU time 0.59 seconds
Started Jun 21 04:43:07 PM PDT 24
Finished Jun 21 04:43:10 PM PDT 24
Peak memory 194268 kb
Host smart-e893b757-5183-47a1-8270-81d92a7fda56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855800789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.1855800789
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.2106234096
Short name T1126
Test name
Test status
Simulation time 14717598 ps
CPU time 0.58 seconds
Started Jun 21 04:43:29 PM PDT 24
Finished Jun 21 04:43:34 PM PDT 24
Peak memory 194264 kb
Host smart-43eca14a-1801-4084-b2ad-560f58d85044
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106234096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.2106234096
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.757581278
Short name T1144
Test name
Test status
Simulation time 94675685 ps
CPU time 0.76 seconds
Started Jun 21 04:43:08 PM PDT 24
Finished Jun 21 04:43:12 PM PDT 24
Peak memory 196084 kb
Host smart-72dc9afa-e6be-48d0-8dfa-12c25042a635
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757581278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.757581278
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.4172752114
Short name T1234
Test name
Test status
Simulation time 224389691 ps
CPU time 1.61 seconds
Started Jun 21 04:42:57 PM PDT 24
Finished Jun 21 04:43:00 PM PDT 24
Peak memory 197764 kb
Host smart-0ac7126f-7f78-446f-b112-ea04851aff0a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172752114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.4172752114
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2904708842
Short name T76
Test name
Test status
Simulation time 63152931 ps
CPU time 0.59 seconds
Started Jun 21 04:42:35 PM PDT 24
Finished Jun 21 04:42:37 PM PDT 24
Peak memory 195252 kb
Host smart-58dcdd30-8e5d-482b-93af-86f5dda98e7f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904708842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.2904708842
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2524631909
Short name T1129
Test name
Test status
Simulation time 22043070 ps
CPU time 0.7 seconds
Started Jun 21 04:42:37 PM PDT 24
Finished Jun 21 04:42:39 PM PDT 24
Peak memory 197592 kb
Host smart-9e561240-5c87-4900-a5d4-0409ae803fd5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524631909 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.2524631909
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.1283230949
Short name T85
Test name
Test status
Simulation time 40030300 ps
CPU time 0.6 seconds
Started Jun 21 04:42:50 PM PDT 24
Finished Jun 21 04:42:53 PM PDT 24
Peak memory 195220 kb
Host smart-efb07f32-4c80-47f8-8e1e-4ac5b4da9931
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283230949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.1283230949
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.62006702
Short name T1192
Test name
Test status
Simulation time 14772131 ps
CPU time 0.58 seconds
Started Jun 21 04:43:16 PM PDT 24
Finished Jun 21 04:43:21 PM PDT 24
Peak memory 194320 kb
Host smart-83697f16-967b-45a4-80d6-3640a0c773fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62006702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.62006702
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.1020376029
Short name T87
Test name
Test status
Simulation time 20170235 ps
CPU time 0.7 seconds
Started Jun 21 04:42:59 PM PDT 24
Finished Jun 21 04:43:03 PM PDT 24
Peak memory 194744 kb
Host smart-b044f746-a732-4c14-99db-670697ccddac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020376029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.1020376029
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.2812183465
Short name T1142
Test name
Test status
Simulation time 328317693 ps
CPU time 2.14 seconds
Started Jun 21 04:42:42 PM PDT 24
Finished Jun 21 04:42:46 PM PDT 24
Peak memory 199176 kb
Host smart-e6841c1f-a1ca-4e23-95e1-b0cb08f5c1ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812183465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.2812183465
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.3733891043
Short name T132
Test name
Test status
Simulation time 49168538 ps
CPU time 0.93 seconds
Started Jun 21 04:43:09 PM PDT 24
Finished Jun 21 04:43:13 PM PDT 24
Peak memory 198956 kb
Host smart-5144edbf-3c64-47fd-8e40-7c2c0a5c8cb1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733891043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.3733891043
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.2922199075
Short name T1159
Test name
Test status
Simulation time 33953389 ps
CPU time 0.57 seconds
Started Jun 21 04:43:14 PM PDT 24
Finished Jun 21 04:43:19 PM PDT 24
Peak memory 194232 kb
Host smart-4df87773-3ac1-4e80-a825-e8b5ef53fab8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922199075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.2922199075
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.4071437177
Short name T1231
Test name
Test status
Simulation time 16945531 ps
CPU time 0.55 seconds
Started Jun 21 04:43:27 PM PDT 24
Finished Jun 21 04:43:33 PM PDT 24
Peak memory 194264 kb
Host smart-26632eff-f813-4bc0-87d5-bd3ed942f7d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071437177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.4071437177
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.158942077
Short name T1225
Test name
Test status
Simulation time 16828305 ps
CPU time 0.59 seconds
Started Jun 21 04:43:15 PM PDT 24
Finished Jun 21 04:43:20 PM PDT 24
Peak memory 194248 kb
Host smart-ce6276c0-cd11-4ac5-90eb-55088863358a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158942077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.158942077
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.3302839853
Short name T1111
Test name
Test status
Simulation time 11849628 ps
CPU time 0.56 seconds
Started Jun 21 04:43:07 PM PDT 24
Finished Jun 21 04:43:10 PM PDT 24
Peak memory 194200 kb
Host smart-bffce57e-af8e-4a0f-8047-7fd857b7fda4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302839853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.3302839853
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.71483556
Short name T1118
Test name
Test status
Simulation time 42966886 ps
CPU time 0.56 seconds
Started Jun 21 04:43:10 PM PDT 24
Finished Jun 21 04:43:14 PM PDT 24
Peak memory 194200 kb
Host smart-00ebac70-12f2-4480-a946-7620a739da48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71483556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.71483556
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.562024199
Short name T1157
Test name
Test status
Simulation time 14722349 ps
CPU time 0.57 seconds
Started Jun 21 04:43:10 PM PDT 24
Finished Jun 21 04:43:14 PM PDT 24
Peak memory 194196 kb
Host smart-26348d92-1625-4132-aa2c-d41531001278
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562024199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.562024199
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.2567914645
Short name T1220
Test name
Test status
Simulation time 30972646 ps
CPU time 0.56 seconds
Started Jun 21 04:43:24 PM PDT 24
Finished Jun 21 04:43:30 PM PDT 24
Peak memory 194276 kb
Host smart-2bca983d-deb1-4b0b-b52f-a78f06ee18b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567914645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.2567914645
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.650508701
Short name T1188
Test name
Test status
Simulation time 17941823 ps
CPU time 0.58 seconds
Started Jun 21 04:43:24 PM PDT 24
Finished Jun 21 04:43:29 PM PDT 24
Peak memory 194272 kb
Host smart-c712d68d-d276-4f70-91bd-99cc5f04eeb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650508701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.650508701
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.4196038117
Short name T1105
Test name
Test status
Simulation time 18865453 ps
CPU time 0.59 seconds
Started Jun 21 04:43:16 PM PDT 24
Finished Jun 21 04:43:20 PM PDT 24
Peak memory 194200 kb
Host smart-e69c38fe-1fd5-47b8-8e47-8fb3e095ead4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196038117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.4196038117
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.3433889169
Short name T1121
Test name
Test status
Simulation time 13000528 ps
CPU time 0.58 seconds
Started Jun 21 04:43:05 PM PDT 24
Finished Jun 21 04:43:08 PM PDT 24
Peak memory 194340 kb
Host smart-864a0599-09a3-4983-9300-04905ac62760
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433889169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.3433889169
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2574713510
Short name T1230
Test name
Test status
Simulation time 42849166 ps
CPU time 0.83 seconds
Started Jun 21 04:42:59 PM PDT 24
Finished Jun 21 04:43:02 PM PDT 24
Peak memory 199716 kb
Host smart-3d4acb94-dab1-4764-a0fa-b6993237c1f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574713510 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.2574713510
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.234357233
Short name T1133
Test name
Test status
Simulation time 41292387 ps
CPU time 0.68 seconds
Started Jun 21 04:42:44 PM PDT 24
Finished Jun 21 04:42:46 PM PDT 24
Peak memory 195300 kb
Host smart-b2b47a73-8c79-4aba-810f-a283cb4689af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234357233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.234357233
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.275518066
Short name T1136
Test name
Test status
Simulation time 16864428 ps
CPU time 0.57 seconds
Started Jun 21 04:42:59 PM PDT 24
Finished Jun 21 04:43:02 PM PDT 24
Peak memory 194188 kb
Host smart-49a55f55-f841-4c7e-a3e2-37c917d38970
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275518066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.275518066
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2719966311
Short name T83
Test name
Test status
Simulation time 49914515 ps
CPU time 0.68 seconds
Started Jun 21 04:43:20 PM PDT 24
Finished Jun 21 04:43:25 PM PDT 24
Peak memory 194712 kb
Host smart-a7577782-a6f0-44b3-84fb-ae907c80c895
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719966311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.2719966311
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.703733613
Short name T1175
Test name
Test status
Simulation time 22519413 ps
CPU time 0.98 seconds
Started Jun 21 04:42:58 PM PDT 24
Finished Jun 21 04:43:00 PM PDT 24
Peak memory 199692 kb
Host smart-84f494c0-5d30-4cfa-ae82-3d7d91c4a562
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703733613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.703733613
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.2749666578
Short name T1172
Test name
Test status
Simulation time 153665415 ps
CPU time 1.38 seconds
Started Jun 21 04:43:05 PM PDT 24
Finished Jun 21 04:43:08 PM PDT 24
Peak memory 199132 kb
Host smart-732e91b5-ac3a-486e-b3f3-595c2e00ea98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749666578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.2749666578
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.674908469
Short name T1180
Test name
Test status
Simulation time 22102795 ps
CPU time 0.71 seconds
Started Jun 21 04:42:33 PM PDT 24
Finished Jun 21 04:42:35 PM PDT 24
Peak memory 197464 kb
Host smart-5ee1d091-2104-4faf-aee6-02b87efe7c90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674908469 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.674908469
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.3434032064
Short name T1171
Test name
Test status
Simulation time 22309440 ps
CPU time 0.59 seconds
Started Jun 21 04:43:10 PM PDT 24
Finished Jun 21 04:43:15 PM PDT 24
Peak memory 195388 kb
Host smart-74993963-c4f0-481e-a8d2-012acd694e4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434032064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.3434032064
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.3351933092
Short name T1195
Test name
Test status
Simulation time 50417587 ps
CPU time 0.55 seconds
Started Jun 21 04:43:20 PM PDT 24
Finished Jun 21 04:43:24 PM PDT 24
Peak memory 194192 kb
Host smart-52c42b27-4e56-46d1-8320-e01b1d1111f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351933092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.3351933092
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.3043620177
Short name T1216
Test name
Test status
Simulation time 67370927 ps
CPU time 0.66 seconds
Started Jun 21 04:43:17 PM PDT 24
Finished Jun 21 04:43:22 PM PDT 24
Peak memory 196384 kb
Host smart-340fff1a-2c9e-4f09-bfa4-b448b2a6934e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043620177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.3043620177
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.2297007272
Short name T1119
Test name
Test status
Simulation time 46173674 ps
CPU time 2.33 seconds
Started Jun 21 04:42:46 PM PDT 24
Finished Jun 21 04:42:51 PM PDT 24
Peak memory 199752 kb
Host smart-8e3ac1ae-7614-4943-8098-c013134d2ec1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297007272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.2297007272
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.2975439195
Short name T104
Test name
Test status
Simulation time 96401788 ps
CPU time 1.34 seconds
Started Jun 21 04:42:49 PM PDT 24
Finished Jun 21 04:42:53 PM PDT 24
Peak memory 199248 kb
Host smart-3e44c66c-cb67-4358-98aa-6068074b64a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975439195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.2975439195
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2611638868
Short name T1167
Test name
Test status
Simulation time 38278389 ps
CPU time 0.99 seconds
Started Jun 21 04:42:41 PM PDT 24
Finished Jun 21 04:42:43 PM PDT 24
Peak memory 199696 kb
Host smart-34c8754c-f9b4-490d-b8ec-d5607a5a933b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611638868 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.2611638868
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.1558292263
Short name T1219
Test name
Test status
Simulation time 16146975 ps
CPU time 0.66 seconds
Started Jun 21 04:42:47 PM PDT 24
Finished Jun 21 04:42:50 PM PDT 24
Peak memory 195332 kb
Host smart-e6bc2b1d-6b84-4c70-ba85-ac31194e4218
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558292263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.1558292263
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.2469543005
Short name T1115
Test name
Test status
Simulation time 76174970 ps
CPU time 0.6 seconds
Started Jun 21 04:42:50 PM PDT 24
Finished Jun 21 04:42:53 PM PDT 24
Peak memory 194256 kb
Host smart-35e9976a-685b-4157-9600-549566e1529e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469543005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.2469543005
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2306428531
Short name T1198
Test name
Test status
Simulation time 137266195 ps
CPU time 0.8 seconds
Started Jun 21 04:42:52 PM PDT 24
Finished Jun 21 04:42:55 PM PDT 24
Peak memory 196404 kb
Host smart-fd035427-9e94-4bbf-9a51-030d210f1f47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306428531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.2306428531
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.983050275
Short name T1132
Test name
Test status
Simulation time 110639632 ps
CPU time 1.58 seconds
Started Jun 21 04:42:52 PM PDT 24
Finished Jun 21 04:42:56 PM PDT 24
Peak memory 199836 kb
Host smart-25d54edf-fe3b-466f-b483-71492efa8bf0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983050275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.983050275
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1924346105
Short name T1187
Test name
Test status
Simulation time 1594725783 ps
CPU time 1.45 seconds
Started Jun 21 04:42:34 PM PDT 24
Finished Jun 21 04:42:37 PM PDT 24
Peak memory 199220 kb
Host smart-64d45b87-7b2f-48d5-b39d-2a846ad1b067
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924346105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.1924346105
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3201124387
Short name T1211
Test name
Test status
Simulation time 49657796 ps
CPU time 0.9 seconds
Started Jun 21 04:42:52 PM PDT 24
Finished Jun 21 04:42:55 PM PDT 24
Peak memory 199660 kb
Host smart-c3042033-451e-4936-a7cd-98017412614c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201124387 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.3201124387
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.2476884962
Short name T1158
Test name
Test status
Simulation time 13793194 ps
CPU time 0.6 seconds
Started Jun 21 04:42:54 PM PDT 24
Finished Jun 21 04:43:01 PM PDT 24
Peak memory 195220 kb
Host smart-c52b848e-76eb-4280-9d93-e01ff473f5a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476884962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.2476884962
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.742987708
Short name T1116
Test name
Test status
Simulation time 32922394 ps
CPU time 0.55 seconds
Started Jun 21 04:42:58 PM PDT 24
Finished Jun 21 04:43:00 PM PDT 24
Peak memory 194188 kb
Host smart-6c5fa351-32cc-4460-b546-9d7402e2461c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742987708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.742987708
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.2035092078
Short name T89
Test name
Test status
Simulation time 73202204 ps
CPU time 0.74 seconds
Started Jun 21 04:42:57 PM PDT 24
Finished Jun 21 04:42:59 PM PDT 24
Peak memory 197912 kb
Host smart-f99d47c9-69bc-4cf2-b95a-2c507cec1190
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035092078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.2035092078
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.2250935858
Short name T1235
Test name
Test status
Simulation time 163135298 ps
CPU time 2.01 seconds
Started Jun 21 04:42:49 PM PDT 24
Finished Jun 21 04:42:54 PM PDT 24
Peak memory 199816 kb
Host smart-3bff61e1-2ea5-4a14-b31a-bd41ff61065b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250935858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.2250935858
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.3887937776
Short name T103
Test name
Test status
Simulation time 95143871 ps
CPU time 1.1 seconds
Started Jun 21 04:43:01 PM PDT 24
Finished Jun 21 04:43:04 PM PDT 24
Peak memory 198796 kb
Host smart-d72f29fa-04cf-44ef-8a74-df7ee5d2aaf3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887937776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.3887937776
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3253881130
Short name T1236
Test name
Test status
Simulation time 107996574 ps
CPU time 1.39 seconds
Started Jun 21 04:43:15 PM PDT 24
Finished Jun 21 04:43:21 PM PDT 24
Peak memory 199848 kb
Host smart-273797b1-18f1-497a-9c80-9b672cf9b47a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253881130 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.3253881130
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.1309182147
Short name T1156
Test name
Test status
Simulation time 53402766 ps
CPU time 0.6 seconds
Started Jun 21 04:43:08 PM PDT 24
Finished Jun 21 04:43:12 PM PDT 24
Peak memory 195292 kb
Host smart-1f8bd74b-3ecb-4cb0-97f5-345c86ae5f39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309182147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.1309182147
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.2633506411
Short name T1212
Test name
Test status
Simulation time 28474340 ps
CPU time 0.55 seconds
Started Jun 21 04:42:45 PM PDT 24
Finished Jun 21 04:42:48 PM PDT 24
Peak memory 193940 kb
Host smart-da2ebf29-fa34-468a-9a5e-6df91cf50455
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633506411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.2633506411
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.555051728
Short name T1222
Test name
Test status
Simulation time 15854602 ps
CPU time 0.75 seconds
Started Jun 21 04:42:45 PM PDT 24
Finished Jun 21 04:42:49 PM PDT 24
Peak memory 196836 kb
Host smart-af7b6f6a-5ac5-46aa-bf55-9423133b5c2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555051728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr_
outstanding.555051728
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.2574609513
Short name T1193
Test name
Test status
Simulation time 215033481 ps
CPU time 1.48 seconds
Started Jun 21 04:42:39 PM PDT 24
Finished Jun 21 04:42:41 PM PDT 24
Peak memory 199860 kb
Host smart-a958048b-107f-4621-9b0a-0b74dd156bc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574609513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.2574609513
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.3163706959
Short name T133
Test name
Test status
Simulation time 83851789 ps
CPU time 1.42 seconds
Started Jun 21 04:42:49 PM PDT 24
Finished Jun 21 04:42:53 PM PDT 24
Peak memory 199336 kb
Host smart-72c52c1f-36fd-438b-a6c3-be9aa54c707c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163706959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.3163706959
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.2270110986
Short name T448
Test name
Test status
Simulation time 22845913 ps
CPU time 0.56 seconds
Started Jun 21 04:44:10 PM PDT 24
Finished Jun 21 04:44:14 PM PDT 24
Peak memory 196024 kb
Host smart-338f61b4-91ec-4c4d-953c-1ec6d2e4efb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270110986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2270110986
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.845286609
Short name T595
Test name
Test status
Simulation time 123182493712 ps
CPU time 48.44 seconds
Started Jun 21 04:44:21 PM PDT 24
Finished Jun 21 04:45:15 PM PDT 24
Peak memory 200624 kb
Host smart-046cd6d9-5f3a-457a-a64d-7afdf9c7f166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845286609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.845286609
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.3257706368
Short name T587
Test name
Test status
Simulation time 24673623851 ps
CPU time 16.9 seconds
Started Jun 21 04:44:19 PM PDT 24
Finished Jun 21 04:44:40 PM PDT 24
Peak memory 200216 kb
Host smart-b1d9bb37-bab8-4c26-b788-3d37481ce270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257706368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.3257706368
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_intr.2856131638
Short name T1017
Test name
Test status
Simulation time 6105237000 ps
CPU time 9.16 seconds
Started Jun 21 04:44:10 PM PDT 24
Finished Jun 21 04:44:22 PM PDT 24
Peak memory 197292 kb
Host smart-a07b961e-515f-41be-a687-192897135c8f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856131638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.2856131638
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.3548676669
Short name T663
Test name
Test status
Simulation time 84128520870 ps
CPU time 406.76 seconds
Started Jun 21 04:44:11 PM PDT 24
Finished Jun 21 04:51:00 PM PDT 24
Peak memory 200632 kb
Host smart-596c4b51-ea35-4353-82e2-55cba8a64a4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3548676669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.3548676669
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.2121811263
Short name T437
Test name
Test status
Simulation time 595795071 ps
CPU time 0.87 seconds
Started Jun 21 04:44:15 PM PDT 24
Finished Jun 21 04:44:19 PM PDT 24
Peak memory 196672 kb
Host smart-61615701-122c-48f1-a099-dcb735d8b024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121811263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.2121811263
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_perf.722775495
Short name T1035
Test name
Test status
Simulation time 17686877632 ps
CPU time 760.16 seconds
Started Jun 21 04:44:19 PM PDT 24
Finished Jun 21 04:57:04 PM PDT 24
Peak memory 200600 kb
Host smart-0abb15bb-ca4e-4ef5-b2ea-828b68117782
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=722775495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.722775495
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.3071912018
Short name T910
Test name
Test status
Simulation time 3693631657 ps
CPU time 28.7 seconds
Started Jun 21 04:44:15 PM PDT 24
Finished Jun 21 04:44:47 PM PDT 24
Peak memory 198836 kb
Host smart-2078aa0c-6227-46b7-8402-f41579e29334
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3071912018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.3071912018
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.3592745515
Short name T309
Test name
Test status
Simulation time 63029985574 ps
CPU time 155 seconds
Started Jun 21 04:44:10 PM PDT 24
Finished Jun 21 04:46:48 PM PDT 24
Peak memory 200544 kb
Host smart-1f0b0af4-17ef-40ca-9959-d191e0efe7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592745515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.3592745515
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.3977386386
Short name T841
Test name
Test status
Simulation time 1638575646 ps
CPU time 1.16 seconds
Started Jun 21 04:44:17 PM PDT 24
Finished Jun 21 04:44:22 PM PDT 24
Peak memory 196088 kb
Host smart-3a50ce7f-0031-4d87-aa33-39fd8f9736af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977386386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.3977386386
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.1472436745
Short name T410
Test name
Test status
Simulation time 292791548 ps
CPU time 2.05 seconds
Started Jun 21 04:44:21 PM PDT 24
Finished Jun 21 04:44:28 PM PDT 24
Peak memory 199648 kb
Host smart-54d0e46f-f480-440a-a46d-56418c56b47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472436745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.1472436745
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.1432074998
Short name T726
Test name
Test status
Simulation time 1119689485 ps
CPU time 4.45 seconds
Started Jun 21 04:44:11 PM PDT 24
Finished Jun 21 04:44:18 PM PDT 24
Peak memory 200244 kb
Host smart-5e4fb95f-8626-438f-93f8-e04cdf272036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432074998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.1432074998
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.3727030477
Short name T382
Test name
Test status
Simulation time 52120424001 ps
CPU time 21.75 seconds
Started Jun 21 04:44:21 PM PDT 24
Finished Jun 21 04:44:51 PM PDT 24
Peak memory 200552 kb
Host smart-ca8a6bbb-8541-4563-9a78-eacdde5deb00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727030477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.3727030477
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.3259109944
Short name T1004
Test name
Test status
Simulation time 57550856741 ps
CPU time 89.08 seconds
Started Jun 21 04:44:24 PM PDT 24
Finished Jun 21 04:45:57 PM PDT 24
Peak memory 200520 kb
Host smart-d7dd7f75-094a-41af-95e9-03f3fa6a53b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259109944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.3259109944
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.1882208539
Short name T891
Test name
Test status
Simulation time 9678872496 ps
CPU time 11.42 seconds
Started Jun 21 04:44:48 PM PDT 24
Finished Jun 21 04:45:04 PM PDT 24
Peak memory 200364 kb
Host smart-29261013-8bff-45df-8d2c-ce5833f0978d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882208539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.1882208539
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.279885092
Short name T416
Test name
Test status
Simulation time 47289166838 ps
CPU time 74.81 seconds
Started Jun 21 04:44:15 PM PDT 24
Finished Jun 21 04:45:34 PM PDT 24
Peak memory 200516 kb
Host smart-1c3e5ff9-3a48-419c-b86f-c0959f07317c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279885092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.279885092
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_loopback.2599652835
Short name T487
Test name
Test status
Simulation time 3094576892 ps
CPU time 2.97 seconds
Started Jun 21 04:44:17 PM PDT 24
Finished Jun 21 04:44:24 PM PDT 24
Peak memory 199404 kb
Host smart-d3429d67-66b6-4b33-9cb4-3d331105fef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599652835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.2599652835
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_perf.4130029997
Short name T29
Test name
Test status
Simulation time 21676015049 ps
CPU time 493.17 seconds
Started Jun 21 04:44:12 PM PDT 24
Finished Jun 21 04:52:28 PM PDT 24
Peak memory 200572 kb
Host smart-0d07eabf-5435-459b-bbd5-4df63aab7208
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4130029997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.4130029997
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.271912034
Short name T986
Test name
Test status
Simulation time 3784861454 ps
CPU time 7.72 seconds
Started Jun 21 04:44:19 PM PDT 24
Finished Jun 21 04:44:32 PM PDT 24
Peak memory 199756 kb
Host smart-0c67774a-dfa0-4557-8c6f-9782c1ac4ae0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=271912034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.271912034
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.351123726
Short name T454
Test name
Test status
Simulation time 8824904564 ps
CPU time 15.3 seconds
Started Jun 21 04:44:44 PM PDT 24
Finished Jun 21 04:45:03 PM PDT 24
Peak memory 200600 kb
Host smart-e1e69660-97bb-4acc-9e62-8cb009437a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351123726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.351123726
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.923778742
Short name T674
Test name
Test status
Simulation time 4588995088 ps
CPU time 1.15 seconds
Started Jun 21 04:44:17 PM PDT 24
Finished Jun 21 04:44:22 PM PDT 24
Peak memory 196692 kb
Host smart-ff4a89d3-44fd-4d50-8b68-154916f1ec97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923778742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.923778742
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.4087114622
Short name T36
Test name
Test status
Simulation time 38982087 ps
CPU time 0.79 seconds
Started Jun 21 04:44:21 PM PDT 24
Finished Jun 21 04:44:27 PM PDT 24
Peak memory 218836 kb
Host smart-523a141e-2a09-4313-b380-76cc0dddfb1a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087114622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.4087114622
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.1187146070
Short name T959
Test name
Test status
Simulation time 713364520 ps
CPU time 2.85 seconds
Started Jun 21 04:44:10 PM PDT 24
Finished Jun 21 04:44:15 PM PDT 24
Peak memory 198856 kb
Host smart-a054c9d1-7d65-4ba2-acb5-c694a7742b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187146070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.1187146070
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.989656741
Short name T42
Test name
Test status
Simulation time 10406240424 ps
CPU time 152.37 seconds
Started Jun 21 04:44:11 PM PDT 24
Finished Jun 21 04:46:47 PM PDT 24
Peak memory 208904 kb
Host smart-bffdcbc8-253e-4572-9ceb-1436f5f3406c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989656741 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.989656741
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.2166360765
Short name T924
Test name
Test status
Simulation time 6723154866 ps
CPU time 27.74 seconds
Started Jun 21 04:44:18 PM PDT 24
Finished Jun 21 04:44:50 PM PDT 24
Peak memory 200520 kb
Host smart-fc362676-bfd8-49ba-8ea3-57235d0e5369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166360765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.2166360765
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_alert_test.707876519
Short name T7
Test name
Test status
Simulation time 46269393 ps
CPU time 0.56 seconds
Started Jun 21 04:44:54 PM PDT 24
Finished Jun 21 04:44:58 PM PDT 24
Peak memory 196008 kb
Host smart-84b3e994-a76a-4c96-945b-273843c711a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707876519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.707876519
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.2677252556
Short name T356
Test name
Test status
Simulation time 39978925384 ps
CPU time 5.6 seconds
Started Jun 21 04:44:51 PM PDT 24
Finished Jun 21 04:45:00 PM PDT 24
Peak memory 199764 kb
Host smart-08020f84-e7f9-4878-93ef-569b3f4adce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677252556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.2677252556
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.980598376
Short name T611
Test name
Test status
Simulation time 116741060764 ps
CPU time 175.94 seconds
Started Jun 21 04:44:54 PM PDT 24
Finished Jun 21 04:47:53 PM PDT 24
Peak memory 200560 kb
Host smart-2400b00f-58bc-4fed-b984-546faae2a785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980598376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.980598376
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_intr.3320322129
Short name T1074
Test name
Test status
Simulation time 29304806489 ps
CPU time 26.22 seconds
Started Jun 21 04:44:43 PM PDT 24
Finished Jun 21 04:45:12 PM PDT 24
Peak memory 200464 kb
Host smart-e3c71b19-37b1-4189-b848-c283a3921379
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320322129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.3320322129
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.2492818950
Short name T671
Test name
Test status
Simulation time 116959924240 ps
CPU time 855.03 seconds
Started Jun 21 04:44:55 PM PDT 24
Finished Jun 21 04:59:13 PM PDT 24
Peak memory 200608 kb
Host smart-115e2210-d776-4a0f-8de7-66e6da66ae4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2492818950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.2492818950
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.3389644357
Short name T836
Test name
Test status
Simulation time 10464073093 ps
CPU time 9.53 seconds
Started Jun 21 04:44:44 PM PDT 24
Finished Jun 21 04:44:55 PM PDT 24
Peak memory 200528 kb
Host smart-d6110c16-3741-4fc3-b451-db46b7a65380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389644357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.3389644357
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_perf.3867288867
Short name T681
Test name
Test status
Simulation time 9072230359 ps
CPU time 571.25 seconds
Started Jun 21 04:44:50 PM PDT 24
Finished Jun 21 04:54:25 PM PDT 24
Peak memory 200552 kb
Host smart-acfd2480-81f0-4394-9beb-d55b8fcc304c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3867288867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.3867288867
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.281566501
Short name T449
Test name
Test status
Simulation time 7229069214 ps
CPU time 16.81 seconds
Started Jun 21 04:44:49 PM PDT 24
Finished Jun 21 04:45:10 PM PDT 24
Peak memory 200404 kb
Host smart-be4807e4-320e-45df-b35b-567898d18211
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=281566501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.281566501
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.4189253046
Short name T616
Test name
Test status
Simulation time 63787470250 ps
CPU time 87.29 seconds
Started Jun 21 04:44:48 PM PDT 24
Finished Jun 21 04:46:20 PM PDT 24
Peak memory 200568 kb
Host smart-381ac011-c0cb-463b-b1f1-1b4421c88b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189253046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.4189253046
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.1886861799
Short name T969
Test name
Test status
Simulation time 6328527997 ps
CPU time 10.62 seconds
Started Jun 21 04:44:45 PM PDT 24
Finished Jun 21 04:45:00 PM PDT 24
Peak memory 196632 kb
Host smart-2a9a3bca-fe9e-4741-bd6c-bb00af4a688d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886861799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.1886861799
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.2140951112
Short name T366
Test name
Test status
Simulation time 500708529 ps
CPU time 1.26 seconds
Started Jun 21 04:44:50 PM PDT 24
Finished Jun 21 04:44:56 PM PDT 24
Peak memory 199068 kb
Host smart-b06bf24e-54ae-417c-99b2-d7f198dc393d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140951112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.2140951112
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.2659601134
Short name T914
Test name
Test status
Simulation time 653638806221 ps
CPU time 814.09 seconds
Started Jun 21 04:44:45 PM PDT 24
Finished Jun 21 04:58:22 PM PDT 24
Peak memory 200548 kb
Host smart-10b9245d-98e3-4866-b209-73e80e6d8bea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659601134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.2659601134
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.1901773843
Short name T73
Test name
Test status
Simulation time 83927715147 ps
CPU time 685.88 seconds
Started Jun 21 04:44:43 PM PDT 24
Finished Jun 21 04:56:11 PM PDT 24
Peak memory 217036 kb
Host smart-bfb5e564-e102-4063-a318-babd09387dbc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901773843 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.1901773843
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.3717622293
Short name T596
Test name
Test status
Simulation time 1147084397 ps
CPU time 3.94 seconds
Started Jun 21 04:44:45 PM PDT 24
Finished Jun 21 04:44:53 PM PDT 24
Peak memory 200508 kb
Host smart-3d9b9189-c088-41e9-a586-33f02b35c77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717622293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.3717622293
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.900805356
Short name T642
Test name
Test status
Simulation time 4405287661 ps
CPU time 7.6 seconds
Started Jun 21 04:44:53 PM PDT 24
Finished Jun 21 04:45:04 PM PDT 24
Peak memory 199088 kb
Host smart-6fdff21f-b8e9-46a3-99b5-6af9c7005c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900805356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.900805356
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.922282491
Short name T714
Test name
Test status
Simulation time 143796028717 ps
CPU time 75.01 seconds
Started Jun 21 04:47:22 PM PDT 24
Finished Jun 21 04:48:42 PM PDT 24
Peak memory 200576 kb
Host smart-acc1521e-5d4c-4686-9195-1c9173ed9f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922282491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.922282491
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.1661542190
Short name T161
Test name
Test status
Simulation time 162328878572 ps
CPU time 27.52 seconds
Started Jun 21 04:47:23 PM PDT 24
Finished Jun 21 04:47:56 PM PDT 24
Peak memory 200600 kb
Host smart-a5b9a520-a9af-4a39-8358-d0dbfe7e7079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661542190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.1661542190
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.1687000218
Short name T191
Test name
Test status
Simulation time 35821301682 ps
CPU time 33.28 seconds
Started Jun 21 04:47:24 PM PDT 24
Finished Jun 21 04:48:05 PM PDT 24
Peak memory 200628 kb
Host smart-5903c002-8b4e-41ab-8c04-3a63071522b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687000218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.1687000218
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.201150208
Short name T112
Test name
Test status
Simulation time 20922566143 ps
CPU time 21.09 seconds
Started Jun 21 04:47:24 PM PDT 24
Finished Jun 21 04:47:52 PM PDT 24
Peak memory 200628 kb
Host smart-6c4c8c68-f244-49f5-9965-d63782fe4300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201150208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.201150208
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.888503621
Short name T940
Test name
Test status
Simulation time 96935615598 ps
CPU time 155.97 seconds
Started Jun 21 04:47:29 PM PDT 24
Finished Jun 21 04:50:14 PM PDT 24
Peak memory 200420 kb
Host smart-8074516d-996c-4eb9-b4d4-153155f87873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888503621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.888503621
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.1221325131
Short name T761
Test name
Test status
Simulation time 92567765127 ps
CPU time 45.42 seconds
Started Jun 21 04:47:30 PM PDT 24
Finished Jun 21 04:48:24 PM PDT 24
Peak memory 200628 kb
Host smart-27dca14b-7cc6-4e35-9086-aecaf5aca484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221325131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.1221325131
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.3629444232
Short name T300
Test name
Test status
Simulation time 198469275628 ps
CPU time 48.59 seconds
Started Jun 21 04:47:26 PM PDT 24
Finished Jun 21 04:48:22 PM PDT 24
Peak memory 200592 kb
Host smart-f31f3e3a-d76e-48b9-b066-eaf3216700f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629444232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.3629444232
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.4241380978
Short name T981
Test name
Test status
Simulation time 60473812606 ps
CPU time 53.86 seconds
Started Jun 21 04:47:24 PM PDT 24
Finished Jun 21 04:48:24 PM PDT 24
Peak memory 200624 kb
Host smart-6a89ce85-26a9-42ae-ad7d-ddb9fcdd7825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241380978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.4241380978
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.2640967258
Short name T824
Test name
Test status
Simulation time 12568469 ps
CPU time 0.59 seconds
Started Jun 21 04:44:53 PM PDT 24
Finished Jun 21 04:44:57 PM PDT 24
Peak memory 195764 kb
Host smart-eb03cc08-f516-4f52-912b-6f94679734f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640967258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.2640967258
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.3208543046
Short name T1043
Test name
Test status
Simulation time 310660621839 ps
CPU time 30.3 seconds
Started Jun 21 04:44:54 PM PDT 24
Finished Jun 21 04:45:28 PM PDT 24
Peak memory 200652 kb
Host smart-2bdee097-9139-4d25-a24c-a49f1f570017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208543046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.3208543046
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.3834577936
Short name T1067
Test name
Test status
Simulation time 104726997952 ps
CPU time 10.18 seconds
Started Jun 21 04:44:43 PM PDT 24
Finished Jun 21 04:44:55 PM PDT 24
Peak memory 200292 kb
Host smart-1d732157-6509-4d8a-b627-fd0a253593aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834577936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.3834577936
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.748389217
Short name T862
Test name
Test status
Simulation time 141093517179 ps
CPU time 14.91 seconds
Started Jun 21 04:44:49 PM PDT 24
Finished Jun 21 04:45:08 PM PDT 24
Peak memory 200588 kb
Host smart-a5421b63-5e15-42e6-b3a0-77e1688742a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748389217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.748389217
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.63333756
Short name T918
Test name
Test status
Simulation time 14125392328 ps
CPU time 10.42 seconds
Started Jun 21 04:44:50 PM PDT 24
Finished Jun 21 04:45:04 PM PDT 24
Peak memory 198444 kb
Host smart-df34066f-35e8-479a-b0d3-930dd0170ed1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63333756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.63333756
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.3889045201
Short name T409
Test name
Test status
Simulation time 79955791351 ps
CPU time 361.31 seconds
Started Jun 21 04:44:51 PM PDT 24
Finished Jun 21 04:50:56 PM PDT 24
Peak memory 200640 kb
Host smart-98b4e718-e0cb-4a84-ac6e-f4c58b2e51b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3889045201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.3889045201
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.787790857
Short name T422
Test name
Test status
Simulation time 3119957004 ps
CPU time 2.07 seconds
Started Jun 21 04:44:45 PM PDT 24
Finished Jun 21 04:44:50 PM PDT 24
Peak memory 198900 kb
Host smart-308e0aaf-d648-4141-9672-52dda066e447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787790857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.787790857
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_perf.1136595675
Short name T92
Test name
Test status
Simulation time 7917555667 ps
CPU time 298 seconds
Started Jun 21 04:44:46 PM PDT 24
Finished Jun 21 04:49:48 PM PDT 24
Peak memory 200556 kb
Host smart-d421b885-638b-4c65-8ddd-6e000118b46f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1136595675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.1136595675
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.3117822401
Short name T497
Test name
Test status
Simulation time 7218699021 ps
CPU time 63.93 seconds
Started Jun 21 04:44:53 PM PDT 24
Finished Jun 21 04:46:00 PM PDT 24
Peak memory 199308 kb
Host smart-44a967b3-a71f-474a-a76b-4efcf35aba38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3117822401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.3117822401
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.421036712
Short name T967
Test name
Test status
Simulation time 74152835450 ps
CPU time 28.34 seconds
Started Jun 21 04:44:44 PM PDT 24
Finished Jun 21 04:45:15 PM PDT 24
Peak memory 200656 kb
Host smart-7ebda684-72e9-4622-86d5-2a94720f63ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421036712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.421036712
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.2230622484
Short name T370
Test name
Test status
Simulation time 4629068532 ps
CPU time 1.17 seconds
Started Jun 21 04:45:05 PM PDT 24
Finished Jun 21 04:45:08 PM PDT 24
Peak memory 196728 kb
Host smart-7c5a2850-211d-496e-a484-64f18e2c4d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230622484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.2230622484
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.4267299194
Short name T791
Test name
Test status
Simulation time 517029442 ps
CPU time 2.42 seconds
Started Jun 21 04:44:58 PM PDT 24
Finished Jun 21 04:45:04 PM PDT 24
Peak memory 199356 kb
Host smart-0fdc82a7-9484-41e5-8363-2b41bd66631f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267299194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.4267299194
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.1078703271
Short name T503
Test name
Test status
Simulation time 228983694540 ps
CPU time 580.17 seconds
Started Jun 21 04:44:45 PM PDT 24
Finished Jun 21 04:54:29 PM PDT 24
Peak memory 200580 kb
Host smart-e1e9d84a-248d-4e08-983b-7d47dce55011
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078703271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.1078703271
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.750346474
Short name T597
Test name
Test status
Simulation time 405658340 ps
CPU time 1.47 seconds
Started Jun 21 04:44:43 PM PDT 24
Finished Jun 21 04:44:46 PM PDT 24
Peak memory 199224 kb
Host smart-ecc12505-6bd4-4a8e-9581-a9d2d6220fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750346474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.750346474
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.3605656283
Short name T650
Test name
Test status
Simulation time 47738618172 ps
CPU time 100.61 seconds
Started Jun 21 04:44:45 PM PDT 24
Finished Jun 21 04:46:28 PM PDT 24
Peak memory 200624 kb
Host smart-3751d5c9-14b3-418c-b4bf-f2b579752541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605656283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.3605656283
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.677623111
Short name T982
Test name
Test status
Simulation time 142481224301 ps
CPU time 199.06 seconds
Started Jun 21 04:47:26 PM PDT 24
Finished Jun 21 04:50:52 PM PDT 24
Peak memory 200648 kb
Host smart-006989f7-1c14-4dba-962d-7de1769c66e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677623111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.677623111
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.160146967
Short name T1071
Test name
Test status
Simulation time 195285348368 ps
CPU time 117 seconds
Started Jun 21 04:47:29 PM PDT 24
Finished Jun 21 04:49:34 PM PDT 24
Peak memory 200744 kb
Host smart-871b12d6-929e-4c5c-88c9-7b3300b9fa22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160146967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.160146967
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.1953668332
Short name T198
Test name
Test status
Simulation time 170686442363 ps
CPU time 111.05 seconds
Started Jun 21 04:47:26 PM PDT 24
Finished Jun 21 04:49:25 PM PDT 24
Peak memory 200540 kb
Host smart-ab038cb0-e061-4f31-95d5-f6f4fb0cf0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953668332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.1953668332
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.2099407815
Short name T202
Test name
Test status
Simulation time 76171597860 ps
CPU time 63.82 seconds
Started Jun 21 04:47:29 PM PDT 24
Finished Jun 21 04:48:41 PM PDT 24
Peak memory 200196 kb
Host smart-d6348b4e-18f7-49a5-bf87-e3bdb3f42cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099407815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.2099407815
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.22347683
Short name T1037
Test name
Test status
Simulation time 326866841805 ps
CPU time 74.79 seconds
Started Jun 21 04:47:28 PM PDT 24
Finished Jun 21 04:48:52 PM PDT 24
Peak memory 200224 kb
Host smart-e2b6534e-f269-450a-b3c3-f7853ec5719a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22347683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.22347683
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.1137267048
Short name T1048
Test name
Test status
Simulation time 4582336390 ps
CPU time 9.1 seconds
Started Jun 21 04:47:25 PM PDT 24
Finished Jun 21 04:47:42 PM PDT 24
Peak memory 200452 kb
Host smart-5dfe5d9b-bf79-48d1-bd1e-735f512306f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137267048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.1137267048
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.909071723
Short name T236
Test name
Test status
Simulation time 15082727440 ps
CPU time 16.7 seconds
Started Jun 21 04:47:30 PM PDT 24
Finished Jun 21 04:47:55 PM PDT 24
Peak memory 200620 kb
Host smart-9d55af9e-8555-4d3f-b1ca-7d033dddac9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909071723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.909071723
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.22974418
Short name T116
Test name
Test status
Simulation time 25436073310 ps
CPU time 9.95 seconds
Started Jun 21 04:47:30 PM PDT 24
Finished Jun 21 04:47:48 PM PDT 24
Peak memory 200744 kb
Host smart-918286d2-b5b9-490b-99ab-789f81063c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22974418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.22974418
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.2857593548
Short name T1100
Test name
Test status
Simulation time 15992790 ps
CPU time 0.59 seconds
Started Jun 21 04:44:50 PM PDT 24
Finished Jun 21 04:44:55 PM PDT 24
Peak memory 195964 kb
Host smart-7e1c1d37-93a3-46e1-b4cb-f091c95177d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857593548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.2857593548
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.3462233345
Short name T424
Test name
Test status
Simulation time 50680081120 ps
CPU time 85.43 seconds
Started Jun 21 04:44:52 PM PDT 24
Finished Jun 21 04:46:21 PM PDT 24
Peak memory 200604 kb
Host smart-6cf93d51-f132-4e02-9be2-8f50d79bbd48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462233345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.3462233345
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.2574276443
Short name T966
Test name
Test status
Simulation time 24823000309 ps
CPU time 41.52 seconds
Started Jun 21 04:44:53 PM PDT 24
Finished Jun 21 04:45:38 PM PDT 24
Peak memory 200620 kb
Host smart-e0029891-a1d4-4630-83b7-35688ad5663f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574276443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.2574276443
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.2396014118
Short name T911
Test name
Test status
Simulation time 219109040264 ps
CPU time 21.97 seconds
Started Jun 21 04:44:53 PM PDT 24
Finished Jun 21 04:45:19 PM PDT 24
Peak memory 200576 kb
Host smart-95a3ae8d-b618-4daf-9953-4e2a0b72db00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396014118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.2396014118
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.3213515669
Short name T371
Test name
Test status
Simulation time 17459224348 ps
CPU time 27.48 seconds
Started Jun 21 04:44:54 PM PDT 24
Finished Jun 21 04:45:25 PM PDT 24
Peak memory 197592 kb
Host smart-a71079fa-1cc0-4a54-bda8-03727a99895e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213515669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.3213515669
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_loopback.2989492746
Short name T1038
Test name
Test status
Simulation time 10403002787 ps
CPU time 4.87 seconds
Started Jun 21 04:44:52 PM PDT 24
Finished Jun 21 04:45:01 PM PDT 24
Peak memory 199368 kb
Host smart-0c507e07-4a16-46b3-8185-ef9af8f31622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989492746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.2989492746
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.481504496
Short name T430
Test name
Test status
Simulation time 4011778822 ps
CPU time 6.61 seconds
Started Jun 21 04:44:49 PM PDT 24
Finished Jun 21 04:45:00 PM PDT 24
Peak memory 197888 kb
Host smart-908e3d27-d308-4b78-9cd8-1c6e958ecadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481504496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.481504496
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.2422129601
Short name T528
Test name
Test status
Simulation time 9227603043 ps
CPU time 334.76 seconds
Started Jun 21 04:44:52 PM PDT 24
Finished Jun 21 04:50:31 PM PDT 24
Peak memory 200652 kb
Host smart-0f62c690-75ec-403a-8656-39a9168748ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2422129601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.2422129601
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.4179976124
Short name T348
Test name
Test status
Simulation time 6001868890 ps
CPU time 8.1 seconds
Started Jun 21 04:44:50 PM PDT 24
Finished Jun 21 04:45:02 PM PDT 24
Peak memory 199412 kb
Host smart-eda1e28a-792b-4723-8a4a-2af06bd82378
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4179976124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.4179976124
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.1716768148
Short name T971
Test name
Test status
Simulation time 23712436732 ps
CPU time 17.81 seconds
Started Jun 21 04:44:53 PM PDT 24
Finished Jun 21 04:45:14 PM PDT 24
Peak memory 200552 kb
Host smart-767a4b01-0aa8-4a7e-b1b0-df681f228da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716768148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.1716768148
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.3774041371
Short name T888
Test name
Test status
Simulation time 5728107116 ps
CPU time 1.49 seconds
Started Jun 21 04:44:52 PM PDT 24
Finished Jun 21 04:44:57 PM PDT 24
Peak memory 196876 kb
Host smart-3a8ba560-efb6-46ba-96fa-7aa5c982fd8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774041371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.3774041371
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.3883186774
Short name T788
Test name
Test status
Simulation time 669615042 ps
CPU time 1.48 seconds
Started Jun 21 04:44:45 PM PDT 24
Finished Jun 21 04:44:50 PM PDT 24
Peak memory 199524 kb
Host smart-1b265b84-397d-495f-b8e7-3fd2321e4917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883186774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.3883186774
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.2953003202
Short name T980
Test name
Test status
Simulation time 177819398042 ps
CPU time 871.87 seconds
Started Jun 21 04:44:49 PM PDT 24
Finished Jun 21 04:59:25 PM PDT 24
Peak memory 217056 kb
Host smart-2964fc1b-e220-485e-8dbd-e20b4a1f8860
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953003202 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.2953003202
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.3529658994
Short name T740
Test name
Test status
Simulation time 1441137167 ps
CPU time 3.69 seconds
Started Jun 21 04:44:53 PM PDT 24
Finished Jun 21 04:45:01 PM PDT 24
Peak memory 198988 kb
Host smart-97a8e905-96e0-4119-893e-e5f2ca27c517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529658994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.3529658994
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.409397629
Short name T589
Test name
Test status
Simulation time 18600963680 ps
CPU time 19.78 seconds
Started Jun 21 04:44:49 PM PDT 24
Finished Jun 21 04:45:12 PM PDT 24
Peak memory 200628 kb
Host smart-752800f9-836b-46c2-b385-e0861945a246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409397629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.409397629
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.598519688
Short name T604
Test name
Test status
Simulation time 115961576339 ps
CPU time 23.88 seconds
Started Jun 21 04:47:29 PM PDT 24
Finished Jun 21 04:48:02 PM PDT 24
Peak memory 200800 kb
Host smart-495df4eb-cd1d-43ab-9528-dfe472d57faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598519688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.598519688
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.382473172
Short name T335
Test name
Test status
Simulation time 18121290714 ps
CPU time 27.44 seconds
Started Jun 21 04:47:27 PM PDT 24
Finished Jun 21 04:48:03 PM PDT 24
Peak memory 200592 kb
Host smart-60f04528-aae7-4964-bd82-b2be01157302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382473172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.382473172
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.762048270
Short name T58
Test name
Test status
Simulation time 106264982544 ps
CPU time 90.74 seconds
Started Jun 21 04:47:29 PM PDT 24
Finished Jun 21 04:49:09 PM PDT 24
Peak memory 200564 kb
Host smart-07f01140-9a21-4493-9a3f-791ee6999a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762048270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.762048270
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.3154150089
Short name T486
Test name
Test status
Simulation time 110402479675 ps
CPU time 42.99 seconds
Started Jun 21 04:47:28 PM PDT 24
Finished Jun 21 04:48:19 PM PDT 24
Peak memory 200688 kb
Host smart-33b46ea7-eba7-4b9e-aa43-bf482e3be91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154150089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.3154150089
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.2737026422
Short name T150
Test name
Test status
Simulation time 34967538377 ps
CPU time 30.13 seconds
Started Jun 21 04:47:28 PM PDT 24
Finished Jun 21 04:48:07 PM PDT 24
Peak memory 200576 kb
Host smart-cac3bf95-bfaa-4d82-8d3e-b20b44f08f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737026422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.2737026422
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.2559497440
Short name T653
Test name
Test status
Simulation time 108882394384 ps
CPU time 41.03 seconds
Started Jun 21 04:47:18 PM PDT 24
Finished Jun 21 04:48:01 PM PDT 24
Peak memory 200620 kb
Host smart-eefc8f72-07aa-49b5-b928-8fec450666cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559497440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.2559497440
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.3238132188
Short name T965
Test name
Test status
Simulation time 116057995101 ps
CPU time 132.19 seconds
Started Jun 21 04:47:29 PM PDT 24
Finished Jun 21 04:49:50 PM PDT 24
Peak memory 200660 kb
Host smart-f7749642-dcfd-43a8-955f-bee7327ccc2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238132188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.3238132188
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.1727658317
Short name T715
Test name
Test status
Simulation time 37908895 ps
CPU time 0.59 seconds
Started Jun 21 04:45:03 PM PDT 24
Finished Jun 21 04:45:06 PM PDT 24
Peak memory 195908 kb
Host smart-df5f6b7a-8ee7-43fe-bece-2d06ea16ecf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727658317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.1727658317
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.1421659076
Short name T956
Test name
Test status
Simulation time 28633909923 ps
CPU time 40.43 seconds
Started Jun 21 04:44:52 PM PDT 24
Finished Jun 21 04:45:36 PM PDT 24
Peak memory 200624 kb
Host smart-715348b0-d5b6-464b-8793-5b8d04587f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421659076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.1421659076
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.1887509495
Short name T52
Test name
Test status
Simulation time 14272515162 ps
CPU time 24.33 seconds
Started Jun 21 04:44:53 PM PDT 24
Finished Jun 21 04:45:22 PM PDT 24
Peak memory 200524 kb
Host smart-1c0cedce-fdde-45de-b741-fdc088e67d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887509495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.1887509495
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.2097024128
Short name T331
Test name
Test status
Simulation time 43764573379 ps
CPU time 130.25 seconds
Started Jun 21 04:44:55 PM PDT 24
Finished Jun 21 04:47:09 PM PDT 24
Peak memory 200632 kb
Host smart-6d6d38a0-c846-406a-b8ec-1208bec9f4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097024128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.2097024128
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.1216369521
Short name T732
Test name
Test status
Simulation time 41702043263 ps
CPU time 69 seconds
Started Jun 21 04:44:56 PM PDT 24
Finished Jun 21 04:46:09 PM PDT 24
Peak memory 200468 kb
Host smart-fb733a87-46e7-4eac-9d85-662fb0dad344
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216369521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.1216369521
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.2354876823
Short name T961
Test name
Test status
Simulation time 148776960133 ps
CPU time 297.75 seconds
Started Jun 21 04:44:48 PM PDT 24
Finished Jun 21 04:49:49 PM PDT 24
Peak memory 200672 kb
Host smart-0dbc62fa-2a74-48a9-892f-0e98bc57d9bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2354876823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.2354876823
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.816689857
Short name T2
Test name
Test status
Simulation time 8414212539 ps
CPU time 6.73 seconds
Started Jun 21 04:44:53 PM PDT 24
Finished Jun 21 04:45:04 PM PDT 24
Peak memory 200564 kb
Host smart-88306823-7ab6-4d78-896e-9d88b6c8a64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816689857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.816689857
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_perf.809290397
Short name T53
Test name
Test status
Simulation time 21017262490 ps
CPU time 908.82 seconds
Started Jun 21 04:45:01 PM PDT 24
Finished Jun 21 05:00:12 PM PDT 24
Peak memory 200560 kb
Host smart-82acc515-0629-4230-9ef3-e9b7637e3163
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=809290397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.809290397
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.3824211419
Short name T795
Test name
Test status
Simulation time 5757205519 ps
CPU time 13.05 seconds
Started Jun 21 04:44:57 PM PDT 24
Finished Jun 21 04:45:13 PM PDT 24
Peak memory 199320 kb
Host smart-d6244d4c-4f6f-49ad-9d93-1c7fdce83026
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3824211419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.3824211419
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.4081129762
Short name T923
Test name
Test status
Simulation time 62647481083 ps
CPU time 41.02 seconds
Started Jun 21 04:44:53 PM PDT 24
Finished Jun 21 04:45:38 PM PDT 24
Peak memory 200660 kb
Host smart-e135fbf4-ede0-4dc5-b006-d93c315357cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081129762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.4081129762
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.771294747
Short name T286
Test name
Test status
Simulation time 32221424537 ps
CPU time 48.86 seconds
Started Jun 21 04:44:59 PM PDT 24
Finished Jun 21 04:45:50 PM PDT 24
Peak memory 197008 kb
Host smart-432800d7-2722-4e0f-8def-b0d71d461ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771294747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.771294747
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.959518525
Short name T645
Test name
Test status
Simulation time 651469407 ps
CPU time 4.38 seconds
Started Jun 21 04:45:03 PM PDT 24
Finished Jun 21 04:45:10 PM PDT 24
Peak memory 200112 kb
Host smart-eed010ac-0448-4da4-9b4a-fb1bc8eb3edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959518525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.959518525
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.4144596199
Short name T128
Test name
Test status
Simulation time 94438600940 ps
CPU time 449.26 seconds
Started Jun 21 04:45:00 PM PDT 24
Finished Jun 21 04:52:31 PM PDT 24
Peak memory 200488 kb
Host smart-983a7175-7e05-4575-b2ad-783e090fb8ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144596199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.4144596199
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.2895029791
Short name T1000
Test name
Test status
Simulation time 44253149003 ps
CPU time 858.48 seconds
Started Jun 21 04:45:10 PM PDT 24
Finished Jun 21 04:59:31 PM PDT 24
Peak memory 217000 kb
Host smart-aed71a64-1f62-45fe-9a8c-096bc0089b1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895029791 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.2895029791
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.3268800803
Short name T878
Test name
Test status
Simulation time 7322880321 ps
CPU time 11.77 seconds
Started Jun 21 04:44:52 PM PDT 24
Finished Jun 21 04:45:08 PM PDT 24
Peak memory 200668 kb
Host smart-5adae8b7-0abc-4e6b-a11d-ee56b1488fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268800803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.3268800803
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.1096036120
Short name T1041
Test name
Test status
Simulation time 74550156349 ps
CPU time 83.04 seconds
Started Jun 21 04:44:50 PM PDT 24
Finished Jun 21 04:46:17 PM PDT 24
Peak memory 200564 kb
Host smart-3bf12588-2c0b-4c67-8341-a2487a2ef0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096036120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.1096036120
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.2806119735
Short name T850
Test name
Test status
Simulation time 119539744740 ps
CPU time 378.32 seconds
Started Jun 21 04:47:29 PM PDT 24
Finished Jun 21 04:53:56 PM PDT 24
Peak memory 200632 kb
Host smart-edfc39e0-3c25-4555-b65c-06ef17a119b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806119735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.2806119735
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.119664911
Short name T748
Test name
Test status
Simulation time 98268835367 ps
CPU time 18.45 seconds
Started Jun 21 04:47:22 PM PDT 24
Finished Jun 21 04:47:47 PM PDT 24
Peak memory 200576 kb
Host smart-642a9455-1bf7-44a8-bbe3-27cdf2a85345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119664911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.119664911
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.35695427
Short name T762
Test name
Test status
Simulation time 51347271355 ps
CPU time 25.11 seconds
Started Jun 21 04:47:23 PM PDT 24
Finished Jun 21 04:47:54 PM PDT 24
Peak memory 200620 kb
Host smart-ad11f4c8-bea7-4a84-83f0-6a54d3d55242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35695427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.35695427
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.2827477851
Short name T466
Test name
Test status
Simulation time 104572327110 ps
CPU time 85.41 seconds
Started Jun 21 04:47:23 PM PDT 24
Finished Jun 21 04:48:54 PM PDT 24
Peak memory 200560 kb
Host smart-d20c1668-14a8-4894-a808-09d646c53258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827477851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.2827477851
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.1705007139
Short name T566
Test name
Test status
Simulation time 73036496816 ps
CPU time 229.53 seconds
Started Jun 21 04:47:27 PM PDT 24
Finished Jun 21 04:51:24 PM PDT 24
Peak memory 200504 kb
Host smart-a10b84e8-f31e-4cef-9468-41e6fcdcd980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705007139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.1705007139
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.1147655629
Short name T215
Test name
Test status
Simulation time 27672059969 ps
CPU time 29.55 seconds
Started Jun 21 04:47:21 PM PDT 24
Finished Jun 21 04:47:54 PM PDT 24
Peak memory 200620 kb
Host smart-10f4f5b6-d622-44ad-8829-61dea266b666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147655629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.1147655629
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.1136678493
Short name T1028
Test name
Test status
Simulation time 45736307061 ps
CPU time 17.85 seconds
Started Jun 21 04:47:21 PM PDT 24
Finished Jun 21 04:47:44 PM PDT 24
Peak memory 200636 kb
Host smart-c2ff3f59-e756-4c96-bc09-01a7c6bb3886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136678493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.1136678493
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.3886303449
Short name T269
Test name
Test status
Simulation time 18984703263 ps
CPU time 31.29 seconds
Started Jun 21 04:47:23 PM PDT 24
Finished Jun 21 04:48:00 PM PDT 24
Peak memory 200664 kb
Host smart-062a76d4-b8c4-4499-bcc4-1f2a62740759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886303449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.3886303449
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.661243218
Short name T311
Test name
Test status
Simulation time 106393147160 ps
CPU time 227.27 seconds
Started Jun 21 04:47:18 PM PDT 24
Finished Jun 21 04:51:08 PM PDT 24
Peak memory 200716 kb
Host smart-f590a714-2e46-400c-a3d2-35c58affb16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661243218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.661243218
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.3428442501
Short name T359
Test name
Test status
Simulation time 30721698 ps
CPU time 0.55 seconds
Started Jun 21 04:44:53 PM PDT 24
Finished Jun 21 04:44:58 PM PDT 24
Peak memory 196000 kb
Host smart-1efc3454-cc09-4f23-a1b1-2616bb8e81d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428442501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.3428442501
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.3136337494
Short name T944
Test name
Test status
Simulation time 22684041456 ps
CPU time 44.49 seconds
Started Jun 21 04:44:59 PM PDT 24
Finished Jun 21 04:45:46 PM PDT 24
Peak memory 200652 kb
Host smart-455a4130-40ca-4297-821c-708a236a1ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136337494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.3136337494
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.1622864408
Short name T701
Test name
Test status
Simulation time 171948542115 ps
CPU time 35.43 seconds
Started Jun 21 04:44:58 PM PDT 24
Finished Jun 21 04:45:36 PM PDT 24
Peak memory 200580 kb
Host smart-c9b92a3b-4232-49bf-a2a2-307a68a45a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622864408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.1622864408
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.614867397
Short name T819
Test name
Test status
Simulation time 30786218485 ps
CPU time 27.82 seconds
Started Jun 21 04:44:58 PM PDT 24
Finished Jun 21 04:45:28 PM PDT 24
Peak memory 200696 kb
Host smart-6538bf43-1012-449c-a192-0384d40d0983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614867397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.614867397
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.1406463851
Short name T493
Test name
Test status
Simulation time 47128037801 ps
CPU time 86.19 seconds
Started Jun 21 04:44:57 PM PDT 24
Finished Jun 21 04:46:26 PM PDT 24
Peak memory 200604 kb
Host smart-e4f2d55b-d63c-4f74-aad7-c3d6e0483309
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406463851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.1406463851
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.4180811234
Short name T562
Test name
Test status
Simulation time 90455559783 ps
CPU time 130.8 seconds
Started Jun 21 04:45:03 PM PDT 24
Finished Jun 21 04:47:16 PM PDT 24
Peak memory 200608 kb
Host smart-22488a10-fbbd-4327-a76a-dcb79f95fb42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4180811234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.4180811234
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.3792990082
Short name T419
Test name
Test status
Simulation time 11528734267 ps
CPU time 16.16 seconds
Started Jun 21 04:45:10 PM PDT 24
Finished Jun 21 04:45:28 PM PDT 24
Peak memory 200488 kb
Host smart-b106203e-b420-40fe-a98e-e51bc5694001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792990082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.3792990082
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_perf.40578590
Short name T1083
Test name
Test status
Simulation time 21522603653 ps
CPU time 1310.46 seconds
Started Jun 21 04:44:59 PM PDT 24
Finished Jun 21 05:06:52 PM PDT 24
Peak memory 200612 kb
Host smart-f05f9dd0-3dee-4959-96d4-2a635263f037
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=40578590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.40578590
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.474895200
Short name T346
Test name
Test status
Simulation time 4638307141 ps
CPU time 9.96 seconds
Started Jun 21 04:45:02 PM PDT 24
Finished Jun 21 04:45:15 PM PDT 24
Peak memory 199888 kb
Host smart-e1722625-bda0-48de-a97a-86576549e076
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=474895200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.474895200
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.2252289240
Short name T1098
Test name
Test status
Simulation time 84458186606 ps
CPU time 147.62 seconds
Started Jun 21 04:45:10 PM PDT 24
Finished Jun 21 04:47:40 PM PDT 24
Peak memory 200488 kb
Host smart-0b36febe-8812-481c-8e46-ca787eb615b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252289240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.2252289240
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.1593651987
Short name T472
Test name
Test status
Simulation time 5857883369 ps
CPU time 2.92 seconds
Started Jun 21 04:44:54 PM PDT 24
Finished Jun 21 04:45:01 PM PDT 24
Peak memory 196692 kb
Host smart-4204ca34-8e3f-45b4-8291-e3b293848199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593651987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.1593651987
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.2909067414
Short name T469
Test name
Test status
Simulation time 5300951389 ps
CPU time 13.26 seconds
Started Jun 21 04:45:02 PM PDT 24
Finished Jun 21 04:45:18 PM PDT 24
Peak memory 200016 kb
Host smart-c0b3076e-9281-46a2-874b-08b29ca6a894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909067414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.2909067414
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.188359870
Short name T369
Test name
Test status
Simulation time 633083235 ps
CPU time 1.44 seconds
Started Jun 21 04:44:58 PM PDT 24
Finished Jun 21 04:45:03 PM PDT 24
Peak memory 200256 kb
Host smart-810d7bfc-f11e-432a-a93c-0acd34cbebfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188359870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.188359870
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.3500389723
Short name T1077
Test name
Test status
Simulation time 7611062897 ps
CPU time 11.88 seconds
Started Jun 21 04:44:56 PM PDT 24
Finished Jun 21 04:45:11 PM PDT 24
Peak memory 200396 kb
Host smart-b02a8d38-07ff-4342-815d-ff0f254a9a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500389723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.3500389723
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.1982315531
Short name T787
Test name
Test status
Simulation time 24890915432 ps
CPU time 48.1 seconds
Started Jun 21 04:47:27 PM PDT 24
Finished Jun 21 04:48:23 PM PDT 24
Peak memory 200628 kb
Host smart-7bcb31bf-9f1b-49c7-ba34-70e8c409dee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982315531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.1982315531
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.3176923629
Short name T245
Test name
Test status
Simulation time 128839176586 ps
CPU time 45.41 seconds
Started Jun 21 04:47:20 PM PDT 24
Finished Jun 21 04:48:07 PM PDT 24
Peak memory 200552 kb
Host smart-4068be74-efa4-4744-9702-b72e46ca85fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176923629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.3176923629
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.1327673165
Short name T793
Test name
Test status
Simulation time 31282068091 ps
CPU time 89.4 seconds
Started Jun 21 04:47:23 PM PDT 24
Finished Jun 21 04:48:58 PM PDT 24
Peak memory 200696 kb
Host smart-8ab74188-0fd4-40a0-b7d1-2f29386314d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327673165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.1327673165
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.2230887435
Short name T547
Test name
Test status
Simulation time 83157347442 ps
CPU time 32.39 seconds
Started Jun 21 04:47:24 PM PDT 24
Finished Jun 21 04:48:04 PM PDT 24
Peak memory 200524 kb
Host smart-01705d40-eeac-42d4-aed5-e7025ea6d11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230887435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.2230887435
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.1664667075
Short name T147
Test name
Test status
Simulation time 104325184964 ps
CPU time 85.58 seconds
Started Jun 21 04:47:21 PM PDT 24
Finished Jun 21 04:48:51 PM PDT 24
Peak memory 200576 kb
Host smart-c1c1cab1-aa8b-4054-8744-0d2ac88d5638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664667075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.1664667075
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.917882212
Short name T482
Test name
Test status
Simulation time 16606274263 ps
CPU time 7.47 seconds
Started Jun 21 04:47:22 PM PDT 24
Finished Jun 21 04:47:34 PM PDT 24
Peak memory 200088 kb
Host smart-560035e4-7dce-4330-a993-1d0213710e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917882212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.917882212
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.4257655882
Short name T504
Test name
Test status
Simulation time 33921022663 ps
CPU time 66.95 seconds
Started Jun 21 04:47:23 PM PDT 24
Finished Jun 21 04:48:38 PM PDT 24
Peak memory 200588 kb
Host smart-76f83236-bf8e-49fd-a538-4956968e45b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257655882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.4257655882
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.3732675372
Short name T315
Test name
Test status
Simulation time 14414497703 ps
CPU time 10.64 seconds
Started Jun 21 04:47:23 PM PDT 24
Finished Jun 21 04:47:41 PM PDT 24
Peak memory 200276 kb
Host smart-89460596-f0b7-4ecd-b59c-dfef23327274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732675372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.3732675372
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.1557344129
Short name T455
Test name
Test status
Simulation time 23837483 ps
CPU time 0.57 seconds
Started Jun 21 04:45:00 PM PDT 24
Finished Jun 21 04:45:03 PM PDT 24
Peak memory 196032 kb
Host smart-a1a85e4b-fcf1-492b-95b5-7b807fcd1a1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557344129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.1557344129
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.4229049724
Short name T858
Test name
Test status
Simulation time 111492667573 ps
CPU time 22.88 seconds
Started Jun 21 04:45:10 PM PDT 24
Finished Jun 21 04:45:34 PM PDT 24
Peak memory 200544 kb
Host smart-f93ddd3d-a80e-46d1-924b-a92ef9f3efdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229049724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.4229049724
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.2719220592
Short name T144
Test name
Test status
Simulation time 74442772152 ps
CPU time 29.48 seconds
Started Jun 21 04:44:58 PM PDT 24
Finished Jun 21 04:45:31 PM PDT 24
Peak memory 200604 kb
Host smart-1318c13e-7fca-4c8f-a967-6d1c8a6b565d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719220592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.2719220592
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.2850650398
Short name T590
Test name
Test status
Simulation time 83967233776 ps
CPU time 43.81 seconds
Started Jun 21 04:45:03 PM PDT 24
Finished Jun 21 04:45:49 PM PDT 24
Peak memory 200592 kb
Host smart-4ebea04d-2ea8-49df-ac62-93c903a8a1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850650398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.2850650398
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.743772053
Short name T125
Test name
Test status
Simulation time 57245552508 ps
CPU time 28.21 seconds
Started Jun 21 04:44:55 PM PDT 24
Finished Jun 21 04:45:26 PM PDT 24
Peak memory 200596 kb
Host smart-c68da56b-c5dc-4575-ab76-cdd118b53f39
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743772053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.743772053
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.2119133589
Short name T1090
Test name
Test status
Simulation time 129927197133 ps
CPU time 1377.65 seconds
Started Jun 21 04:45:03 PM PDT 24
Finished Jun 21 05:08:03 PM PDT 24
Peak memory 200612 kb
Host smart-af1bb77c-9e7c-42ed-b220-e75aae3cf179
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2119133589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.2119133589
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.4022737744
Short name T553
Test name
Test status
Simulation time 8191974729 ps
CPU time 15.49 seconds
Started Jun 21 04:44:57 PM PDT 24
Finished Jun 21 04:45:15 PM PDT 24
Peak memory 199784 kb
Host smart-3b5ac221-d9b3-4e8f-b598-af75d375e57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022737744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.4022737744
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_perf.2352245891
Short name T247
Test name
Test status
Simulation time 13718841487 ps
CPU time 517.71 seconds
Started Jun 21 04:45:10 PM PDT 24
Finished Jun 21 04:53:50 PM PDT 24
Peak memory 200516 kb
Host smart-1b0844ca-987b-45b2-a7cb-c116e0a2ca63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2352245891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.2352245891
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.4047419680
Short name T592
Test name
Test status
Simulation time 1401358994 ps
CPU time 0.98 seconds
Started Jun 21 04:44:57 PM PDT 24
Finished Jun 21 04:45:00 PM PDT 24
Peak memory 196184 kb
Host smart-2e7b8f4b-cd3b-4e02-9066-bc5939c7dab6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4047419680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.4047419680
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.2469790045
Short name T962
Test name
Test status
Simulation time 14575745806 ps
CPU time 7.14 seconds
Started Jun 21 04:44:58 PM PDT 24
Finished Jun 21 04:45:08 PM PDT 24
Peak memory 200640 kb
Host smart-3916de96-3e0f-4b36-802a-9f9388956fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469790045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.2469790045
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.3388919899
Short name T501
Test name
Test status
Simulation time 2425670601 ps
CPU time 2.63 seconds
Started Jun 21 04:44:59 PM PDT 24
Finished Jun 21 04:45:04 PM PDT 24
Peak memory 196596 kb
Host smart-cac31e71-78e7-42e7-8b23-a3b8b3840ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388919899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.3388919899
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.3211734164
Short name T652
Test name
Test status
Simulation time 623366187 ps
CPU time 1.75 seconds
Started Jun 21 04:45:03 PM PDT 24
Finished Jun 21 04:45:07 PM PDT 24
Peak memory 199620 kb
Host smart-267fbdf5-5861-4b45-bf43-dc73cb41db36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211734164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.3211734164
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.2420532271
Short name T350
Test name
Test status
Simulation time 1064485358 ps
CPU time 2.18 seconds
Started Jun 21 04:44:59 PM PDT 24
Finished Jun 21 04:45:04 PM PDT 24
Peak memory 200352 kb
Host smart-44b5fa31-f135-4303-8ec3-33868fb04439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420532271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.2420532271
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.1042941063
Short name T308
Test name
Test status
Simulation time 11187921772 ps
CPU time 3.89 seconds
Started Jun 21 04:44:56 PM PDT 24
Finished Jun 21 04:45:03 PM PDT 24
Peak memory 200628 kb
Host smart-da8b2b36-a3e8-4bbb-b241-2a39eb437f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042941063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.1042941063
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.234231699
Short name T523
Test name
Test status
Simulation time 36791192405 ps
CPU time 60.05 seconds
Started Jun 21 04:47:23 PM PDT 24
Finished Jun 21 04:48:28 PM PDT 24
Peak memory 200528 kb
Host smart-9041c004-618a-419c-a876-8fac795a58df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234231699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.234231699
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.3547884267
Short name T508
Test name
Test status
Simulation time 77086248899 ps
CPU time 31.4 seconds
Started Jun 21 04:47:24 PM PDT 24
Finished Jun 21 04:48:02 PM PDT 24
Peak memory 200672 kb
Host smart-f453c7f6-ebb9-427c-ab2f-90ee17ed14f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547884267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.3547884267
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.695491169
Short name T948
Test name
Test status
Simulation time 20621598202 ps
CPU time 34.04 seconds
Started Jun 21 04:47:24 PM PDT 24
Finished Jun 21 04:48:05 PM PDT 24
Peak memory 200584 kb
Host smart-379c6955-80d2-4cbf-a7b0-175ac05c9321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695491169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.695491169
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.3936052338
Short name T555
Test name
Test status
Simulation time 37795927457 ps
CPU time 19.36 seconds
Started Jun 21 04:47:23 PM PDT 24
Finished Jun 21 04:47:48 PM PDT 24
Peak memory 200376 kb
Host smart-cac84657-1671-41b4-923d-d8b31068998e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936052338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.3936052338
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.1702983194
Short name T814
Test name
Test status
Simulation time 33780037828 ps
CPU time 19.66 seconds
Started Jun 21 04:47:29 PM PDT 24
Finished Jun 21 04:47:57 PM PDT 24
Peak memory 200624 kb
Host smart-23c37b3e-b469-4c61-af8e-8a0a820a4b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702983194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.1702983194
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.3405287934
Short name T575
Test name
Test status
Simulation time 4565534562 ps
CPU time 8.84 seconds
Started Jun 21 04:47:24 PM PDT 24
Finished Jun 21 04:47:40 PM PDT 24
Peak memory 200628 kb
Host smart-d3a26b7c-1459-486b-b3f2-80e68e61ec98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405287934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.3405287934
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.372299318
Short name T146
Test name
Test status
Simulation time 60587811982 ps
CPU time 60.95 seconds
Started Jun 21 04:47:24 PM PDT 24
Finished Jun 21 04:48:32 PM PDT 24
Peak memory 200628 kb
Host smart-5dc25a4d-9b0b-43dc-935a-a99e6e0d4e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372299318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.372299318
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.937793654
Short name T223
Test name
Test status
Simulation time 37740872980 ps
CPU time 15.03 seconds
Started Jun 21 04:47:26 PM PDT 24
Finished Jun 21 04:47:49 PM PDT 24
Peak memory 200156 kb
Host smart-86dd162f-b7f7-48c8-802d-2d2bbb3faa2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937793654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.937793654
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.13569441
Short name T1065
Test name
Test status
Simulation time 81282041 ps
CPU time 0.53 seconds
Started Jun 21 04:45:07 PM PDT 24
Finished Jun 21 04:45:09 PM PDT 24
Peak memory 196020 kb
Host smart-7a45820e-ea8c-493b-abf9-c1b6c105cdbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13569441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.13569441
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.3073298681
Short name T666
Test name
Test status
Simulation time 34308941978 ps
CPU time 66.43 seconds
Started Jun 21 04:45:00 PM PDT 24
Finished Jun 21 04:46:10 PM PDT 24
Peak memory 200612 kb
Host smart-c639eb1b-fe58-4ebe-8116-79885ad9eb21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073298681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.3073298681
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.4103674376
Short name T651
Test name
Test status
Simulation time 154171154321 ps
CPU time 44.27 seconds
Started Jun 21 04:45:08 PM PDT 24
Finished Jun 21 04:45:54 PM PDT 24
Peak memory 200580 kb
Host smart-4d0885ed-3e48-42a3-b4dd-e4af99c893bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103674376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.4103674376
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.4218799299
Short name T871
Test name
Test status
Simulation time 183222017973 ps
CPU time 73.98 seconds
Started Jun 21 04:45:07 PM PDT 24
Finished Jun 21 04:46:23 PM PDT 24
Peak memory 200564 kb
Host smart-6083737f-ef51-46ef-993e-461b000a9a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218799299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.4218799299
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.3501213302
Short name T276
Test name
Test status
Simulation time 24482996892 ps
CPU time 10.04 seconds
Started Jun 21 04:45:02 PM PDT 24
Finished Jun 21 04:45:14 PM PDT 24
Peak memory 200420 kb
Host smart-286652a7-c12b-447d-bc48-5510ddd51f82
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501213302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.3501213302
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.2252952995
Short name T263
Test name
Test status
Simulation time 157196184153 ps
CPU time 1251.18 seconds
Started Jun 21 04:45:07 PM PDT 24
Finished Jun 21 05:06:00 PM PDT 24
Peak memory 200584 kb
Host smart-4fc45705-7c94-444e-89a9-198ea0922402
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2252952995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.2252952995
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.1064867959
Short name T807
Test name
Test status
Simulation time 1361001029 ps
CPU time 1.29 seconds
Started Jun 21 04:45:04 PM PDT 24
Finished Jun 21 04:45:07 PM PDT 24
Peak memory 197740 kb
Host smart-76dfd1df-e211-4b81-bae3-bd55a858dd86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064867959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.1064867959
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_perf.3633789699
Short name T1024
Test name
Test status
Simulation time 14667778198 ps
CPU time 672.96 seconds
Started Jun 21 04:45:00 PM PDT 24
Finished Jun 21 04:56:16 PM PDT 24
Peak memory 200608 kb
Host smart-ade1ef37-4774-4bcc-96ff-943162797d9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3633789699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.3633789699
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.3453448786
Short name T887
Test name
Test status
Simulation time 1917620503 ps
CPU time 3.38 seconds
Started Jun 21 04:45:08 PM PDT 24
Finished Jun 21 04:45:13 PM PDT 24
Peak memory 199984 kb
Host smart-46812d6a-7380-4b72-9493-ae42c418d32d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3453448786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.3453448786
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.335225126
Short name T950
Test name
Test status
Simulation time 186061525906 ps
CPU time 143.29 seconds
Started Jun 21 04:45:02 PM PDT 24
Finished Jun 21 04:47:28 PM PDT 24
Peak memory 200632 kb
Host smart-67097f35-d15f-43e9-9044-c5da6f5d396a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335225126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.335225126
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.2347288177
Short name T856
Test name
Test status
Simulation time 1605850729 ps
CPU time 1.98 seconds
Started Jun 21 04:45:02 PM PDT 24
Finished Jun 21 04:45:06 PM PDT 24
Peak memory 196072 kb
Host smart-6e99ec9c-4b55-481a-b1da-d2648121ca0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347288177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.2347288177
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.3610190084
Short name T953
Test name
Test status
Simulation time 108465416 ps
CPU time 0.85 seconds
Started Jun 21 04:45:01 PM PDT 24
Finished Jun 21 04:45:04 PM PDT 24
Peak memory 199780 kb
Host smart-7f5bd94b-7f50-422f-a05f-a478834af65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610190084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.3610190084
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.2350049944
Short name T818
Test name
Test status
Simulation time 40676120902 ps
CPU time 275.09 seconds
Started Jun 21 04:45:04 PM PDT 24
Finished Jun 21 04:49:41 PM PDT 24
Peak memory 217116 kb
Host smart-dbc6f630-e6d2-422d-8e8f-15986fef1707
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350049944 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.2350049944
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.3846545619
Short name T682
Test name
Test status
Simulation time 1137622155 ps
CPU time 1.91 seconds
Started Jun 21 04:45:10 PM PDT 24
Finished Jun 21 04:45:14 PM PDT 24
Peak memory 199500 kb
Host smart-d8875edd-cec7-44a1-86f1-260c031aac26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846545619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.3846545619
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.2351100208
Short name T649
Test name
Test status
Simulation time 73265235795 ps
CPU time 113.6 seconds
Started Jun 21 04:45:11 PM PDT 24
Finished Jun 21 04:47:08 PM PDT 24
Peak memory 200632 kb
Host smart-e351e5fb-f991-4873-b7eb-9e540e7635f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351100208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.2351100208
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.1122943345
Short name T916
Test name
Test status
Simulation time 12803637594 ps
CPU time 34.11 seconds
Started Jun 21 04:47:26 PM PDT 24
Finished Jun 21 04:48:08 PM PDT 24
Peak memory 200632 kb
Host smart-c6f76476-bccb-4977-9001-5b2675cbcaca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122943345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.1122943345
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.3681005717
Short name T717
Test name
Test status
Simulation time 16894678880 ps
CPU time 13.74 seconds
Started Jun 21 04:47:26 PM PDT 24
Finished Jun 21 04:47:48 PM PDT 24
Peak memory 200624 kb
Host smart-9eec4c94-47eb-4b7b-9a00-8ee9490a711c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681005717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.3681005717
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.838152233
Short name T764
Test name
Test status
Simulation time 75895957665 ps
CPU time 126.27 seconds
Started Jun 21 04:47:23 PM PDT 24
Finished Jun 21 04:49:37 PM PDT 24
Peak memory 200424 kb
Host smart-debb1ff6-a2a3-44b1-814a-03b1395dfd3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838152233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.838152233
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.2034730442
Short name T1013
Test name
Test status
Simulation time 51326595834 ps
CPU time 12.5 seconds
Started Jun 21 04:47:28 PM PDT 24
Finished Jun 21 04:47:50 PM PDT 24
Peak memory 200592 kb
Host smart-16057d3e-8fce-414f-8ada-e39a9ed4e12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034730442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.2034730442
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.1299143696
Short name T402
Test name
Test status
Simulation time 240343294369 ps
CPU time 60.29 seconds
Started Jun 21 04:47:27 PM PDT 24
Finished Jun 21 04:48:35 PM PDT 24
Peak memory 200540 kb
Host smart-3900cdf5-bb9d-4855-9213-1f6df3c02014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299143696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.1299143696
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.1053950982
Short name T1056
Test name
Test status
Simulation time 87916413705 ps
CPU time 244.51 seconds
Started Jun 21 04:47:28 PM PDT 24
Finished Jun 21 04:51:42 PM PDT 24
Peak memory 200164 kb
Host smart-2a874969-8ccd-494f-93ae-46bbac6549ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053950982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.1053950982
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.1803322485
Short name T470
Test name
Test status
Simulation time 114420527410 ps
CPU time 132.38 seconds
Started Jun 21 04:47:20 PM PDT 24
Finished Jun 21 04:49:35 PM PDT 24
Peak memory 200532 kb
Host smart-ba3c8e40-6995-49aa-8da9-6c5d930d40ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803322485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.1803322485
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.1337359994
Short name T257
Test name
Test status
Simulation time 67855380847 ps
CPU time 57.22 seconds
Started Jun 21 04:47:30 PM PDT 24
Finished Jun 21 04:48:36 PM PDT 24
Peak memory 200600 kb
Host smart-06e0eaea-3f44-4598-8a32-df96dbc66819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337359994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.1337359994
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.3031423834
Short name T689
Test name
Test status
Simulation time 68530301481 ps
CPU time 102.48 seconds
Started Jun 21 04:47:30 PM PDT 24
Finished Jun 21 04:49:21 PM PDT 24
Peak memory 200652 kb
Host smart-86c595c0-803b-4a36-b593-e7176ca863d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031423834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.3031423834
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.2783609270
Short name T889
Test name
Test status
Simulation time 21838560615 ps
CPU time 44.67 seconds
Started Jun 21 04:47:28 PM PDT 24
Finished Jun 21 04:48:22 PM PDT 24
Peak memory 200728 kb
Host smart-025a7fe1-2ffe-4a34-9e29-2bfca4b1c367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783609270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.2783609270
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.1198403926
Short name T114
Test name
Test status
Simulation time 22552540 ps
CPU time 0.57 seconds
Started Jun 21 04:45:18 PM PDT 24
Finished Jun 21 04:45:19 PM PDT 24
Peak memory 195964 kb
Host smart-5b0adc2e-965d-4ff0-9a86-3d624dbd3c76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198403926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.1198403926
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.3204605685
Short name T434
Test name
Test status
Simulation time 40052869581 ps
CPU time 43.28 seconds
Started Jun 21 04:45:11 PM PDT 24
Finished Jun 21 04:45:57 PM PDT 24
Peak memory 200540 kb
Host smart-ced493b7-4714-4c7c-9b72-c76a8857f245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204605685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.3204605685
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.3925454321
Short name T859
Test name
Test status
Simulation time 9561482019 ps
CPU time 7.52 seconds
Started Jun 21 04:45:01 PM PDT 24
Finished Jun 21 04:45:11 PM PDT 24
Peak memory 200396 kb
Host smart-d070621a-c5d0-4507-80ff-232b3714e9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925454321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.3925454321
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.3403197649
Short name T465
Test name
Test status
Simulation time 104243926079 ps
CPU time 132.87 seconds
Started Jun 21 04:45:08 PM PDT 24
Finished Jun 21 04:47:22 PM PDT 24
Peak memory 200672 kb
Host smart-0624c164-768b-490a-8b0d-e3c86de480e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403197649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.3403197649
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.3218515943
Short name T727
Test name
Test status
Simulation time 42862189453 ps
CPU time 20 seconds
Started Jun 21 04:45:07 PM PDT 24
Finished Jun 21 04:45:29 PM PDT 24
Peak memory 200392 kb
Host smart-4673ba0f-7a4c-4fbd-8067-251148eb696d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218515943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.3218515943
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.3539918618
Short name T582
Test name
Test status
Simulation time 64579358130 ps
CPU time 57.14 seconds
Started Jun 21 04:45:02 PM PDT 24
Finished Jun 21 04:46:02 PM PDT 24
Peak memory 200584 kb
Host smart-f7538bf6-59ac-4739-a580-7c7f3e033d8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3539918618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.3539918618
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.2603035013
Short name T342
Test name
Test status
Simulation time 10568272395 ps
CPU time 2.31 seconds
Started Jun 21 04:45:11 PM PDT 24
Finished Jun 21 04:45:16 PM PDT 24
Peak memory 200196 kb
Host smart-09127168-33ad-43ef-aa52-df9933054bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603035013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.2603035013
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_perf.2780709057
Short name T1049
Test name
Test status
Simulation time 22032892663 ps
CPU time 172.47 seconds
Started Jun 21 04:45:03 PM PDT 24
Finished Jun 21 04:47:58 PM PDT 24
Peak memory 200508 kb
Host smart-4baa5620-99b6-4ae5-b22a-05a42a6b68cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2780709057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.2780709057
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.796984527
Short name T467
Test name
Test status
Simulation time 6711645100 ps
CPU time 30.74 seconds
Started Jun 21 04:45:03 PM PDT 24
Finished Jun 21 04:45:36 PM PDT 24
Peak memory 198836 kb
Host smart-6b0587fc-b6a2-4d30-8dff-53db3c9f84a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=796984527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.796984527
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.3581720120
Short name T885
Test name
Test status
Simulation time 103658580404 ps
CPU time 36.97 seconds
Started Jun 21 04:45:07 PM PDT 24
Finished Jun 21 04:45:45 PM PDT 24
Peak memory 200676 kb
Host smart-a273c813-ec0e-48da-b9fd-d46e6fc28346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581720120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.3581720120
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.1822589005
Short name T262
Test name
Test status
Simulation time 27465229655 ps
CPU time 21.55 seconds
Started Jun 21 04:45:05 PM PDT 24
Finished Jun 21 04:45:28 PM PDT 24
Peak memory 196424 kb
Host smart-9faa1b22-2c38-4e01-92c4-b224a418bbd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822589005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.1822589005
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.292270523
Short name T741
Test name
Test status
Simulation time 287900908 ps
CPU time 1.45 seconds
Started Jun 21 04:45:10 PM PDT 24
Finished Jun 21 04:45:15 PM PDT 24
Peak memory 199172 kb
Host smart-6d6218a0-d454-4a3d-bcf0-498221a934b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292270523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.292270523
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.725848075
Short name T920
Test name
Test status
Simulation time 27571924971 ps
CPU time 281.62 seconds
Started Jun 21 04:45:05 PM PDT 24
Finished Jun 21 04:49:48 PM PDT 24
Peak memory 217128 kb
Host smart-becf6615-928e-4457-a835-2d42f4620c7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725848075 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.725848075
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.2772490131
Short name T520
Test name
Test status
Simulation time 761008841 ps
CPU time 2.01 seconds
Started Jun 21 04:45:03 PM PDT 24
Finished Jun 21 04:45:07 PM PDT 24
Peak memory 199976 kb
Host smart-85bdb8f1-4c5b-4d8f-9c22-fb48dee7d40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772490131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.2772490131
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.3562813997
Short name T1095
Test name
Test status
Simulation time 19080869208 ps
CPU time 32.48 seconds
Started Jun 21 04:45:03 PM PDT 24
Finished Jun 21 04:45:38 PM PDT 24
Peak memory 200664 kb
Host smart-d0140f67-920e-41c5-ba65-a6646a4893c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562813997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.3562813997
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.3637517872
Short name T199
Test name
Test status
Simulation time 45087126307 ps
CPU time 35.93 seconds
Started Jun 21 04:47:25 PM PDT 24
Finished Jun 21 04:48:09 PM PDT 24
Peak memory 200564 kb
Host smart-4ec3eb43-6906-4a31-b427-c6749bcdd2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637517872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.3637517872
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.925865644
Short name T142
Test name
Test status
Simulation time 20757380647 ps
CPU time 35.76 seconds
Started Jun 21 04:47:29 PM PDT 24
Finished Jun 21 04:48:14 PM PDT 24
Peak memory 200796 kb
Host smart-add82692-a650-4ae4-9ad4-53b45345d6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925865644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.925865644
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.3749540373
Short name T552
Test name
Test status
Simulation time 61147583731 ps
CPU time 130.77 seconds
Started Jun 21 04:47:28 PM PDT 24
Finished Jun 21 04:49:48 PM PDT 24
Peak memory 200788 kb
Host smart-9610b4ab-7452-4a1e-9265-be53ee64cbfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749540373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.3749540373
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.3600427505
Short name T866
Test name
Test status
Simulation time 67441804473 ps
CPU time 46.49 seconds
Started Jun 21 04:47:29 PM PDT 24
Finished Jun 21 04:48:24 PM PDT 24
Peak memory 200636 kb
Host smart-69d2f682-fb0d-48d4-99e1-4afae9369505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600427505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.3600427505
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.4117098414
Short name T207
Test name
Test status
Simulation time 18596903982 ps
CPU time 14.18 seconds
Started Jun 21 04:47:29 PM PDT 24
Finished Jun 21 04:47:52 PM PDT 24
Peak memory 199620 kb
Host smart-bd7d615e-4ee9-44f2-9728-fe8e8251dbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117098414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.4117098414
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.1130107223
Short name T855
Test name
Test status
Simulation time 118727343120 ps
CPU time 127.55 seconds
Started Jun 21 04:47:29 PM PDT 24
Finished Jun 21 04:49:46 PM PDT 24
Peak memory 200576 kb
Host smart-b42ee051-5e8d-41ae-8598-98e91b79e203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130107223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.1130107223
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.1983708716
Short name T328
Test name
Test status
Simulation time 167519156954 ps
CPU time 23.72 seconds
Started Jun 21 04:47:26 PM PDT 24
Finished Jun 21 04:47:57 PM PDT 24
Peak memory 200620 kb
Host smart-59cc9132-f627-47da-83d1-48d8f42c550b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983708716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.1983708716
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.422469253
Short name T695
Test name
Test status
Simulation time 41838100 ps
CPU time 0.54 seconds
Started Jun 21 04:45:11 PM PDT 24
Finished Jun 21 04:45:15 PM PDT 24
Peak memory 195972 kb
Host smart-845e1709-5972-4dd9-bb83-5f74f2f3a666
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422469253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.422469253
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.1563671819
Short name T537
Test name
Test status
Simulation time 46326159647 ps
CPU time 75.37 seconds
Started Jun 21 04:45:10 PM PDT 24
Finished Jun 21 04:46:29 PM PDT 24
Peak memory 200660 kb
Host smart-8e68baa4-0b79-4a3e-950b-12f84db43278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563671819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.1563671819
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.3453874309
Short name T863
Test name
Test status
Simulation time 62482878208 ps
CPU time 138.34 seconds
Started Jun 21 04:45:10 PM PDT 24
Finished Jun 21 04:47:31 PM PDT 24
Peak memory 200412 kb
Host smart-5e30923c-bf5c-4665-b674-7484454d0b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453874309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.3453874309
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.1764606256
Short name T397
Test name
Test status
Simulation time 16810596497 ps
CPU time 26.69 seconds
Started Jun 21 04:45:00 PM PDT 24
Finished Jun 21 04:45:29 PM PDT 24
Peak memory 200632 kb
Host smart-fd1d8e29-2c7a-4cd2-922e-b8b2c2a9322c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764606256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.1764606256
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.2544185278
Short name T317
Test name
Test status
Simulation time 47617830652 ps
CPU time 42.82 seconds
Started Jun 21 04:45:07 PM PDT 24
Finished Jun 21 04:45:51 PM PDT 24
Peak memory 200580 kb
Host smart-e7334163-92d7-4a99-aebd-d927a88872a9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544185278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.2544185278
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.1070638659
Short name T381
Test name
Test status
Simulation time 161724305120 ps
CPU time 348.42 seconds
Started Jun 21 04:45:14 PM PDT 24
Finished Jun 21 04:51:05 PM PDT 24
Peak memory 200492 kb
Host smart-38ccd1cb-2c90-48a1-a246-d78f0b6546cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1070638659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.1070638659
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.487719651
Short name T758
Test name
Test status
Simulation time 5563893457 ps
CPU time 3.36 seconds
Started Jun 21 04:45:10 PM PDT 24
Finished Jun 21 04:45:17 PM PDT 24
Peak memory 196376 kb
Host smart-a8d67c87-cc8b-4bad-9d4c-5aadd833da61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487719651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.487719651
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_perf.1148830890
Short name T1055
Test name
Test status
Simulation time 19382264930 ps
CPU time 218.18 seconds
Started Jun 21 04:45:08 PM PDT 24
Finished Jun 21 04:48:47 PM PDT 24
Peak memory 200516 kb
Host smart-3daa7f22-5526-4c68-9ef8-93bb4985752c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1148830890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.1148830890
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.2199803470
Short name T463
Test name
Test status
Simulation time 1872943482 ps
CPU time 6.54 seconds
Started Jun 21 04:45:11 PM PDT 24
Finished Jun 21 04:45:21 PM PDT 24
Peak memory 198632 kb
Host smart-a5e1329a-acfc-4014-95c3-c8836f3467c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2199803470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.2199803470
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.3547255686
Short name T170
Test name
Test status
Simulation time 14433373582 ps
CPU time 21.42 seconds
Started Jun 21 04:45:14 PM PDT 24
Finished Jun 21 04:45:37 PM PDT 24
Peak memory 200564 kb
Host smart-9b7b2cef-14c1-497d-ac08-e7980df5ec2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547255686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.3547255686
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.4207680619
Short name T1072
Test name
Test status
Simulation time 46918385299 ps
CPU time 11.16 seconds
Started Jun 21 04:45:15 PM PDT 24
Finished Jun 21 04:45:28 PM PDT 24
Peak memory 196740 kb
Host smart-8ad15e76-a030-4ae3-bae8-3a5f6fac76dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207680619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.4207680619
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.214307612
Short name T821
Test name
Test status
Simulation time 131640674 ps
CPU time 0.98 seconds
Started Jun 21 04:45:06 PM PDT 24
Finished Jun 21 04:45:08 PM PDT 24
Peak memory 198996 kb
Host smart-e510dc3e-6278-43ed-b601-8aa9292ce9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214307612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.214307612
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.1487655258
Short name T95
Test name
Test status
Simulation time 11594604859 ps
CPU time 60.79 seconds
Started Jun 21 04:45:09 PM PDT 24
Finished Jun 21 04:46:11 PM PDT 24
Peak memory 200604 kb
Host smart-00975a42-e079-4441-9b3f-87d91c13710f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487655258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.1487655258
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.3003646154
Short name T847
Test name
Test status
Simulation time 227729155464 ps
CPU time 798.63 seconds
Started Jun 21 04:45:10 PM PDT 24
Finished Jun 21 04:58:32 PM PDT 24
Peak memory 217028 kb
Host smart-dfeef71c-aafc-4df6-a794-a3d759d80aa3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003646154 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.3003646154
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.2861450892
Short name T373
Test name
Test status
Simulation time 475960263 ps
CPU time 1.8 seconds
Started Jun 21 04:45:16 PM PDT 24
Finished Jun 21 04:45:19 PM PDT 24
Peak memory 199404 kb
Host smart-302f669f-3312-49e4-8435-a628b348b5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861450892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.2861450892
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.1879206173
Short name T332
Test name
Test status
Simulation time 61724933079 ps
CPU time 103.84 seconds
Started Jun 21 04:45:07 PM PDT 24
Finished Jun 21 04:46:52 PM PDT 24
Peak memory 200680 kb
Host smart-ada7e9db-0b2c-4180-bec8-c1bad93a8052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879206173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.1879206173
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.880692254
Short name T773
Test name
Test status
Simulation time 11406839430 ps
CPU time 9.92 seconds
Started Jun 21 04:47:28 PM PDT 24
Finished Jun 21 04:47:47 PM PDT 24
Peak memory 200204 kb
Host smart-2ffc9c5f-f8d3-451a-af2a-bfde59757046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880692254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.880692254
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.153003249
Short name T784
Test name
Test status
Simulation time 12719512059 ps
CPU time 9.3 seconds
Started Jun 21 04:47:23 PM PDT 24
Finished Jun 21 04:47:37 PM PDT 24
Peak memory 200644 kb
Host smart-2a6ed177-fae2-490a-a044-da70967a2b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153003249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.153003249
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.1755454766
Short name T546
Test name
Test status
Simulation time 24861234814 ps
CPU time 35.48 seconds
Started Jun 21 04:47:23 PM PDT 24
Finished Jun 21 04:48:06 PM PDT 24
Peak memory 200560 kb
Host smart-752675c6-e518-4408-940d-6678ac0e5087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755454766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.1755454766
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.2448861501
Short name T661
Test name
Test status
Simulation time 166414347124 ps
CPU time 81.51 seconds
Started Jun 21 04:47:23 PM PDT 24
Finished Jun 21 04:48:52 PM PDT 24
Peak memory 200584 kb
Host smart-fcb3d3f4-8f56-4391-9b4b-5ab7366aeb69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448861501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.2448861501
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.3145296029
Short name T997
Test name
Test status
Simulation time 27214718035 ps
CPU time 44.91 seconds
Started Jun 21 04:47:21 PM PDT 24
Finished Jun 21 04:48:09 PM PDT 24
Peak memory 200632 kb
Host smart-a3da3386-b0d8-47d9-a4f8-af1fa3601809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145296029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.3145296029
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.241969009
Short name T757
Test name
Test status
Simulation time 135652219838 ps
CPU time 23.06 seconds
Started Jun 21 04:47:22 PM PDT 24
Finished Jun 21 04:47:51 PM PDT 24
Peak memory 200536 kb
Host smart-b220536c-e995-4c65-b5bd-c2d60bbe4450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241969009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.241969009
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.3730251329
Short name T301
Test name
Test status
Simulation time 142651036763 ps
CPU time 239.29 seconds
Started Jun 21 04:47:23 PM PDT 24
Finished Jun 21 04:51:27 PM PDT 24
Peak memory 200640 kb
Host smart-0016f10c-a4c4-4b16-bb58-59ba8d2e9823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730251329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.3730251329
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.2695574111
Short name T1066
Test name
Test status
Simulation time 199470632932 ps
CPU time 77.36 seconds
Started Jun 21 04:47:21 PM PDT 24
Finished Jun 21 04:48:42 PM PDT 24
Peak memory 200072 kb
Host smart-b06a88a0-44e5-4fe1-aa21-10e837104f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695574111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.2695574111
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.2796841522
Short name T60
Test name
Test status
Simulation time 13156070 ps
CPU time 0.59 seconds
Started Jun 21 04:45:14 PM PDT 24
Finished Jun 21 04:45:16 PM PDT 24
Peak memory 195972 kb
Host smart-37a0874c-0941-41e8-896b-39aa4be47da1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796841522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.2796841522
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.767274718
Short name T481
Test name
Test status
Simulation time 58588672842 ps
CPU time 25.58 seconds
Started Jun 21 04:45:11 PM PDT 24
Finished Jun 21 04:45:40 PM PDT 24
Peak memory 200756 kb
Host smart-088798de-9a27-4aab-94a1-3681c446a524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767274718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.767274718
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.2404369885
Short name T1050
Test name
Test status
Simulation time 93509387278 ps
CPU time 66.21 seconds
Started Jun 21 04:45:11 PM PDT 24
Finished Jun 21 04:46:21 PM PDT 24
Peak memory 200396 kb
Host smart-bf15f274-0cf0-4b7c-a76c-df8940716c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404369885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.2404369885
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.3319658284
Short name T264
Test name
Test status
Simulation time 440876166991 ps
CPU time 162.01 seconds
Started Jun 21 04:45:13 PM PDT 24
Finished Jun 21 04:47:57 PM PDT 24
Peak memory 200632 kb
Host smart-80668183-7294-456b-ac13-24f81a8ea3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319658284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.3319658284
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.397852763
Short name T384
Test name
Test status
Simulation time 35314302179 ps
CPU time 20.08 seconds
Started Jun 21 04:45:11 PM PDT 24
Finished Jun 21 04:45:34 PM PDT 24
Peak memory 200248 kb
Host smart-0d569867-b179-4486-8cb0-eb1d2a0019e4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397852763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.397852763
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.2059232080
Short name T853
Test name
Test status
Simulation time 149523918001 ps
CPU time 1226.34 seconds
Started Jun 21 04:45:09 PM PDT 24
Finished Jun 21 05:05:38 PM PDT 24
Peak memory 200672 kb
Host smart-8fb27700-a8a8-4543-895b-e0154dbeec43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2059232080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.2059232080
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.4236201298
Short name T1
Test name
Test status
Simulation time 5323675331 ps
CPU time 9.2 seconds
Started Jun 21 04:45:09 PM PDT 24
Finished Jun 21 04:45:20 PM PDT 24
Peak memory 199520 kb
Host smart-6bf447e6-1f42-43a6-85c8-e493d1f44ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236201298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.4236201298
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_perf.526808462
Short name T993
Test name
Test status
Simulation time 16325819477 ps
CPU time 209.16 seconds
Started Jun 21 04:45:17 PM PDT 24
Finished Jun 21 04:48:46 PM PDT 24
Peak memory 200548 kb
Host smart-e3d8d556-07ee-47cc-a9de-090d8f11fc8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=526808462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.526808462
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.1693636265
Short name T817
Test name
Test status
Simulation time 5221091036 ps
CPU time 11.45 seconds
Started Jun 21 04:45:10 PM PDT 24
Finished Jun 21 04:45:24 PM PDT 24
Peak memory 200172 kb
Host smart-c2795fb3-0a33-42aa-bcf2-4ab7e0c0a94e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1693636265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.1693636265
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.2746683084
Short name T718
Test name
Test status
Simulation time 16119887337 ps
CPU time 26.94 seconds
Started Jun 21 04:45:10 PM PDT 24
Finished Jun 21 04:45:40 PM PDT 24
Peak memory 200732 kb
Host smart-0c912037-71d1-47f7-8ed0-b5c73c22e27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746683084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.2746683084
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.1845582541
Short name T633
Test name
Test status
Simulation time 35789260566 ps
CPU time 12.84 seconds
Started Jun 21 04:45:12 PM PDT 24
Finished Jun 21 04:45:28 PM PDT 24
Peak memory 196684 kb
Host smart-dada6bf9-31f3-4d16-b4a6-8cabc15f1922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845582541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.1845582541
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.1866511786
Short name T273
Test name
Test status
Simulation time 686681481 ps
CPU time 1.49 seconds
Started Jun 21 04:45:12 PM PDT 24
Finished Jun 21 04:45:17 PM PDT 24
Peak memory 200224 kb
Host smart-b5e4d3b7-7c9a-44f4-9691-780516aa0bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866511786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.1866511786
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.1287695824
Short name T735
Test name
Test status
Simulation time 210779686948 ps
CPU time 126.46 seconds
Started Jun 21 04:45:12 PM PDT 24
Finished Jun 21 04:47:22 PM PDT 24
Peak memory 200576 kb
Host smart-ae560661-e424-4ca1-9091-49d3d59352f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287695824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.1287695824
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.3171871731
Short name T731
Test name
Test status
Simulation time 1808000835 ps
CPU time 1.99 seconds
Started Jun 21 04:45:12 PM PDT 24
Finished Jun 21 04:45:17 PM PDT 24
Peak memory 199272 kb
Host smart-0a94c73d-9d1e-4705-a102-fc3e8a8cf81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171871731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.3171871731
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.2051780115
Short name T399
Test name
Test status
Simulation time 25587179465 ps
CPU time 45.65 seconds
Started Jun 21 04:45:13 PM PDT 24
Finished Jun 21 04:46:01 PM PDT 24
Peak memory 200572 kb
Host smart-ad6bab72-486b-403c-8c9e-a793801ebdc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051780115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.2051780115
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.3512500580
Short name T175
Test name
Test status
Simulation time 78541272592 ps
CPU time 107.98 seconds
Started Jun 21 04:47:24 PM PDT 24
Finished Jun 21 04:49:19 PM PDT 24
Peak memory 200612 kb
Host smart-94095f5b-28a4-4e1d-8fe3-718238ff8519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512500580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.3512500580
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.2066074550
Short name T849
Test name
Test status
Simulation time 35006538434 ps
CPU time 58.15 seconds
Started Jun 21 04:47:29 PM PDT 24
Finished Jun 21 04:48:37 PM PDT 24
Peak memory 200576 kb
Host smart-a9b401a9-fcec-40f5-9594-5f3df7498d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066074550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.2066074550
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.885087960
Short name T212
Test name
Test status
Simulation time 73232227726 ps
CPU time 17.3 seconds
Started Jun 21 04:47:32 PM PDT 24
Finished Jun 21 04:47:57 PM PDT 24
Peak memory 200596 kb
Host smart-d2d6d6c6-2ef3-4aa4-9504-37c5d1f2ebd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885087960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.885087960
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.2591491198
Short name T51
Test name
Test status
Simulation time 169165988071 ps
CPU time 98.77 seconds
Started Jun 21 04:47:28 PM PDT 24
Finished Jun 21 04:49:16 PM PDT 24
Peak memory 200636 kb
Host smart-13510898-cdc9-4d83-84d3-9868e3168dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591491198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.2591491198
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.4121961795
Short name T766
Test name
Test status
Simulation time 76901092172 ps
CPU time 52.9 seconds
Started Jun 21 04:47:28 PM PDT 24
Finished Jun 21 04:48:30 PM PDT 24
Peak memory 200612 kb
Host smart-f37b26c4-5347-4ea3-b317-f88405072e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121961795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.4121961795
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.1144346826
Short name T692
Test name
Test status
Simulation time 130374266716 ps
CPU time 53.69 seconds
Started Jun 21 04:47:27 PM PDT 24
Finished Jun 21 04:48:29 PM PDT 24
Peak memory 200512 kb
Host smart-30eeee94-995d-4995-8f52-e97980f22dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144346826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.1144346826
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.3860873312
Short name T779
Test name
Test status
Simulation time 12739899801 ps
CPU time 28.29 seconds
Started Jun 21 04:47:31 PM PDT 24
Finished Jun 21 04:48:07 PM PDT 24
Peak memory 200516 kb
Host smart-7959fc7b-8975-4136-ad99-87321e92a6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860873312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.3860873312
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.1666644233
Short name T476
Test name
Test status
Simulation time 161075476091 ps
CPU time 63.93 seconds
Started Jun 21 04:47:32 PM PDT 24
Finished Jun 21 04:48:44 PM PDT 24
Peak memory 200644 kb
Host smart-c258bbe5-1ef2-4e63-936e-17ca45b1f999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666644233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.1666644233
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.1085885234
Short name T427
Test name
Test status
Simulation time 27973449 ps
CPU time 0.61 seconds
Started Jun 21 04:44:20 PM PDT 24
Finished Jun 21 04:44:25 PM PDT 24
Peak memory 195288 kb
Host smart-5aeac41c-047f-4313-9376-0873b4d9f128
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085885234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.1085885234
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.3422902947
Short name T733
Test name
Test status
Simulation time 107860690938 ps
CPU time 95.39 seconds
Started Jun 21 04:44:10 PM PDT 24
Finished Jun 21 04:45:48 PM PDT 24
Peak memory 200508 kb
Host smart-d830f710-7c4c-4b78-a4d9-fa498c353f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422902947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.3422902947
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.3692427715
Short name T526
Test name
Test status
Simulation time 90733023594 ps
CPU time 38.52 seconds
Started Jun 21 04:44:21 PM PDT 24
Finished Jun 21 04:45:04 PM PDT 24
Peak memory 200508 kb
Host smart-1c00c568-b2c8-4a6e-9b35-534b2a1b0175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692427715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.3692427715
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.480419938
Short name T64
Test name
Test status
Simulation time 80529188747 ps
CPU time 110.04 seconds
Started Jun 21 04:44:21 PM PDT 24
Finished Jun 21 04:46:17 PM PDT 24
Peak memory 200296 kb
Host smart-7596911b-907f-4d37-85c5-09551d246c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480419938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.480419938
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.1482953501
Short name T97
Test name
Test status
Simulation time 197185435412 ps
CPU time 129.25 seconds
Started Jun 21 04:44:21 PM PDT 24
Finished Jun 21 04:46:35 PM PDT 24
Peak memory 200548 kb
Host smart-dddb15e4-b8a5-4472-909a-e31acae6d3c9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482953501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.1482953501
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.887620577
Short name T377
Test name
Test status
Simulation time 79261387727 ps
CPU time 202.49 seconds
Started Jun 21 04:44:19 PM PDT 24
Finished Jun 21 04:47:46 PM PDT 24
Peak memory 200512 kb
Host smart-0e4def8d-72f5-4400-bde2-9237995ffc5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=887620577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.887620577
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.1593099700
Short name T831
Test name
Test status
Simulation time 229460544 ps
CPU time 1.74 seconds
Started Jun 21 04:44:21 PM PDT 24
Finished Jun 21 04:44:28 PM PDT 24
Peak memory 199404 kb
Host smart-62f74344-7bcf-47eb-bdae-23111c7dbe64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593099700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.1593099700
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_perf.3771666498
Short name T494
Test name
Test status
Simulation time 19631345300 ps
CPU time 61.16 seconds
Started Jun 21 04:44:09 PM PDT 24
Finished Jun 21 04:45:12 PM PDT 24
Peak memory 200592 kb
Host smart-2a256a69-f75f-4ab7-9991-79b6ee3131b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3771666498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.3771666498
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.3260735613
Short name T390
Test name
Test status
Simulation time 4956804337 ps
CPU time 2.43 seconds
Started Jun 21 04:44:16 PM PDT 24
Finished Jun 21 04:44:22 PM PDT 24
Peak memory 199280 kb
Host smart-3de261db-db9e-45da-b600-2f99f824afab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3260735613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.3260735613
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.3181599278
Short name T260
Test name
Test status
Simulation time 31450889739 ps
CPU time 12.38 seconds
Started Jun 21 04:44:19 PM PDT 24
Finished Jun 21 04:44:36 PM PDT 24
Peak memory 196876 kb
Host smart-0cd74a2d-8952-4515-b830-9a5897cfdd0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181599278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.3181599278
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.343377446
Short name T38
Test name
Test status
Simulation time 357254388 ps
CPU time 0.86 seconds
Started Jun 21 04:44:23 PM PDT 24
Finished Jun 21 04:44:28 PM PDT 24
Peak memory 218540 kb
Host smart-2e0c60cc-2b30-44d5-b7ce-0625f7df92fa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343377446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.343377446
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.2996650830
Short name T588
Test name
Test status
Simulation time 882689238 ps
CPU time 3.83 seconds
Started Jun 21 04:44:19 PM PDT 24
Finished Jun 21 04:44:27 PM PDT 24
Peak memory 199700 kb
Host smart-51eea198-fd62-4b8f-9697-8eb76bb7b959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996650830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.2996650830
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.271278476
Short name T599
Test name
Test status
Simulation time 88956955563 ps
CPU time 196.13 seconds
Started Jun 21 04:44:23 PM PDT 24
Finished Jun 21 04:47:44 PM PDT 24
Peak memory 199724 kb
Host smart-fd275d85-4f23-4839-b372-a3666bc25cfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271278476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.271278476
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.2238787234
Short name T320
Test name
Test status
Simulation time 142286517407 ps
CPU time 903.87 seconds
Started Jun 21 04:44:24 PM PDT 24
Finished Jun 21 04:59:33 PM PDT 24
Peak memory 214780 kb
Host smart-d8cad1a3-5eef-4c4f-9fe5-405135347bd9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238787234 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.2238787234
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.2065467810
Short name T505
Test name
Test status
Simulation time 1104488489 ps
CPU time 2.71 seconds
Started Jun 21 04:44:16 PM PDT 24
Finished Jun 21 04:44:23 PM PDT 24
Peak memory 199024 kb
Host smart-1859a8b6-3d1f-4c36-a8b5-dfeee7e5d14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065467810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.2065467810
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.231654127
Short name T417
Test name
Test status
Simulation time 43035226482 ps
CPU time 56.42 seconds
Started Jun 21 04:44:17 PM PDT 24
Finished Jun 21 04:45:19 PM PDT 24
Peak memory 200552 kb
Host smart-afb9e183-c896-4e32-aa7a-66b0273804cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231654127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.231654127
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.1988855266
Short name T804
Test name
Test status
Simulation time 49579157 ps
CPU time 0.54 seconds
Started Jun 21 04:45:10 PM PDT 24
Finished Jun 21 04:45:14 PM PDT 24
Peak memory 195972 kb
Host smart-4eb450ed-15b4-4c2c-a529-14a5cbb6ec3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988855266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.1988855266
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.3239239817
Short name T750
Test name
Test status
Simulation time 33285716657 ps
CPU time 50.29 seconds
Started Jun 21 04:45:13 PM PDT 24
Finished Jun 21 04:46:06 PM PDT 24
Peak memory 200664 kb
Host smart-392ea52a-480e-4005-8b7d-775087b2ae3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239239817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.3239239817
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.1258911233
Short name T994
Test name
Test status
Simulation time 13446179978 ps
CPU time 7.6 seconds
Started Jun 21 04:45:10 PM PDT 24
Finished Jun 21 04:45:21 PM PDT 24
Peak memory 200588 kb
Host smart-33ed7a83-f3eb-43f9-b576-0fc6dbe9b04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258911233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.1258911233
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.3389230543
Short name T577
Test name
Test status
Simulation time 155684108914 ps
CPU time 185.68 seconds
Started Jun 21 04:45:20 PM PDT 24
Finished Jun 21 04:48:26 PM PDT 24
Peak memory 200660 kb
Host smart-881a6558-55d5-43eb-a600-6a9d82e5a961
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389230543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.3389230543
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.3093562090
Short name T1015
Test name
Test status
Simulation time 47503397201 ps
CPU time 352.02 seconds
Started Jun 21 04:45:11 PM PDT 24
Finished Jun 21 04:51:06 PM PDT 24
Peak memory 200556 kb
Host smart-28288ef3-4a4d-4465-9b03-ed6dda681fed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3093562090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.3093562090
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.2114048157
Short name T345
Test name
Test status
Simulation time 7832063580 ps
CPU time 25.23 seconds
Started Jun 21 04:45:12 PM PDT 24
Finished Jun 21 04:45:40 PM PDT 24
Peak memory 198980 kb
Host smart-a7a3c454-df1c-42a3-8aaa-132da9c374a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114048157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.2114048157
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_perf.2044199109
Short name T737
Test name
Test status
Simulation time 13279388057 ps
CPU time 341.98 seconds
Started Jun 21 04:45:18 PM PDT 24
Finished Jun 21 04:51:01 PM PDT 24
Peak memory 200652 kb
Host smart-23c6cf16-696f-4cb5-b62b-5aeb7659a9c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2044199109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.2044199109
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.2813575745
Short name T343
Test name
Test status
Simulation time 2230878702 ps
CPU time 12.55 seconds
Started Jun 21 04:45:11 PM PDT 24
Finished Jun 21 04:45:27 PM PDT 24
Peak memory 198520 kb
Host smart-eaa36a8c-18e3-4e77-9f58-faa98141ee7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2813575745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.2813575745
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.1849138854
Short name T1021
Test name
Test status
Simulation time 76911981417 ps
CPU time 84.54 seconds
Started Jun 21 04:45:11 PM PDT 24
Finished Jun 21 04:46:39 PM PDT 24
Peak memory 200668 kb
Host smart-60836b0a-74ad-4f56-b5a2-c13b612a9d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849138854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.1849138854
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.2685179633
Short name T303
Test name
Test status
Simulation time 3219731901 ps
CPU time 1.93 seconds
Started Jun 21 04:45:13 PM PDT 24
Finished Jun 21 04:45:17 PM PDT 24
Peak memory 197188 kb
Host smart-5b6d5974-2a1a-4f24-848b-80579bd77e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685179633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.2685179633
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.3092416646
Short name T693
Test name
Test status
Simulation time 322595396 ps
CPU time 1.02 seconds
Started Jun 21 04:45:09 PM PDT 24
Finished Jun 21 04:45:11 PM PDT 24
Peak memory 200080 kb
Host smart-861cab95-7ff3-4b3b-b86a-4159ad566422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092416646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.3092416646
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.3779810774
Short name T743
Test name
Test status
Simulation time 248609123880 ps
CPU time 1051.68 seconds
Started Jun 21 04:45:09 PM PDT 24
Finished Jun 21 05:02:42 PM PDT 24
Peak memory 200592 kb
Host smart-e715f182-0c98-4124-9f15-f0ffa1f319ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779810774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.3779810774
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.2940659923
Short name T45
Test name
Test status
Simulation time 22951565805 ps
CPU time 133.94 seconds
Started Jun 21 04:45:12 PM PDT 24
Finished Jun 21 04:47:29 PM PDT 24
Peak memory 217116 kb
Host smart-a11e330b-148b-4355-b6f1-a84cc4d7ad89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940659923 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.2940659923
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.396964821
Short name T978
Test name
Test status
Simulation time 12251572036 ps
CPU time 24.15 seconds
Started Jun 21 04:45:17 PM PDT 24
Finished Jun 21 04:45:42 PM PDT 24
Peak memory 200512 kb
Host smart-c8127705-1e19-4bc4-99e4-df334446da3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396964821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.396964821
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.4071384251
Short name T312
Test name
Test status
Simulation time 79490294115 ps
CPU time 267.69 seconds
Started Jun 21 04:45:11 PM PDT 24
Finished Jun 21 04:49:42 PM PDT 24
Peak memory 200560 kb
Host smart-866ae67f-79bb-47e8-adb0-2536135d7c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071384251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.4071384251
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.3066719060
Short name T327
Test name
Test status
Simulation time 44732902367 ps
CPU time 21.11 seconds
Started Jun 21 04:47:20 PM PDT 24
Finished Jun 21 04:47:44 PM PDT 24
Peak memory 200628 kb
Host smart-f8b855ec-625d-4db3-91ac-e1a2157b67b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066719060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.3066719060
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.1110824030
Short name T407
Test name
Test status
Simulation time 144051645736 ps
CPU time 139.2 seconds
Started Jun 21 04:47:31 PM PDT 24
Finished Jun 21 04:49:58 PM PDT 24
Peak memory 200596 kb
Host smart-33393da7-44e7-4dba-a439-3c4706177d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110824030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.1110824030
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.311156961
Short name T185
Test name
Test status
Simulation time 24250091605 ps
CPU time 18.6 seconds
Started Jun 21 04:47:28 PM PDT 24
Finished Jun 21 04:47:56 PM PDT 24
Peak memory 200072 kb
Host smart-7c7c9562-c272-4cb7-857c-1779c7def92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311156961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.311156961
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.654329768
Short name T167
Test name
Test status
Simulation time 60565394174 ps
CPU time 26.49 seconds
Started Jun 21 04:47:28 PM PDT 24
Finished Jun 21 04:48:03 PM PDT 24
Peak memory 200612 kb
Host smart-6bec9276-217b-4097-84d1-5dbb0d7e7658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654329768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.654329768
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.2177784027
Short name T12
Test name
Test status
Simulation time 9917465943 ps
CPU time 18.14 seconds
Started Jun 21 04:47:31 PM PDT 24
Finished Jun 21 04:47:57 PM PDT 24
Peak memory 200536 kb
Host smart-d233da5d-a984-4f76-8a8b-439cdb93d5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177784027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.2177784027
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.783863317
Short name T602
Test name
Test status
Simulation time 229670032357 ps
CPU time 21.3 seconds
Started Jun 21 04:47:31 PM PDT 24
Finished Jun 21 04:48:01 PM PDT 24
Peak memory 200564 kb
Host smart-4cb1c480-67a4-4c07-8d61-a618d74ee791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783863317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.783863317
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.1642344465
Short name T765
Test name
Test status
Simulation time 80323025592 ps
CPU time 33.4 seconds
Started Jun 21 04:47:27 PM PDT 24
Finished Jun 21 04:48:09 PM PDT 24
Peak memory 200588 kb
Host smart-da23a765-5c78-447e-aad1-d9defcf57495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642344465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.1642344465
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.3867442284
Short name T182
Test name
Test status
Simulation time 74783715141 ps
CPU time 40.88 seconds
Started Jun 21 04:47:33 PM PDT 24
Finished Jun 21 04:48:21 PM PDT 24
Peak memory 200544 kb
Host smart-289efc71-9f8e-431d-b80f-e93dc7633d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867442284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.3867442284
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.2053567453
Short name T532
Test name
Test status
Simulation time 88975909 ps
CPU time 0.52 seconds
Started Jun 21 04:45:09 PM PDT 24
Finished Jun 21 04:45:12 PM PDT 24
Peak memory 195992 kb
Host smart-6286aebc-2a56-47a2-9130-8207f2e60ff8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053567453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.2053567453
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.113710676
Short name T634
Test name
Test status
Simulation time 42570902349 ps
CPU time 26.17 seconds
Started Jun 21 04:45:13 PM PDT 24
Finished Jun 21 04:45:42 PM PDT 24
Peak memory 200692 kb
Host smart-80c3e4e5-d270-424a-a588-5231e3c6c814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113710676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.113710676
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.2983592294
Short name T181
Test name
Test status
Simulation time 120185687503 ps
CPU time 22.25 seconds
Started Jun 21 04:45:11 PM PDT 24
Finished Jun 21 04:45:36 PM PDT 24
Peak memory 200236 kb
Host smart-0d2f67cd-d410-45a6-ab4c-58180e9a71bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983592294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.2983592294
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.399427380
Short name T139
Test name
Test status
Simulation time 222878605651 ps
CPU time 47.25 seconds
Started Jun 21 04:45:10 PM PDT 24
Finished Jun 21 04:46:01 PM PDT 24
Peak memory 200596 kb
Host smart-20b9537f-bd28-4a82-8d71-66a7bebc4e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399427380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.399427380
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.3117457388
Short name T291
Test name
Test status
Simulation time 41138764503 ps
CPU time 8.44 seconds
Started Jun 21 04:45:11 PM PDT 24
Finished Jun 21 04:45:22 PM PDT 24
Peak memory 200644 kb
Host smart-f24d6c70-a1de-4958-9153-82df7d026eb1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117457388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.3117457388
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.1325631515
Short name T834
Test name
Test status
Simulation time 132852224987 ps
CPU time 1090.67 seconds
Started Jun 21 04:45:11 PM PDT 24
Finished Jun 21 05:03:25 PM PDT 24
Peak memory 200556 kb
Host smart-31a3bd6e-f3c6-4e29-9343-052d4f71cb90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1325631515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.1325631515
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.1967539210
Short name T418
Test name
Test status
Simulation time 8842543670 ps
CPU time 17.18 seconds
Started Jun 21 04:45:12 PM PDT 24
Finished Jun 21 04:45:32 PM PDT 24
Peak memory 200624 kb
Host smart-bf795b8a-9baa-4ee4-9cbe-004c0ed6bebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967539210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.1967539210
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_perf.1183656123
Short name T452
Test name
Test status
Simulation time 9038038870 ps
CPU time 84.02 seconds
Started Jun 21 04:45:18 PM PDT 24
Finished Jun 21 04:46:43 PM PDT 24
Peak memory 200516 kb
Host smart-317b9f75-e1c2-4a93-a3e0-94f2ebefe961
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1183656123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.1183656123
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.1713630479
Short name T363
Test name
Test status
Simulation time 1617012200 ps
CPU time 2.06 seconds
Started Jun 21 04:45:10 PM PDT 24
Finished Jun 21 04:45:14 PM PDT 24
Peak memory 199200 kb
Host smart-9b7b4e96-b0e1-46e4-9a58-7589a047dbd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1713630479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.1713630479
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.1586041759
Short name T949
Test name
Test status
Simulation time 174987483348 ps
CPU time 140.77 seconds
Started Jun 21 04:45:11 PM PDT 24
Finished Jun 21 04:47:35 PM PDT 24
Peak memory 200624 kb
Host smart-cb665835-f53f-4585-b915-65b87cfa6ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586041759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.1586041759
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.2708692288
Short name T893
Test name
Test status
Simulation time 42653814839 ps
CPU time 6.68 seconds
Started Jun 21 04:45:11 PM PDT 24
Finished Jun 21 04:45:21 PM PDT 24
Peak memory 196880 kb
Host smart-ec031fe7-e601-41c4-8a86-df8fec8a7a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708692288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.2708692288
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.2876754121
Short name T977
Test name
Test status
Simulation time 5581858717 ps
CPU time 8.47 seconds
Started Jun 21 04:45:11 PM PDT 24
Finished Jun 21 04:45:23 PM PDT 24
Peak memory 200456 kb
Host smart-6b8d9342-25dc-43ae-9cf0-68b845c98409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876754121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.2876754121
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.3052029355
Short name T610
Test name
Test status
Simulation time 204440871809 ps
CPU time 194.22 seconds
Started Jun 21 04:45:18 PM PDT 24
Finished Jun 21 04:48:34 PM PDT 24
Peak memory 200504 kb
Host smart-76dd0dd4-d512-4950-a13e-047be15c7bb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052029355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.3052029355
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.3528770915
Short name T119
Test name
Test status
Simulation time 74381587705 ps
CPU time 388.36 seconds
Started Jun 21 04:45:16 PM PDT 24
Finished Jun 21 04:51:45 PM PDT 24
Peak memory 217060 kb
Host smart-aa230167-4088-410e-801f-7decfc5c1986
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528770915 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.3528770915
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.2863800993
Short name T522
Test name
Test status
Simulation time 906387670 ps
CPU time 2.09 seconds
Started Jun 21 04:45:10 PM PDT 24
Finished Jun 21 04:45:15 PM PDT 24
Peak memory 198900 kb
Host smart-8feca653-3793-4163-9013-97965691bc33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863800993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.2863800993
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.1086424812
Short name T985
Test name
Test status
Simulation time 68698617199 ps
CPU time 53.95 seconds
Started Jun 21 04:45:11 PM PDT 24
Finished Jun 21 04:46:08 PM PDT 24
Peak memory 200668 kb
Host smart-ce8e4b7e-378e-45dc-afce-d30670d45d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086424812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.1086424812
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.161431268
Short name T489
Test name
Test status
Simulation time 9754238912 ps
CPU time 15.85 seconds
Started Jun 21 04:47:32 PM PDT 24
Finished Jun 21 04:47:56 PM PDT 24
Peak memory 199784 kb
Host smart-6d8d5df1-009f-4edd-ab46-e0b28b7722a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161431268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.161431268
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.2261955847
Short name T57
Test name
Test status
Simulation time 21809534033 ps
CPU time 30.32 seconds
Started Jun 21 04:47:33 PM PDT 24
Finished Jun 21 04:48:11 PM PDT 24
Peak memory 200592 kb
Host smart-9ca916e5-84ca-48ab-8c99-2e2e167ab61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261955847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.2261955847
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.1284221806
Short name T710
Test name
Test status
Simulation time 130662290736 ps
CPU time 35.34 seconds
Started Jun 21 04:47:33 PM PDT 24
Finished Jun 21 04:48:15 PM PDT 24
Peak memory 200616 kb
Host smart-888881c8-5d88-4d0e-ab8c-79ed93efa9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284221806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.1284221806
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.1511820165
Short name T310
Test name
Test status
Simulation time 131013497831 ps
CPU time 276.55 seconds
Started Jun 21 04:47:31 PM PDT 24
Finished Jun 21 04:52:15 PM PDT 24
Peak memory 200596 kb
Host smart-0820935b-8d58-4641-851c-1df5af069b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511820165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.1511820165
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.3149284869
Short name T404
Test name
Test status
Simulation time 15199163590 ps
CPU time 11.43 seconds
Started Jun 21 04:47:28 PM PDT 24
Finished Jun 21 04:47:48 PM PDT 24
Peak memory 198872 kb
Host smart-e41e01e1-5b4a-4ee3-9396-e976eaf0dd0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149284869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.3149284869
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.1116864357
Short name T224
Test name
Test status
Simulation time 18684477715 ps
CPU time 36.22 seconds
Started Jun 21 04:47:32 PM PDT 24
Finished Jun 21 04:48:16 PM PDT 24
Peak memory 200564 kb
Host smart-1d680ee5-985c-477b-b8e7-0b88baa29cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116864357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.1116864357
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.2054696715
Short name T933
Test name
Test status
Simulation time 120846167229 ps
CPU time 38.31 seconds
Started Jun 21 04:47:28 PM PDT 24
Finished Jun 21 04:48:15 PM PDT 24
Peak memory 200512 kb
Host smart-35567755-120e-43cc-af35-6e85574d613a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054696715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.2054696715
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.4170572484
Short name T684
Test name
Test status
Simulation time 39467410052 ps
CPU time 16.37 seconds
Started Jun 21 04:47:28 PM PDT 24
Finished Jun 21 04:47:52 PM PDT 24
Peak memory 200608 kb
Host smart-a7afc1c5-f307-4937-8249-19c51e2e747a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170572484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.4170572484
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.1648039480
Short name T96
Test name
Test status
Simulation time 148515237672 ps
CPU time 58.41 seconds
Started Jun 21 04:47:34 PM PDT 24
Finished Jun 21 04:48:39 PM PDT 24
Peak memory 200704 kb
Host smart-e53571a6-5dcc-4eab-a3d2-4479f51cd1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648039480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.1648039480
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.1657700313
Short name T708
Test name
Test status
Simulation time 13573315 ps
CPU time 0.56 seconds
Started Jun 21 04:45:42 PM PDT 24
Finished Jun 21 04:45:44 PM PDT 24
Peak memory 196028 kb
Host smart-748c62e0-5937-43e8-aa8e-c64b2b4fc753
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657700313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.1657700313
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.844601170
Short name T574
Test name
Test status
Simulation time 79915080275 ps
CPU time 63.7 seconds
Started Jun 21 04:45:12 PM PDT 24
Finished Jun 21 04:46:19 PM PDT 24
Peak memory 200544 kb
Host smart-816f8c88-2926-49e7-9d7f-36963a2b6bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844601170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.844601170
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.2993611080
Short name T143
Test name
Test status
Simulation time 10497900817 ps
CPU time 17.03 seconds
Started Jun 21 04:45:19 PM PDT 24
Finished Jun 21 04:45:37 PM PDT 24
Peak memory 200348 kb
Host smart-d6976d66-2129-46a8-a910-df5331112c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993611080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.2993611080
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.1530150286
Short name T519
Test name
Test status
Simulation time 75659800447 ps
CPU time 21.6 seconds
Started Jun 21 04:45:11 PM PDT 24
Finished Jun 21 04:45:35 PM PDT 24
Peak memory 200608 kb
Host smart-fb8b0960-7613-4ee8-958b-9f156defd5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530150286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.1530150286
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.2835967778
Short name T1011
Test name
Test status
Simulation time 39561892977 ps
CPU time 32.49 seconds
Started Jun 21 04:45:12 PM PDT 24
Finished Jun 21 04:45:47 PM PDT 24
Peak memory 200624 kb
Host smart-5f713e64-c18a-4a7f-98d3-c1e7ee3c234a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835967778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.2835967778
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.1332826845
Short name T647
Test name
Test status
Simulation time 326763041883 ps
CPU time 416.34 seconds
Started Jun 21 04:45:41 PM PDT 24
Finished Jun 21 04:52:39 PM PDT 24
Peak memory 200668 kb
Host smart-573638ef-67b9-4282-9821-ba5195911420
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1332826845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.1332826845
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.2657149018
Short name T512
Test name
Test status
Simulation time 2499719719 ps
CPU time 5.39 seconds
Started Jun 21 04:45:40 PM PDT 24
Finished Jun 21 04:45:47 PM PDT 24
Peak memory 199840 kb
Host smart-5bf453ff-f6ca-4ca5-89ea-8839aad396a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657149018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.2657149018
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_perf.3168771107
Short name T326
Test name
Test status
Simulation time 2944051535 ps
CPU time 141.23 seconds
Started Jun 21 04:45:40 PM PDT 24
Finished Jun 21 04:48:02 PM PDT 24
Peak memory 200576 kb
Host smart-fe499696-8d67-4a21-b8ce-b8ce14acff04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3168771107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.3168771107
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.262576637
Short name T654
Test name
Test status
Simulation time 3788899280 ps
CPU time 7.57 seconds
Started Jun 21 04:45:16 PM PDT 24
Finished Jun 21 04:45:24 PM PDT 24
Peak memory 198876 kb
Host smart-439c23ca-47ee-4e1d-9366-e245a60da52a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=262576637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.262576637
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.2451288273
Short name T1057
Test name
Test status
Simulation time 109312714528 ps
CPU time 212.51 seconds
Started Jun 21 04:45:12 PM PDT 24
Finished Jun 21 04:48:48 PM PDT 24
Peak memory 200700 kb
Host smart-d2a8947d-f73d-4d6e-9285-03aaf5da5568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451288273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.2451288273
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.1936522410
Short name T380
Test name
Test status
Simulation time 4228396075 ps
CPU time 7.26 seconds
Started Jun 21 04:45:18 PM PDT 24
Finished Jun 21 04:45:26 PM PDT 24
Peak memory 196660 kb
Host smart-b49dd96c-8f08-4bef-8434-00feb8602b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936522410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.1936522410
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.3859558335
Short name T261
Test name
Test status
Simulation time 738128979 ps
CPU time 1.91 seconds
Started Jun 21 04:45:19 PM PDT 24
Finished Jun 21 04:45:22 PM PDT 24
Peak memory 200168 kb
Host smart-73882e8c-0e05-4217-85a6-f549f97b90e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859558335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.3859558335
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.2339367401
Short name T1053
Test name
Test status
Simulation time 126274806222 ps
CPU time 548.82 seconds
Started Jun 21 04:45:40 PM PDT 24
Finished Jun 21 04:54:50 PM PDT 24
Peak memory 200552 kb
Host smart-fe91ca19-3655-4144-a28d-f4ca7a8b9212
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339367401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.2339367401
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.2011885029
Short name T69
Test name
Test status
Simulation time 44809851527 ps
CPU time 373.92 seconds
Started Jun 21 04:45:40 PM PDT 24
Finished Jun 21 04:51:56 PM PDT 24
Peak memory 215796 kb
Host smart-c033d709-bd23-4600-af23-cef92a42407e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011885029 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.2011885029
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.2499846992
Short name T298
Test name
Test status
Simulation time 677191209 ps
CPU time 2.05 seconds
Started Jun 21 04:45:39 PM PDT 24
Finished Jun 21 04:45:42 PM PDT 24
Peak memory 199188 kb
Host smart-c94b972b-7662-4ec2-8761-4cdfbd360d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499846992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.2499846992
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.2375320283
Short name T709
Test name
Test status
Simulation time 114925749940 ps
CPU time 77.64 seconds
Started Jun 21 04:45:12 PM PDT 24
Finished Jun 21 04:46:33 PM PDT 24
Peak memory 200668 kb
Host smart-cde2cfa8-beac-4eb2-996a-230adc172eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375320283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.2375320283
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.1239959685
Short name T593
Test name
Test status
Simulation time 251474924845 ps
CPU time 75.51 seconds
Started Jun 21 04:47:59 PM PDT 24
Finished Jun 21 04:49:16 PM PDT 24
Peak memory 200212 kb
Host smart-8ccbb90f-8041-43b2-a88c-0ee03f7d292e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239959685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.1239959685
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.4015671070
Short name T1023
Test name
Test status
Simulation time 17319920824 ps
CPU time 31.98 seconds
Started Jun 21 04:47:30 PM PDT 24
Finished Jun 21 04:48:11 PM PDT 24
Peak memory 200624 kb
Host smart-84778378-a5ef-4bb2-8cbe-433912d00c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015671070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.4015671070
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.3491092973
Short name T600
Test name
Test status
Simulation time 98262939792 ps
CPU time 80.19 seconds
Started Jun 21 04:47:26 PM PDT 24
Finished Jun 21 04:48:55 PM PDT 24
Peak memory 200680 kb
Host smart-dc172166-53b8-4881-a177-9c680a2d33d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491092973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.3491092973
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.2792143871
Short name T678
Test name
Test status
Simulation time 27265532981 ps
CPU time 21.54 seconds
Started Jun 21 04:47:28 PM PDT 24
Finished Jun 21 04:47:59 PM PDT 24
Peak memory 200628 kb
Host smart-684ca947-cb27-4166-88de-a41ffc07c638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792143871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.2792143871
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.2639930823
Short name T906
Test name
Test status
Simulation time 151030028805 ps
CPU time 63.77 seconds
Started Jun 21 04:47:27 PM PDT 24
Finished Jun 21 04:48:39 PM PDT 24
Peak memory 200452 kb
Host smart-23976d62-227c-4b0b-aa21-bca057261460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639930823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.2639930823
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.2574638616
Short name T746
Test name
Test status
Simulation time 26338211775 ps
CPU time 70.06 seconds
Started Jun 21 04:47:30 PM PDT 24
Finished Jun 21 04:48:49 PM PDT 24
Peak memory 200540 kb
Host smart-e14c6fe2-f16a-4f44-b428-3bdd40c72e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574638616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.2574638616
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.930914610
Short name T780
Test name
Test status
Simulation time 388401311240 ps
CPU time 33.47 seconds
Started Jun 21 04:47:34 PM PDT 24
Finished Jun 21 04:48:14 PM PDT 24
Peak memory 200512 kb
Host smart-0e32a885-04a3-45f9-96fa-b7d5bf067b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930914610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.930914610
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.4222613526
Short name T983
Test name
Test status
Simulation time 86524829380 ps
CPU time 146.08 seconds
Started Jun 21 04:47:27 PM PDT 24
Finished Jun 21 04:50:01 PM PDT 24
Peak memory 200544 kb
Host smart-2be8dd64-35f1-4e30-a120-796188f071b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222613526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.4222613526
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.1151294651
Short name T1034
Test name
Test status
Simulation time 21638712598 ps
CPU time 28.45 seconds
Started Jun 21 04:47:30 PM PDT 24
Finished Jun 21 04:48:07 PM PDT 24
Peak memory 200648 kb
Host smart-f390aad3-a885-4dae-a259-e42fde084ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151294651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.1151294651
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.3029618581
Short name T802
Test name
Test status
Simulation time 13989577 ps
CPU time 0.57 seconds
Started Jun 21 04:45:42 PM PDT 24
Finished Jun 21 04:45:44 PM PDT 24
Peak memory 194940 kb
Host smart-4287f3d0-41c3-4b80-a142-f52ff3f9c51e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029618581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.3029618581
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.2197354241
Short name T556
Test name
Test status
Simulation time 15334127863 ps
CPU time 26.04 seconds
Started Jun 21 04:45:39 PM PDT 24
Finished Jun 21 04:46:05 PM PDT 24
Peak memory 200572 kb
Host smart-65fc5351-0ecb-4409-a5a1-7ed07c0c3f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197354241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.2197354241
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.2554120972
Short name T412
Test name
Test status
Simulation time 70496388993 ps
CPU time 20.49 seconds
Started Jun 21 04:45:40 PM PDT 24
Finished Jun 21 04:46:03 PM PDT 24
Peak memory 200564 kb
Host smart-5792a59e-9a74-4316-be88-5d9290517861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554120972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.2554120972
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.2207522663
Short name T998
Test name
Test status
Simulation time 68706921369 ps
CPU time 69.32 seconds
Started Jun 21 04:45:40 PM PDT 24
Finished Jun 21 04:46:50 PM PDT 24
Peak memory 200672 kb
Host smart-2f759771-8855-43c0-8c32-05ff6e377ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207522663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.2207522663
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.2144630683
Short name T557
Test name
Test status
Simulation time 138652122468 ps
CPU time 218.75 seconds
Started Jun 21 04:45:41 PM PDT 24
Finished Jun 21 04:49:21 PM PDT 24
Peak memory 198556 kb
Host smart-33b9bb63-bc51-465c-b22f-8ad745a44b1c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144630683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.2144630683
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.2507395056
Short name T408
Test name
Test status
Simulation time 64082160009 ps
CPU time 399.99 seconds
Started Jun 21 04:45:41 PM PDT 24
Finished Jun 21 04:52:22 PM PDT 24
Peak memory 200592 kb
Host smart-eb617287-c625-4b46-aa81-6868bcf85d80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2507395056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.2507395056
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.1488825659
Short name T823
Test name
Test status
Simulation time 7260811655 ps
CPU time 12.77 seconds
Started Jun 21 04:45:42 PM PDT 24
Finished Jun 21 04:45:56 PM PDT 24
Peak memory 199064 kb
Host smart-dafdb630-7d12-4e09-8781-6167a546251d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488825659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.1488825659
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_perf.3063890451
Short name T337
Test name
Test status
Simulation time 19739198563 ps
CPU time 238.88 seconds
Started Jun 21 04:45:41 PM PDT 24
Finished Jun 21 04:49:41 PM PDT 24
Peak memory 200568 kb
Host smart-a3f21b15-a9fa-4572-8032-4120b093b993
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3063890451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.3063890451
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.3704049487
Short name T939
Test name
Test status
Simulation time 1410694799 ps
CPU time 1.38 seconds
Started Jun 21 04:45:42 PM PDT 24
Finished Jun 21 04:45:45 PM PDT 24
Peak memory 199780 kb
Host smart-a7703c16-7591-4abe-b2f2-aaa6b914b20b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3704049487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.3704049487
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.486149046
Short name T138
Test name
Test status
Simulation time 99181216508 ps
CPU time 145.53 seconds
Started Jun 21 04:45:41 PM PDT 24
Finished Jun 21 04:48:08 PM PDT 24
Peak memory 200672 kb
Host smart-e8de6f0b-f3dc-49e2-b1cd-049b7d2e131c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486149046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.486149046
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.269365225
Short name T285
Test name
Test status
Simulation time 3124030719 ps
CPU time 5.22 seconds
Started Jun 21 04:45:38 PM PDT 24
Finished Jun 21 04:45:44 PM PDT 24
Peak memory 196464 kb
Host smart-212e80e0-7729-4368-b240-8b8b494ebb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269365225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.269365225
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.1721057589
Short name T777
Test name
Test status
Simulation time 5790671458 ps
CPU time 20.01 seconds
Started Jun 21 04:45:43 PM PDT 24
Finished Jun 21 04:46:05 PM PDT 24
Peak memory 200632 kb
Host smart-ca8d81ad-0f7c-4433-bfb4-2cc4c2152cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721057589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.1721057589
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.4283251277
Short name T525
Test name
Test status
Simulation time 136605860463 ps
CPU time 284.46 seconds
Started Jun 21 04:45:44 PM PDT 24
Finished Jun 21 04:50:30 PM PDT 24
Peak memory 200604 kb
Host smart-6a7839ca-2d41-4dfd-8172-403d0f17e9a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283251277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.4283251277
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.3158678511
Short name T720
Test name
Test status
Simulation time 83200867538 ps
CPU time 59.98 seconds
Started Jun 21 04:45:40 PM PDT 24
Finished Jun 21 04:46:41 PM PDT 24
Peak memory 208920 kb
Host smart-b6598431-5831-4efb-8258-c0177ff86964
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158678511 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.3158678511
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.3215016329
Short name T420
Test name
Test status
Simulation time 1219534316 ps
CPU time 5.91 seconds
Started Jun 21 04:45:42 PM PDT 24
Finished Jun 21 04:45:49 PM PDT 24
Peak memory 199516 kb
Host smart-907900d4-ad91-4496-b382-3ce14460628c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215016329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.3215016329
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.3110058310
Short name T534
Test name
Test status
Simulation time 18694399223 ps
CPU time 15.89 seconds
Started Jun 21 04:45:43 PM PDT 24
Finished Jun 21 04:46:01 PM PDT 24
Peak memory 200576 kb
Host smart-f0de8f07-c868-4b9c-a853-9188560b4e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110058310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.3110058310
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.4251040771
Short name T544
Test name
Test status
Simulation time 35932194779 ps
CPU time 60.87 seconds
Started Jun 21 04:47:27 PM PDT 24
Finished Jun 21 04:48:36 PM PDT 24
Peak memory 200688 kb
Host smart-e76175d7-0a89-4c38-8f90-f0c526f32140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251040771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.4251040771
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.2748040544
Short name T601
Test name
Test status
Simulation time 27743793798 ps
CPU time 40.77 seconds
Started Jun 21 04:47:27 PM PDT 24
Finished Jun 21 04:48:16 PM PDT 24
Peak memory 199580 kb
Host smart-fc446243-7e92-471c-8be9-ebc20382fe59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748040544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.2748040544
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.435453731
Short name T256
Test name
Test status
Simulation time 51506033207 ps
CPU time 82.34 seconds
Started Jun 21 04:47:34 PM PDT 24
Finished Jun 21 04:49:03 PM PDT 24
Peak memory 200676 kb
Host smart-b2ada691-31b1-4950-a0ef-b83797642d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435453731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.435453731
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.2362311856
Short name T165
Test name
Test status
Simulation time 36994009258 ps
CPU time 20.97 seconds
Started Jun 21 04:47:28 PM PDT 24
Finished Jun 21 04:47:57 PM PDT 24
Peak memory 200568 kb
Host smart-4cd07688-71fe-4887-ae9e-5118da95fe36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362311856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.2362311856
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.3325723514
Short name T485
Test name
Test status
Simulation time 59561435509 ps
CPU time 41.59 seconds
Started Jun 21 04:47:26 PM PDT 24
Finished Jun 21 04:48:15 PM PDT 24
Peak memory 200576 kb
Host smart-f7fc66a2-9cd5-4b51-829b-686252393c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325723514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.3325723514
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.3181140386
Short name T1047
Test name
Test status
Simulation time 58773937354 ps
CPU time 75.99 seconds
Started Jun 21 04:47:28 PM PDT 24
Finished Jun 21 04:48:52 PM PDT 24
Peak memory 200648 kb
Host smart-3578fef6-484f-4af8-874b-d6cc6601b0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181140386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.3181140386
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.2415242469
Short name T581
Test name
Test status
Simulation time 118355539584 ps
CPU time 50.31 seconds
Started Jun 21 04:47:28 PM PDT 24
Finished Jun 21 04:48:26 PM PDT 24
Peak memory 200572 kb
Host smart-2d7aa3a2-39e8-4375-a607-5c9fe6d3c114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415242469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.2415242469
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.747362634
Short name T192
Test name
Test status
Simulation time 53156679879 ps
CPU time 63.39 seconds
Started Jun 21 04:47:25 PM PDT 24
Finished Jun 21 04:48:36 PM PDT 24
Peak memory 200564 kb
Host smart-945756a1-37f2-413b-8853-9b1b6ffdcb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747362634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.747362634
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.4202916104
Short name T433
Test name
Test status
Simulation time 42682106 ps
CPU time 0.57 seconds
Started Jun 21 04:45:43 PM PDT 24
Finished Jun 21 04:45:45 PM PDT 24
Peak memory 195964 kb
Host smart-e6f83ade-6c97-4b3c-8ac4-ab6f5b324945
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202916104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.4202916104
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.1768132207
Short name T615
Test name
Test status
Simulation time 15704478688 ps
CPU time 26.1 seconds
Started Jun 21 04:45:39 PM PDT 24
Finished Jun 21 04:46:06 PM PDT 24
Peak memory 200424 kb
Host smart-19685b70-e124-4be2-a042-c95ec2ce9813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768132207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.1768132207
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.608344086
Short name T912
Test name
Test status
Simulation time 60694767565 ps
CPU time 147.45 seconds
Started Jun 21 04:45:41 PM PDT 24
Finished Jun 21 04:48:10 PM PDT 24
Peak memory 200828 kb
Host smart-fb76cd84-b5dc-4579-8cbd-0b5bbc988b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608344086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.608344086
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_intr.2843786740
Short name T1003
Test name
Test status
Simulation time 10790845505 ps
CPU time 5.38 seconds
Started Jun 21 04:45:39 PM PDT 24
Finished Jun 21 04:45:46 PM PDT 24
Peak memory 200660 kb
Host smart-5508382b-0bfa-469c-96d8-3064d808d069
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843786740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.2843786740
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.418431026
Short name T421
Test name
Test status
Simulation time 192620292370 ps
CPU time 1165.17 seconds
Started Jun 21 04:45:40 PM PDT 24
Finished Jun 21 05:05:06 PM PDT 24
Peak memory 200580 kb
Host smart-5f26084b-1095-40d1-8734-827bb80e162c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=418431026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.418431026
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.963079931
Short name T372
Test name
Test status
Simulation time 10773167725 ps
CPU time 8.18 seconds
Started Jun 21 04:45:40 PM PDT 24
Finished Jun 21 04:45:49 PM PDT 24
Peak memory 199332 kb
Host smart-327df230-f8f7-43c1-800d-d50decdd2030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963079931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.963079931
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_perf.4032099000
Short name T734
Test name
Test status
Simulation time 25239846205 ps
CPU time 353.93 seconds
Started Jun 21 04:45:39 PM PDT 24
Finished Jun 21 04:51:33 PM PDT 24
Peak memory 200588 kb
Host smart-97172112-56e0-41ca-afa1-be2bd9986406
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4032099000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.4032099000
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.2747001927
Short name T110
Test name
Test status
Simulation time 6301161992 ps
CPU time 50.46 seconds
Started Jun 21 04:45:41 PM PDT 24
Finished Jun 21 04:46:33 PM PDT 24
Peak memory 199712 kb
Host smart-a5d61e86-5a21-4997-921e-4f2797de7e70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2747001927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.2747001927
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.247025674
Short name T383
Test name
Test status
Simulation time 3331599650 ps
CPU time 3.43 seconds
Started Jun 21 04:45:41 PM PDT 24
Finished Jun 21 04:45:46 PM PDT 24
Peak memory 196472 kb
Host smart-243e6439-e2bf-461b-9be2-b94c7976ebe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247025674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.247025674
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.1406485770
Short name T851
Test name
Test status
Simulation time 5545468723 ps
CPU time 17.77 seconds
Started Jun 21 04:45:42 PM PDT 24
Finished Jun 21 04:46:01 PM PDT 24
Peak memory 200644 kb
Host smart-14ef4c1f-ed22-4ec2-baba-b2389d87f23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406485770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.1406485770
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.1272612520
Short name T900
Test name
Test status
Simulation time 25811268677 ps
CPU time 643.34 seconds
Started Jun 21 04:45:42 PM PDT 24
Finished Jun 21 04:56:27 PM PDT 24
Peak memory 217052 kb
Host smart-6dfedb52-c658-43a1-9123-3465cc80be70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272612520 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.1272612520
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.709083186
Short name T919
Test name
Test status
Simulation time 1397839213 ps
CPU time 2.68 seconds
Started Jun 21 04:45:41 PM PDT 24
Finished Jun 21 04:45:46 PM PDT 24
Peak memory 199640 kb
Host smart-3c30a2bc-8e0c-4e5a-817a-907e6e275002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709083186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.709083186
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.2876829669
Short name T307
Test name
Test status
Simulation time 29962049046 ps
CPU time 46.31 seconds
Started Jun 21 04:45:42 PM PDT 24
Finished Jun 21 04:46:29 PM PDT 24
Peak memory 200700 kb
Host smart-2c544b60-ed7e-4312-b717-b53d563fa250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876829669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.2876829669
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.1686026609
Short name T227
Test name
Test status
Simulation time 42639043527 ps
CPU time 60.34 seconds
Started Jun 21 04:47:35 PM PDT 24
Finished Jun 21 04:48:42 PM PDT 24
Peak memory 200580 kb
Host smart-a8874ea6-1e8e-49e7-897a-9f47c89e79ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686026609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.1686026609
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.3109894787
Short name T288
Test name
Test status
Simulation time 31008657684 ps
CPU time 100.47 seconds
Started Jun 21 04:47:37 PM PDT 24
Finished Jun 21 04:49:22 PM PDT 24
Peak memory 200620 kb
Host smart-1871690c-1da3-4793-9597-e359046ae980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109894787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.3109894787
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.3414481428
Short name T221
Test name
Test status
Simulation time 10566413739 ps
CPU time 39.99 seconds
Started Jun 21 04:47:34 PM PDT 24
Finished Jun 21 04:48:21 PM PDT 24
Peak memory 200676 kb
Host smart-09f7645b-bd15-41ce-961c-7b26c130d1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414481428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.3414481428
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.3655703612
Short name T840
Test name
Test status
Simulation time 66329872311 ps
CPU time 29.76 seconds
Started Jun 21 04:47:34 PM PDT 24
Finished Jun 21 04:48:11 PM PDT 24
Peak memory 200504 kb
Host smart-1e3c56d8-93fa-432f-815c-52ce0db672e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655703612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.3655703612
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.2165189497
Short name T992
Test name
Test status
Simulation time 34660335430 ps
CPU time 36.42 seconds
Started Jun 21 04:47:38 PM PDT 24
Finished Jun 21 04:48:18 PM PDT 24
Peak memory 200628 kb
Host smart-8cb74ded-b1c8-4fd2-b832-20aebc4f181a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165189497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.2165189497
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.4089168320
Short name T613
Test name
Test status
Simulation time 102696354289 ps
CPU time 45.83 seconds
Started Jun 21 04:47:38 PM PDT 24
Finished Jun 21 04:48:28 PM PDT 24
Peak memory 200604 kb
Host smart-1e0bb545-77ab-460a-86ec-c6bd9502cc6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089168320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.4089168320
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.2098308987
Short name T828
Test name
Test status
Simulation time 61541730292 ps
CPU time 228.58 seconds
Started Jun 21 04:47:38 PM PDT 24
Finished Jun 21 04:51:31 PM PDT 24
Peak memory 200536 kb
Host smart-b538d53a-4191-4798-af60-d2558b899f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098308987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.2098308987
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.4139843449
Short name T1046
Test name
Test status
Simulation time 71166111237 ps
CPU time 27.84 seconds
Started Jun 21 04:47:37 PM PDT 24
Finished Jun 21 04:48:10 PM PDT 24
Peak memory 200512 kb
Host smart-9b0ae3c5-a9b2-4575-bd80-69f1f1204bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139843449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.4139843449
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.2717319909
Short name T951
Test name
Test status
Simulation time 180570145162 ps
CPU time 95.79 seconds
Started Jun 21 04:47:35 PM PDT 24
Finished Jun 21 04:49:17 PM PDT 24
Peak memory 200688 kb
Host smart-236b5170-67c7-48e4-abce-34066d7d68f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717319909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.2717319909
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.3605970542
Short name T136
Test name
Test status
Simulation time 74773673890 ps
CPU time 115.1 seconds
Started Jun 21 04:47:40 PM PDT 24
Finished Jun 21 04:49:38 PM PDT 24
Peak memory 200612 kb
Host smart-c6a63abf-b0ce-4741-b036-9ed73c04424d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605970542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.3605970542
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.1086623758
Short name T536
Test name
Test status
Simulation time 37829201 ps
CPU time 0.61 seconds
Started Jun 21 04:45:46 PM PDT 24
Finished Jun 21 04:45:47 PM PDT 24
Peak memory 195972 kb
Host smart-358cf7d8-2f52-4f58-90c1-b76c276fa82d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086623758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.1086623758
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.1914862586
Short name T484
Test name
Test status
Simulation time 35749832545 ps
CPU time 29.04 seconds
Started Jun 21 04:45:43 PM PDT 24
Finished Jun 21 04:46:13 PM PDT 24
Peak memory 200684 kb
Host smart-cf6deb32-4407-4d1b-81bd-8e17331386b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914862586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.1914862586
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.3669250758
Short name T677
Test name
Test status
Simulation time 67458408605 ps
CPU time 42.11 seconds
Started Jun 21 04:45:40 PM PDT 24
Finished Jun 21 04:46:24 PM PDT 24
Peak memory 200644 kb
Host smart-46ce32bf-c082-414e-be6f-aca0ec6e6588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669250758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.3669250758
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.3650242154
Short name T772
Test name
Test status
Simulation time 141765525615 ps
CPU time 258.89 seconds
Started Jun 21 04:45:46 PM PDT 24
Finished Jun 21 04:50:06 PM PDT 24
Peak memory 200560 kb
Host smart-df5c23e7-8888-4886-8de7-809fe21a38c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650242154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.3650242154
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.1670057
Short name T25
Test name
Test status
Simulation time 40862492881 ps
CPU time 59.2 seconds
Started Jun 21 04:45:42 PM PDT 24
Finished Jun 21 04:46:43 PM PDT 24
Peak memory 200440 kb
Host smart-dc01c92f-0a64-4ebb-abfa-7f78d27c2724
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.1670057
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.1963983348
Short name T624
Test name
Test status
Simulation time 94638623345 ps
CPU time 806.28 seconds
Started Jun 21 04:45:44 PM PDT 24
Finished Jun 21 04:59:12 PM PDT 24
Peak memory 200616 kb
Host smart-3126a40a-2259-4b86-9ee0-d2021e99b1f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1963983348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.1963983348
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.1829033879
Short name T728
Test name
Test status
Simulation time 666885533 ps
CPU time 1.55 seconds
Started Jun 21 04:45:44 PM PDT 24
Finished Jun 21 04:45:47 PM PDT 24
Peak memory 196636 kb
Host smart-2b860183-0ed2-46fa-a80a-e19f9445bae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829033879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.1829033879
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_perf.975409048
Short name T509
Test name
Test status
Simulation time 7846758886 ps
CPU time 94.53 seconds
Started Jun 21 04:45:46 PM PDT 24
Finished Jun 21 04:47:21 PM PDT 24
Peak memory 200612 kb
Host smart-49d3caf3-8ce7-4cd9-bbe3-e85208b5f67e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=975409048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.975409048
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.3866857815
Short name T955
Test name
Test status
Simulation time 2236127031 ps
CPU time 3.48 seconds
Started Jun 21 04:45:40 PM PDT 24
Finished Jun 21 04:45:44 PM PDT 24
Peak memory 198764 kb
Host smart-801cbdba-b4b5-4b79-98aa-4d0cd90efc64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3866857815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.3866857815
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.2975574249
Short name T1060
Test name
Test status
Simulation time 141988522998 ps
CPU time 130.85 seconds
Started Jun 21 04:45:42 PM PDT 24
Finished Jun 21 04:47:55 PM PDT 24
Peak memory 200600 kb
Host smart-96aee98b-bcbb-4af4-a36f-0185dcb23d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975574249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.2975574249
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.3178080503
Short name T30
Test name
Test status
Simulation time 3122102116 ps
CPU time 2.93 seconds
Started Jun 21 04:45:46 PM PDT 24
Finished Jun 21 04:45:50 PM PDT 24
Peak memory 196628 kb
Host smart-def13d6c-bb58-4fe5-9854-a902f3db523d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178080503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.3178080503
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.4154369712
Short name T913
Test name
Test status
Simulation time 459007716 ps
CPU time 1.77 seconds
Started Jun 21 04:45:43 PM PDT 24
Finished Jun 21 04:45:46 PM PDT 24
Peak memory 200568 kb
Host smart-b5899fc7-89b7-4ea7-ba03-224be5b07d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154369712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.4154369712
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.3635496304
Short name T496
Test name
Test status
Simulation time 23427810205 ps
CPU time 101.02 seconds
Started Jun 21 04:45:40 PM PDT 24
Finished Jun 21 04:47:23 PM PDT 24
Peak memory 199940 kb
Host smart-fc75ffe1-668a-492d-9909-7ef1a48ac080
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635496304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.3635496304
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.1995728100
Short name T800
Test name
Test status
Simulation time 974404946 ps
CPU time 2.93 seconds
Started Jun 21 04:45:44 PM PDT 24
Finished Jun 21 04:45:48 PM PDT 24
Peak memory 198900 kb
Host smart-57fc6e17-a068-4ef0-b140-890d60963b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995728100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.1995728100
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.2338027579
Short name T561
Test name
Test status
Simulation time 15871908330 ps
CPU time 6.25 seconds
Started Jun 21 04:45:43 PM PDT 24
Finished Jun 21 04:45:51 PM PDT 24
Peak memory 198884 kb
Host smart-207322c2-7baa-48bf-ad5f-3ab72a9f17d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338027579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.2338027579
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.4161251361
Short name T530
Test name
Test status
Simulation time 107968746975 ps
CPU time 238.78 seconds
Started Jun 21 04:47:32 PM PDT 24
Finished Jun 21 04:51:38 PM PDT 24
Peak memory 200560 kb
Host smart-c805c2e9-d3e1-46ec-b03f-f6b933910a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161251361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.4161251361
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.3998113938
Short name T220
Test name
Test status
Simulation time 17875659185 ps
CPU time 37.41 seconds
Started Jun 21 04:47:33 PM PDT 24
Finished Jun 21 04:48:18 PM PDT 24
Peak memory 200628 kb
Host smart-013991a6-12c6-4ce3-b1a1-03489cc9c4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998113938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.3998113938
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.4065701575
Short name T827
Test name
Test status
Simulation time 145000478835 ps
CPU time 56.38 seconds
Started Jun 21 04:47:37 PM PDT 24
Finished Jun 21 04:48:38 PM PDT 24
Peak memory 200540 kb
Host smart-acbb8bf2-4819-442b-98fc-f4a772e297f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065701575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.4065701575
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.1584269358
Short name T177
Test name
Test status
Simulation time 115797287790 ps
CPU time 54.15 seconds
Started Jun 21 04:47:37 PM PDT 24
Finished Jun 21 04:48:36 PM PDT 24
Peak memory 200628 kb
Host smart-9c6ef748-9230-487c-9824-5ed78a71b81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584269358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.1584269358
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.1159747407
Short name T252
Test name
Test status
Simulation time 72454169725 ps
CPU time 152.73 seconds
Started Jun 21 04:47:32 PM PDT 24
Finished Jun 21 04:50:13 PM PDT 24
Peak memory 200176 kb
Host smart-a173287d-3595-4963-9113-d50d5ce9b75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159747407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.1159747407
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.508436938
Short name T375
Test name
Test status
Simulation time 64006187382 ps
CPU time 28.99 seconds
Started Jun 21 04:47:43 PM PDT 24
Finished Jun 21 04:48:14 PM PDT 24
Peak memory 200592 kb
Host smart-4d515660-92eb-4916-85ca-6d02cead2461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508436938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.508436938
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.3912894582
Short name T1088
Test name
Test status
Simulation time 163330486215 ps
CPU time 71.45 seconds
Started Jun 21 04:47:48 PM PDT 24
Finished Jun 21 04:49:01 PM PDT 24
Peak memory 200632 kb
Host smart-136360bd-13ed-469d-af34-5e1138760994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912894582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.3912894582
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.3217487871
Short name T892
Test name
Test status
Simulation time 9373101246 ps
CPU time 15.67 seconds
Started Jun 21 04:47:44 PM PDT 24
Finished Jun 21 04:48:01 PM PDT 24
Peak memory 200688 kb
Host smart-95442b1f-968a-4d1a-9ed0-32b52b9b222f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217487871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.3217487871
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.1258779530
Short name T333
Test name
Test status
Simulation time 73343166373 ps
CPU time 106.4 seconds
Started Jun 21 04:47:44 PM PDT 24
Finished Jun 21 04:49:32 PM PDT 24
Peak memory 200648 kb
Host smart-2bc38f7b-d209-49c8-81c4-04cb8af429b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258779530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.1258779530
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.1850534967
Short name T583
Test name
Test status
Simulation time 100559685560 ps
CPU time 18.4 seconds
Started Jun 21 04:47:42 PM PDT 24
Finished Jun 21 04:48:02 PM PDT 24
Peak memory 200676 kb
Host smart-99dbbc1d-39af-4b9b-bc38-9477814882cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850534967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.1850534967
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.1995073713
Short name T34
Test name
Test status
Simulation time 15700262 ps
CPU time 0.57 seconds
Started Jun 21 04:45:53 PM PDT 24
Finished Jun 21 04:45:54 PM PDT 24
Peak memory 196000 kb
Host smart-3ceecbdf-4203-42a3-b748-3bc3081102c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995073713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.1995073713
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.1434105157
Short name T59
Test name
Test status
Simulation time 352076382761 ps
CPU time 79.13 seconds
Started Jun 21 04:45:46 PM PDT 24
Finished Jun 21 04:47:06 PM PDT 24
Peak memory 200624 kb
Host smart-78a49b88-c495-4c73-9b62-e6e8a2a5c5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434105157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.1434105157
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.1738499771
Short name T957
Test name
Test status
Simulation time 219534601648 ps
CPU time 118.21 seconds
Started Jun 21 04:45:58 PM PDT 24
Finished Jun 21 04:48:01 PM PDT 24
Peak memory 200572 kb
Host smart-e69d4a56-eed9-4f3a-81da-e2a8df1c0f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738499771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.1738499771
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_intr.3831745350
Short name T1101
Test name
Test status
Simulation time 19773919749 ps
CPU time 9.26 seconds
Started Jun 21 04:45:53 PM PDT 24
Finished Jun 21 04:46:03 PM PDT 24
Peak memory 198544 kb
Host smart-d8eeb976-7992-4223-8eee-ec5e8f88e4cc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831745350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.3831745350
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.3936572520
Short name T405
Test name
Test status
Simulation time 63771951327 ps
CPU time 413.39 seconds
Started Jun 21 04:45:55 PM PDT 24
Finished Jun 21 04:52:52 PM PDT 24
Peak memory 200520 kb
Host smart-672a1a81-e3cb-4fbb-8e08-5961f1af0123
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3936572520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.3936572520
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.4055180087
Short name T367
Test name
Test status
Simulation time 5190275367 ps
CPU time 15.54 seconds
Started Jun 21 04:45:56 PM PDT 24
Finished Jun 21 04:46:16 PM PDT 24
Peak memory 200384 kb
Host smart-608bd6be-72e1-441f-95ca-b188c819accf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055180087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.4055180087
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_perf.567130717
Short name T603
Test name
Test status
Simulation time 6343970569 ps
CPU time 184 seconds
Started Jun 21 04:45:52 PM PDT 24
Finished Jun 21 04:48:57 PM PDT 24
Peak memory 200664 kb
Host smart-82f29ca4-37d3-4cf6-8107-b982355c4fd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=567130717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.567130717
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.4089923957
Short name T756
Test name
Test status
Simulation time 6013279660 ps
CPU time 8.88 seconds
Started Jun 21 04:45:53 PM PDT 24
Finished Jun 21 04:46:04 PM PDT 24
Peak memory 198572 kb
Host smart-5daf7dcd-f987-4aa0-898e-efb36f1d2ad2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4089923957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.4089923957
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.3651585186
Short name T1036
Test name
Test status
Simulation time 115085340475 ps
CPU time 87.44 seconds
Started Jun 21 04:45:57 PM PDT 24
Finished Jun 21 04:47:30 PM PDT 24
Peak memory 200564 kb
Host smart-5eb03333-fcc6-400f-be50-5edc7e31a61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651585186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.3651585186
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.2512103262
Short name T947
Test name
Test status
Simulation time 42403186969 ps
CPU time 10.84 seconds
Started Jun 21 04:45:55 PM PDT 24
Finished Jun 21 04:46:09 PM PDT 24
Peak memory 196380 kb
Host smart-ed28e3ea-9c0b-40bc-914d-92924508f781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512103262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.2512103262
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.4023520853
Short name T283
Test name
Test status
Simulation time 500853144 ps
CPU time 2.18 seconds
Started Jun 21 04:45:46 PM PDT 24
Finished Jun 21 04:45:50 PM PDT 24
Peak memory 199612 kb
Host smart-a0bbfd6c-4f03-47c3-bea9-156953a0a6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023520853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.4023520853
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.2764971378
Short name T753
Test name
Test status
Simulation time 107947277173 ps
CPU time 175.54 seconds
Started Jun 21 04:45:52 PM PDT 24
Finished Jun 21 04:48:49 PM PDT 24
Peak memory 200560 kb
Host smart-b0f53282-1445-46d8-a527-fa4e37b07f91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764971378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.2764971378
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.2412151955
Short name T535
Test name
Test status
Simulation time 97762711848 ps
CPU time 616.93 seconds
Started Jun 21 04:45:53 PM PDT 24
Finished Jun 21 04:56:11 PM PDT 24
Peak memory 208948 kb
Host smart-10ebb32b-7685-4839-b3b3-51986e425b06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412151955 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.2412151955
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.2440159817
Short name T942
Test name
Test status
Simulation time 1217678650 ps
CPU time 2.36 seconds
Started Jun 21 04:45:50 PM PDT 24
Finished Jun 21 04:45:53 PM PDT 24
Peak memory 199572 kb
Host smart-fc52c29d-2082-4d16-9b93-f1f600c7a527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440159817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.2440159817
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.1078205039
Short name T313
Test name
Test status
Simulation time 186658744480 ps
CPU time 71.79 seconds
Started Jun 21 04:45:40 PM PDT 24
Finished Jun 21 04:46:53 PM PDT 24
Peak memory 200664 kb
Host smart-eafeaf0a-6e07-4273-839c-736fd8f9be2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078205039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.1078205039
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.2855788149
Short name T395
Test name
Test status
Simulation time 151133813705 ps
CPU time 16.54 seconds
Started Jun 21 04:47:43 PM PDT 24
Finished Jun 21 04:48:01 PM PDT 24
Peak memory 200160 kb
Host smart-86b47462-4771-44e9-a90f-257a5d264ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855788149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.2855788149
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.855934478
Short name T1073
Test name
Test status
Simulation time 20316741819 ps
CPU time 18.34 seconds
Started Jun 21 04:47:45 PM PDT 24
Finished Jun 21 04:48:04 PM PDT 24
Peak memory 200696 kb
Host smart-75995600-25b0-4b66-968c-35fcf781f081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855934478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.855934478
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.1835130372
Short name T958
Test name
Test status
Simulation time 75103503324 ps
CPU time 29.49 seconds
Started Jun 21 04:47:43 PM PDT 24
Finished Jun 21 04:48:14 PM PDT 24
Peak memory 200680 kb
Host smart-264ce297-0064-4b50-ac79-fd55bbd55429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835130372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.1835130372
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.3511179202
Short name T975
Test name
Test status
Simulation time 28325615755 ps
CPU time 38.63 seconds
Started Jun 21 04:47:43 PM PDT 24
Finished Jun 21 04:48:23 PM PDT 24
Peak memory 200180 kb
Host smart-f6c32069-9795-46f9-9ccf-460a40eb004e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511179202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.3511179202
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.4256155299
Short name T852
Test name
Test status
Simulation time 14629557849 ps
CPU time 26.5 seconds
Started Jun 21 04:47:58 PM PDT 24
Finished Jun 21 04:48:26 PM PDT 24
Peak memory 200612 kb
Host smart-6f75d745-c22f-4711-981b-17d41df81ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256155299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.4256155299
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.778083209
Short name T225
Test name
Test status
Simulation time 174053149524 ps
CPU time 76.8 seconds
Started Jun 21 04:48:00 PM PDT 24
Finished Jun 21 04:49:18 PM PDT 24
Peak memory 200652 kb
Host smart-fa7fa745-59ff-4431-899d-da79628b29a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778083209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.778083209
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.2694315633
Short name T209
Test name
Test status
Simulation time 14560111230 ps
CPU time 23.81 seconds
Started Jun 21 04:48:00 PM PDT 24
Finished Jun 21 04:48:26 PM PDT 24
Peak memory 200604 kb
Host smart-6286235e-476c-428e-a1d8-df6c44f4831a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694315633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.2694315633
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.3681808753
Short name T156
Test name
Test status
Simulation time 69943560539 ps
CPU time 181.02 seconds
Started Jun 21 04:48:00 PM PDT 24
Finished Jun 21 04:51:03 PM PDT 24
Peak memory 200600 kb
Host smart-a63bb8ae-5a38-4a43-b110-2394a6a920d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681808753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.3681808753
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.2781793867
Short name T637
Test name
Test status
Simulation time 32392178 ps
CPU time 0.55 seconds
Started Jun 21 04:45:52 PM PDT 24
Finished Jun 21 04:45:54 PM PDT 24
Peak memory 194988 kb
Host smart-7ac462a0-6bae-495a-9dec-889ad564aaec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781793867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.2781793867
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.285214801
Short name T586
Test name
Test status
Simulation time 54964177415 ps
CPU time 35.61 seconds
Started Jun 21 04:45:54 PM PDT 24
Finished Jun 21 04:46:32 PM PDT 24
Peak memory 200612 kb
Host smart-09772f6d-475e-42ab-aeda-6f08d671ea3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285214801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.285214801
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.3185259896
Short name T571
Test name
Test status
Simulation time 29950017249 ps
CPU time 35.7 seconds
Started Jun 21 04:45:53 PM PDT 24
Finished Jun 21 04:46:31 PM PDT 24
Peak memory 200560 kb
Host smart-805cebdd-5bfd-40b5-80b9-6ddb44747141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185259896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.3185259896
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.3119509354
Short name T886
Test name
Test status
Simulation time 214110472889 ps
CPU time 33.32 seconds
Started Jun 21 04:45:54 PM PDT 24
Finished Jun 21 04:46:28 PM PDT 24
Peak memory 200612 kb
Host smart-39068f21-3876-4ec1-a19b-5748d7c68d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119509354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.3119509354
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.2529073513
Short name T18
Test name
Test status
Simulation time 43097079657 ps
CPU time 91.02 seconds
Started Jun 21 04:45:56 PM PDT 24
Finished Jun 21 04:47:31 PM PDT 24
Peak memory 200584 kb
Host smart-27ee9181-cbb7-4211-89ab-45aeeaf6a24b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529073513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.2529073513
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.1599223359
Short name T607
Test name
Test status
Simulation time 58255812134 ps
CPU time 453.49 seconds
Started Jun 21 04:46:00 PM PDT 24
Finished Jun 21 04:53:40 PM PDT 24
Peak memory 200576 kb
Host smart-4f09e6bd-ae98-4836-95a2-a2aa85dcd00e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1599223359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.1599223359
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.2922098565
Short name T799
Test name
Test status
Simulation time 7950361567 ps
CPU time 11.16 seconds
Started Jun 21 04:45:54 PM PDT 24
Finished Jun 21 04:46:08 PM PDT 24
Peak memory 200544 kb
Host smart-b68c8ec5-c10f-49f9-af40-506186a8db79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922098565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.2922098565
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_perf.1220429060
Short name T705
Test name
Test status
Simulation time 17104843670 ps
CPU time 202.29 seconds
Started Jun 21 04:46:02 PM PDT 24
Finished Jun 21 04:49:31 PM PDT 24
Peak memory 200600 kb
Host smart-94345170-34e1-442a-b629-fcf61c06b2f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1220429060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.1220429060
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.2388328666
Short name T680
Test name
Test status
Simulation time 6328111313 ps
CPU time 14.02 seconds
Started Jun 21 04:45:56 PM PDT 24
Finished Jun 21 04:46:15 PM PDT 24
Peak memory 199500 kb
Host smart-abf29080-6c31-4c8a-85ec-b5edc9d37f5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2388328666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.2388328666
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.738864883
Short name T450
Test name
Test status
Simulation time 26989810977 ps
CPU time 47.32 seconds
Started Jun 21 04:45:57 PM PDT 24
Finished Jun 21 04:46:49 PM PDT 24
Peak memory 200644 kb
Host smart-bee76d1e-cea4-4940-98ad-ed7cbaab8c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738864883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.738864883
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.1203213736
Short name T567
Test name
Test status
Simulation time 35576360262 ps
CPU time 28.07 seconds
Started Jun 21 04:45:57 PM PDT 24
Finished Jun 21 04:46:31 PM PDT 24
Peak memory 196592 kb
Host smart-788c3f1c-751c-4843-9bdf-6036ba96e958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203213736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.1203213736
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.152950046
Short name T436
Test name
Test status
Simulation time 740308365 ps
CPU time 1.95 seconds
Started Jun 21 04:45:57 PM PDT 24
Finished Jun 21 04:46:04 PM PDT 24
Peak memory 198956 kb
Host smart-6bd8d503-9073-4b2d-8d50-182a789d86a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152950046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.152950046
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.798160140
Short name T739
Test name
Test status
Simulation time 421334641959 ps
CPU time 1145.11 seconds
Started Jun 21 04:45:59 PM PDT 24
Finished Jun 21 05:05:11 PM PDT 24
Peak memory 200228 kb
Host smart-21e37621-c8b2-42c6-a50a-cb0126ee7ac7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798160140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.798160140
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.249149178
Short name T988
Test name
Test status
Simulation time 472430099 ps
CPU time 1.13 seconds
Started Jun 21 04:45:53 PM PDT 24
Finished Jun 21 04:45:56 PM PDT 24
Peak memory 197756 kb
Host smart-5f6b1d2c-c845-4c0b-9045-4385dd90d3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249149178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.249149178
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.1757838933
Short name T387
Test name
Test status
Simulation time 72171250086 ps
CPU time 20.3 seconds
Started Jun 21 04:45:53 PM PDT 24
Finished Jun 21 04:46:15 PM PDT 24
Peak memory 200660 kb
Host smart-aa252425-460c-4150-a345-54a10e8a0e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757838933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.1757838933
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.3722901471
Short name T278
Test name
Test status
Simulation time 5733821228 ps
CPU time 5.18 seconds
Started Jun 21 04:47:56 PM PDT 24
Finished Jun 21 04:48:02 PM PDT 24
Peak memory 200620 kb
Host smart-ae2ba289-5747-45ab-a1ff-85ba25f29261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722901471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.3722901471
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.2990158360
Short name T1099
Test name
Test status
Simulation time 156637933672 ps
CPU time 76.76 seconds
Started Jun 21 04:47:57 PM PDT 24
Finished Jun 21 04:49:14 PM PDT 24
Peak memory 200620 kb
Host smart-5044edec-4c24-45a0-8676-86d2ba1dd6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990158360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.2990158360
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.2285675113
Short name T1086
Test name
Test status
Simulation time 61464658652 ps
CPU time 14.37 seconds
Started Jun 21 04:47:58 PM PDT 24
Finished Jun 21 04:48:13 PM PDT 24
Peak memory 200560 kb
Host smart-ca5d35b2-d876-4ba2-ae13-59385a8a515c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285675113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.2285675113
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.2437841740
Short name T518
Test name
Test status
Simulation time 26960930678 ps
CPU time 14.25 seconds
Started Jun 21 04:47:59 PM PDT 24
Finished Jun 21 04:48:15 PM PDT 24
Peak memory 200580 kb
Host smart-b0993ea5-d33f-4e1b-9427-7f62d0571b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437841740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.2437841740
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.3350112729
Short name T109
Test name
Test status
Simulation time 76394264132 ps
CPU time 110.37 seconds
Started Jun 21 04:48:01 PM PDT 24
Finished Jun 21 04:49:53 PM PDT 24
Peak memory 200616 kb
Host smart-c58973ee-c5ed-4fd9-afa1-67ec61ef5381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350112729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.3350112729
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.2535456753
Short name T406
Test name
Test status
Simulation time 12892092073 ps
CPU time 21.44 seconds
Started Jun 21 04:48:00 PM PDT 24
Finished Jun 21 04:48:23 PM PDT 24
Peak memory 198524 kb
Host smart-02bde9bf-2f56-48a3-9f61-4172f26763c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535456753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.2535456753
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.2433290911
Short name T639
Test name
Test status
Simulation time 79498587426 ps
CPU time 35.41 seconds
Started Jun 21 04:48:02 PM PDT 24
Finished Jun 21 04:48:38 PM PDT 24
Peak memory 200636 kb
Host smart-159d6f01-cb62-41de-b47c-464d6acd5de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433290911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.2433290911
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.3908351414
Short name T745
Test name
Test status
Simulation time 83776401912 ps
CPU time 29.21 seconds
Started Jun 21 04:47:56 PM PDT 24
Finished Jun 21 04:48:26 PM PDT 24
Peak memory 200684 kb
Host smart-d8d198a8-226b-4b93-be48-92280eb23566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908351414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.3908351414
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.3737596059
Short name T620
Test name
Test status
Simulation time 12123551 ps
CPU time 0.54 seconds
Started Jun 21 04:45:54 PM PDT 24
Finished Jun 21 04:45:57 PM PDT 24
Peak memory 195948 kb
Host smart-7054da8a-69c7-436a-b503-c439235f2c8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737596059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.3737596059
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.1705953912
Short name T550
Test name
Test status
Simulation time 152906774756 ps
CPU time 253.44 seconds
Started Jun 21 04:45:56 PM PDT 24
Finished Jun 21 04:50:13 PM PDT 24
Peak memory 200628 kb
Host smart-60988ea7-7d61-42cf-9869-c2a0100f9158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705953912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.1705953912
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.1783957693
Short name T473
Test name
Test status
Simulation time 21426350362 ps
CPU time 35.57 seconds
Started Jun 21 04:45:56 PM PDT 24
Finished Jun 21 04:46:36 PM PDT 24
Peak memory 200524 kb
Host smart-16fa6b06-0473-45fb-ae9c-acc211103646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783957693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.1783957693
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_intr.2927925249
Short name T672
Test name
Test status
Simulation time 37207928774 ps
CPU time 16.44 seconds
Started Jun 21 04:45:54 PM PDT 24
Finished Jun 21 04:46:13 PM PDT 24
Peak memory 200536 kb
Host smart-8aca241d-55a5-4135-b419-27fe96ba08fa
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927925249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.2927925249
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.3159768907
Short name T502
Test name
Test status
Simulation time 194654075489 ps
CPU time 462.18 seconds
Started Jun 21 04:46:02 PM PDT 24
Finished Jun 21 04:53:51 PM PDT 24
Peak memory 200516 kb
Host smart-d18f4f0c-60d4-4232-8837-ffc9ca118852
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3159768907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.3159768907
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.1094628936
Short name T423
Test name
Test status
Simulation time 10645295833 ps
CPU time 20.25 seconds
Started Jun 21 04:45:55 PM PDT 24
Finished Jun 21 04:46:19 PM PDT 24
Peak memory 200492 kb
Host smart-80ff655c-e1d5-49a7-8fa9-f7f5530b70d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094628936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.1094628936
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_perf.503917167
Short name T1076
Test name
Test status
Simulation time 16891140595 ps
CPU time 465.52 seconds
Started Jun 21 04:45:57 PM PDT 24
Finished Jun 21 04:53:47 PM PDT 24
Peak memory 200604 kb
Host smart-d0a1b181-6ee3-41a5-85e7-ad16da02295c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=503917167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.503917167
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.161627463
Short name T729
Test name
Test status
Simulation time 3047635391 ps
CPU time 9.67 seconds
Started Jun 21 04:45:56 PM PDT 24
Finished Jun 21 04:46:11 PM PDT 24
Peak memory 198716 kb
Host smart-73dfbba1-ba69-46a8-98ff-d30ca683bf9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=161627463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.161627463
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.4137064229
Short name T832
Test name
Test status
Simulation time 21005043730 ps
CPU time 66.62 seconds
Started Jun 21 04:45:52 PM PDT 24
Finished Jun 21 04:46:59 PM PDT 24
Peak memory 200640 kb
Host smart-16138703-f928-4f4c-86cb-5181fb8366fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137064229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.4137064229
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.3874599353
Short name T282
Test name
Test status
Simulation time 2181890998 ps
CPU time 3.08 seconds
Started Jun 21 04:45:57 PM PDT 24
Finished Jun 21 04:46:05 PM PDT 24
Peak memory 196308 kb
Host smart-2d84ff1a-f7ac-4baf-a94c-b4d3bdff4682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874599353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.3874599353
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.2826205695
Short name T636
Test name
Test status
Simulation time 505053572 ps
CPU time 2.13 seconds
Started Jun 21 04:45:55 PM PDT 24
Finished Jun 21 04:46:00 PM PDT 24
Peak memory 200392 kb
Host smart-2991770f-acff-473d-8f25-c77e49818c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826205695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.2826205695
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.2016371912
Short name T990
Test name
Test status
Simulation time 351396386631 ps
CPU time 77.26 seconds
Started Jun 21 04:45:55 PM PDT 24
Finished Jun 21 04:47:17 PM PDT 24
Peak memory 200516 kb
Host smart-b6cc4d20-e464-4cf1-b70d-7ced7c0cc730
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016371912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.2016371912
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.1011254696
Short name T929
Test name
Test status
Simulation time 330834841695 ps
CPU time 741.7 seconds
Started Jun 21 04:45:51 PM PDT 24
Finished Jun 21 04:58:14 PM PDT 24
Peak memory 217060 kb
Host smart-306b4f5d-fc3f-4ecf-8303-6859d58ec391
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011254696 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.1011254696
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.883319138
Short name T1007
Test name
Test status
Simulation time 1206735807 ps
CPU time 1.47 seconds
Started Jun 21 04:45:53 PM PDT 24
Finished Jun 21 04:45:55 PM PDT 24
Peak memory 199036 kb
Host smart-71391e39-0fd5-4d0d-a5d5-c84ee79fe4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883319138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.883319138
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.1091236712
Short name T323
Test name
Test status
Simulation time 26072185515 ps
CPU time 30.35 seconds
Started Jun 21 04:45:53 PM PDT 24
Finished Jun 21 04:46:25 PM PDT 24
Peak memory 200648 kb
Host smart-4eebb8df-7ce5-4053-ae64-98bd448adc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091236712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.1091236712
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.1759139368
Short name T162
Test name
Test status
Simulation time 78045730223 ps
CPU time 27.64 seconds
Started Jun 21 04:47:59 PM PDT 24
Finished Jun 21 04:48:28 PM PDT 24
Peak memory 200656 kb
Host smart-390b4ee0-b793-40a9-ba11-e7b411cfdf01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759139368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.1759139368
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.2137293871
Short name T218
Test name
Test status
Simulation time 14751587883 ps
CPU time 26.44 seconds
Started Jun 21 04:48:02 PM PDT 24
Finished Jun 21 04:48:29 PM PDT 24
Peak memory 200536 kb
Host smart-a3ad503c-5dac-42be-a59b-c1d1258c09a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137293871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.2137293871
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.3433954862
Short name T14
Test name
Test status
Simulation time 253268547369 ps
CPU time 31.76 seconds
Started Jun 21 04:47:58 PM PDT 24
Finished Jun 21 04:48:31 PM PDT 24
Peak memory 200656 kb
Host smart-db2e95fe-a53c-40d8-981c-d6f615f181b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433954862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.3433954862
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.2303318286
Short name T820
Test name
Test status
Simulation time 36882582888 ps
CPU time 45.87 seconds
Started Jun 21 04:47:57 PM PDT 24
Finished Jun 21 04:48:44 PM PDT 24
Peak memory 200636 kb
Host smart-b4164347-ac0f-4018-bb17-b106374bd9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303318286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.2303318286
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.4207208304
Short name T329
Test name
Test status
Simulation time 12484767872 ps
CPU time 23.48 seconds
Started Jun 21 04:47:59 PM PDT 24
Finished Jun 21 04:48:23 PM PDT 24
Peak memory 200636 kb
Host smart-619ddd12-1325-4a21-adf0-6561ebdd7738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207208304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.4207208304
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.2540933606
Short name T694
Test name
Test status
Simulation time 149685653401 ps
CPU time 302.32 seconds
Started Jun 21 04:47:59 PM PDT 24
Finished Jun 21 04:53:03 PM PDT 24
Peak memory 200688 kb
Host smart-50f819f0-cb43-48e2-8d54-c7e5e59711d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540933606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.2540933606
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.4050525986
Short name T1025
Test name
Test status
Simulation time 52707930284 ps
CPU time 25.09 seconds
Started Jun 21 04:47:57 PM PDT 24
Finished Jun 21 04:48:23 PM PDT 24
Peak memory 200688 kb
Host smart-6fbb2257-1941-4447-9ffb-63b0b799a553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050525986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.4050525986
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.2789606027
Short name T1078
Test name
Test status
Simulation time 17616421925 ps
CPU time 7.71 seconds
Started Jun 21 04:47:59 PM PDT 24
Finished Jun 21 04:48:08 PM PDT 24
Peak memory 200508 kb
Host smart-0ff05e01-5073-48d9-b15e-a6ea8014976e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789606027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.2789606027
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.2818984857
Short name T352
Test name
Test status
Simulation time 25164435 ps
CPU time 0.6 seconds
Started Jun 21 04:46:01 PM PDT 24
Finished Jun 21 04:46:08 PM PDT 24
Peak memory 195264 kb
Host smart-9ca8bda2-7feb-4d9c-9912-d5cecfbd4d77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818984857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.2818984857
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.3159328433
Short name T846
Test name
Test status
Simulation time 113512068864 ps
CPU time 291.99 seconds
Started Jun 21 04:45:56 PM PDT 24
Finished Jun 21 04:50:53 PM PDT 24
Peak memory 200660 kb
Host smart-d3e2da0b-1beb-4463-a275-68dacb0e8952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159328433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.3159328433
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.2238921005
Short name T619
Test name
Test status
Simulation time 118661987141 ps
CPU time 111.2 seconds
Started Jun 21 04:45:57 PM PDT 24
Finished Jun 21 04:47:52 PM PDT 24
Peak memory 200624 kb
Host smart-3d70678a-fd41-4596-b5b6-a3b25dc9dcfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238921005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.2238921005
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.630167602
Short name T189
Test name
Test status
Simulation time 101063682736 ps
CPU time 94.38 seconds
Started Jun 21 04:45:54 PM PDT 24
Finished Jun 21 04:47:31 PM PDT 24
Peak memory 200676 kb
Host smart-07f75a4f-0459-47b6-8be8-9f0c8e756286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630167602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.630167602
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.2822786379
Short name T686
Test name
Test status
Simulation time 38194995940 ps
CPU time 70.81 seconds
Started Jun 21 04:45:58 PM PDT 24
Finished Jun 21 04:47:14 PM PDT 24
Peak memory 200604 kb
Host smart-9eda1b80-a740-4aa3-b3c9-d3d6ec331f28
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822786379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.2822786379
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.371405618
Short name T461
Test name
Test status
Simulation time 150775229724 ps
CPU time 1090.8 seconds
Started Jun 21 04:46:00 PM PDT 24
Finished Jun 21 05:04:16 PM PDT 24
Peak memory 200664 kb
Host smart-c67c6c5b-2120-4e7a-be53-77a10a5b1690
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=371405618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.371405618
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.1930404428
Short name T632
Test name
Test status
Simulation time 7372771103 ps
CPU time 12.64 seconds
Started Jun 21 04:45:59 PM PDT 24
Finished Jun 21 04:46:18 PM PDT 24
Peak memory 199708 kb
Host smart-a0677b72-5209-47af-9449-7c5712459912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930404428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.1930404428
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_perf.3075094317
Short name T299
Test name
Test status
Simulation time 7130973737 ps
CPU time 95.46 seconds
Started Jun 21 04:45:58 PM PDT 24
Finished Jun 21 04:47:39 PM PDT 24
Peak memory 200592 kb
Host smart-1d33e2e6-e559-42de-9aba-a144bb1ec83c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3075094317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.3075094317
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.634497313
Short name T442
Test name
Test status
Simulation time 5286823629 ps
CPU time 28.47 seconds
Started Jun 21 04:45:56 PM PDT 24
Finished Jun 21 04:46:29 PM PDT 24
Peak memory 199028 kb
Host smart-44dcb326-08d0-41a4-b1bc-10cafdcb5b46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=634497313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.634497313
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.1763946917
Short name T1091
Test name
Test status
Simulation time 46457087707 ps
CPU time 92.03 seconds
Started Jun 21 04:45:55 PM PDT 24
Finished Jun 21 04:47:30 PM PDT 24
Peak memory 200572 kb
Host smart-a84c94ea-a9a2-47c2-bf89-87fc0d7e5f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763946917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.1763946917
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.513596131
Short name T627
Test name
Test status
Simulation time 34664530328 ps
CPU time 5.99 seconds
Started Jun 21 04:45:58 PM PDT 24
Finished Jun 21 04:46:09 PM PDT 24
Peak memory 196756 kb
Host smart-0080c92d-9234-4ff0-ad19-eb358309711b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513596131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.513596131
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.1718073424
Short name T49
Test name
Test status
Simulation time 691383344 ps
CPU time 1.66 seconds
Started Jun 21 04:45:56 PM PDT 24
Finished Jun 21 04:46:03 PM PDT 24
Peak memory 199112 kb
Host smart-6bcd7ea6-679e-4840-9455-859c3e21794b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718073424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.1718073424
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.3946977058
Short name T1018
Test name
Test status
Simulation time 256023416358 ps
CPU time 67.88 seconds
Started Jun 21 04:45:58 PM PDT 24
Finished Jun 21 04:47:12 PM PDT 24
Peak memory 200540 kb
Host smart-81d5e1fc-9c61-4999-9f0e-64e6ca0f4f3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946977058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.3946977058
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.1388687747
Short name T926
Test name
Test status
Simulation time 514173278 ps
CPU time 1.1 seconds
Started Jun 21 04:45:58 PM PDT 24
Finished Jun 21 04:46:04 PM PDT 24
Peak memory 197896 kb
Host smart-55935f34-4d6b-4726-9a7b-d5616b028f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388687747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.1388687747
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.2583843456
Short name T630
Test name
Test status
Simulation time 78448581035 ps
CPU time 52.48 seconds
Started Jun 21 04:45:56 PM PDT 24
Finished Jun 21 04:46:53 PM PDT 24
Peak memory 200576 kb
Host smart-9247cda7-5069-4fbd-8c0d-999a29eca81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583843456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.2583843456
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.352819761
Short name T872
Test name
Test status
Simulation time 20263177917 ps
CPU time 43.21 seconds
Started Jun 21 04:47:59 PM PDT 24
Finished Jun 21 04:48:43 PM PDT 24
Peak memory 200636 kb
Host smart-dacb9842-7bd1-4ca6-b349-addf6694cd5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352819761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.352819761
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.1247642144
Short name T656
Test name
Test status
Simulation time 100066599216 ps
CPU time 72.17 seconds
Started Jun 21 04:48:00 PM PDT 24
Finished Jun 21 04:49:13 PM PDT 24
Peak memory 200684 kb
Host smart-e2df4f76-eab1-4ffb-a6af-9331f9c7e169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247642144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.1247642144
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.4213623902
Short name T842
Test name
Test status
Simulation time 100653851321 ps
CPU time 57.26 seconds
Started Jun 21 04:47:58 PM PDT 24
Finished Jun 21 04:48:56 PM PDT 24
Peak memory 200468 kb
Host smart-ebcd3712-0e4f-45b6-b8ab-ec86c2bd3e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213623902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.4213623902
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.3043003518
Short name T211
Test name
Test status
Simulation time 34864668891 ps
CPU time 56.37 seconds
Started Jun 21 04:48:00 PM PDT 24
Finished Jun 21 04:48:58 PM PDT 24
Peak memory 200628 kb
Host smart-f72b6b52-7dfd-4988-aa78-e9e15fe794f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043003518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.3043003518
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.4286866257
Short name T151
Test name
Test status
Simulation time 167226342931 ps
CPU time 50.29 seconds
Started Jun 21 04:47:58 PM PDT 24
Finished Jun 21 04:48:49 PM PDT 24
Peak memory 200628 kb
Host smart-33114fd3-855d-4670-9684-58d57b5eb208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286866257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.4286866257
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.2615580902
Short name T153
Test name
Test status
Simulation time 67906338341 ps
CPU time 209.1 seconds
Started Jun 21 04:48:02 PM PDT 24
Finished Jun 21 04:51:32 PM PDT 24
Peak memory 200576 kb
Host smart-be2e8700-d3d3-45c4-97ac-0b11a8f83532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615580902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.2615580902
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.289157970
Short name T742
Test name
Test status
Simulation time 28833741079 ps
CPU time 45.87 seconds
Started Jun 21 04:48:07 PM PDT 24
Finished Jun 21 04:48:55 PM PDT 24
Peak memory 200616 kb
Host smart-fd0b9669-2bdb-415f-a120-4dd799dec137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289157970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.289157970
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.1863703521
Short name T759
Test name
Test status
Simulation time 166490107351 ps
CPU time 219.24 seconds
Started Jun 21 04:48:09 PM PDT 24
Finished Jun 21 04:51:51 PM PDT 24
Peak memory 200536 kb
Host smart-db08cefd-ff80-4500-8efe-309955316e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863703521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.1863703521
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.237595480
Short name T438
Test name
Test status
Simulation time 23868602 ps
CPU time 0.57 seconds
Started Jun 21 04:44:23 PM PDT 24
Finished Jun 21 04:44:28 PM PDT 24
Peak memory 195952 kb
Host smart-b213f16c-44bf-48e8-9b9e-c15a3760491e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237595480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.237595480
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.1751882861
Short name T623
Test name
Test status
Simulation time 221119667448 ps
CPU time 82.71 seconds
Started Jun 21 04:44:23 PM PDT 24
Finished Jun 21 04:45:50 PM PDT 24
Peak memory 200364 kb
Host smart-b21c5d30-045c-4bc7-b046-9afdc165ad50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751882861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.1751882861
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.3570479576
Short name T158
Test name
Test status
Simulation time 60328070815 ps
CPU time 65.91 seconds
Started Jun 21 04:44:26 PM PDT 24
Finished Jun 21 04:45:35 PM PDT 24
Peak memory 200152 kb
Host smart-86b51bb4-6f7c-4284-b97f-0d4177568499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570479576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.3570479576
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.1739639656
Short name T848
Test name
Test status
Simulation time 31932101189 ps
CPU time 25.83 seconds
Started Jun 21 04:44:18 PM PDT 24
Finished Jun 21 04:44:48 PM PDT 24
Peak memory 200592 kb
Host smart-cf8c2816-3942-4f44-b599-732c5f1374ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739639656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.1739639656
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.17671955
Short name T1008
Test name
Test status
Simulation time 58670580086 ps
CPU time 101.37 seconds
Started Jun 21 04:44:26 PM PDT 24
Finished Jun 21 04:46:10 PM PDT 24
Peak memory 199988 kb
Host smart-9a487d34-63a7-46b9-8845-f19e3d5e8ea2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17671955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.17671955
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.4175622746
Short name T697
Test name
Test status
Simulation time 55457046821 ps
CPU time 248.62 seconds
Started Jun 21 04:44:07 PM PDT 24
Finished Jun 21 04:48:18 PM PDT 24
Peak memory 200592 kb
Host smart-c85103dc-27c8-49ac-91f3-e4822ec42e81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4175622746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.4175622746
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.4169733160
Short name T1012
Test name
Test status
Simulation time 3092894834 ps
CPU time 3.56 seconds
Started Jun 21 04:44:41 PM PDT 24
Finished Jun 21 04:44:46 PM PDT 24
Peak memory 199952 kb
Host smart-ec8c2597-a7ab-40b7-a983-372084d27836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169733160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.4169733160
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_perf.164027366
Short name T280
Test name
Test status
Simulation time 23355621403 ps
CPU time 1052.28 seconds
Started Jun 21 04:44:20 PM PDT 24
Finished Jun 21 05:01:57 PM PDT 24
Peak memory 200596 kb
Host smart-d3551fbe-5713-46ca-81f1-45a8952de647
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=164027366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.164027366
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.1027483872
Short name T388
Test name
Test status
Simulation time 1888050920 ps
CPU time 7.63 seconds
Started Jun 21 04:44:23 PM PDT 24
Finished Jun 21 04:44:35 PM PDT 24
Peak memory 198652 kb
Host smart-61fb97c2-4897-4084-a2f0-e4b13d5606be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1027483872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.1027483872
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.625671769
Short name T572
Test name
Test status
Simulation time 162302416769 ps
CPU time 63.88 seconds
Started Jun 21 04:44:18 PM PDT 24
Finished Jun 21 04:45:27 PM PDT 24
Peak memory 200604 kb
Host smart-0d524e3b-de1e-4d8d-a9cb-2b396cafb811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625671769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.625671769
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.3038931652
Short name T704
Test name
Test status
Simulation time 2751561096 ps
CPU time 1.75 seconds
Started Jun 21 04:44:23 PM PDT 24
Finished Jun 21 04:44:29 PM PDT 24
Peak memory 196584 kb
Host smart-f5a41861-722a-4a40-a0dd-64f7ed7839b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038931652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.3038931652
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.3363884309
Short name T107
Test name
Test status
Simulation time 78013767 ps
CPU time 0.89 seconds
Started Jun 21 04:44:45 PM PDT 24
Finished Jun 21 04:44:49 PM PDT 24
Peak memory 218920 kb
Host smart-c628e5df-4ff8-4356-b9c5-6150c217ad26
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363884309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.3363884309
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.923919
Short name T386
Test name
Test status
Simulation time 248010830 ps
CPU time 1.49 seconds
Started Jun 21 04:44:23 PM PDT 24
Finished Jun 21 04:44:29 PM PDT 24
Peak memory 199024 kb
Host smart-8df48afa-3930-4670-a985-5236325f2cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.923919
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.1083895737
Short name T1020
Test name
Test status
Simulation time 130016238763 ps
CPU time 93.2 seconds
Started Jun 21 04:44:18 PM PDT 24
Finished Jun 21 04:45:56 PM PDT 24
Peak memory 200608 kb
Host smart-02e02715-783e-455e-9751-051aa7209a80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083895737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.1083895737
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.3926205952
Short name T658
Test name
Test status
Simulation time 205009805891 ps
CPU time 972.11 seconds
Started Jun 21 04:44:18 PM PDT 24
Finished Jun 21 05:00:35 PM PDT 24
Peak memory 229596 kb
Host smart-2c3cca4e-8df4-41dc-bd78-103bde545daa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926205952 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.3926205952
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.3765719060
Short name T344
Test name
Test status
Simulation time 839457807 ps
CPU time 2.05 seconds
Started Jun 21 04:44:24 PM PDT 24
Finished Jun 21 04:44:31 PM PDT 24
Peak memory 196244 kb
Host smart-68356ed6-74c5-4645-b5bc-eb95ee4ac9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765719060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.3765719060
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.580629760
Short name T1069
Test name
Test status
Simulation time 25854993508 ps
CPU time 37.66 seconds
Started Jun 21 04:44:14 PM PDT 24
Finished Jun 21 04:44:54 PM PDT 24
Peak memory 200540 kb
Host smart-5a2a26f5-9eac-467b-942f-70a6ba64fe3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580629760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.580629760
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.413305952
Short name T495
Test name
Test status
Simulation time 82022950 ps
CPU time 0.53 seconds
Started Jun 21 04:45:54 PM PDT 24
Finished Jun 21 04:45:56 PM PDT 24
Peak memory 196012 kb
Host smart-1b0659f1-56f7-409e-8c79-2990bdf68093
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413305952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.413305952
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.3331651115
Short name T141
Test name
Test status
Simulation time 20529896074 ps
CPU time 17.54 seconds
Started Jun 21 04:46:05 PM PDT 24
Finished Jun 21 04:46:29 PM PDT 24
Peak memory 200560 kb
Host smart-37c77f36-7b3e-4886-8eb7-cd29d43679b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331651115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.3331651115
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.709523147
Short name T168
Test name
Test status
Simulation time 255641233683 ps
CPU time 26.47 seconds
Started Jun 21 04:46:05 PM PDT 24
Finished Jun 21 04:46:38 PM PDT 24
Peak memory 200560 kb
Host smart-8a43bfb1-1b5f-4f3c-a0e2-82d86811972c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709523147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.709523147
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.3715668144
Short name T870
Test name
Test status
Simulation time 132560710069 ps
CPU time 96.32 seconds
Started Jun 21 04:46:05 PM PDT 24
Finished Jun 21 04:47:48 PM PDT 24
Peak memory 200560 kb
Host smart-27e731d1-0355-43b7-ae4b-05afb5e0f8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715668144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.3715668144
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.3408557020
Short name T551
Test name
Test status
Simulation time 4275348926 ps
CPU time 11.67 seconds
Started Jun 21 04:46:05 PM PDT 24
Finished Jun 21 04:46:24 PM PDT 24
Peak memory 199892 kb
Host smart-a1e2258d-96d5-4584-a979-13574999a614
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408557020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.3408557020
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.4121852863
Short name T774
Test name
Test status
Simulation time 88851088082 ps
CPU time 219.44 seconds
Started Jun 21 04:45:59 PM PDT 24
Finished Jun 21 04:49:45 PM PDT 24
Peak memory 200516 kb
Host smart-761c6079-6b58-467a-b2e4-da6a1da167d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4121852863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.4121852863
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.429251427
Short name T768
Test name
Test status
Simulation time 4572980800 ps
CPU time 5.16 seconds
Started Jun 21 04:46:02 PM PDT 24
Finished Jun 21 04:46:14 PM PDT 24
Peak memory 199736 kb
Host smart-587bc5d3-df38-45fc-958d-2858ab2a5be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429251427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.429251427
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_perf.2202169296
Short name T898
Test name
Test status
Simulation time 31754454150 ps
CPU time 157.54 seconds
Started Jun 21 04:45:57 PM PDT 24
Finished Jun 21 04:48:40 PM PDT 24
Peak memory 200596 kb
Host smart-8d331dfd-4fdc-4618-a52b-4b6dc5912b0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2202169296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.2202169296
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.3901730273
Short name T349
Test name
Test status
Simulation time 1613607240 ps
CPU time 1.92 seconds
Started Jun 21 04:46:04 PM PDT 24
Finished Jun 21 04:46:13 PM PDT 24
Peak memory 198684 kb
Host smart-0924e17b-3900-4db8-8502-154f31f2c300
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3901730273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.3901730273
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.428241
Short name T973
Test name
Test status
Simulation time 62764900255 ps
CPU time 100.27 seconds
Started Jun 21 04:46:03 PM PDT 24
Finished Jun 21 04:47:50 PM PDT 24
Peak memory 200564 kb
Host smart-40703bbd-7699-4cbc-be2a-53f4f253b09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.428241
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.3884797564
Short name T1089
Test name
Test status
Simulation time 7248366525 ps
CPU time 5.3 seconds
Started Jun 21 04:46:05 PM PDT 24
Finished Jun 21 04:46:17 PM PDT 24
Peak memory 196716 kb
Host smart-23752fc2-599c-4d08-b2cf-2d1c3aaa30ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884797564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.3884797564
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.3427586600
Short name T289
Test name
Test status
Simulation time 500050501 ps
CPU time 1.34 seconds
Started Jun 21 04:45:59 PM PDT 24
Finished Jun 21 04:46:06 PM PDT 24
Peak memory 199476 kb
Host smart-0007a35b-630b-46fc-bdef-7e77f4aa11ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427586600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.3427586600
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.221364201
Short name T713
Test name
Test status
Simulation time 78201569846 ps
CPU time 1315.87 seconds
Started Jun 21 04:45:56 PM PDT 24
Finished Jun 21 05:07:57 PM PDT 24
Peak memory 200488 kb
Host smart-1d7199fa-ebec-4aab-a8d3-761568bd65a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221364201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.221364201
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.1227395394
Short name T46
Test name
Test status
Simulation time 112830360321 ps
CPU time 313.78 seconds
Started Jun 21 04:46:02 PM PDT 24
Finished Jun 21 04:51:23 PM PDT 24
Peak memory 210308 kb
Host smart-e7725b63-ef84-441c-b23e-48f5b22bf455
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227395394 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.1227395394
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.415999746
Short name T711
Test name
Test status
Simulation time 1164332923 ps
CPU time 1.56 seconds
Started Jun 21 04:46:05 PM PDT 24
Finished Jun 21 04:46:14 PM PDT 24
Peak memory 198524 kb
Host smart-643aea8c-ddd2-49e4-af2c-bf48b39ba601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415999746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.415999746
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.3831472007
Short name T294
Test name
Test status
Simulation time 69596806118 ps
CPU time 118.91 seconds
Started Jun 21 04:46:04 PM PDT 24
Finished Jun 21 04:48:10 PM PDT 24
Peak memory 200568 kb
Host smart-7cd3f421-dd89-4c9b-b9d3-44bdf20a7753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831472007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.3831472007
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.3493465346
Short name T459
Test name
Test status
Simulation time 40440912 ps
CPU time 0.56 seconds
Started Jun 21 04:46:03 PM PDT 24
Finished Jun 21 04:46:10 PM PDT 24
Peak memory 195936 kb
Host smart-7b4451a0-8219-4b84-b822-37e2bbeba469
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493465346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.3493465346
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.4293870174
Short name T511
Test name
Test status
Simulation time 19110436888 ps
CPU time 15.56 seconds
Started Jun 21 04:45:55 PM PDT 24
Finished Jun 21 04:46:13 PM PDT 24
Peak memory 200088 kb
Host smart-c261c8a1-de7d-44e0-b08c-cf19d6eec483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293870174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.4293870174
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.1433989690
Short name T15
Test name
Test status
Simulation time 96718315650 ps
CPU time 36.31 seconds
Started Jun 21 04:45:59 PM PDT 24
Finished Jun 21 04:46:41 PM PDT 24
Peak memory 200384 kb
Host smart-8185d16c-8fa7-4cac-a720-6631b17f9fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433989690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.1433989690
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.2470615261
Short name T205
Test name
Test status
Simulation time 48789732153 ps
CPU time 75.37 seconds
Started Jun 21 04:45:55 PM PDT 24
Finished Jun 21 04:47:13 PM PDT 24
Peak memory 200696 kb
Host smart-c8fcfd7c-787f-4465-8cf5-c41543351240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470615261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.2470615261
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.1345014243
Short name T857
Test name
Test status
Simulation time 247424901035 ps
CPU time 108.96 seconds
Started Jun 21 04:46:00 PM PDT 24
Finished Jun 21 04:47:56 PM PDT 24
Peak memory 200488 kb
Host smart-f915afe7-9f31-4ce3-b87a-04003d41d218
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345014243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.1345014243
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.2545806190
Short name T790
Test name
Test status
Simulation time 122897960402 ps
CPU time 569.74 seconds
Started Jun 21 04:46:00 PM PDT 24
Finished Jun 21 04:55:36 PM PDT 24
Peak memory 200688 kb
Host smart-59e5ca7e-a271-4636-83f3-13528ae903f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2545806190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.2545806190
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.3280787301
Short name T357
Test name
Test status
Simulation time 8494314888 ps
CPU time 5.79 seconds
Started Jun 21 04:46:02 PM PDT 24
Finished Jun 21 04:46:15 PM PDT 24
Peak memory 200232 kb
Host smart-b9458fa0-7772-441d-887c-e6e9b400a06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280787301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.3280787301
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_perf.2442475
Short name T480
Test name
Test status
Simulation time 14994807389 ps
CPU time 601.54 seconds
Started Jun 21 04:46:04 PM PDT 24
Finished Jun 21 04:56:13 PM PDT 24
Peak memory 200532 kb
Host smart-6ac87d86-6303-467e-9577-bc6c51598518
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2442475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.2442475
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.4060276946
Short name T655
Test name
Test status
Simulation time 1669934741 ps
CPU time 1.42 seconds
Started Jun 21 04:45:55 PM PDT 24
Finished Jun 21 04:46:00 PM PDT 24
Peak memory 198716 kb
Host smart-bd6adff6-8d07-4e35-9d5f-e0f30ec93ff7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4060276946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.4060276946
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.2029006925
Short name T702
Test name
Test status
Simulation time 120441992845 ps
CPU time 168.75 seconds
Started Jun 21 04:45:58 PM PDT 24
Finished Jun 21 04:48:52 PM PDT 24
Peak memory 200624 kb
Host smart-4be46f9e-a125-49e4-8faa-9d6b933ec733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029006925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.2029006925
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.1373284155
Short name T441
Test name
Test status
Simulation time 48490052780 ps
CPU time 73.97 seconds
Started Jun 21 04:45:59 PM PDT 24
Finished Jun 21 04:47:18 PM PDT 24
Peak memory 196644 kb
Host smart-1bc4ad3c-6f16-425b-934c-ecd89fc9985e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373284155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.1373284155
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.4023397927
Short name T621
Test name
Test status
Simulation time 5840290642 ps
CPU time 17.54 seconds
Started Jun 21 04:45:56 PM PDT 24
Finished Jun 21 04:46:18 PM PDT 24
Peak memory 200688 kb
Host smart-77eff504-9557-419a-a04c-0b9ae0da6462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023397927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.4023397927
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.1496710734
Short name T786
Test name
Test status
Simulation time 619439391024 ps
CPU time 523.88 seconds
Started Jun 21 04:46:05 PM PDT 24
Finished Jun 21 04:54:57 PM PDT 24
Peak memory 200204 kb
Host smart-8e9266c7-6559-42cc-af58-a2b1797afb3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496710734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.1496710734
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.2727682850
Short name T882
Test name
Test status
Simulation time 78400370636 ps
CPU time 190.46 seconds
Started Jun 21 04:46:02 PM PDT 24
Finished Jun 21 04:49:19 PM PDT 24
Peak memory 209932 kb
Host smart-02de0a96-9146-4b20-95c2-382fd7efd74e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727682850 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.2727682850
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.1571919833
Short name T22
Test name
Test status
Simulation time 7445983234 ps
CPU time 15.67 seconds
Started Jun 21 04:46:02 PM PDT 24
Finished Jun 21 04:46:25 PM PDT 24
Peak memory 200016 kb
Host smart-f5438940-4736-426c-a1dd-88a22e53ef19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571919833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1571919833
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.278342708
Short name T747
Test name
Test status
Simulation time 18539544634 ps
CPU time 10.9 seconds
Started Jun 21 04:45:57 PM PDT 24
Finished Jun 21 04:46:14 PM PDT 24
Peak memory 200368 kb
Host smart-c4c7ea01-354d-4f06-9afa-eaec92e00b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278342708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.278342708
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.989086654
Short name T507
Test name
Test status
Simulation time 17306331 ps
CPU time 0.55 seconds
Started Jun 21 04:46:09 PM PDT 24
Finished Jun 21 04:46:16 PM PDT 24
Peak memory 195968 kb
Host smart-76d111ec-96f9-4ce6-bd5d-c9b9aab5e96d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989086654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.989086654
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.2529387197
Short name T174
Test name
Test status
Simulation time 150815773936 ps
CPU time 202.61 seconds
Started Jun 21 04:46:04 PM PDT 24
Finished Jun 21 04:49:34 PM PDT 24
Peak memory 200604 kb
Host smart-0f0f5a29-d564-4854-96d6-fd4aecab53e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529387197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.2529387197
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.2235970890
Short name T825
Test name
Test status
Simulation time 18891657746 ps
CPU time 32.98 seconds
Started Jun 21 04:46:01 PM PDT 24
Finished Jun 21 04:46:40 PM PDT 24
Peak memory 200624 kb
Host smart-34cebd1b-28d9-4edc-879b-937c9749e9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235970890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.2235970890
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.2331176224
Short name T1019
Test name
Test status
Simulation time 38472513203 ps
CPU time 46.31 seconds
Started Jun 21 04:46:04 PM PDT 24
Finished Jun 21 04:46:57 PM PDT 24
Peak memory 200592 kb
Host smart-db61ca27-3192-4e03-93f6-3ac0343fcb8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331176224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.2331176224
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.143579528
Short name T360
Test name
Test status
Simulation time 19646795063 ps
CPU time 6.2 seconds
Started Jun 21 04:46:03 PM PDT 24
Finished Jun 21 04:46:16 PM PDT 24
Peak memory 200240 kb
Host smart-33b0bbdd-9b21-448b-8b7d-80a2cd8a408a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143579528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.143579528
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.1153102048
Short name T644
Test name
Test status
Simulation time 131019379003 ps
CPU time 648.64 seconds
Started Jun 21 04:46:03 PM PDT 24
Finished Jun 21 04:56:58 PM PDT 24
Peak memory 200612 kb
Host smart-24865809-77b8-46e8-8094-05a2f3f9badd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1153102048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.1153102048
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.2217316983
Short name T670
Test name
Test status
Simulation time 8790857228 ps
CPU time 20.36 seconds
Started Jun 21 04:46:09 PM PDT 24
Finished Jun 21 04:46:36 PM PDT 24
Peak memory 200364 kb
Host smart-0012ebaa-5216-45fa-82c1-3829e25e977b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217316983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.2217316983
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_perf.3217722601
Short name T431
Test name
Test status
Simulation time 22134627264 ps
CPU time 588.44 seconds
Started Jun 21 04:46:09 PM PDT 24
Finished Jun 21 04:56:04 PM PDT 24
Peak memory 200544 kb
Host smart-3d96c4f9-27de-4175-81c2-c93fc684af17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3217722601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.3217722601
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.3202136887
Short name T1042
Test name
Test status
Simulation time 6286994297 ps
CPU time 54.49 seconds
Started Jun 21 04:46:04 PM PDT 24
Finished Jun 21 04:47:06 PM PDT 24
Peak memory 199540 kb
Host smart-97f14342-2ef8-4e95-b592-412aaafaff58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3202136887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.3202136887
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.107925021
Short name T594
Test name
Test status
Simulation time 30545115923 ps
CPU time 56.7 seconds
Started Jun 21 04:46:03 PM PDT 24
Finished Jun 21 04:47:08 PM PDT 24
Peak memory 200520 kb
Host smart-ea6adcf3-65f9-49af-b248-63147bf7ef70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107925021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.107925021
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.1065601524
Short name T538
Test name
Test status
Simulation time 1559021726 ps
CPU time 3.25 seconds
Started Jun 21 04:45:56 PM PDT 24
Finished Jun 21 04:46:03 PM PDT 24
Peak memory 196044 kb
Host smart-b66752ff-1ef3-428c-a600-4b8ed58aa1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065601524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.1065601524
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.3178439723
Short name T1045
Test name
Test status
Simulation time 430132857 ps
CPU time 1.89 seconds
Started Jun 21 04:45:56 PM PDT 24
Finished Jun 21 04:46:03 PM PDT 24
Peak memory 200336 kb
Host smart-28169833-795e-499b-aecb-b50abd3f07b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178439723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.3178439723
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.1403781872
Short name T782
Test name
Test status
Simulation time 534837827514 ps
CPU time 509.83 seconds
Started Jun 21 04:45:56 PM PDT 24
Finished Jun 21 04:54:31 PM PDT 24
Peak memory 200504 kb
Host smart-c78e83b8-9d44-4a0c-9eb6-8bae264b5804
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403781872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.1403781872
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.2268707575
Short name T897
Test name
Test status
Simulation time 34278076507 ps
CPU time 767.52 seconds
Started Jun 21 04:46:04 PM PDT 24
Finished Jun 21 04:58:59 PM PDT 24
Peak memory 217024 kb
Host smart-161ccf57-1c33-4b81-b615-a3afbe18b5b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268707575 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.2268707575
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.181192979
Short name T267
Test name
Test status
Simulation time 6521197289 ps
CPU time 15.41 seconds
Started Jun 21 04:46:09 PM PDT 24
Finished Jun 21 04:46:30 PM PDT 24
Peak memory 200016 kb
Host smart-e6c7dc89-5f0c-496e-b0df-1270081a11d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181192979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.181192979
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.1645780447
Short name T622
Test name
Test status
Simulation time 42156142843 ps
CPU time 37.24 seconds
Started Jun 21 04:46:06 PM PDT 24
Finished Jun 21 04:46:50 PM PDT 24
Peak memory 199988 kb
Host smart-6eaaeb2d-3df9-4c98-a2a2-ae14fb1fa8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645780447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.1645780447
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.853932489
Short name T837
Test name
Test status
Simulation time 14714198 ps
CPU time 0.56 seconds
Started Jun 21 04:45:55 PM PDT 24
Finished Jun 21 04:46:00 PM PDT 24
Peak memory 195968 kb
Host smart-d73703e0-b0bc-4e7a-b396-572cc9719b27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853932489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.853932489
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.1210256518
Short name T738
Test name
Test status
Simulation time 106863498096 ps
CPU time 38.28 seconds
Started Jun 21 04:46:02 PM PDT 24
Finished Jun 21 04:46:47 PM PDT 24
Peak memory 200096 kb
Host smart-511f37d2-75bb-437f-8f4a-fa09a6e17a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210256518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.1210256518
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.313220856
Short name T1026
Test name
Test status
Simulation time 48871339256 ps
CPU time 70.68 seconds
Started Jun 21 04:46:05 PM PDT 24
Finished Jun 21 04:47:24 PM PDT 24
Peak memory 200588 kb
Host smart-20330412-b4c3-46e0-8d44-b5b784083d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313220856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.313220856
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.2223553604
Short name T414
Test name
Test status
Simulation time 67359106223 ps
CPU time 100.36 seconds
Started Jun 21 04:46:04 PM PDT 24
Finished Jun 21 04:47:51 PM PDT 24
Peak memory 200552 kb
Host smart-6fc3adc1-47d5-4186-88d2-5c47de20c3b0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223553604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.2223553604
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.1779590752
Short name T392
Test name
Test status
Simulation time 115693099976 ps
CPU time 731.82 seconds
Started Jun 21 04:45:55 PM PDT 24
Finished Jun 21 04:58:10 PM PDT 24
Peak memory 200656 kb
Host smart-b49b4c34-da6b-499e-99a3-7007871e9382
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1779590752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.1779590752
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.166051465
Short name T675
Test name
Test status
Simulation time 5005463458 ps
CPU time 3.02 seconds
Started Jun 21 04:46:09 PM PDT 24
Finished Jun 21 04:46:18 PM PDT 24
Peak memory 200340 kb
Host smart-b925e78e-6728-46f4-8f49-c4ac2a92cbe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166051465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.166051465
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_perf.1330939900
Short name T643
Test name
Test status
Simulation time 28122069708 ps
CPU time 1066.54 seconds
Started Jun 21 04:45:55 PM PDT 24
Finished Jun 21 05:03:44 PM PDT 24
Peak memory 200588 kb
Host smart-8c06b28b-a969-4974-b333-919b7e2b5241
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1330939900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.1330939900
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.75939113
Short name T24
Test name
Test status
Simulation time 2752948507 ps
CPU time 3.7 seconds
Started Jun 21 04:45:56 PM PDT 24
Finished Jun 21 04:46:03 PM PDT 24
Peak memory 198656 kb
Host smart-d9b02612-9dbc-446c-8cf9-d52f7a6b9cb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=75939113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.75939113
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.3709037708
Short name T374
Test name
Test status
Simulation time 33791642060 ps
CPU time 55.68 seconds
Started Jun 21 04:45:55 PM PDT 24
Finished Jun 21 04:46:55 PM PDT 24
Peak memory 200508 kb
Host smart-81a45088-145f-4488-9269-2e36d3fb6699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709037708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.3709037708
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.3165042373
Short name T32
Test name
Test status
Simulation time 2031159040 ps
CPU time 2.68 seconds
Started Jun 21 04:46:08 PM PDT 24
Finished Jun 21 04:46:18 PM PDT 24
Peak memory 196224 kb
Host smart-00aaa847-2acf-4a74-b064-cfc4e26d56f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165042373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.3165042373
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.649680748
Short name T499
Test name
Test status
Simulation time 6009602154 ps
CPU time 8.01 seconds
Started Jun 21 04:46:09 PM PDT 24
Finished Jun 21 04:46:23 PM PDT 24
Peak memory 200000 kb
Host smart-15702905-a2d2-4542-a54d-19c80f2e4ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649680748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.649680748
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.2724318368
Short name T719
Test name
Test status
Simulation time 368271079885 ps
CPU time 418.73 seconds
Started Jun 21 04:45:57 PM PDT 24
Finished Jun 21 04:53:02 PM PDT 24
Peak memory 200632 kb
Host smart-6eec5391-cc3a-49b1-9567-d22dff9e93ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724318368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.2724318368
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.3306068035
Short name T318
Test name
Test status
Simulation time 58265328184 ps
CPU time 611.29 seconds
Started Jun 21 04:45:58 PM PDT 24
Finished Jun 21 04:56:14 PM PDT 24
Peak memory 216400 kb
Host smart-262a471e-17fe-4540-8a8e-d4f2b9838c78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306068035 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.3306068035
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.4011535498
Short name T425
Test name
Test status
Simulation time 6555995883 ps
CPU time 11.8 seconds
Started Jun 21 04:45:55 PM PDT 24
Finished Jun 21 04:46:10 PM PDT 24
Peak memory 200520 kb
Host smart-e010bbe7-ba35-4538-9935-53ee53ab7a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011535498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.4011535498
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.3989290118
Short name T287
Test name
Test status
Simulation time 51604344119 ps
CPU time 23.42 seconds
Started Jun 21 04:45:58 PM PDT 24
Finished Jun 21 04:46:27 PM PDT 24
Peak memory 200572 kb
Host smart-44bf054a-b43a-4e35-b684-e5b238cb6c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989290118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.3989290118
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.2732704658
Short name T365
Test name
Test status
Simulation time 45278761 ps
CPU time 0.57 seconds
Started Jun 21 04:46:04 PM PDT 24
Finished Jun 21 04:46:12 PM PDT 24
Peak memory 195944 kb
Host smart-15d99b69-c9ea-4959-a7b2-50d71e013144
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732704658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.2732704658
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.118031192
Short name T803
Test name
Test status
Simulation time 54908023117 ps
CPU time 12.67 seconds
Started Jun 21 04:45:55 PM PDT 24
Finished Jun 21 04:46:12 PM PDT 24
Peak memory 200408 kb
Host smart-5bb30b2b-3727-4e2d-a1f6-c97f2489a356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118031192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.118031192
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.1145688371
Short name T894
Test name
Test status
Simulation time 36316807311 ps
CPU time 25.15 seconds
Started Jun 21 04:45:57 PM PDT 24
Finished Jun 21 04:46:28 PM PDT 24
Peak memory 200676 kb
Host smart-7fc99a57-3242-41bf-a624-792d58c9afa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145688371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.1145688371
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.4031485275
Short name T659
Test name
Test status
Simulation time 61070728803 ps
CPU time 36.44 seconds
Started Jun 21 04:45:57 PM PDT 24
Finished Jun 21 04:46:39 PM PDT 24
Peak memory 200620 kb
Host smart-6c551422-eb3b-4b81-8b87-20e392f3906e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031485275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.4031485275
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.3646111232
Short name T1092
Test name
Test status
Simulation time 88010517355 ps
CPU time 617.89 seconds
Started Jun 21 04:46:06 PM PDT 24
Finished Jun 21 04:56:31 PM PDT 24
Peak memory 200548 kb
Host smart-d884ac5d-157a-47a4-bc1b-fee46b69a48f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3646111232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.3646111232
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.4077261992
Short name T876
Test name
Test status
Simulation time 3207870893 ps
CPU time 7.54 seconds
Started Jun 21 04:46:02 PM PDT 24
Finished Jun 21 04:46:16 PM PDT 24
Peak memory 200008 kb
Host smart-f434e487-a24c-4315-bc20-a0889bfcc27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077261992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.4077261992
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_perf.352856279
Short name T1006
Test name
Test status
Simulation time 25432574056 ps
CPU time 314.32 seconds
Started Jun 21 04:45:54 PM PDT 24
Finished Jun 21 04:51:10 PM PDT 24
Peak memory 200640 kb
Host smart-05a4ee76-58fc-49dc-8c0e-215dac7ed362
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=352856279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.352856279
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.1688173224
Short name T810
Test name
Test status
Simulation time 7429748149 ps
CPU time 34.31 seconds
Started Jun 21 04:45:57 PM PDT 24
Finished Jun 21 04:46:37 PM PDT 24
Peak memory 199820 kb
Host smart-cabe4ade-7cab-484b-942f-245d46e9ecee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1688173224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.1688173224
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.1485869419
Short name T754
Test name
Test status
Simulation time 54752845549 ps
CPU time 21.13 seconds
Started Jun 21 04:46:01 PM PDT 24
Finished Jun 21 04:46:29 PM PDT 24
Peak memory 200472 kb
Host smart-aa361ae6-46f8-4864-ac4c-756f026fb586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485869419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.1485869419
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.1049873794
Short name T932
Test name
Test status
Simulation time 499709559 ps
CPU time 0.84 seconds
Started Jun 21 04:46:01 PM PDT 24
Finished Jun 21 04:46:08 PM PDT 24
Peak memory 196124 kb
Host smart-327f24e7-c9b0-44b6-b181-4472399f240b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049873794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.1049873794
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.922042288
Short name T999
Test name
Test status
Simulation time 556777598 ps
CPU time 1.21 seconds
Started Jun 21 04:45:55 PM PDT 24
Finished Jun 21 04:45:59 PM PDT 24
Peak memory 199748 kb
Host smart-fcdb8e9a-8f0d-451b-8d3b-3c68f325b359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922042288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.922042288
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.2962253772
Short name T667
Test name
Test status
Simulation time 441982979466 ps
CPU time 391.51 seconds
Started Jun 21 04:46:03 PM PDT 24
Finished Jun 21 04:52:41 PM PDT 24
Peak memory 200616 kb
Host smart-94f40317-9136-490d-a431-5577ad6c6411
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962253772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.2962253772
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.2381668989
Short name T251
Test name
Test status
Simulation time 128532840647 ps
CPU time 206.74 seconds
Started Jun 21 04:46:03 PM PDT 24
Finished Jun 21 04:49:36 PM PDT 24
Peak memory 210196 kb
Host smart-75fc3c57-d28a-4965-b9c2-6d1663a1fc6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381668989 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.2381668989
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.3417963250
Short name T609
Test name
Test status
Simulation time 1859043934 ps
CPU time 1.84 seconds
Started Jun 21 04:46:00 PM PDT 24
Finished Jun 21 04:46:09 PM PDT 24
Peak memory 200576 kb
Host smart-1bab6be4-47b2-437e-9c5a-ffa5b956f6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417963250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.3417963250
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.2451779135
Short name T629
Test name
Test status
Simulation time 34485333087 ps
CPU time 55.01 seconds
Started Jun 21 04:46:01 PM PDT 24
Finished Jun 21 04:47:02 PM PDT 24
Peak memory 200588 kb
Host smart-6ac02b08-0d22-4bc3-866b-a81ed6f5caa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451779135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.2451779135
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.2915480262
Short name T769
Test name
Test status
Simulation time 52003345 ps
CPU time 0.55 seconds
Started Jun 21 04:46:04 PM PDT 24
Finished Jun 21 04:46:12 PM PDT 24
Peak memory 195968 kb
Host smart-0346541d-a7d1-488f-ae7e-d770ce6c469b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915480262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.2915480262
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.230087366
Short name T934
Test name
Test status
Simulation time 139792690925 ps
CPU time 55.37 seconds
Started Jun 21 04:46:06 PM PDT 24
Finished Jun 21 04:47:08 PM PDT 24
Peak memory 200184 kb
Host smart-392eecac-3b57-49d1-80bf-348a00def6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230087366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.230087366
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.2619722944
Short name T815
Test name
Test status
Simulation time 114079930279 ps
CPU time 99.59 seconds
Started Jun 21 04:46:05 PM PDT 24
Finished Jun 21 04:47:52 PM PDT 24
Peak memory 200180 kb
Host smart-45518184-11df-42bf-8149-0d1e5694a42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619722944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.2619722944
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_intr.3665616579
Short name T324
Test name
Test status
Simulation time 17377279629 ps
CPU time 8.07 seconds
Started Jun 21 04:46:03 PM PDT 24
Finished Jun 21 04:46:18 PM PDT 24
Peak memory 198252 kb
Host smart-06023a44-b95b-49c0-b1f8-d7238b1f5a0e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665616579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.3665616579
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.569613391
Short name T458
Test name
Test status
Simulation time 43925125576 ps
CPU time 78.95 seconds
Started Jun 21 04:46:03 PM PDT 24
Finished Jun 21 04:47:29 PM PDT 24
Peak memory 200568 kb
Host smart-eb001f50-1412-43db-b25f-110007bfefbc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=569613391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.569613391
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.2152621977
Short name T378
Test name
Test status
Simulation time 1976327203 ps
CPU time 2.32 seconds
Started Jun 21 04:46:03 PM PDT 24
Finished Jun 21 04:46:12 PM PDT 24
Peak memory 198124 kb
Host smart-424582a0-cfb3-49f1-81cc-4ab13fef503d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152621977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.2152621977
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_perf.2134147347
Short name T460
Test name
Test status
Simulation time 15638114998 ps
CPU time 874.53 seconds
Started Jun 21 04:46:04 PM PDT 24
Finished Jun 21 05:00:46 PM PDT 24
Peak memory 200568 kb
Host smart-0aeaaf08-6677-49e0-8d8c-5459f657a085
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2134147347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.2134147347
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.2833085252
Short name T703
Test name
Test status
Simulation time 5603170062 ps
CPU time 9.64 seconds
Started Jun 21 04:46:03 PM PDT 24
Finished Jun 21 04:46:19 PM PDT 24
Peak memory 199360 kb
Host smart-75a71435-ce99-459e-9507-dd9d70a773fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2833085252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.2833085252
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.4052481261
Short name T20
Test name
Test status
Simulation time 146380395530 ps
CPU time 30.83 seconds
Started Jun 21 04:46:03 PM PDT 24
Finished Jun 21 04:46:40 PM PDT 24
Peak memory 200452 kb
Host smart-0b867f93-4008-412f-9e65-730be8acc9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052481261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.4052481261
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.433265490
Short name T578
Test name
Test status
Simulation time 3433986976 ps
CPU time 3.3 seconds
Started Jun 21 04:46:03 PM PDT 24
Finished Jun 21 04:46:13 PM PDT 24
Peak memory 197088 kb
Host smart-fb200ea1-f909-4f60-9a3a-401a35affec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433265490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.433265490
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.2548324673
Short name T353
Test name
Test status
Simulation time 532707449 ps
CPU time 2.4 seconds
Started Jun 21 04:46:04 PM PDT 24
Finished Jun 21 04:46:13 PM PDT 24
Peak memory 199376 kb
Host smart-e02ac8e6-97ec-4212-aafa-5864ed8855f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548324673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.2548324673
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.3820727815
Short name T976
Test name
Test status
Simulation time 185404610420 ps
CPU time 881.49 seconds
Started Jun 21 04:46:09 PM PDT 24
Finished Jun 21 05:00:57 PM PDT 24
Peak memory 200552 kb
Host smart-df2e1ceb-7bf1-46c7-ba3f-6aefb7ef9311
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820727815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.3820727815
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.4222166448
Short name T798
Test name
Test status
Simulation time 1794946622 ps
CPU time 2.54 seconds
Started Jun 21 04:46:03 PM PDT 24
Finished Jun 21 04:46:12 PM PDT 24
Peak memory 200340 kb
Host smart-98e4c2b2-272e-4fe5-91d0-62045a87eb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222166448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.4222166448
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.980633024
Short name T972
Test name
Test status
Simulation time 62272639713 ps
CPU time 100.08 seconds
Started Jun 21 04:46:04 PM PDT 24
Finished Jun 21 04:47:51 PM PDT 24
Peak memory 200508 kb
Host smart-39ef37f2-e28c-4f2b-9b3b-891233ec15f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980633024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.980633024
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.2745583384
Short name T890
Test name
Test status
Simulation time 13496990 ps
CPU time 0.56 seconds
Started Jun 21 04:45:57 PM PDT 24
Finished Jun 21 04:46:03 PM PDT 24
Peak memory 195972 kb
Host smart-9112d4c2-99da-4a5a-b5d8-c5712b404e5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745583384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.2745583384
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.2539130260
Short name T113
Test name
Test status
Simulation time 173589734148 ps
CPU time 172.31 seconds
Started Jun 21 04:45:59 PM PDT 24
Finished Jun 21 04:48:57 PM PDT 24
Peak memory 200624 kb
Host smart-257d6878-7f78-42fd-9485-23f5a80bb7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539130260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.2539130260
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.2757850983
Short name T974
Test name
Test status
Simulation time 56498984783 ps
CPU time 78.69 seconds
Started Jun 21 04:46:05 PM PDT 24
Finished Jun 21 04:47:31 PM PDT 24
Peak memory 200472 kb
Host smart-5e5f855a-b882-4eaa-abfe-17d62f8f7e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757850983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.2757850983
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.3378018284
Short name T687
Test name
Test status
Simulation time 130297446959 ps
CPU time 51.74 seconds
Started Jun 21 04:46:06 PM PDT 24
Finished Jun 21 04:47:05 PM PDT 24
Peak memory 200016 kb
Host smart-1afae3ca-a9cf-4e77-b952-1ed7bb75d653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378018284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.3378018284
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.3286658470
Short name T921
Test name
Test status
Simulation time 30530817895 ps
CPU time 51.3 seconds
Started Jun 21 04:46:09 PM PDT 24
Finished Jun 21 04:47:06 PM PDT 24
Peak memory 198992 kb
Host smart-65ceb406-7d59-4092-9915-0bfc594e85ed
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286658470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.3286658470
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.3134649583
Short name T884
Test name
Test status
Simulation time 77682023841 ps
CPU time 496.94 seconds
Started Jun 21 04:45:57 PM PDT 24
Finished Jun 21 04:54:19 PM PDT 24
Peak memory 200660 kb
Host smart-d7cd628a-9a28-4d55-84d1-b7ecffe4cd68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3134649583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.3134649583
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.1117886039
Short name T843
Test name
Test status
Simulation time 10560725949 ps
CPU time 6.59 seconds
Started Jun 21 04:45:58 PM PDT 24
Finished Jun 21 04:46:10 PM PDT 24
Peak memory 200360 kb
Host smart-9f1624c2-56bc-48da-9f71-eb59e70e03bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117886039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.1117886039
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_perf.1550459425
Short name T901
Test name
Test status
Simulation time 15228063839 ps
CPU time 638.3 seconds
Started Jun 21 04:46:02 PM PDT 24
Finished Jun 21 04:56:47 PM PDT 24
Peak memory 200100 kb
Host smart-a7a46a56-9366-481b-87aa-ee26497ec383
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1550459425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.1550459425
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.95588872
Short name T908
Test name
Test status
Simulation time 5245945069 ps
CPU time 42.09 seconds
Started Jun 21 04:46:08 PM PDT 24
Finished Jun 21 04:46:57 PM PDT 24
Peak memory 199860 kb
Host smart-07532bde-7441-490e-b531-72995f07b742
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=95588872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.95588872
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.1930587334
Short name T297
Test name
Test status
Simulation time 34250807194 ps
CPU time 13.16 seconds
Started Jun 21 04:46:08 PM PDT 24
Finished Jun 21 04:46:27 PM PDT 24
Peak memory 200372 kb
Host smart-ecdf4a32-4a13-406b-9dc6-5422791db303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930587334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.1930587334
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.223812626
Short name T883
Test name
Test status
Simulation time 3255016699 ps
CPU time 3.01 seconds
Started Jun 21 04:46:08 PM PDT 24
Finished Jun 21 04:46:17 PM PDT 24
Peak memory 196520 kb
Host smart-d33334a4-0ece-42bd-bbf1-ec7836a479cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223812626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.223812626
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.2296708415
Short name T6
Test name
Test status
Simulation time 268305470 ps
CPU time 1.83 seconds
Started Jun 21 04:46:09 PM PDT 24
Finished Jun 21 04:46:17 PM PDT 24
Peak memory 200296 kb
Host smart-a8cee7b7-57c7-40c1-a03c-3ad09a188d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296708415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.2296708415
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.4225464683
Short name T296
Test name
Test status
Simulation time 80168648531 ps
CPU time 32.48 seconds
Started Jun 21 04:46:01 PM PDT 24
Finished Jun 21 04:46:40 PM PDT 24
Peak memory 200572 kb
Host smart-deffa63d-49d4-479a-a466-dd5ba1c78fc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225464683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.4225464683
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.3817763912
Short name T322
Test name
Test status
Simulation time 1152396763 ps
CPU time 2.37 seconds
Started Jun 21 04:46:02 PM PDT 24
Finished Jun 21 04:46:11 PM PDT 24
Peak memory 199680 kb
Host smart-fc5fe9d3-1e13-4b04-8d34-ac3ebf164782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817763912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.3817763912
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.2222537253
Short name T576
Test name
Test status
Simulation time 92604441026 ps
CPU time 37.98 seconds
Started Jun 21 04:46:09 PM PDT 24
Finished Jun 21 04:46:53 PM PDT 24
Peak memory 200172 kb
Host smart-7cb4d922-d374-4cc5-9271-9aec177b69b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222537253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.2222537253
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.202642845
Short name T579
Test name
Test status
Simulation time 100006094 ps
CPU time 0.55 seconds
Started Jun 21 04:46:04 PM PDT 24
Finished Jun 21 04:46:12 PM PDT 24
Peak memory 195956 kb
Host smart-f5995cc3-ca61-41e9-b58b-785584f099e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202642845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.202642845
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.2960915941
Short name T1093
Test name
Test status
Simulation time 40842674431 ps
CPU time 69.53 seconds
Started Jun 21 04:45:59 PM PDT 24
Finished Jun 21 04:47:15 PM PDT 24
Peak memory 200684 kb
Host smart-4dc7dd44-a6b0-4e2c-a179-8eb1f60723f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960915941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.2960915941
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.2307276235
Short name T691
Test name
Test status
Simulation time 141031227791 ps
CPU time 35.05 seconds
Started Jun 21 04:46:01 PM PDT 24
Finished Jun 21 04:46:43 PM PDT 24
Peak memory 200624 kb
Host smart-1aa6abde-40d2-4433-8e09-2abd78afd79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307276235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.2307276235
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.1209028923
Short name T440
Test name
Test status
Simulation time 33664994426 ps
CPU time 16.64 seconds
Started Jun 21 04:46:02 PM PDT 24
Finished Jun 21 04:46:26 PM PDT 24
Peak memory 200656 kb
Host smart-71827ced-2e99-49db-8999-14f54c8d2ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209028923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.1209028923
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.1521192738
Short name T389
Test name
Test status
Simulation time 86412566448 ps
CPU time 74.45 seconds
Started Jun 21 04:46:00 PM PDT 24
Finished Jun 21 04:47:21 PM PDT 24
Peak memory 200668 kb
Host smart-609ed2d8-354d-4d73-bd7a-cb2dc9767f66
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521192738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.1521192738
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.4198660075
Short name T631
Test name
Test status
Simulation time 67103820451 ps
CPU time 267.42 seconds
Started Jun 21 04:46:04 PM PDT 24
Finished Jun 21 04:50:37 PM PDT 24
Peak memory 200572 kb
Host smart-18a06129-9a5f-44d1-9473-46768a21f4bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4198660075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.4198660075
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.1120172676
Short name T443
Test name
Test status
Simulation time 6018266875 ps
CPU time 9.2 seconds
Started Jun 21 04:46:01 PM PDT 24
Finished Jun 21 04:46:17 PM PDT 24
Peak memory 200324 kb
Host smart-919213ca-905a-4534-91f6-4540def5d866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120172676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.1120172676
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_perf.1403858113
Short name T93
Test name
Test status
Simulation time 9561860810 ps
CPU time 530.44 seconds
Started Jun 21 04:46:04 PM PDT 24
Finished Jun 21 04:55:02 PM PDT 24
Peak memory 200536 kb
Host smart-7f1e3754-b3ad-4649-83cd-22795b3e00df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1403858113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.1403858113
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.1241384504
Short name T498
Test name
Test status
Simulation time 3494169307 ps
CPU time 22.98 seconds
Started Jun 21 04:46:00 PM PDT 24
Finished Jun 21 04:46:30 PM PDT 24
Peak memory 199012 kb
Host smart-6dd7bca0-276e-4f6f-8ed4-b8820763674a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1241384504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.1241384504
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.3440833723
Short name T270
Test name
Test status
Simulation time 119149532870 ps
CPU time 98.69 seconds
Started Jun 21 04:45:56 PM PDT 24
Finished Jun 21 04:47:40 PM PDT 24
Peak memory 200640 kb
Host smart-719b4eca-80fd-4d4e-829f-14e52228eb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440833723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.3440833723
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.4095280951
Short name T1039
Test name
Test status
Simulation time 3364156811 ps
CPU time 3.44 seconds
Started Jun 21 04:46:05 PM PDT 24
Finished Jun 21 04:46:15 PM PDT 24
Peak memory 196876 kb
Host smart-b1ada8dc-a02d-46d4-8048-3fe1258d8367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095280951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.4095280951
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.116927448
Short name T1061
Test name
Test status
Simulation time 681201040 ps
CPU time 1.57 seconds
Started Jun 21 04:45:58 PM PDT 24
Finished Jun 21 04:46:05 PM PDT 24
Peak memory 199804 kb
Host smart-1a6ad63a-59b2-422b-966d-8d1f12e7dff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116927448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.116927448
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.1564699215
Short name T398
Test name
Test status
Simulation time 209771116662 ps
CPU time 160.51 seconds
Started Jun 21 04:46:13 PM PDT 24
Finished Jun 21 04:48:59 PM PDT 24
Peak memory 200664 kb
Host smart-2195e4f3-43bf-4b28-8c8e-7df14a3d0547
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564699215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.1564699215
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.3939805779
Short name T584
Test name
Test status
Simulation time 1203982866 ps
CPU time 3.25 seconds
Started Jun 21 04:46:02 PM PDT 24
Finished Jun 21 04:46:12 PM PDT 24
Peak memory 199524 kb
Host smart-7938d48b-7598-4af7-bfd1-2398d27921e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939805779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.3939805779
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.1956443202
Short name T1052
Test name
Test status
Simulation time 61203942730 ps
CPU time 19.56 seconds
Started Jun 21 04:46:01 PM PDT 24
Finished Jun 21 04:46:27 PM PDT 24
Peak memory 200632 kb
Host smart-ceec6df7-d9ee-47c1-b101-7ecc4988888c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956443202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.1956443202
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.1058589163
Short name T736
Test name
Test status
Simulation time 22268954 ps
CPU time 0.57 seconds
Started Jun 21 04:46:14 PM PDT 24
Finished Jun 21 04:46:19 PM PDT 24
Peak memory 195348 kb
Host smart-b3310312-8f30-4cdf-9931-85e5a4c9b728
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058589163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.1058589163
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.3906980010
Short name T830
Test name
Test status
Simulation time 240441784379 ps
CPU time 483.52 seconds
Started Jun 21 04:46:02 PM PDT 24
Finished Jun 21 04:54:12 PM PDT 24
Peak memory 200660 kb
Host smart-0f86bf1d-c854-40ab-9d51-ca339e0965fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906980010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.3906980010
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.2594635082
Short name T928
Test name
Test status
Simulation time 54203029405 ps
CPU time 89.31 seconds
Started Jun 21 04:45:59 PM PDT 24
Finished Jun 21 04:47:35 PM PDT 24
Peak memory 200624 kb
Host smart-2fd4a1e5-9a44-43dc-a673-e069e08495e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594635082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.2594635082
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.4044558442
Short name T554
Test name
Test status
Simulation time 40495553654 ps
CPU time 33.43 seconds
Started Jun 21 04:46:03 PM PDT 24
Finished Jun 21 04:46:43 PM PDT 24
Peak memory 200572 kb
Host smart-8bafe8f8-4ea1-42a5-bca3-85adca8279a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044558442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.4044558442
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.2928667610
Short name T854
Test name
Test status
Simulation time 677277895642 ps
CPU time 321.06 seconds
Started Jun 21 04:46:09 PM PDT 24
Finished Jun 21 04:51:36 PM PDT 24
Peak memory 200632 kb
Host smart-7e6c0a97-fb49-4534-b2b1-b242c6a8d814
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928667610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.2928667610
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.405284643
Short name T941
Test name
Test status
Simulation time 105157948357 ps
CPU time 223.57 seconds
Started Jun 21 04:46:15 PM PDT 24
Finished Jun 21 04:50:03 PM PDT 24
Peak memory 200660 kb
Host smart-cd47f71a-29d2-43b7-b9b0-5213e3dcfe11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=405284643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.405284643
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.234498263
Short name T868
Test name
Test status
Simulation time 4303787403 ps
CPU time 8.49 seconds
Started Jun 21 04:46:11 PM PDT 24
Finished Jun 21 04:46:26 PM PDT 24
Peak memory 199432 kb
Host smart-0b5c3610-b448-4be6-b745-e4ba363586b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234498263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.234498263
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_perf.801762236
Short name T860
Test name
Test status
Simulation time 15938696534 ps
CPU time 413.96 seconds
Started Jun 21 04:46:04 PM PDT 24
Finished Jun 21 04:53:05 PM PDT 24
Peak memory 200512 kb
Host smart-f10c24d8-0080-4325-93a1-6fd72af3d7a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=801762236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.801762236
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.2477457912
Short name T801
Test name
Test status
Simulation time 6127064063 ps
CPU time 13.4 seconds
Started Jun 21 04:46:04 PM PDT 24
Finished Jun 21 04:46:24 PM PDT 24
Peak memory 199524 kb
Host smart-ee767d3d-fb7c-40b4-8228-54e52d04e8ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2477457912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.2477457912
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.824529395
Short name T290
Test name
Test status
Simulation time 99518586640 ps
CPU time 42.92 seconds
Started Jun 21 04:46:11 PM PDT 24
Finished Jun 21 04:46:59 PM PDT 24
Peak memory 200612 kb
Host smart-8a805989-440a-47a7-bedb-2934fcdd3244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824529395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.824529395
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.2470438459
Short name T491
Test name
Test status
Simulation time 5439716349 ps
CPU time 9.34 seconds
Started Jun 21 04:46:04 PM PDT 24
Finished Jun 21 04:46:21 PM PDT 24
Peak memory 196684 kb
Host smart-6d615175-6617-4007-8fe6-97e051cf1192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470438459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.2470438459
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.4229550575
Short name T696
Test name
Test status
Simulation time 947693608 ps
CPU time 1.59 seconds
Started Jun 21 04:46:11 PM PDT 24
Finished Jun 21 04:46:19 PM PDT 24
Peak memory 199076 kb
Host smart-3b013f3d-a937-45bf-955b-72d73d31a68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229550575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.4229550575
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.146140158
Short name T474
Test name
Test status
Simulation time 159479878011 ps
CPU time 411.29 seconds
Started Jun 21 04:46:14 PM PDT 24
Finished Jun 21 04:53:10 PM PDT 24
Peak memory 200500 kb
Host smart-1c89e391-97f5-4308-8cff-a0d3da00b3b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146140158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.146140158
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.732290564
Short name T706
Test name
Test status
Simulation time 33488174653 ps
CPU time 529.41 seconds
Started Jun 21 04:46:05 PM PDT 24
Finished Jun 21 04:55:01 PM PDT 24
Peak memory 216200 kb
Host smart-389cb8b5-5a7c-4315-9ae0-bc3d4dfc6039
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732290564 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.732290564
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.2228553126
Short name T355
Test name
Test status
Simulation time 1286536147 ps
CPU time 3.9 seconds
Started Jun 21 04:46:14 PM PDT 24
Finished Jun 21 04:46:23 PM PDT 24
Peak memory 199908 kb
Host smart-f41599ff-4017-4ab7-b2c4-b10677c44a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228553126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.2228553126
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.377389469
Short name T524
Test name
Test status
Simulation time 112288647398 ps
CPU time 43.73 seconds
Started Jun 21 04:46:05 PM PDT 24
Finished Jun 21 04:46:57 PM PDT 24
Peak memory 200572 kb
Host smart-8746a2f6-25e4-426c-959e-dd35ba82326d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377389469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.377389469
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.2686757904
Short name T35
Test name
Test status
Simulation time 15776414 ps
CPU time 0.57 seconds
Started Jun 21 04:46:15 PM PDT 24
Finished Jun 21 04:46:20 PM PDT 24
Peak memory 196024 kb
Host smart-71d6730b-67b2-44fd-ba35-200af8d6155f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686757904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.2686757904
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.2880592705
Short name T529
Test name
Test status
Simulation time 289470559686 ps
CPU time 151.2 seconds
Started Jun 21 04:46:15 PM PDT 24
Finished Jun 21 04:48:51 PM PDT 24
Peak memory 200648 kb
Host smart-673d62a1-a07f-44fb-9eec-84c2cd3f6b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880592705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.2880592705
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.794082638
Short name T545
Test name
Test status
Simulation time 34010182832 ps
CPU time 16.45 seconds
Started Jun 21 04:46:05 PM PDT 24
Finished Jun 21 04:46:29 PM PDT 24
Peak memory 200632 kb
Host smart-85d66665-3672-4e9e-a68f-4a58ad19ff6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794082638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.794082638
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.3023031248
Short name T188
Test name
Test status
Simulation time 238362254580 ps
CPU time 387.25 seconds
Started Jun 21 04:46:10 PM PDT 24
Finished Jun 21 04:52:44 PM PDT 24
Peak memory 200596 kb
Host smart-4355841d-5805-41ef-8dc5-fcc4c1f3140f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023031248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.3023031248
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.49682180
Short name T468
Test name
Test status
Simulation time 18839052210 ps
CPU time 8.81 seconds
Started Jun 21 04:46:12 PM PDT 24
Finished Jun 21 04:46:26 PM PDT 24
Peak memory 199608 kb
Host smart-5f061d04-bd3c-426c-b1d8-82534f88579c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49682180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.49682180
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.3420906545
Short name T1010
Test name
Test status
Simulation time 86310443645 ps
CPU time 122.94 seconds
Started Jun 21 04:46:11 PM PDT 24
Finished Jun 21 04:48:19 PM PDT 24
Peak memory 200656 kb
Host smart-ca703965-e60e-4023-bf96-287cddf79c2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3420906545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.3420906545
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.3669179890
Short name T510
Test name
Test status
Simulation time 451566965 ps
CPU time 1.38 seconds
Started Jun 21 04:46:11 PM PDT 24
Finished Jun 21 04:46:19 PM PDT 24
Peak memory 197716 kb
Host smart-0c2aa695-3749-452e-bc0a-c0f3046fbcf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669179890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.3669179890
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_perf.836993726
Short name T8
Test name
Test status
Simulation time 16733965160 ps
CPU time 970.6 seconds
Started Jun 21 04:46:12 PM PDT 24
Finished Jun 21 05:02:28 PM PDT 24
Peak memory 200480 kb
Host smart-75f42663-e9bf-4bb8-8a5e-2622b438bd59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=836993726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.836993726
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.3100993326
Short name T111
Test name
Test status
Simulation time 2431344599 ps
CPU time 16.55 seconds
Started Jun 21 04:46:08 PM PDT 24
Finished Jun 21 04:46:32 PM PDT 24
Peak memory 198704 kb
Host smart-befc55a6-b6fe-4646-bf68-b49cd230eb09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3100993326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.3100993326
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.2829465805
Short name T752
Test name
Test status
Simulation time 118788469765 ps
CPU time 182.89 seconds
Started Jun 21 04:46:08 PM PDT 24
Finished Jun 21 04:49:18 PM PDT 24
Peak memory 200508 kb
Host smart-c4ebabbe-b966-41e2-8815-e3116b3363bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829465805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.2829465805
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.1415522542
Short name T1097
Test name
Test status
Simulation time 46828248063 ps
CPU time 11.17 seconds
Started Jun 21 04:46:14 PM PDT 24
Finished Jun 21 04:46:30 PM PDT 24
Peak memory 196216 kb
Host smart-b0788fbe-70cc-4dd1-83f9-496f6b8dbeb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415522542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.1415522542
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.1722728169
Short name T1040
Test name
Test status
Simulation time 585531713 ps
CPU time 1.39 seconds
Started Jun 21 04:46:08 PM PDT 24
Finished Jun 21 04:46:16 PM PDT 24
Peak memory 199512 kb
Host smart-0a5f0243-d4b9-4a57-92fc-9a17869ecfd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722728169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.1722728169
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.1956427269
Short name T43
Test name
Test status
Simulation time 62434812037 ps
CPU time 521.74 seconds
Started Jun 21 04:46:11 PM PDT 24
Finished Jun 21 04:54:59 PM PDT 24
Peak memory 213000 kb
Host smart-9c94bb8a-fb33-445e-8eda-26a959944d84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956427269 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.1956427269
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.3056857623
Short name T451
Test name
Test status
Simulation time 1343044248 ps
CPU time 1.64 seconds
Started Jun 21 04:46:10 PM PDT 24
Finished Jun 21 04:46:18 PM PDT 24
Peak memory 199244 kb
Host smart-a0199fa6-db5f-467f-9fd8-0de2187e33fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056857623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.3056857623
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.3390374867
Short name T569
Test name
Test status
Simulation time 67887898199 ps
CPU time 98.14 seconds
Started Jun 21 04:46:11 PM PDT 24
Finished Jun 21 04:47:55 PM PDT 24
Peak memory 200620 kb
Host smart-29accd02-c644-40cb-9b53-40ad9e393d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390374867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.3390374867
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.214934062
Short name T785
Test name
Test status
Simulation time 18138756 ps
CPU time 0.56 seconds
Started Jun 21 04:44:28 PM PDT 24
Finished Jun 21 04:44:31 PM PDT 24
Peak memory 195924 kb
Host smart-3c60e5ec-5326-46f1-881a-502e880549ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214934062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.214934062
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.805580367
Short name T1022
Test name
Test status
Simulation time 117589228258 ps
CPU time 361.03 seconds
Started Jun 21 04:44:29 PM PDT 24
Finished Jun 21 04:50:32 PM PDT 24
Peak memory 200600 kb
Host smart-34c99925-7602-4bb5-a818-c7c58a73f51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805580367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.805580367
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.1416359358
Short name T492
Test name
Test status
Simulation time 36331015962 ps
CPU time 60.87 seconds
Started Jun 21 04:44:24 PM PDT 24
Finished Jun 21 04:45:29 PM PDT 24
Peak memory 198392 kb
Host smart-6952acdb-8b08-4325-aaa2-05fb0fadda4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416359358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.1416359358
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.3571546238
Short name T716
Test name
Test status
Simulation time 18054328978 ps
CPU time 37.17 seconds
Started Jun 21 04:44:34 PM PDT 24
Finished Jun 21 04:45:12 PM PDT 24
Peak memory 200672 kb
Host smart-90bb1671-abc7-4036-832b-8a5bc1516c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571546238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.3571546238
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.3209260976
Short name T1044
Test name
Test status
Simulation time 13263076755 ps
CPU time 11.19 seconds
Started Jun 21 04:44:29 PM PDT 24
Finished Jun 21 04:44:43 PM PDT 24
Peak memory 200580 kb
Host smart-69db84b0-b4f9-4bad-b9ba-f87564e9b9cb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209260976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.3209260976
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.1296221622
Short name T314
Test name
Test status
Simulation time 61821591237 ps
CPU time 89.84 seconds
Started Jun 21 04:44:27 PM PDT 24
Finished Jun 21 04:46:00 PM PDT 24
Peak memory 200612 kb
Host smart-f58fcf8f-c58a-4165-b8d4-9ffeffb7dd93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1296221622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.1296221622
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.1994481661
Short name T954
Test name
Test status
Simulation time 8430251516 ps
CPU time 13.51 seconds
Started Jun 21 04:44:38 PM PDT 24
Finished Jun 21 04:44:53 PM PDT 24
Peak memory 200384 kb
Host smart-5e656476-88dc-4105-a915-d14c0d99652f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994481661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.1994481661
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_perf.1748903867
Short name T1030
Test name
Test status
Simulation time 18143277734 ps
CPU time 67.01 seconds
Started Jun 21 04:44:28 PM PDT 24
Finished Jun 21 04:45:37 PM PDT 24
Peak memory 200608 kb
Host smart-18ec03c9-ee66-4e7a-881b-242d33014ec9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1748903867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.1748903867
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.3141151295
Short name T608
Test name
Test status
Simulation time 5297373245 ps
CPU time 45.51 seconds
Started Jun 21 04:44:36 PM PDT 24
Finished Jun 21 04:45:23 PM PDT 24
Peak memory 199872 kb
Host smart-02896a28-e845-42c1-9324-2d6b1ac0d831
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3141151295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.3141151295
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.1948585213
Short name T539
Test name
Test status
Simulation time 136191415570 ps
CPU time 197.77 seconds
Started Jun 21 04:44:35 PM PDT 24
Finished Jun 21 04:47:54 PM PDT 24
Peak memory 200296 kb
Host smart-d8e89dc8-f22e-4318-86cd-87a99bbc8d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948585213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.1948585213
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.882395637
Short name T935
Test name
Test status
Simulation time 28934884401 ps
CPU time 22.88 seconds
Started Jun 21 04:44:31 PM PDT 24
Finished Jun 21 04:44:56 PM PDT 24
Peak memory 196664 kb
Host smart-3a54c313-1271-4a7e-9d1d-f2bdfa2fe3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882395637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.882395637
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.3695707851
Short name T37
Test name
Test status
Simulation time 58443901 ps
CPU time 0.86 seconds
Started Jun 21 04:44:45 PM PDT 24
Finished Jun 21 04:44:50 PM PDT 24
Peak memory 218908 kb
Host smart-73b5ecac-1faa-462f-aedc-868ea7768953
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695707851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.3695707851
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.1058579998
Short name T403
Test name
Test status
Simulation time 5455719987 ps
CPU time 24.93 seconds
Started Jun 21 04:44:29 PM PDT 24
Finished Jun 21 04:44:56 PM PDT 24
Peak memory 200560 kb
Host smart-39ef318c-0f0a-4dc6-a8ad-de8633e79b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058579998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.1058579998
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.890578116
Short name T638
Test name
Test status
Simulation time 144785087507 ps
CPU time 397.47 seconds
Started Jun 21 04:44:31 PM PDT 24
Finished Jun 21 04:51:11 PM PDT 24
Peak memory 217040 kb
Host smart-a924b84c-d641-4773-a713-138fa8ab0f33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890578116 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.890578116
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.760923812
Short name T792
Test name
Test status
Simulation time 1025737979 ps
CPU time 4.24 seconds
Started Jun 21 04:44:29 PM PDT 24
Finished Jun 21 04:44:35 PM PDT 24
Peak memory 200360 kb
Host smart-ea404bb6-1cfe-4a45-b93f-49605d4f9777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760923812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.760923812
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.524553905
Short name T302
Test name
Test status
Simulation time 42836440702 ps
CPU time 36.18 seconds
Started Jun 21 04:44:10 PM PDT 24
Finished Jun 21 04:44:49 PM PDT 24
Peak memory 200580 kb
Host smart-40870b89-e16e-45fc-a833-de37ebdec506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524553905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.524553905
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.117640826
Short name T515
Test name
Test status
Simulation time 14183983 ps
CPU time 0.55 seconds
Started Jun 21 04:46:11 PM PDT 24
Finished Jun 21 04:46:18 PM PDT 24
Peak memory 196108 kb
Host smart-01cf8fa8-5a8d-4862-8d76-a69faa89137e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117640826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.117640826
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.2568169169
Short name T917
Test name
Test status
Simulation time 21101208580 ps
CPU time 73.3 seconds
Started Jun 21 04:46:10 PM PDT 24
Finished Jun 21 04:47:30 PM PDT 24
Peak memory 200564 kb
Host smart-3f672d64-763b-4dc8-8faa-9add22953154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568169169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.2568169169
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.1131490832
Short name T598
Test name
Test status
Simulation time 103368037040 ps
CPU time 133.55 seconds
Started Jun 21 04:46:11 PM PDT 24
Finished Jun 21 04:48:30 PM PDT 24
Peak memory 200672 kb
Host smart-3eeb06ab-52bf-4f14-a76f-1bf4f23b9b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131490832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.1131490832
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.3804832772
Short name T585
Test name
Test status
Simulation time 16747667123 ps
CPU time 25.98 seconds
Started Jun 21 04:46:15 PM PDT 24
Finished Jun 21 04:46:45 PM PDT 24
Peak memory 200624 kb
Host smart-cbd06a30-161e-4c0e-9bfd-fb9bd3dacee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804832772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.3804832772
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.2966422831
Short name T991
Test name
Test status
Simulation time 95856030037 ps
CPU time 66.11 seconds
Started Jun 21 04:46:14 PM PDT 24
Finished Jun 21 04:47:25 PM PDT 24
Peak memory 196556 kb
Host smart-99f3e10a-e874-4c04-a723-e35334495033
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966422831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.2966422831
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.2365364954
Short name T275
Test name
Test status
Simulation time 82422597724 ps
CPU time 162.57 seconds
Started Jun 21 04:46:05 PM PDT 24
Finished Jun 21 04:48:55 PM PDT 24
Peak memory 200556 kb
Host smart-1685ffe0-b22b-4241-b4b9-fabb453a8172
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2365364954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.2365364954
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.767593843
Short name T690
Test name
Test status
Simulation time 9607550916 ps
CPU time 6.36 seconds
Started Jun 21 04:45:58 PM PDT 24
Finished Jun 21 04:46:11 PM PDT 24
Peak memory 199744 kb
Host smart-2f38d827-97e5-4c1e-a199-961135f14412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767593843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.767593843
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_perf.183857441
Short name T873
Test name
Test status
Simulation time 4041776671 ps
CPU time 155.83 seconds
Started Jun 21 04:46:14 PM PDT 24
Finished Jun 21 04:48:55 PM PDT 24
Peak memory 200604 kb
Host smart-67179c41-90a8-4899-bdc6-256f1d5dc002
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=183857441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.183857441
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.1986404440
Short name T605
Test name
Test status
Simulation time 3653273860 ps
CPU time 11.49 seconds
Started Jun 21 04:46:11 PM PDT 24
Finished Jun 21 04:46:29 PM PDT 24
Peak memory 198764 kb
Host smart-27f39f38-f208-4678-902d-5e5130becc4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1986404440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.1986404440
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.1401046868
Short name T184
Test name
Test status
Simulation time 36790505868 ps
CPU time 58 seconds
Started Jun 21 04:46:06 PM PDT 24
Finished Jun 21 04:47:11 PM PDT 24
Peak memory 200572 kb
Host smart-ede31eb0-759f-4f3a-bd51-1ebaa0fa6df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401046868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.1401046868
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.2117453047
Short name T368
Test name
Test status
Simulation time 39686105545 ps
CPU time 16.28 seconds
Started Jun 21 04:46:10 PM PDT 24
Finished Jun 21 04:46:32 PM PDT 24
Peak memory 196852 kb
Host smart-66cdaaef-fc18-431e-b685-e923c0864485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117453047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.2117453047
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.3003455382
Short name T796
Test name
Test status
Simulation time 792333809 ps
CPU time 1.38 seconds
Started Jun 21 04:46:15 PM PDT 24
Finished Jun 21 04:46:21 PM PDT 24
Peak memory 200592 kb
Host smart-b62a83d0-36db-4cf5-a815-c6e6455a5a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003455382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.3003455382
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.25968175
Short name T70
Test name
Test status
Simulation time 133991621407 ps
CPU time 1024.64 seconds
Started Jun 21 04:46:11 PM PDT 24
Finished Jun 21 05:03:21 PM PDT 24
Peak memory 225288 kb
Host smart-d503f439-48ea-44d9-ae06-2d90b2e67527
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25968175 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.25968175
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.598130146
Short name T259
Test name
Test status
Simulation time 1295083717 ps
CPU time 3.2 seconds
Started Jun 21 04:46:14 PM PDT 24
Finished Jun 21 04:46:22 PM PDT 24
Peak memory 199952 kb
Host smart-a6b782e4-a4d4-469a-bce2-7b0f9cee75e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598130146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.598130146
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.1190742828
Short name T1058
Test name
Test status
Simulation time 61003707208 ps
CPU time 21.8 seconds
Started Jun 21 04:46:11 PM PDT 24
Finished Jun 21 04:46:39 PM PDT 24
Peak memory 200364 kb
Host smart-2d907b42-966b-4ff4-b43b-7a8588e1a5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190742828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.1190742828
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.566832978
Short name T447
Test name
Test status
Simulation time 61718020 ps
CPU time 0.55 seconds
Started Jun 21 04:46:16 PM PDT 24
Finished Jun 21 04:46:20 PM PDT 24
Peak memory 195944 kb
Host smart-8f02b0e8-6634-4fca-a1e7-8a72f3a08354
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566832978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.566832978
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.3881413740
Short name T488
Test name
Test status
Simulation time 40599609660 ps
CPU time 29.19 seconds
Started Jun 21 04:46:06 PM PDT 24
Finished Jun 21 04:46:42 PM PDT 24
Peak memory 200632 kb
Host smart-ad2d3f2b-ca73-41e1-a377-fa7b7644070a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881413740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.3881413740
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.975197203
Short name T1079
Test name
Test status
Simulation time 71604157905 ps
CPU time 35.95 seconds
Started Jun 21 04:46:12 PM PDT 24
Finished Jun 21 04:46:53 PM PDT 24
Peak memory 200624 kb
Host smart-e9370532-c727-4638-8edf-a903551c3afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975197203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.975197203
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.3081372494
Short name T665
Test name
Test status
Simulation time 50514365371 ps
CPU time 15.41 seconds
Started Jun 21 04:46:14 PM PDT 24
Finished Jun 21 04:46:34 PM PDT 24
Peak memory 200564 kb
Host smart-cae62f96-022f-494a-96c3-39afedeac549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081372494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.3081372494
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.3045048057
Short name T457
Test name
Test status
Simulation time 24222940498 ps
CPU time 5.82 seconds
Started Jun 21 04:46:05 PM PDT 24
Finished Jun 21 04:46:18 PM PDT 24
Peak memory 200348 kb
Host smart-99e0b18c-dadb-4f4d-a81c-fe0b82bb77a9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045048057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.3045048057
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.2430851908
Short name T635
Test name
Test status
Simulation time 88293127138 ps
CPU time 151.38 seconds
Started Jun 21 04:46:10 PM PDT 24
Finished Jun 21 04:48:47 PM PDT 24
Peak memory 200608 kb
Host smart-23abf3ae-6bb9-48b8-98e6-6f9c43e079eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2430851908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.2430851908
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.2859895538
Short name T809
Test name
Test status
Simulation time 9200693978 ps
CPU time 7.11 seconds
Started Jun 21 04:46:16 PM PDT 24
Finished Jun 21 04:46:27 PM PDT 24
Peak memory 200120 kb
Host smart-d3a1fd74-79c1-47df-ab9e-00e155d4d288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859895538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.2859895538
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_perf.1624097889
Short name T258
Test name
Test status
Simulation time 23625787662 ps
CPU time 197.59 seconds
Started Jun 21 04:46:09 PM PDT 24
Finished Jun 21 04:49:33 PM PDT 24
Peak memory 200608 kb
Host smart-139c2819-83f5-4371-99ca-d03fa0cf646f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1624097889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.1624097889
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.2851398235
Short name T984
Test name
Test status
Simulation time 1377383764 ps
CPU time 2.81 seconds
Started Jun 21 04:46:14 PM PDT 24
Finished Jun 21 04:46:22 PM PDT 24
Peak memory 198836 kb
Host smart-8de1f698-2226-4687-bbb4-e0c26e658478
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2851398235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.2851398235
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.1088070485
Short name T794
Test name
Test status
Simulation time 6720719255 ps
CPU time 3.37 seconds
Started Jun 21 04:46:12 PM PDT 24
Finished Jun 21 04:46:21 PM PDT 24
Peak memory 200592 kb
Host smart-93adc939-8f8f-48f1-b127-6f9ea5180814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088070485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.1088070485
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.4229128348
Short name T462
Test name
Test status
Simulation time 5464221909 ps
CPU time 2.4 seconds
Started Jun 21 04:46:18 PM PDT 24
Finished Jun 21 04:46:22 PM PDT 24
Peak memory 196880 kb
Host smart-aa1f9bf5-b6b3-4718-ada9-b21f2b600faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229128348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.4229128348
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.3925555593
Short name T679
Test name
Test status
Simulation time 487010608 ps
CPU time 1.27 seconds
Started Jun 21 04:46:12 PM PDT 24
Finished Jun 21 04:46:19 PM PDT 24
Peak memory 200316 kb
Host smart-5dbcf111-8936-4e33-bfd2-9183f27cb7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925555593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.3925555593
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.3260185443
Short name T27
Test name
Test status
Simulation time 64660854604 ps
CPU time 438.24 seconds
Started Jun 21 04:46:14 PM PDT 24
Finished Jun 21 04:53:37 PM PDT 24
Peak memory 208848 kb
Host smart-676a6408-94c4-41f5-aeb0-6674d689ee60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260185443 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.3260185443
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.320205415
Short name T351
Test name
Test status
Simulation time 1199044293 ps
CPU time 3.67 seconds
Started Jun 21 04:46:11 PM PDT 24
Finished Jun 21 04:46:20 PM PDT 24
Peak memory 200192 kb
Host smart-e726f0bf-182c-4f9b-8ba5-eafde97bea27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320205415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.320205415
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.337935911
Short name T11
Test name
Test status
Simulation time 39643005443 ps
CPU time 14.84 seconds
Started Jun 21 04:46:10 PM PDT 24
Finished Jun 21 04:46:31 PM PDT 24
Peak memory 199572 kb
Host smart-0028786f-ff81-4d94-a53a-6ef467430f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337935911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.337935911
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.3030015655
Short name T341
Test name
Test status
Simulation time 22393358 ps
CPU time 0.53 seconds
Started Jun 21 04:46:18 PM PDT 24
Finished Jun 21 04:46:21 PM PDT 24
Peak memory 195476 kb
Host smart-9f4d49ef-620f-414b-ac58-2a0a938feb43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030015655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.3030015655
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.1709752949
Short name T669
Test name
Test status
Simulation time 47692827205 ps
CPU time 23.1 seconds
Started Jun 21 04:46:11 PM PDT 24
Finished Jun 21 04:46:40 PM PDT 24
Peak memory 200624 kb
Host smart-1968f14f-dafe-48bd-a375-ac98ee71364c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709752949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.1709752949
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.1421473794
Short name T513
Test name
Test status
Simulation time 150801532696 ps
CPU time 77.45 seconds
Started Jun 21 04:46:14 PM PDT 24
Finished Jun 21 04:47:36 PM PDT 24
Peak memory 200632 kb
Host smart-01c34b70-faa8-4282-9485-f65572ebe264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421473794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.1421473794
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.2898792436
Short name T626
Test name
Test status
Simulation time 167185443941 ps
CPU time 49.56 seconds
Started Jun 21 04:46:22 PM PDT 24
Finished Jun 21 04:47:14 PM PDT 24
Peak memory 200644 kb
Host smart-66e6fada-294d-4e8b-b794-8ebfb7f82c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898792436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.2898792436
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.3087970102
Short name T844
Test name
Test status
Simulation time 157315774364 ps
CPU time 124.15 seconds
Started Jun 21 04:46:18 PM PDT 24
Finished Jun 21 04:48:24 PM PDT 24
Peak memory 196884 kb
Host smart-4f274078-3229-465a-a62d-098756394bc5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087970102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.3087970102
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.1219148509
Short name T1031
Test name
Test status
Simulation time 117644222040 ps
CPU time 266.45 seconds
Started Jun 21 04:46:18 PM PDT 24
Finished Jun 21 04:50:46 PM PDT 24
Peak memory 200596 kb
Host smart-835dd22b-8803-48dd-9169-37d1b356bf9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1219148509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.1219148509
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.3116607301
Short name T338
Test name
Test status
Simulation time 2204253005 ps
CPU time 2.01 seconds
Started Jun 21 04:46:20 PM PDT 24
Finished Jun 21 04:46:23 PM PDT 24
Peak memory 199404 kb
Host smart-bffbc768-dfc4-487e-af60-e726aba6e0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116607301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.3116607301
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_perf.3586429316
Short name T565
Test name
Test status
Simulation time 19425848562 ps
CPU time 275.11 seconds
Started Jun 21 04:46:11 PM PDT 24
Finished Jun 21 04:50:52 PM PDT 24
Peak memory 200600 kb
Host smart-291703b2-59d4-4182-ada1-db9532ac1e7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3586429316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.3586429316
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.2988511872
Short name T361
Test name
Test status
Simulation time 3410496455 ps
CPU time 6.86 seconds
Started Jun 21 04:46:10 PM PDT 24
Finished Jun 21 04:46:22 PM PDT 24
Peak memory 198776 kb
Host smart-d62d6a90-6651-44f5-9ec3-a4e6dced0454
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2988511872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.2988511872
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.3241184802
Short name T306
Test name
Test status
Simulation time 211767420902 ps
CPU time 26.82 seconds
Started Jun 21 04:46:15 PM PDT 24
Finished Jun 21 04:46:46 PM PDT 24
Peak memory 200360 kb
Host smart-27ee0e02-39cc-47cf-bfa4-dde91b62af22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241184802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.3241184802
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.2184917719
Short name T271
Test name
Test status
Simulation time 4646247446 ps
CPU time 1.96 seconds
Started Jun 21 04:46:10 PM PDT 24
Finished Jun 21 04:46:18 PM PDT 24
Peak memory 197320 kb
Host smart-cf1134a3-0907-4f70-b812-f7546b844129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184917719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.2184917719
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.1619569038
Short name T364
Test name
Test status
Simulation time 482488030 ps
CPU time 1.97 seconds
Started Jun 21 04:46:09 PM PDT 24
Finished Jun 21 04:46:18 PM PDT 24
Peak memory 199416 kb
Host smart-bd7d48ac-e384-4ec2-98ae-dbefd837e520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619569038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.1619569038
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.3713834551
Short name T930
Test name
Test status
Simulation time 237568023507 ps
CPU time 536.15 seconds
Started Jun 21 04:46:16 PM PDT 24
Finished Jun 21 04:55:16 PM PDT 24
Peak memory 200612 kb
Host smart-cc3bbda1-f90e-429d-8b84-36ee7d63f2bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713834551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.3713834551
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.3741647278
Short name T698
Test name
Test status
Simulation time 119993853579 ps
CPU time 472.65 seconds
Started Jun 21 04:46:12 PM PDT 24
Finished Jun 21 04:54:10 PM PDT 24
Peak memory 211528 kb
Host smart-ef0b7d5e-abe2-473d-8b31-e90e92434d2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741647278 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.3741647278
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.1392915214
Short name T568
Test name
Test status
Simulation time 7236130852 ps
CPU time 18.21 seconds
Started Jun 21 04:46:12 PM PDT 24
Finished Jun 21 04:46:36 PM PDT 24
Peak memory 200540 kb
Host smart-f734c355-77c3-4085-9376-214a9ffe84d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392915214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.1392915214
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.2395753153
Short name T805
Test name
Test status
Simulation time 19855404582 ps
CPU time 36.33 seconds
Started Jun 21 04:46:11 PM PDT 24
Finished Jun 21 04:46:53 PM PDT 24
Peak memory 200660 kb
Host smart-3832df61-bd44-4306-8ee6-d3e3d14c85ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395753153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.2395753153
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.4903555
Short name T339
Test name
Test status
Simulation time 13904646 ps
CPU time 0.56 seconds
Started Jun 21 04:46:29 PM PDT 24
Finished Jun 21 04:46:30 PM PDT 24
Peak memory 195960 kb
Host smart-a23929f8-571e-4dc3-87d7-7889446574f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4903555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.4903555
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.2618947501
Short name T1059
Test name
Test status
Simulation time 153121278140 ps
CPU time 126.31 seconds
Started Jun 21 04:46:31 PM PDT 24
Finished Jun 21 04:48:38 PM PDT 24
Peak memory 200672 kb
Host smart-35b7f941-70bd-45f7-a477-4f43849a2e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618947501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.2618947501
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.52305033
Short name T833
Test name
Test status
Simulation time 139763413543 ps
CPU time 216.18 seconds
Started Jun 21 04:46:30 PM PDT 24
Finished Jun 21 04:50:07 PM PDT 24
Peak memory 200560 kb
Host smart-da9a1b45-23ea-41d6-972e-9b17e2a53cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52305033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.52305033
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.19832446
Short name T213
Test name
Test status
Simulation time 126456470456 ps
CPU time 47.3 seconds
Started Jun 21 04:46:22 PM PDT 24
Finished Jun 21 04:47:11 PM PDT 24
Peak memory 200532 kb
Host smart-e122d438-bc17-4172-88e4-bec3f0b532d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19832446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.19832446
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.3363289938
Short name T989
Test name
Test status
Simulation time 20480181368 ps
CPU time 9.73 seconds
Started Jun 21 04:46:26 PM PDT 24
Finished Jun 21 04:46:36 PM PDT 24
Peak memory 198188 kb
Host smart-8d0995c3-6eb6-4e1e-9b8c-6cc565dce039
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363289938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.3363289938
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.3878486378
Short name T763
Test name
Test status
Simulation time 132349931558 ps
CPU time 1258.28 seconds
Started Jun 21 04:46:22 PM PDT 24
Finished Jun 21 05:07:21 PM PDT 24
Peak memory 200596 kb
Host smart-1155d416-1783-4711-a775-91268a6428d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3878486378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.3878486378
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.2173267827
Short name T26
Test name
Test status
Simulation time 5359549781 ps
CPU time 8.95 seconds
Started Jun 21 04:46:29 PM PDT 24
Finished Jun 21 04:46:39 PM PDT 24
Peak memory 199768 kb
Host smart-7bfac347-99a6-4311-9eae-11648ea59a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173267827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.2173267827
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.1632628299
Short name T612
Test name
Test status
Simulation time 179738831781 ps
CPU time 29.16 seconds
Started Jun 21 04:46:25 PM PDT 24
Finished Jun 21 04:46:56 PM PDT 24
Peak memory 200576 kb
Host smart-7e0f1bcf-57b8-4e6c-a793-f21b8fed895f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632628299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.1632628299
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.198939477
Short name T516
Test name
Test status
Simulation time 18694660174 ps
CPU time 1109.56 seconds
Started Jun 21 04:46:27 PM PDT 24
Finished Jun 21 05:04:58 PM PDT 24
Peak memory 200576 kb
Host smart-1e0c7500-4d06-478f-904f-ba07278586f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=198939477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.198939477
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.1712079277
Short name T783
Test name
Test status
Simulation time 4510240906 ps
CPU time 8.22 seconds
Started Jun 21 04:46:28 PM PDT 24
Finished Jun 21 04:46:37 PM PDT 24
Peak memory 199884 kb
Host smart-f3e8511c-9221-4ea9-82b7-d796ba236428
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1712079277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.1712079277
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.1412659709
Short name T662
Test name
Test status
Simulation time 253579764526 ps
CPU time 129.56 seconds
Started Jun 21 04:46:22 PM PDT 24
Finished Jun 21 04:48:33 PM PDT 24
Peak memory 200532 kb
Host smart-efaeb4b7-eaae-4e0b-99b6-3c487b06b506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412659709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.1412659709
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.2207428047
Short name T1027
Test name
Test status
Simulation time 4728964321 ps
CPU time 2.32 seconds
Started Jun 21 04:46:26 PM PDT 24
Finished Jun 21 04:46:29 PM PDT 24
Peak memory 197372 kb
Host smart-81d9c92d-b53a-424d-a4bf-316955c6e6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207428047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.2207428047
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.856987794
Short name T657
Test name
Test status
Simulation time 742195556 ps
CPU time 2.56 seconds
Started Jun 21 04:46:22 PM PDT 24
Finished Jun 21 04:46:25 PM PDT 24
Peak memory 198836 kb
Host smart-41bdddd4-6015-4ed4-a06d-3373a7021b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856987794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.856987794
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.2020999128
Short name T117
Test name
Test status
Simulation time 92796340357 ps
CPU time 192.19 seconds
Started Jun 21 04:46:27 PM PDT 24
Finished Jun 21 04:49:41 PM PDT 24
Peak memory 216908 kb
Host smart-04bfd663-45de-4078-bb4e-d41236454225
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020999128 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.2020999128
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.4244513114
Short name T640
Test name
Test status
Simulation time 6250266337 ps
CPU time 6.26 seconds
Started Jun 21 04:46:27 PM PDT 24
Finished Jun 21 04:46:35 PM PDT 24
Peak memory 200616 kb
Host smart-7489d369-292c-4178-9ae3-e8ce8548d4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244513114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.4244513114
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.1459037589
Short name T1016
Test name
Test status
Simulation time 5981007936 ps
CPU time 3.68 seconds
Started Jun 21 04:46:26 PM PDT 24
Finished Jun 21 04:46:30 PM PDT 24
Peak memory 200684 kb
Host smart-b07118bc-0967-4164-b552-2dd841bbe4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459037589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.1459037589
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.3940143654
Short name T479
Test name
Test status
Simulation time 13770573 ps
CPU time 0.53 seconds
Started Jun 21 04:46:22 PM PDT 24
Finished Jun 21 04:46:23 PM PDT 24
Peak memory 194988 kb
Host smart-1fc31f39-24a7-4922-82f7-6f4a75cbf611
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940143654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.3940143654
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.824257386
Short name T880
Test name
Test status
Simulation time 51435079227 ps
CPU time 68.14 seconds
Started Jun 21 04:46:22 PM PDT 24
Finished Jun 21 04:47:31 PM PDT 24
Peak memory 200588 kb
Host smart-aff28a90-6170-4bca-855a-3b6f4c1801c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824257386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.824257386
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.343691273
Short name T401
Test name
Test status
Simulation time 17566827001 ps
CPU time 8.19 seconds
Started Jun 21 04:46:28 PM PDT 24
Finished Jun 21 04:46:38 PM PDT 24
Peak memory 200356 kb
Host smart-4c9d505f-a424-4782-881a-270170d3a5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343691273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.343691273
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.1714185851
Short name T186
Test name
Test status
Simulation time 9431783030 ps
CPU time 19.43 seconds
Started Jun 21 04:46:23 PM PDT 24
Finished Jun 21 04:46:44 PM PDT 24
Peak memory 200584 kb
Host smart-9cae8ce3-124f-43fd-b555-beb8f3606787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714185851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.1714185851
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.1678838993
Short name T426
Test name
Test status
Simulation time 11430450115 ps
CPU time 9.67 seconds
Started Jun 21 04:46:27 PM PDT 24
Finished Jun 21 04:46:38 PM PDT 24
Peak memory 197264 kb
Host smart-c9cb5db2-a8a3-40c3-bd59-62051bdfea7e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678838993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.1678838993
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.59162522
Short name T907
Test name
Test status
Simulation time 57130952227 ps
CPU time 129.17 seconds
Started Jun 21 04:46:22 PM PDT 24
Finished Jun 21 04:48:32 PM PDT 24
Peak memory 200548 kb
Host smart-63fbf1d3-f0e6-4c68-a536-a4f29ebdaa37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=59162522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.59162522
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.1753426939
Short name T676
Test name
Test status
Simulation time 3067200636 ps
CPU time 2.79 seconds
Started Jun 21 04:46:28 PM PDT 24
Finished Jun 21 04:46:32 PM PDT 24
Peak memory 196920 kb
Host smart-8e055601-22d2-429c-8418-f27d8be8119b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753426939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.1753426939
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_perf.3240874899
Short name T1033
Test name
Test status
Simulation time 8862560207 ps
CPU time 31.25 seconds
Started Jun 21 04:46:29 PM PDT 24
Finished Jun 21 04:47:01 PM PDT 24
Peak memory 200648 kb
Host smart-450af8bc-8195-42cb-93e7-a0ade4dc598d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3240874899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.3240874899
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.98227390
Short name T475
Test name
Test status
Simulation time 2728408945 ps
CPU time 20.68 seconds
Started Jun 21 04:46:26 PM PDT 24
Finished Jun 21 04:46:47 PM PDT 24
Peak memory 198632 kb
Host smart-98908e0b-32b9-451b-a767-5ee08b60148e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=98227390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.98227390
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.2705217500
Short name T979
Test name
Test status
Simulation time 22646173808 ps
CPU time 43.24 seconds
Started Jun 21 04:46:26 PM PDT 24
Finished Jun 21 04:47:10 PM PDT 24
Peak memory 200684 kb
Host smart-b1494215-431b-48d7-aeab-841947a4b51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705217500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.2705217500
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.1066062194
Short name T1014
Test name
Test status
Simulation time 35594416906 ps
CPU time 11.54 seconds
Started Jun 21 04:46:32 PM PDT 24
Finished Jun 21 04:46:44 PM PDT 24
Peak memory 197116 kb
Host smart-ae50cdea-cd4e-40c6-b041-73521faea139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066062194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.1066062194
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.450172341
Short name T292
Test name
Test status
Simulation time 5643728871 ps
CPU time 16.67 seconds
Started Jun 21 04:46:28 PM PDT 24
Finished Jun 21 04:46:45 PM PDT 24
Peak memory 200532 kb
Host smart-688f8c1a-dc59-42d3-8f02-a5cdc85ef891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450172341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.450172341
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.1107479929
Short name T304
Test name
Test status
Simulation time 69247602806 ps
CPU time 264.42 seconds
Started Jun 21 04:46:23 PM PDT 24
Finished Jun 21 04:50:49 PM PDT 24
Peak memory 209216 kb
Host smart-348c6f71-7053-4c35-8991-ca10828a78aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107479929 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.1107479929
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.368807848
Short name T540
Test name
Test status
Simulation time 8551580856 ps
CPU time 5.74 seconds
Started Jun 21 04:46:22 PM PDT 24
Finished Jun 21 04:46:30 PM PDT 24
Peak memory 200608 kb
Host smart-28eae2c8-feba-4c1e-b328-62ed782e495a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368807848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.368807848
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.2354259036
Short name T9
Test name
Test status
Simulation time 38637318921 ps
CPU time 31.94 seconds
Started Jun 21 04:46:23 PM PDT 24
Finished Jun 21 04:46:57 PM PDT 24
Peak memory 200552 kb
Host smart-b74f49c9-1e06-4857-af60-ba0352a8ab0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354259036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.2354259036
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.2018851805
Short name T945
Test name
Test status
Simulation time 26172771 ps
CPU time 0.58 seconds
Started Jun 21 04:47:05 PM PDT 24
Finished Jun 21 04:47:09 PM PDT 24
Peak memory 196024 kb
Host smart-c36a076a-8e89-43fa-bbb7-ce519bbfc963
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018851805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.2018851805
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.1570620288
Short name T781
Test name
Test status
Simulation time 34807405789 ps
CPU time 38.6 seconds
Started Jun 21 04:47:07 PM PDT 24
Finished Jun 21 04:47:50 PM PDT 24
Peak memory 200612 kb
Host smart-fec341d3-15c2-4976-a0d4-a3407e247efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570620288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.1570620288
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.1798976969
Short name T563
Test name
Test status
Simulation time 76135118020 ps
CPU time 65.8 seconds
Started Jun 21 04:47:05 PM PDT 24
Finished Jun 21 04:48:14 PM PDT 24
Peak memory 200684 kb
Host smart-8d282c53-7b24-4f43-82c4-101bd5cb3d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798976969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.1798976969
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.1384052780
Short name T210
Test name
Test status
Simulation time 39329854392 ps
CPU time 56.04 seconds
Started Jun 21 04:47:08 PM PDT 24
Finished Jun 21 04:48:07 PM PDT 24
Peak memory 200596 kb
Host smart-30948665-ec4d-47e7-9dde-00f0a7d92307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384052780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.1384052780
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.3490200819
Short name T905
Test name
Test status
Simulation time 36031693775 ps
CPU time 57.71 seconds
Started Jun 21 04:47:06 PM PDT 24
Finished Jun 21 04:48:08 PM PDT 24
Peak memory 197512 kb
Host smart-31a90005-70d0-405a-bfed-2eba05334839
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490200819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.3490200819
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.1974004292
Short name T822
Test name
Test status
Simulation time 68869509978 ps
CPU time 145.16 seconds
Started Jun 21 04:47:08 PM PDT 24
Finished Jun 21 04:49:37 PM PDT 24
Peak memory 200552 kb
Host smart-19818342-2bc3-4b9e-b8a6-91be9f6e39f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1974004292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.1974004292
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.2582230402
Short name T376
Test name
Test status
Simulation time 7187194209 ps
CPU time 5.44 seconds
Started Jun 21 04:47:04 PM PDT 24
Finished Jun 21 04:47:12 PM PDT 24
Peak memory 199308 kb
Host smart-fcdc080a-7a61-4dc1-b073-05315059e2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582230402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.2582230402
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_perf.4241311138
Short name T648
Test name
Test status
Simulation time 18885053414 ps
CPU time 255.38 seconds
Started Jun 21 04:47:07 PM PDT 24
Finished Jun 21 04:51:27 PM PDT 24
Peak memory 200660 kb
Host smart-65ed0de0-639f-48ab-bfa5-2329e4365680
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4241311138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.4241311138
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.3610422870
Short name T902
Test name
Test status
Simulation time 1812334420 ps
CPU time 2.54 seconds
Started Jun 21 04:47:06 PM PDT 24
Finished Jun 21 04:47:12 PM PDT 24
Peak memory 198952 kb
Host smart-2ad1e2f7-6339-4bef-bca4-399899a84c39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3610422870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.3610422870
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.3484707788
Short name T391
Test name
Test status
Simulation time 23180288214 ps
CPU time 37.72 seconds
Started Jun 21 04:47:05 PM PDT 24
Finished Jun 21 04:47:45 PM PDT 24
Peak memory 200612 kb
Host smart-23ccd5d1-e24e-4bb3-b749-9f1fcaba0cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484707788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.3484707788
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.2112371462
Short name T909
Test name
Test status
Simulation time 1147893848 ps
CPU time 2.41 seconds
Started Jun 21 04:47:04 PM PDT 24
Finished Jun 21 04:47:09 PM PDT 24
Peak memory 196124 kb
Host smart-05ea664e-ae7a-486b-b811-0e441afed596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112371462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.2112371462
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.2373763608
Short name T1009
Test name
Test status
Simulation time 690610938 ps
CPU time 2.73 seconds
Started Jun 21 04:47:08 PM PDT 24
Finished Jun 21 04:47:15 PM PDT 24
Peak memory 199552 kb
Host smart-c29df9a1-a447-47a7-a66c-d750b00c0b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373763608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.2373763608
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.2186214129
Short name T946
Test name
Test status
Simulation time 205669977121 ps
CPU time 853.21 seconds
Started Jun 21 04:47:04 PM PDT 24
Finished Jun 21 05:01:18 PM PDT 24
Peak memory 217120 kb
Host smart-951c1852-36f2-4a90-8b1b-27ffc943314e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186214129 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.2186214129
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.3116927986
Short name T62
Test name
Test status
Simulation time 1239132837 ps
CPU time 1.73 seconds
Started Jun 21 04:47:04 PM PDT 24
Finished Jun 21 04:47:08 PM PDT 24
Peak memory 199380 kb
Host smart-397a26db-6b42-4f04-a7f5-9f07da78a2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116927986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.3116927986
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.2143757459
Short name T400
Test name
Test status
Simulation time 74867322917 ps
CPU time 227.7 seconds
Started Jun 21 04:47:06 PM PDT 24
Finished Jun 21 04:50:57 PM PDT 24
Peak memory 200324 kb
Host smart-d0ba7b91-3e69-4a20-b83f-592e36539322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143757459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.2143757459
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.2557947155
Short name T614
Test name
Test status
Simulation time 61521986 ps
CPU time 0.53 seconds
Started Jun 21 04:47:04 PM PDT 24
Finished Jun 21 04:47:07 PM PDT 24
Peak memory 196004 kb
Host smart-3ca0a1da-337c-4a92-ba46-b2b570afda41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557947155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.2557947155
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.3313997493
Short name T444
Test name
Test status
Simulation time 37121435435 ps
CPU time 17.91 seconds
Started Jun 21 04:47:06 PM PDT 24
Finished Jun 21 04:47:28 PM PDT 24
Peak memory 200384 kb
Host smart-ed02ca45-4497-4f8d-9132-d20b6fc4710c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313997493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.3313997493
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.1575337429
Short name T749
Test name
Test status
Simulation time 23817633309 ps
CPU time 47.93 seconds
Started Jun 21 04:47:05 PM PDT 24
Finished Jun 21 04:47:56 PM PDT 24
Peak memory 200564 kb
Host smart-00e7f6c2-0081-4b09-b6fb-0aa7618d72f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575337429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.1575337429
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.3713553751
Short name T845
Test name
Test status
Simulation time 11103229081 ps
CPU time 21.17 seconds
Started Jun 21 04:47:08 PM PDT 24
Finished Jun 21 04:47:33 PM PDT 24
Peak memory 200684 kb
Host smart-d19e21a8-86ad-4ba1-88f9-72149007372d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713553751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.3713553751
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.3987834312
Short name T394
Test name
Test status
Simulation time 10916741582 ps
CPU time 10.03 seconds
Started Jun 21 04:47:05 PM PDT 24
Finished Jun 21 04:47:18 PM PDT 24
Peak memory 198228 kb
Host smart-64bcc7ca-5ac6-4725-a4b1-bb4da5a1f6f2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987834312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.3987834312
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.3085527938
Short name T1096
Test name
Test status
Simulation time 197329810235 ps
CPU time 126.23 seconds
Started Jun 21 04:47:05 PM PDT 24
Finished Jun 21 04:49:13 PM PDT 24
Peak memory 200552 kb
Host smart-4525f45e-3b63-4b4e-afd1-b2c1f23439b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3085527938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.3085527938
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.1416089199
Short name T641
Test name
Test status
Simulation time 8897490995 ps
CPU time 6.19 seconds
Started Jun 21 04:47:08 PM PDT 24
Finished Jun 21 04:47:18 PM PDT 24
Peak memory 200540 kb
Host smart-47944455-7831-4dfc-8afe-d9bed54951f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416089199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.1416089199
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_perf.33040431
Short name T896
Test name
Test status
Simulation time 6978180777 ps
CPU time 295.13 seconds
Started Jun 21 04:47:05 PM PDT 24
Finished Jun 21 04:52:03 PM PDT 24
Peak memory 200652 kb
Host smart-d902b33a-40dc-4070-922b-502f164e675c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=33040431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.33040431
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.1057259509
Short name T770
Test name
Test status
Simulation time 6837169376 ps
CPU time 14.09 seconds
Started Jun 21 04:47:06 PM PDT 24
Finished Jun 21 04:47:23 PM PDT 24
Peak memory 198764 kb
Host smart-50bb3ebf-dcf9-4ba0-8156-9cdf45e7f281
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1057259509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.1057259509
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.3321312331
Short name T265
Test name
Test status
Simulation time 222205116613 ps
CPU time 23.02 seconds
Started Jun 21 04:47:08 PM PDT 24
Finished Jun 21 04:47:35 PM PDT 24
Peak memory 200648 kb
Host smart-7c77b778-eddd-4b8c-b648-10361224828c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321312331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.3321312331
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.3117069310
Short name T943
Test name
Test status
Simulation time 3480911903 ps
CPU time 1.42 seconds
Started Jun 21 04:47:05 PM PDT 24
Finished Jun 21 04:47:10 PM PDT 24
Peak memory 196940 kb
Host smart-1db9966a-f536-467f-a373-59ecf2900186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117069310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.3117069310
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.3510884317
Short name T435
Test name
Test status
Simulation time 539025235 ps
CPU time 1.91 seconds
Started Jun 21 04:47:06 PM PDT 24
Finished Jun 21 04:47:12 PM PDT 24
Peak memory 199728 kb
Host smart-322f6d3e-207b-4ea4-8b25-fabc785d4c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510884317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.3510884317
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.1805279002
Short name T1029
Test name
Test status
Simulation time 39932324562 ps
CPU time 69.67 seconds
Started Jun 21 04:47:06 PM PDT 24
Finished Jun 21 04:48:19 PM PDT 24
Peak memory 200608 kb
Host smart-ff3958a5-da6b-4c92-a5f1-f7d00bd63420
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805279002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.1805279002
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.3918790403
Short name T864
Test name
Test status
Simulation time 1965577864 ps
CPU time 2.13 seconds
Started Jun 21 04:47:06 PM PDT 24
Finished Jun 21 04:47:12 PM PDT 24
Peak memory 198916 kb
Host smart-2870faa6-5593-4eaf-ba55-8b37266d1d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918790403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.3918790403
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.2668109734
Short name T446
Test name
Test status
Simulation time 30086322030 ps
CPU time 14.52 seconds
Started Jun 21 04:47:06 PM PDT 24
Finished Jun 21 04:47:24 PM PDT 24
Peak memory 200668 kb
Host smart-5d1e1550-3ab0-46f2-bf55-609ab2014c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668109734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.2668109734
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.1921151854
Short name T1032
Test name
Test status
Simulation time 10869243 ps
CPU time 0.55 seconds
Started Jun 21 04:47:06 PM PDT 24
Finished Jun 21 04:47:10 PM PDT 24
Peak memory 195464 kb
Host smart-9aaaf626-13a9-4ddf-ad3e-daddf74c9e71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921151854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.1921151854
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.2393301409
Short name T521
Test name
Test status
Simulation time 17379355525 ps
CPU time 9.09 seconds
Started Jun 21 04:47:05 PM PDT 24
Finished Jun 21 04:47:18 PM PDT 24
Peak memory 200612 kb
Host smart-ca620d6f-75cf-44c3-8f2d-ac07d89de35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393301409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.2393301409
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.2320876788
Short name T548
Test name
Test status
Simulation time 109841716699 ps
CPU time 48.32 seconds
Started Jun 21 04:47:06 PM PDT 24
Finished Jun 21 04:47:58 PM PDT 24
Peak memory 200668 kb
Host smart-f01c4593-10e8-42e4-bab5-9cc5c7aa9f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320876788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.2320876788
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.167599917
Short name T238
Test name
Test status
Simulation time 17005712150 ps
CPU time 24.54 seconds
Started Jun 21 04:47:05 PM PDT 24
Finished Jun 21 04:47:32 PM PDT 24
Peak memory 200576 kb
Host smart-27e147ad-f67a-4c1a-9e16-ca748db47578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167599917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.167599917
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.3547507926
Short name T396
Test name
Test status
Simulation time 38961943268 ps
CPU time 57.73 seconds
Started Jun 21 04:47:08 PM PDT 24
Finished Jun 21 04:48:10 PM PDT 24
Peak memory 200604 kb
Host smart-3c7ced04-e732-4e3c-9c5b-e1959588875b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547507926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.3547507926
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.4008060093
Short name T362
Test name
Test status
Simulation time 96422096914 ps
CPU time 533.91 seconds
Started Jun 21 04:47:06 PM PDT 24
Finished Jun 21 04:56:04 PM PDT 24
Peak memory 200340 kb
Host smart-baac9c61-9021-4989-864e-fd3693007c24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4008060093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.4008060093
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.251977390
Short name T542
Test name
Test status
Simulation time 66277512 ps
CPU time 0.74 seconds
Started Jun 21 04:47:07 PM PDT 24
Finished Jun 21 04:47:12 PM PDT 24
Peak memory 196748 kb
Host smart-176bc4bf-5375-47b9-939b-169cd0e8caf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251977390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.251977390
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.1253603871
Short name T277
Test name
Test status
Simulation time 7930049001 ps
CPU time 9.36 seconds
Started Jun 21 04:47:03 PM PDT 24
Finished Jun 21 04:47:13 PM PDT 24
Peak memory 200688 kb
Host smart-233f03b4-9f4c-4eff-ad91-23653f3529d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253603871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.1253603871
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.3628666857
Short name T5
Test name
Test status
Simulation time 21814273237 ps
CPU time 267.05 seconds
Started Jun 21 04:47:07 PM PDT 24
Finished Jun 21 04:51:38 PM PDT 24
Peak memory 200544 kb
Host smart-9a415f46-acd7-4e7a-b9ce-67eaf16c5c54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3628666857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.3628666857
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.1749622700
Short name T987
Test name
Test status
Simulation time 3381460880 ps
CPU time 24.83 seconds
Started Jun 21 04:47:06 PM PDT 24
Finished Jun 21 04:47:34 PM PDT 24
Peak memory 198916 kb
Host smart-6191b323-5f77-47b4-a64a-61dec8ef1991
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1749622700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.1749622700
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.3586674201
Short name T867
Test name
Test status
Simulation time 88696188239 ps
CPU time 78.27 seconds
Started Jun 21 04:47:06 PM PDT 24
Finished Jun 21 04:48:29 PM PDT 24
Peak memory 200680 kb
Host smart-a45613aa-a685-45e0-ba09-7ea9bbc8f926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586674201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.3586674201
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.3744861558
Short name T393
Test name
Test status
Simulation time 38934675860 ps
CPU time 3.51 seconds
Started Jun 21 04:47:05 PM PDT 24
Finished Jun 21 04:47:11 PM PDT 24
Peak memory 196464 kb
Host smart-04b42bbb-3d8f-4c4b-981b-a58f83b07f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744861558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.3744861558
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.2125810359
Short name T937
Test name
Test status
Simulation time 460250972 ps
CPU time 1.74 seconds
Started Jun 21 04:47:02 PM PDT 24
Finished Jun 21 04:47:05 PM PDT 24
Peak memory 199028 kb
Host smart-6f3a2bb7-a3b9-4f1f-bf2a-820ca07a3a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125810359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.2125810359
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.4008379539
Short name T797
Test name
Test status
Simulation time 84449030644 ps
CPU time 525.65 seconds
Started Jun 21 04:47:08 PM PDT 24
Finished Jun 21 04:55:58 PM PDT 24
Peak memory 217000 kb
Host smart-93659852-42f2-4130-a2cd-f6200e01c6f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008379539 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.4008379539
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.4285195904
Short name T723
Test name
Test status
Simulation time 1618693434 ps
CPU time 1.83 seconds
Started Jun 21 04:47:04 PM PDT 24
Finished Jun 21 04:47:08 PM PDT 24
Peak memory 200168 kb
Host smart-5d2dd54b-583f-45a4-bfa6-54544dcf848f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285195904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.4285195904
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.2425241849
Short name T580
Test name
Test status
Simulation time 192031250365 ps
CPU time 48.39 seconds
Started Jun 21 04:47:06 PM PDT 24
Finished Jun 21 04:47:59 PM PDT 24
Peak memory 200556 kb
Host smart-06165984-f93d-4531-b28f-c3d6d944e6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425241849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.2425241849
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.4132010484
Short name T938
Test name
Test status
Simulation time 40053788 ps
CPU time 0.53 seconds
Started Jun 21 04:47:18 PM PDT 24
Finished Jun 21 04:47:21 PM PDT 24
Peak memory 195452 kb
Host smart-18583b27-9ec3-4248-968d-c60e2efa7a10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132010484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.4132010484
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.3997240385
Short name T145
Test name
Test status
Simulation time 36373765651 ps
CPU time 14.96 seconds
Started Jun 21 04:47:06 PM PDT 24
Finished Jun 21 04:47:25 PM PDT 24
Peak memory 200600 kb
Host smart-f8a9cf31-6127-4cb8-9a88-96d456543aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997240385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.3997240385
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_intr.511602727
Short name T429
Test name
Test status
Simulation time 386136550498 ps
CPU time 116.79 seconds
Started Jun 21 04:47:18 PM PDT 24
Finished Jun 21 04:49:17 PM PDT 24
Peak memory 200500 kb
Host smart-70c75bc7-b858-4bcb-a4db-da64ca7b1b1a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511602727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.511602727
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_loopback.2763109896
Short name T865
Test name
Test status
Simulation time 112988291 ps
CPU time 0.77 seconds
Started Jun 21 04:47:20 PM PDT 24
Finished Jun 21 04:47:23 PM PDT 24
Peak memory 197936 kb
Host smart-2a5ada6c-c0f0-4b61-996c-583abda1f446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763109896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.2763109896
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_perf.1165415031
Short name T744
Test name
Test status
Simulation time 9426777679 ps
CPU time 274.67 seconds
Started Jun 21 04:47:19 PM PDT 24
Finished Jun 21 04:51:56 PM PDT 24
Peak memory 200648 kb
Host smart-3de1c084-adeb-4b98-8920-7b056ec55516
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1165415031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.1165415031
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.2801813970
Short name T490
Test name
Test status
Simulation time 6235825623 ps
CPU time 15.82 seconds
Started Jun 21 04:47:16 PM PDT 24
Finished Jun 21 04:47:34 PM PDT 24
Peak memory 199816 kb
Host smart-e4cb690d-0a64-43b4-bc21-24923092937e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2801813970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.2801813970
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.781265368
Short name T179
Test name
Test status
Simulation time 89339553205 ps
CPU time 68.81 seconds
Started Jun 21 04:47:15 PM PDT 24
Finished Jun 21 04:48:26 PM PDT 24
Peak memory 200652 kb
Host smart-eda9752d-1688-4aab-a868-ab2d5d23a3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781265368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.781265368
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.2255644590
Short name T477
Test name
Test status
Simulation time 1610842996 ps
CPU time 3.16 seconds
Started Jun 21 04:47:17 PM PDT 24
Finished Jun 21 04:47:23 PM PDT 24
Peak memory 196064 kb
Host smart-2fc7b95d-3bb1-452d-8dc3-e4a6dcf4b4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255644590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.2255644590
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.167495821
Short name T559
Test name
Test status
Simulation time 501507319 ps
CPU time 1.79 seconds
Started Jun 21 04:47:08 PM PDT 24
Finished Jun 21 04:47:13 PM PDT 24
Peak memory 199288 kb
Host smart-c73a1166-f7a4-44cc-8578-16cd1e37c955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167495821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.167495821
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.926768353
Short name T321
Test name
Test status
Simulation time 57467063628 ps
CPU time 327.78 seconds
Started Jun 21 04:47:20 PM PDT 24
Finished Jun 21 04:52:51 PM PDT 24
Peak memory 217040 kb
Host smart-a8773a9b-9216-4109-8a97-0a02084eb269
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926768353 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.926768353
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.4221667847
Short name T23
Test name
Test status
Simulation time 7101896673 ps
CPU time 29.61 seconds
Started Jun 21 04:47:14 PM PDT 24
Finished Jun 21 04:47:45 PM PDT 24
Peak memory 200444 kb
Host smart-aae64b27-dbda-4acd-bc3f-81a28dfc01e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221667847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.4221667847
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.3923530842
Short name T456
Test name
Test status
Simulation time 83876689965 ps
CPU time 12.92 seconds
Started Jun 21 04:47:03 PM PDT 24
Finished Jun 21 04:47:17 PM PDT 24
Peak memory 199572 kb
Host smart-9c31e29e-b95e-4fd8-b31e-5ede19b39566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923530842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.3923530842
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.4052830318
Short name T379
Test name
Test status
Simulation time 10882913 ps
CPU time 0.53 seconds
Started Jun 21 04:47:22 PM PDT 24
Finished Jun 21 04:47:27 PM PDT 24
Peak memory 196000 kb
Host smart-04ce45cd-684a-40d9-a80b-06c1b1bf46c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052830318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.4052830318
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.1110712157
Short name T284
Test name
Test status
Simulation time 219517872498 ps
CPU time 89.82 seconds
Started Jun 21 04:47:20 PM PDT 24
Finished Jun 21 04:48:51 PM PDT 24
Peak memory 200612 kb
Host smart-00cd0a7f-1bbd-4d9f-b830-07381542ff56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110712157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.1110712157
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.357048969
Short name T172
Test name
Test status
Simulation time 18277260354 ps
CPU time 33.55 seconds
Started Jun 21 04:47:17 PM PDT 24
Finished Jun 21 04:47:53 PM PDT 24
Peak memory 200472 kb
Host smart-e3f5d19e-5366-4a72-a9e2-5527cf129391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357048969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.357048969
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.360003945
Short name T135
Test name
Test status
Simulation time 187486628270 ps
CPU time 300.69 seconds
Started Jun 21 04:47:13 PM PDT 24
Finished Jun 21 04:52:16 PM PDT 24
Peak memory 200620 kb
Host smart-51ce430b-8fae-438e-a267-7803a9374913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360003945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.360003945
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.882739018
Short name T829
Test name
Test status
Simulation time 28881046837 ps
CPU time 4.95 seconds
Started Jun 21 04:47:15 PM PDT 24
Finished Jun 21 04:47:22 PM PDT 24
Peak memory 199700 kb
Host smart-9eef3a24-a6a3-4ba5-b8b3-92cdcad1a695
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882739018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.882739018
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.3277270420
Short name T721
Test name
Test status
Simulation time 97351949223 ps
CPU time 310.09 seconds
Started Jun 21 04:47:20 PM PDT 24
Finished Jun 21 04:52:32 PM PDT 24
Peak memory 200608 kb
Host smart-3331c58f-534d-4403-88ef-487ca044065d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3277270420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.3277270420
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.2799582957
Short name T340
Test name
Test status
Simulation time 7843411591 ps
CPU time 18.1 seconds
Started Jun 21 04:47:24 PM PDT 24
Finished Jun 21 04:47:49 PM PDT 24
Peak memory 200252 kb
Host smart-e32bd294-c136-4753-a243-d9de2ab5ff86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799582957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.2799582957
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_perf.2679755487
Short name T255
Test name
Test status
Simulation time 17650740519 ps
CPU time 1001.4 seconds
Started Jun 21 04:47:17 PM PDT 24
Finished Jun 21 05:04:01 PM PDT 24
Peak memory 200588 kb
Host smart-9bc7bd2b-c907-4059-9e55-5ed8d66429f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2679755487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.2679755487
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.977408228
Short name T1068
Test name
Test status
Simulation time 5405227146 ps
CPU time 22.23 seconds
Started Jun 21 04:47:14 PM PDT 24
Finished Jun 21 04:47:38 PM PDT 24
Peak memory 198860 kb
Host smart-08d6e19e-fef5-4c0e-b6d3-423c609e4164
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=977408228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.977408228
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.1910260355
Short name T169
Test name
Test status
Simulation time 32565143606 ps
CPU time 13.72 seconds
Started Jun 21 04:47:19 PM PDT 24
Finished Jun 21 04:47:35 PM PDT 24
Peak memory 200624 kb
Host smart-b2a6f4df-3b41-4ba5-afda-189fab7d02e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910260355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.1910260355
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.4247376403
Short name T1051
Test name
Test status
Simulation time 30674191794 ps
CPU time 6.15 seconds
Started Jun 21 04:47:24 PM PDT 24
Finished Jun 21 04:47:37 PM PDT 24
Peak memory 196500 kb
Host smart-18806811-4242-46b8-ad26-33782d8413ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247376403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.4247376403
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.2066231053
Short name T533
Test name
Test status
Simulation time 275074235 ps
CPU time 1.06 seconds
Started Jun 21 04:47:16 PM PDT 24
Finished Jun 21 04:47:19 PM PDT 24
Peak memory 200036 kb
Host smart-461233f1-ea7d-4afa-b33c-c3919cc8b620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066231053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.2066231053
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.3956364472
Short name T334
Test name
Test status
Simulation time 125692904066 ps
CPU time 246.92 seconds
Started Jun 21 04:47:18 PM PDT 24
Finished Jun 21 04:51:26 PM PDT 24
Peak memory 200520 kb
Host smart-277afde7-f479-4c44-9220-c66eecec65e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956364472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.3956364472
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.1861090724
Short name T196
Test name
Test status
Simulation time 34188606640 ps
CPU time 476.81 seconds
Started Jun 21 04:47:16 PM PDT 24
Finished Jun 21 04:55:15 PM PDT 24
Peak memory 216452 kb
Host smart-8152e624-fb9f-42cd-a518-7a68911a64fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861090724 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.1861090724
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.3827852807
Short name T617
Test name
Test status
Simulation time 1356474519 ps
CPU time 1.93 seconds
Started Jun 21 04:47:21 PM PDT 24
Finished Jun 21 04:47:28 PM PDT 24
Peak memory 199120 kb
Host smart-b25b586f-d86a-44eb-b08b-28836ed2592a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827852807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.3827852807
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.1695856138
Short name T295
Test name
Test status
Simulation time 73336630854 ps
CPU time 66.31 seconds
Started Jun 21 04:47:16 PM PDT 24
Finished Jun 21 04:48:24 PM PDT 24
Peak memory 200576 kb
Host smart-8debc7da-7676-4c77-bf5a-70130501969e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695856138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.1695856138
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.394853061
Short name T722
Test name
Test status
Simulation time 66894171 ps
CPU time 0.55 seconds
Started Jun 21 04:44:39 PM PDT 24
Finished Jun 21 04:44:41 PM PDT 24
Peak memory 195972 kb
Host smart-d177c8e0-ae8e-445f-a878-41b1c7aca37b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394853061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.394853061
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.1167711143
Short name T879
Test name
Test status
Simulation time 118392608589 ps
CPU time 212.74 seconds
Started Jun 21 04:44:36 PM PDT 24
Finished Jun 21 04:48:11 PM PDT 24
Peak memory 200624 kb
Host smart-f3872eec-d07c-411a-9d93-cf5332e2a690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167711143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.1167711143
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.461466479
Short name T1080
Test name
Test status
Simulation time 54203469877 ps
CPU time 41.15 seconds
Started Jun 21 04:44:27 PM PDT 24
Finished Jun 21 04:45:11 PM PDT 24
Peak memory 200580 kb
Host smart-f2bdbf35-cda4-488f-a5e1-5aeef405ddda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461466479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.461466479
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.345833298
Short name T543
Test name
Test status
Simulation time 66163071375 ps
CPU time 25.56 seconds
Started Jun 21 04:44:27 PM PDT 24
Finished Jun 21 04:44:55 PM PDT 24
Peak memory 200552 kb
Host smart-46db969e-b9ec-4206-b674-141ff4be01e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345833298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.345833298
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.3485597174
Short name T874
Test name
Test status
Simulation time 60685888029 ps
CPU time 21.9 seconds
Started Jun 21 04:44:28 PM PDT 24
Finished Jun 21 04:44:52 PM PDT 24
Peak memory 198916 kb
Host smart-2f1fb8c6-6de8-4263-9271-cf9e3b7c979d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485597174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.3485597174
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.1050676958
Short name T625
Test name
Test status
Simulation time 42708063503 ps
CPU time 91.13 seconds
Started Jun 21 04:44:42 PM PDT 24
Finished Jun 21 04:46:14 PM PDT 24
Peak memory 200564 kb
Host smart-00c5f0ce-1fa0-41c3-9064-b16fa636c578
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1050676958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.1050676958
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.1308576318
Short name T816
Test name
Test status
Simulation time 426154838 ps
CPU time 1.26 seconds
Started Jun 21 04:44:42 PM PDT 24
Finished Jun 21 04:44:44 PM PDT 24
Peak memory 196048 kb
Host smart-f92ddaf7-56c2-4db6-9fcd-5e910356332f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308576318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.1308576318
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.2593267006
Short name T573
Test name
Test status
Simulation time 9854622679 ps
CPU time 15.53 seconds
Started Jun 21 04:44:24 PM PDT 24
Finished Jun 21 04:44:44 PM PDT 24
Peak memory 198288 kb
Host smart-4eaa4a7e-676c-4e6a-868d-9e614ed67995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593267006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.2593267006
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.3865674580
Short name T354
Test name
Test status
Simulation time 4660919216 ps
CPU time 63.01 seconds
Started Jun 21 04:44:33 PM PDT 24
Finished Jun 21 04:45:38 PM PDT 24
Peak memory 200524 kb
Host smart-0e172292-6353-4bc1-aa74-7b380f6584cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3865674580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.3865674580
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.246833443
Short name T755
Test name
Test status
Simulation time 4583786281 ps
CPU time 3.29 seconds
Started Jun 21 04:44:25 PM PDT 24
Finished Jun 21 04:44:32 PM PDT 24
Peak memory 199900 kb
Host smart-fe455817-5626-42fa-81fb-c51febad8a25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=246833443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.246833443
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.23017481
Short name T549
Test name
Test status
Simulation time 51305553201 ps
CPU time 75.91 seconds
Started Jun 21 04:44:44 PM PDT 24
Finished Jun 21 04:46:02 PM PDT 24
Peak memory 200592 kb
Host smart-7baa7bf9-bc04-48e5-b4b0-71913c985796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23017481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.23017481
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.1680342483
Short name T1002
Test name
Test status
Simulation time 630037425 ps
CPU time 0.89 seconds
Started Jun 21 04:44:29 PM PDT 24
Finished Jun 21 04:44:32 PM PDT 24
Peak memory 196056 kb
Host smart-32af0a9b-1b5a-4b27-b4c0-2525b53725ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680342483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.1680342483
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.4075236181
Short name T730
Test name
Test status
Simulation time 669772231 ps
CPU time 2.66 seconds
Started Jun 21 04:44:37 PM PDT 24
Finished Jun 21 04:44:41 PM PDT 24
Peak memory 199324 kb
Host smart-d715c4ad-1e05-4abc-8a70-ee529758245b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075236181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.4075236181
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.1387948454
Short name T122
Test name
Test status
Simulation time 544665429233 ps
CPU time 484.84 seconds
Started Jun 21 04:44:44 PM PDT 24
Finished Jun 21 04:52:51 PM PDT 24
Peak memory 200624 kb
Host smart-1f4eef46-8024-4676-b3d2-f55d730201eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387948454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.1387948454
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.2809390323
Short name T127
Test name
Test status
Simulation time 136835034315 ps
CPU time 1509.47 seconds
Started Jun 21 04:44:47 PM PDT 24
Finished Jun 21 05:10:00 PM PDT 24
Peak memory 225804 kb
Host smart-5ab9e26c-8517-4b36-892b-6b6674b262b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809390323 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.2809390323
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.2179679688
Short name T760
Test name
Test status
Simulation time 475643992 ps
CPU time 1.45 seconds
Started Jun 21 04:44:34 PM PDT 24
Finished Jun 21 04:44:36 PM PDT 24
Peak memory 198668 kb
Host smart-c3a50551-f5eb-4f36-9323-f8791ea283f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179679688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.2179679688
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.405168601
Short name T560
Test name
Test status
Simulation time 36545405094 ps
CPU time 29.94 seconds
Started Jun 21 04:44:41 PM PDT 24
Finished Jun 21 04:45:13 PM PDT 24
Peak memory 200544 kb
Host smart-61991ff8-7392-4a60-81dc-b0502196c2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405168601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.405168601
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.214403247
Short name T570
Test name
Test status
Simulation time 122639005548 ps
CPU time 49.48 seconds
Started Jun 21 04:47:22 PM PDT 24
Finished Jun 21 04:48:16 PM PDT 24
Peak memory 200644 kb
Host smart-1b84f027-9619-4b9d-9f26-464ea439885b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214403247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.214403247
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.1397645550
Short name T178
Test name
Test status
Simulation time 67761306390 ps
CPU time 561.68 seconds
Started Jun 21 04:47:20 PM PDT 24
Finished Jun 21 04:56:44 PM PDT 24
Peak memory 217060 kb
Host smart-a72bfa04-79b1-4ed5-8b51-db94a5b39f6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397645550 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.1397645550
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.2616615540
Short name T305
Test name
Test status
Simulation time 34847418352 ps
CPU time 67.77 seconds
Started Jun 21 04:47:17 PM PDT 24
Finished Jun 21 04:48:26 PM PDT 24
Peak memory 200624 kb
Host smart-e5c780dd-a450-4207-8c90-e23f34ec45d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616615540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.2616615540
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.1850225932
Short name T160
Test name
Test status
Simulation time 115821422089 ps
CPU time 198.51 seconds
Started Jun 21 04:47:24 PM PDT 24
Finished Jun 21 04:50:49 PM PDT 24
Peak memory 200216 kb
Host smart-49d67ae6-8d8c-491d-bd4e-f73adc4e6ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850225932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.1850225932
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.141027467
Short name T120
Test name
Test status
Simulation time 34956141641 ps
CPU time 339.73 seconds
Started Jun 21 04:47:24 PM PDT 24
Finished Jun 21 04:53:10 PM PDT 24
Peak memory 216928 kb
Host smart-6bfa9a3a-bb32-4da3-9a87-c934a3083454
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141027467 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.141027467
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.854974481
Short name T895
Test name
Test status
Simulation time 33700053051 ps
CPU time 11.18 seconds
Started Jun 21 04:47:18 PM PDT 24
Finished Jun 21 04:47:31 PM PDT 24
Peak memory 200584 kb
Host smart-706aa2f2-4e61-4de0-b4af-74c55e1dfec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854974481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.854974481
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.1070584727
Short name T771
Test name
Test status
Simulation time 165374291749 ps
CPU time 1324.26 seconds
Started Jun 21 04:47:20 PM PDT 24
Finished Jun 21 05:09:28 PM PDT 24
Peak memory 225300 kb
Host smart-722ba8e8-e61f-4f00-b095-f297963681f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070584727 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.1070584727
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.3970054257
Short name T963
Test name
Test status
Simulation time 35943189060 ps
CPU time 24.33 seconds
Started Jun 21 04:47:19 PM PDT 24
Finished Jun 21 04:47:45 PM PDT 24
Peak memory 200640 kb
Host smart-a984069f-3925-4fdb-ae6b-f7a563e66d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970054257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.3970054257
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.3495349777
Short name T811
Test name
Test status
Simulation time 50579028395 ps
CPU time 863.92 seconds
Started Jun 21 04:47:18 PM PDT 24
Finished Jun 21 05:01:44 PM PDT 24
Peak memory 216380 kb
Host smart-2e017abc-1559-4f1e-811b-35ed2b35d44e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495349777 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.3495349777
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.3621342116
Short name T200
Test name
Test status
Simulation time 9445824749 ps
CPU time 13.76 seconds
Started Jun 21 04:47:15 PM PDT 24
Finished Jun 21 04:47:31 PM PDT 24
Peak memory 200532 kb
Host smart-5feb4ba4-db83-4faf-931e-af5befa3114a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621342116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.3621342116
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.1893188949
Short name T118
Test name
Test status
Simulation time 72327741017 ps
CPU time 590.89 seconds
Started Jun 21 04:47:22 PM PDT 24
Finished Jun 21 04:57:18 PM PDT 24
Peak memory 217024 kb
Host smart-4ca573ba-3caa-4250-8e8a-17d68622f20a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893188949 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.1893188949
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.3659954860
Short name T193
Test name
Test status
Simulation time 83828488279 ps
CPU time 87.62 seconds
Started Jun 21 04:47:19 PM PDT 24
Finished Jun 21 04:48:49 PM PDT 24
Peak memory 200496 kb
Host smart-491a38cb-052d-4ee3-b674-3f86809a7b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659954860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.3659954860
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.450061498
Short name T776
Test name
Test status
Simulation time 121609937791 ps
CPU time 369.8 seconds
Started Jun 21 04:47:21 PM PDT 24
Finished Jun 21 04:53:34 PM PDT 24
Peak memory 217088 kb
Host smart-70389d44-cf5b-4d47-889d-152f67b7c3b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450061498 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.450061498
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.2952518937
Short name T471
Test name
Test status
Simulation time 39128301195 ps
CPU time 15.21 seconds
Started Jun 21 04:47:21 PM PDT 24
Finished Jun 21 04:47:39 PM PDT 24
Peak memory 200612 kb
Host smart-6cbecf5f-5108-4aec-9a7b-270272657d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952518937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.2952518937
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.3895766557
Short name T506
Test name
Test status
Simulation time 34532060326 ps
CPU time 61.67 seconds
Started Jun 21 04:47:15 PM PDT 24
Finished Jun 21 04:48:19 PM PDT 24
Peak memory 200628 kb
Host smart-5e64ec0b-e7ca-4a6b-8edc-8c08652a14b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895766557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.3895766557
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.1525986162
Short name T707
Test name
Test status
Simulation time 24976287 ps
CPU time 0.62 seconds
Started Jun 21 04:44:42 PM PDT 24
Finished Jun 21 04:44:45 PM PDT 24
Peak memory 195916 kb
Host smart-1865df89-912e-471d-8c90-6540b3def3f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525986162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.1525986162
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.123041195
Short name T1085
Test name
Test status
Simulation time 69305135787 ps
CPU time 76.72 seconds
Started Jun 21 04:44:50 PM PDT 24
Finished Jun 21 04:46:10 PM PDT 24
Peak memory 200660 kb
Host smart-5aaf1d0a-7c5c-44ce-81b1-6a48d4c4e102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123041195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.123041195
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.1249397976
Short name T839
Test name
Test status
Simulation time 103696113333 ps
CPU time 26.55 seconds
Started Jun 21 04:44:45 PM PDT 24
Finished Jun 21 04:45:15 PM PDT 24
Peak memory 200588 kb
Host smart-ccde45fc-dec2-42af-8ea6-86b73acb12f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249397976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.1249397976
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.598690158
Short name T453
Test name
Test status
Simulation time 86961141388 ps
CPU time 78.44 seconds
Started Jun 21 04:44:38 PM PDT 24
Finished Jun 21 04:45:58 PM PDT 24
Peak memory 200624 kb
Host smart-f929e6c9-3ed6-41f7-a9a2-540262451b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598690158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.598690158
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.2661900292
Short name T432
Test name
Test status
Simulation time 62982009057 ps
CPU time 17.05 seconds
Started Jun 21 04:44:39 PM PDT 24
Finished Jun 21 04:44:58 PM PDT 24
Peak memory 200532 kb
Host smart-6fc5bd5e-adff-436c-ac05-6db2bc9dd031
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661900292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.2661900292
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.2160613865
Short name T514
Test name
Test status
Simulation time 120135376904 ps
CPU time 732.3 seconds
Started Jun 21 04:44:44 PM PDT 24
Finished Jun 21 04:56:58 PM PDT 24
Peak memory 200604 kb
Host smart-cf5b5573-5aab-4d89-9dab-0320980bf2d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2160613865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.2160613865
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.1175292671
Short name T968
Test name
Test status
Simulation time 11734816481 ps
CPU time 11.6 seconds
Started Jun 21 04:44:43 PM PDT 24
Finished Jun 21 04:44:56 PM PDT 24
Peak memory 199120 kb
Host smart-4ca7ea27-ad43-47db-a4f1-64e2300ecea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175292671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.1175292671
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.416778714
Short name T415
Test name
Test status
Simulation time 6978416216 ps
CPU time 16.14 seconds
Started Jun 21 04:44:45 PM PDT 24
Finished Jun 21 04:45:05 PM PDT 24
Peak memory 199836 kb
Host smart-c0c1bbb2-fd6e-4a64-8b62-89934e969cbc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=416778714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.416778714
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.2546707286
Short name T254
Test name
Test status
Simulation time 50803511604 ps
CPU time 75.04 seconds
Started Jun 21 04:44:39 PM PDT 24
Finished Jun 21 04:45:57 PM PDT 24
Peak memory 200552 kb
Host smart-6a60e30a-5cbe-480c-a847-a74156ed4792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546707286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.2546707286
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.118134596
Short name T751
Test name
Test status
Simulation time 2019638870 ps
CPU time 3.27 seconds
Started Jun 21 04:44:43 PM PDT 24
Finished Jun 21 04:44:49 PM PDT 24
Peak memory 196060 kb
Host smart-11ed833f-7cb9-4d6d-a962-30f8bc7f0332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118134596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.118134596
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.3558622805
Short name T439
Test name
Test status
Simulation time 713453705 ps
CPU time 1.68 seconds
Started Jun 21 04:44:42 PM PDT 24
Finished Jun 21 04:44:45 PM PDT 24
Peak memory 199272 kb
Host smart-421ef3f6-87e9-4c66-a935-62553a9e8b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558622805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.3558622805
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.204501468
Short name T558
Test name
Test status
Simulation time 38464707738 ps
CPU time 710.71 seconds
Started Jun 21 04:44:45 PM PDT 24
Finished Jun 21 04:56:40 PM PDT 24
Peak memory 217020 kb
Host smart-545ed60d-78ba-4c64-b9e6-fb45f665aaf2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204501468 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.204501468
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.385661640
Short name T464
Test name
Test status
Simulation time 796311810 ps
CPU time 3.74 seconds
Started Jun 21 04:44:46 PM PDT 24
Finished Jun 21 04:44:54 PM PDT 24
Peak memory 199560 kb
Host smart-1d0dbd52-9eea-49e3-8c49-211722d1d77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385661640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.385661640
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.92970706
Short name T527
Test name
Test status
Simulation time 96423005165 ps
CPU time 68.2 seconds
Started Jun 21 04:44:31 PM PDT 24
Finished Jun 21 04:45:41 PM PDT 24
Peak memory 200660 kb
Host smart-4558e5c7-51c2-440f-a378-605c73cdfbb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92970706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.92970706
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.576279727
Short name T1087
Test name
Test status
Simulation time 106010676773 ps
CPU time 38.79 seconds
Started Jun 21 04:47:20 PM PDT 24
Finished Jun 21 04:48:02 PM PDT 24
Peak memory 200608 kb
Host smart-0d7eaa45-864f-4460-814a-92c518641b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576279727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.576279727
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.726425682
Short name T1075
Test name
Test status
Simulation time 43718205155 ps
CPU time 198.09 seconds
Started Jun 21 04:47:14 PM PDT 24
Finished Jun 21 04:50:34 PM PDT 24
Peak memory 208924 kb
Host smart-55733375-2084-4591-b9ea-35248a338c92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726425682 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.726425682
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.3741531836
Short name T960
Test name
Test status
Simulation time 110992975934 ps
CPU time 31.91 seconds
Started Jun 21 04:47:24 PM PDT 24
Finished Jun 21 04:48:02 PM PDT 24
Peak memory 200560 kb
Host smart-162f512b-60b3-4ab4-a497-69b50268c940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741531836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.3741531836
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.3359272306
Short name T411
Test name
Test status
Simulation time 10957322058 ps
CPU time 5.87 seconds
Started Jun 21 04:47:20 PM PDT 24
Finished Jun 21 04:47:28 PM PDT 24
Peak memory 200612 kb
Host smart-1d8e330a-13da-4cfb-923a-7f08a47f7f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359272306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.3359272306
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.1748001016
Short name T970
Test name
Test status
Simulation time 38120471928 ps
CPU time 14.63 seconds
Started Jun 21 04:47:21 PM PDT 24
Finished Jun 21 04:47:40 PM PDT 24
Peak memory 200584 kb
Host smart-5bcb2353-54dd-498e-b207-d2c08a5e48df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748001016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.1748001016
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.2720601824
Short name T835
Test name
Test status
Simulation time 66880536556 ps
CPU time 120.69 seconds
Started Jun 21 04:47:18 PM PDT 24
Finished Jun 21 04:49:20 PM PDT 24
Peak memory 200672 kb
Host smart-5353e43c-5019-4618-b072-e0ac7ece6aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720601824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.2720601824
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.2386073882
Short name T881
Test name
Test status
Simulation time 169261978028 ps
CPU time 306.51 seconds
Started Jun 21 04:47:20 PM PDT 24
Finished Jun 21 04:52:29 PM PDT 24
Peak memory 212232 kb
Host smart-f62ac47d-1cb3-479c-89f6-06b16553d502
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386073882 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.2386073882
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.3617863570
Short name T166
Test name
Test status
Simulation time 15481790103 ps
CPU time 42.64 seconds
Started Jun 21 04:47:15 PM PDT 24
Finished Jun 21 04:47:59 PM PDT 24
Peak memory 200664 kb
Host smart-b3fb74f0-44b9-4b7b-acac-c50108fa446f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617863570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.3617863570
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.148825789
Short name T778
Test name
Test status
Simulation time 62290447290 ps
CPU time 180.11 seconds
Started Jun 21 04:47:19 PM PDT 24
Finished Jun 21 04:50:22 PM PDT 24
Peak memory 216956 kb
Host smart-99d1c49d-3616-4c5f-9390-8e34eb4b3227
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148825789 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.148825789
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.1976985808
Short name T1094
Test name
Test status
Simulation time 41345491512 ps
CPU time 11.05 seconds
Started Jun 21 04:47:28 PM PDT 24
Finished Jun 21 04:47:47 PM PDT 24
Peak memory 200564 kb
Host smart-4e3535dd-5d71-4882-a4ad-61be3371a8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976985808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.1976985808
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.1823100413
Short name T222
Test name
Test status
Simulation time 66793123509 ps
CPU time 286.65 seconds
Started Jun 21 04:47:21 PM PDT 24
Finished Jun 21 04:52:12 PM PDT 24
Peak memory 200632 kb
Host smart-913a2fea-f300-4e17-a2f2-66b813912d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823100413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.1823100413
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.1855224131
Short name T126
Test name
Test status
Simulation time 33723548659 ps
CPU time 534.68 seconds
Started Jun 21 04:47:20 PM PDT 24
Finished Jun 21 04:56:17 PM PDT 24
Peak memory 217092 kb
Host smart-a041fade-e02f-4cb1-b40f-372d29f2635d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855224131 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.1855224131
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.2216795913
Short name T683
Test name
Test status
Simulation time 39817064607 ps
CPU time 16.65 seconds
Started Jun 21 04:47:23 PM PDT 24
Finished Jun 21 04:47:47 PM PDT 24
Peak memory 200664 kb
Host smart-b8bb0ae5-e9ec-49fe-acb1-cb30b44fe002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216795913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.2216795913
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.1029278963
Short name T68
Test name
Test status
Simulation time 133155727991 ps
CPU time 232.79 seconds
Started Jun 21 04:47:21 PM PDT 24
Finished Jun 21 04:51:18 PM PDT 24
Peak memory 216600 kb
Host smart-839d57d4-86d1-431b-836f-4214bec2972b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029278963 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.1029278963
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.3163730905
Short name T483
Test name
Test status
Simulation time 37658763392 ps
CPU time 31.83 seconds
Started Jun 21 04:47:18 PM PDT 24
Finished Jun 21 04:47:51 PM PDT 24
Peak memory 200624 kb
Host smart-c2f3c9b4-58ff-41f7-bc54-8708d2c58142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163730905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.3163730905
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.1224158752
Short name T347
Test name
Test status
Simulation time 72521173 ps
CPU time 0.57 seconds
Started Jun 21 04:44:44 PM PDT 24
Finished Jun 21 04:44:47 PM PDT 24
Peak memory 195016 kb
Host smart-a19db2c7-f938-4825-b7b8-c5b4017aba6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224158752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.1224158752
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.3534080774
Short name T1081
Test name
Test status
Simulation time 116270874262 ps
CPU time 166.13 seconds
Started Jun 21 04:44:30 PM PDT 24
Finished Jun 21 04:47:19 PM PDT 24
Peak memory 200584 kb
Host smart-52c84bbd-49b2-430f-97b0-78e14d3d2b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534080774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.3534080774
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.3807837647
Short name T171
Test name
Test status
Simulation time 18032379955 ps
CPU time 13.56 seconds
Started Jun 21 04:44:39 PM PDT 24
Finished Jun 21 04:44:55 PM PDT 24
Peak memory 200548 kb
Host smart-80d87c98-60db-4e4e-8f55-4000a2c7333e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807837647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.3807837647
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.333488728
Short name T767
Test name
Test status
Simulation time 145549699792 ps
CPU time 124.72 seconds
Started Jun 21 04:44:44 PM PDT 24
Finished Jun 21 04:46:52 PM PDT 24
Peak memory 200568 kb
Host smart-a09fd5c0-0748-4b2e-82ba-0e54eed2da93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333488728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.333488728
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.246721482
Short name T904
Test name
Test status
Simulation time 27127920183 ps
CPU time 25.99 seconds
Started Jun 21 04:44:41 PM PDT 24
Finished Jun 21 04:45:08 PM PDT 24
Peak memory 200564 kb
Host smart-f9701091-cf30-4b48-98ea-e7446bb5d614
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246721482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.246721482
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.1331279970
Short name T248
Test name
Test status
Simulation time 202757763763 ps
CPU time 307.23 seconds
Started Jun 21 04:44:45 PM PDT 24
Finished Jun 21 04:49:56 PM PDT 24
Peak memory 200620 kb
Host smart-e2cc8641-ae0a-41cf-8d77-fe3a89d5296d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1331279970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.1331279970
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.3428053138
Short name T660
Test name
Test status
Simulation time 155309089 ps
CPU time 1.05 seconds
Started Jun 21 04:44:43 PM PDT 24
Finished Jun 21 04:44:46 PM PDT 24
Peak memory 198112 kb
Host smart-199186ce-4903-437d-a916-9180fca0438a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428053138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.3428053138
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_perf.3976296341
Short name T428
Test name
Test status
Simulation time 5829368639 ps
CPU time 71.7 seconds
Started Jun 21 04:44:45 PM PDT 24
Finished Jun 21 04:46:01 PM PDT 24
Peak memory 200544 kb
Host smart-73e509bc-96f8-460c-b761-d8395d3541f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3976296341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.3976296341
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.3611234189
Short name T63
Test name
Test status
Simulation time 2301337996 ps
CPU time 4.63 seconds
Started Jun 21 04:44:42 PM PDT 24
Finished Jun 21 04:44:49 PM PDT 24
Peak memory 199204 kb
Host smart-8e12dc13-f82b-4a1a-a62b-6297d0ab1117
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3611234189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.3611234189
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.3481487681
Short name T964
Test name
Test status
Simulation time 60760584150 ps
CPU time 21.69 seconds
Started Jun 21 04:44:38 PM PDT 24
Finished Jun 21 04:45:01 PM PDT 24
Peak memory 200596 kb
Host smart-831b64ce-fe19-4278-b655-e1bc7bf499b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481487681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.3481487681
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.1789216693
Short name T115
Test name
Test status
Simulation time 1682815082 ps
CPU time 1.8 seconds
Started Jun 21 04:44:45 PM PDT 24
Finished Jun 21 04:44:50 PM PDT 24
Peak memory 196088 kb
Host smart-b7730e72-69e5-4d45-a21c-02f70731a4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789216693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.1789216693
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.3706934557
Short name T274
Test name
Test status
Simulation time 6199625767 ps
CPU time 20.42 seconds
Started Jun 21 04:44:48 PM PDT 24
Finished Jun 21 04:45:13 PM PDT 24
Peak memory 200504 kb
Host smart-6dcb7d0d-1790-4a40-975c-71c97c627bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706934557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.3706934557
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.2486609244
Short name T931
Test name
Test status
Simulation time 1311646111 ps
CPU time 1.78 seconds
Started Jun 21 04:44:45 PM PDT 24
Finished Jun 21 04:44:50 PM PDT 24
Peak memory 199304 kb
Host smart-026c8c1c-2491-4d12-a795-ce9a3e00b53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486609244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.2486609244
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.782545556
Short name T266
Test name
Test status
Simulation time 80768016408 ps
CPU time 87.6 seconds
Started Jun 21 04:44:39 PM PDT 24
Finished Jun 21 04:46:08 PM PDT 24
Peak memory 200620 kb
Host smart-3a21de87-f092-4092-ab2b-1e20a8ca7c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782545556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.782545556
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.2156023032
Short name T243
Test name
Test status
Simulation time 142372868720 ps
CPU time 357.77 seconds
Started Jun 21 04:47:23 PM PDT 24
Finished Jun 21 04:53:28 PM PDT 24
Peak memory 200624 kb
Host smart-bee2b825-2f63-4667-9165-4b2262a72d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156023032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.2156023032
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.1501622034
Short name T231
Test name
Test status
Simulation time 58908696276 ps
CPU time 23.36 seconds
Started Jun 21 04:47:23 PM PDT 24
Finished Jun 21 04:47:51 PM PDT 24
Peak memory 200700 kb
Host smart-a03f015e-5337-4d5d-830b-589488c68697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501622034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.1501622034
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.3587451605
Short name T1084
Test name
Test status
Simulation time 81703228708 ps
CPU time 1037.56 seconds
Started Jun 21 04:47:22 PM PDT 24
Finished Jun 21 05:04:44 PM PDT 24
Peak memory 226592 kb
Host smart-5d5f816d-34b4-49ce-af54-8fdd092ab4d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587451605 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.3587451605
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.1335604195
Short name T903
Test name
Test status
Simulation time 50098575615 ps
CPU time 44.82 seconds
Started Jun 21 04:47:28 PM PDT 24
Finished Jun 21 04:48:21 PM PDT 24
Peak memory 200564 kb
Host smart-774e7302-fb66-4136-866b-4f592ce74c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335604195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.1335604195
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.4121731441
Short name T1005
Test name
Test status
Simulation time 158914793670 ps
CPU time 377.01 seconds
Started Jun 21 04:47:22 PM PDT 24
Finished Jun 21 04:53:44 PM PDT 24
Peak memory 200532 kb
Host smart-85144d31-6981-40d7-aec0-d86efd0eee9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121731441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.4121731441
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.1310953199
Short name T44
Test name
Test status
Simulation time 65973508697 ps
CPU time 542.91 seconds
Started Jun 21 04:47:23 PM PDT 24
Finished Jun 21 04:56:32 PM PDT 24
Peak memory 217116 kb
Host smart-47454828-dac4-4793-b50a-015e3635ad1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310953199 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.1310953199
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.4268114
Short name T197
Test name
Test status
Simulation time 89172823335 ps
CPU time 143.94 seconds
Started Jun 21 04:47:23 PM PDT 24
Finished Jun 21 04:49:52 PM PDT 24
Peak memory 200592 kb
Host smart-b918c160-ab2b-4139-a0bf-7755e1e4aba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.4268114
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.2529290356
Short name T646
Test name
Test status
Simulation time 48568676876 ps
CPU time 83.39 seconds
Started Jun 21 04:47:26 PM PDT 24
Finished Jun 21 04:48:57 PM PDT 24
Peak memory 200624 kb
Host smart-d53c0132-af8a-4f72-9e84-d15b016b1741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529290356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.2529290356
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.3764082150
Short name T180
Test name
Test status
Simulation time 108184617692 ps
CPU time 1527.19 seconds
Started Jun 21 04:47:24 PM PDT 24
Finished Jun 21 05:12:59 PM PDT 24
Peak memory 225256 kb
Host smart-cbf47b49-6057-4a36-8267-cbfd3f2f05b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764082150 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.3764082150
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.1262281651
Short name T564
Test name
Test status
Simulation time 86998092203 ps
CPU time 147.64 seconds
Started Jun 21 04:47:24 PM PDT 24
Finished Jun 21 04:49:59 PM PDT 24
Peak memory 200680 kb
Host smart-ad9f0eeb-bd66-4df3-89c3-8c02e8c36391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262281651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.1262281651
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.2383482250
Short name T246
Test name
Test status
Simulation time 59484588243 ps
CPU time 86.89 seconds
Started Jun 21 04:47:31 PM PDT 24
Finished Jun 21 04:49:06 PM PDT 24
Peak memory 200564 kb
Host smart-6e3cc30c-9aae-401f-a791-30fb84f746d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383482250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.2383482250
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.744263113
Short name T996
Test name
Test status
Simulation time 56052477553 ps
CPU time 459.95 seconds
Started Jun 21 04:47:29 PM PDT 24
Finished Jun 21 04:55:18 PM PDT 24
Peak memory 217016 kb
Host smart-d2a5f3ce-bb12-43dd-a771-2d30c296f45a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744263113 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.744263113
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.2794962837
Short name T241
Test name
Test status
Simulation time 30179067751 ps
CPU time 58.01 seconds
Started Jun 21 04:47:29 PM PDT 24
Finished Jun 21 04:48:36 PM PDT 24
Peak memory 200564 kb
Host smart-27ca68c8-b80c-4d94-90bf-585740629c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794962837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.2794962837
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.656977872
Short name T775
Test name
Test status
Simulation time 22070980868 ps
CPU time 185.39 seconds
Started Jun 21 04:47:26 PM PDT 24
Finished Jun 21 04:50:39 PM PDT 24
Peak memory 217016 kb
Host smart-b911052f-3150-4040-ad64-8a7dca2d96ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656977872 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.656977872
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.2591650618
Short name T316
Test name
Test status
Simulation time 33712698729 ps
CPU time 17.87 seconds
Started Jun 21 04:47:24 PM PDT 24
Finished Jun 21 04:47:48 PM PDT 24
Peak memory 200572 kb
Host smart-e7c473ff-71b6-4ad0-ba55-b1b35d85c141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591650618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.2591650618
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.888222266
Short name T925
Test name
Test status
Simulation time 89799591474 ps
CPU time 1698.06 seconds
Started Jun 21 04:47:27 PM PDT 24
Finished Jun 21 05:15:54 PM PDT 24
Peak memory 225252 kb
Host smart-c93bbed2-446c-4d7b-815f-deb68d10b968
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888222266 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.888222266
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.2231022912
Short name T445
Test name
Test status
Simulation time 42265949 ps
CPU time 0.55 seconds
Started Jun 21 04:44:31 PM PDT 24
Finished Jun 21 04:44:34 PM PDT 24
Peak memory 195972 kb
Host smart-32f51c03-8a17-4c13-9eb7-f484801c57af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231022912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.2231022912
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.3097826493
Short name T330
Test name
Test status
Simulation time 65101873260 ps
CPU time 16.13 seconds
Started Jun 21 04:44:42 PM PDT 24
Finished Jun 21 04:45:00 PM PDT 24
Peak memory 200404 kb
Host smart-ec80178a-cb56-48ec-b5b0-e50e4953ecc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097826493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.3097826493
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.131228459
Short name T664
Test name
Test status
Simulation time 304436662114 ps
CPU time 85.77 seconds
Started Jun 21 04:44:47 PM PDT 24
Finished Jun 21 04:46:17 PM PDT 24
Peak memory 200596 kb
Host smart-7e88d04f-3bc6-4d4b-96d3-24c6c2045d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131228459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.131228459
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.100018970
Short name T618
Test name
Test status
Simulation time 58329769345 ps
CPU time 97 seconds
Started Jun 21 04:44:40 PM PDT 24
Finished Jun 21 04:46:19 PM PDT 24
Peak memory 200556 kb
Host smart-0cb3a8df-0dc7-42e6-8a65-422e4aa06636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100018970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.100018970
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.2785671323
Short name T952
Test name
Test status
Simulation time 48317028371 ps
CPU time 83.74 seconds
Started Jun 21 04:44:48 PM PDT 24
Finished Jun 21 04:46:16 PM PDT 24
Peak memory 200568 kb
Host smart-f15a63a3-410b-4682-bc94-099836230e71
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785671323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.2785671323
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.2927702839
Short name T668
Test name
Test status
Simulation time 64831751114 ps
CPU time 198.78 seconds
Started Jun 21 04:44:55 PM PDT 24
Finished Jun 21 04:48:17 PM PDT 24
Peak memory 200580 kb
Host smart-56c1e442-787d-465c-a1dc-2ed0f021cb24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2927702839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.2927702839
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.1291398643
Short name T1001
Test name
Test status
Simulation time 5365296847 ps
CPU time 9.49 seconds
Started Jun 21 04:44:49 PM PDT 24
Finished Jun 21 04:45:02 PM PDT 24
Peak memory 199616 kb
Host smart-8b5807a1-3ccd-466d-99c5-16c34b43f41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291398643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.1291398643
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_perf.928343709
Short name T869
Test name
Test status
Simulation time 3472611130 ps
CPU time 160.77 seconds
Started Jun 21 04:44:44 PM PDT 24
Finished Jun 21 04:47:28 PM PDT 24
Peak memory 200432 kb
Host smart-06497e5d-8b14-42ff-9895-0f22c936da24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=928343709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.928343709
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.212553856
Short name T31
Test name
Test status
Simulation time 2222936621 ps
CPU time 9.93 seconds
Started Jun 21 04:44:46 PM PDT 24
Finished Jun 21 04:45:00 PM PDT 24
Peak memory 198812 kb
Host smart-3d5bab69-1d07-4925-9d15-82e9d4bf4732
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=212553856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.212553856
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.920626623
Short name T21
Test name
Test status
Simulation time 16203627424 ps
CPU time 26.48 seconds
Started Jun 21 04:44:51 PM PDT 24
Finished Jun 21 04:45:21 PM PDT 24
Peak memory 200616 kb
Host smart-7681ca0c-2db4-4d20-a63f-d75e2e27422f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920626623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.920626623
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.3391923094
Short name T808
Test name
Test status
Simulation time 29466221280 ps
CPU time 45.04 seconds
Started Jun 21 04:44:51 PM PDT 24
Finished Jun 21 04:45:40 PM PDT 24
Peak memory 196632 kb
Host smart-4adb4e51-0ac9-4ab5-88fd-9a523ea0584d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391923094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.3391923094
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.2808735958
Short name T50
Test name
Test status
Simulation time 461063976 ps
CPU time 2.14 seconds
Started Jun 21 04:44:58 PM PDT 24
Finished Jun 21 04:45:03 PM PDT 24
Peak memory 200416 kb
Host smart-43713c67-dd25-4bb8-a0f1-fc63d0dabc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808735958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.2808735958
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.3305619015
Short name T899
Test name
Test status
Simulation time 156259690875 ps
CPU time 240.86 seconds
Started Jun 21 04:44:44 PM PDT 24
Finished Jun 21 04:48:49 PM PDT 24
Peak memory 200508 kb
Host smart-1793d51b-7358-4baa-9506-f3c023b7a3d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305619015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.3305619015
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.1563096002
Short name T1054
Test name
Test status
Simulation time 199817177782 ps
CPU time 224.73 seconds
Started Jun 21 04:44:39 PM PDT 24
Finished Jun 21 04:48:25 PM PDT 24
Peak memory 210500 kb
Host smart-c9e10fe9-40c6-4489-90c6-84fe063dcb3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563096002 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.1563096002
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.3147150620
Short name T531
Test name
Test status
Simulation time 10257349822 ps
CPU time 6.23 seconds
Started Jun 21 04:44:46 PM PDT 24
Finished Jun 21 04:44:56 PM PDT 24
Peak memory 200520 kb
Host smart-915dc7e8-9dc9-4a14-b400-a5520b1085f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147150620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.3147150620
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.1766039194
Short name T826
Test name
Test status
Simulation time 69096466575 ps
CPU time 30.51 seconds
Started Jun 21 04:44:36 PM PDT 24
Finished Jun 21 04:45:08 PM PDT 24
Peak memory 200684 kb
Host smart-1b9ddf6d-00e3-40af-aacb-1bd66bdf5bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766039194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.1766039194
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.189119562
Short name T10
Test name
Test status
Simulation time 173575810773 ps
CPU time 19.5 seconds
Started Jun 21 04:47:26 PM PDT 24
Finished Jun 21 04:47:54 PM PDT 24
Peak memory 200600 kb
Host smart-6931fe6e-81de-481e-8dab-d46275d351e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189119562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.189119562
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.3740055152
Short name T922
Test name
Test status
Simulation time 134279792556 ps
CPU time 378.88 seconds
Started Jun 21 04:47:29 PM PDT 24
Finished Jun 21 04:53:56 PM PDT 24
Peak memory 216764 kb
Host smart-8dd8c4af-7701-4126-9174-c3e048af8dd3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740055152 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.3740055152
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.25902418
Short name T699
Test name
Test status
Simulation time 30359330152 ps
CPU time 35.67 seconds
Started Jun 21 04:47:26 PM PDT 24
Finished Jun 21 04:48:10 PM PDT 24
Peak memory 200600 kb
Host smart-f63dae71-8f94-4c20-8007-9e5d6e1570c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25902418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.25902418
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.3029266627
Short name T1062
Test name
Test status
Simulation time 72479299481 ps
CPU time 199.37 seconds
Started Jun 21 04:47:27 PM PDT 24
Finished Jun 21 04:50:55 PM PDT 24
Peak memory 217028 kb
Host smart-60596449-4e15-4115-ab20-539bb671499e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029266627 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.3029266627
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.2025950514
Short name T157
Test name
Test status
Simulation time 25872578723 ps
CPU time 55.35 seconds
Started Jun 21 04:47:28 PM PDT 24
Finished Jun 21 04:48:31 PM PDT 24
Peak memory 200624 kb
Host smart-112a0cae-509d-46a8-a6b1-ff4d5e012c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025950514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.2025950514
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.3112437307
Short name T1064
Test name
Test status
Simulation time 152954968146 ps
CPU time 148.68 seconds
Started Jun 21 04:47:28 PM PDT 24
Finished Jun 21 04:50:05 PM PDT 24
Peak memory 200800 kb
Host smart-743c5561-9165-4124-b771-a59da248fa68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112437307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.3112437307
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.1135777882
Short name T606
Test name
Test status
Simulation time 23088134891 ps
CPU time 35.05 seconds
Started Jun 21 04:47:29 PM PDT 24
Finished Jun 21 04:48:13 PM PDT 24
Peak memory 200692 kb
Host smart-6df24757-d87b-4645-9e9b-75e5adeeeb37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135777882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.1135777882
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.1404255096
Short name T541
Test name
Test status
Simulation time 28617543097 ps
CPU time 407.97 seconds
Started Jun 21 04:47:26 PM PDT 24
Finished Jun 21 04:54:22 PM PDT 24
Peak memory 216084 kb
Host smart-7f0eb0a3-5fb2-4b2c-8d22-1a445429d092
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404255096 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.1404255096
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.653298415
Short name T385
Test name
Test status
Simulation time 67344490409 ps
CPU time 9.83 seconds
Started Jun 21 04:47:28 PM PDT 24
Finished Jun 21 04:47:47 PM PDT 24
Peak memory 200424 kb
Host smart-4e50dc59-71b9-4b25-8f31-2a92450411da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653298415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.653298415
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.3273396644
Short name T28
Test name
Test status
Simulation time 102262898961 ps
CPU time 594.83 seconds
Started Jun 21 04:47:29 PM PDT 24
Finished Jun 21 04:57:33 PM PDT 24
Peak memory 214316 kb
Host smart-ec4c00ad-b26a-41c7-9826-6f572876e79f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273396644 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.3273396644
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.2964149753
Short name T203
Test name
Test status
Simulation time 35539506572 ps
CPU time 36.48 seconds
Started Jun 21 04:47:28 PM PDT 24
Finished Jun 21 04:48:13 PM PDT 24
Peak memory 200632 kb
Host smart-38bd37f5-f665-41c6-95c9-d4a17e9cdf06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964149753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.2964149753
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.2596499409
Short name T628
Test name
Test status
Simulation time 143857465811 ps
CPU time 434.86 seconds
Started Jun 21 04:47:27 PM PDT 24
Finished Jun 21 04:54:50 PM PDT 24
Peak memory 215408 kb
Host smart-887e8187-61a6-46ee-8b62-7cbf269f7eaa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596499409 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.2596499409
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.3985424302
Short name T1070
Test name
Test status
Simulation time 109480487828 ps
CPU time 175.08 seconds
Started Jun 21 04:47:29 PM PDT 24
Finished Jun 21 04:50:33 PM PDT 24
Peak memory 200588 kb
Host smart-e4623fbf-6644-43fd-8186-14b12db0de7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985424302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.3985424302
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.204940135
Short name T268
Test name
Test status
Simulation time 102806053360 ps
CPU time 33.76 seconds
Started Jun 21 04:47:29 PM PDT 24
Finished Jun 21 04:48:12 PM PDT 24
Peak memory 200544 kb
Host smart-1e78830b-318b-4c09-8128-587dd30756cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204940135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.204940135
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.3791359587
Short name T1063
Test name
Test status
Simulation time 13220371 ps
CPU time 0.54 seconds
Started Jun 21 04:45:00 PM PDT 24
Finished Jun 21 04:45:03 PM PDT 24
Peak memory 195476 kb
Host smart-a655fa1c-cab2-4a57-b407-9aad5a5c2644
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791359587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.3791359587
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.1762304792
Short name T915
Test name
Test status
Simulation time 108444620295 ps
CPU time 45.51 seconds
Started Jun 21 04:44:38 PM PDT 24
Finished Jun 21 04:45:25 PM PDT 24
Peak memory 200560 kb
Host smart-0341269b-7210-490e-80df-b6065ab03a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762304792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.1762304792
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.1333469841
Short name T700
Test name
Test status
Simulation time 58935022953 ps
CPU time 50.24 seconds
Started Jun 21 04:44:55 PM PDT 24
Finished Jun 21 04:45:49 PM PDT 24
Peak memory 199800 kb
Host smart-1ce00bf0-b6e2-46ce-ad27-079688bb3072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333469841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.1333469841
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.1295992069
Short name T813
Test name
Test status
Simulation time 20382288168 ps
CPU time 39.4 seconds
Started Jun 21 04:44:49 PM PDT 24
Finished Jun 21 04:45:32 PM PDT 24
Peak memory 200624 kb
Host smart-bb4cccf8-b12d-4f9e-a866-fb8ebf2716e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295992069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.1295992069
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.3466950409
Short name T806
Test name
Test status
Simulation time 10488118892 ps
CPU time 4.83 seconds
Started Jun 21 04:44:48 PM PDT 24
Finished Jun 21 04:44:57 PM PDT 24
Peak memory 200288 kb
Host smart-29e171c9-38fc-451c-ae9b-71ec7c0c944e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466950409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.3466950409
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.890990195
Short name T838
Test name
Test status
Simulation time 132583126932 ps
CPU time 1363.54 seconds
Started Jun 21 04:44:44 PM PDT 24
Finished Jun 21 05:07:30 PM PDT 24
Peak memory 200524 kb
Host smart-d16353cb-1fff-4e06-b960-40622ed29c6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=890990195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.890990195
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.1173298291
Short name T500
Test name
Test status
Simulation time 1960978578 ps
CPU time 1.32 seconds
Started Jun 21 04:44:44 PM PDT 24
Finished Jun 21 04:44:49 PM PDT 24
Peak memory 196600 kb
Host smart-4733e34a-17da-4b39-b752-9db93eea5b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173298291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.1173298291
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_perf.3607374890
Short name T712
Test name
Test status
Simulation time 20497355489 ps
CPU time 892.6 seconds
Started Jun 21 04:44:46 PM PDT 24
Finished Jun 21 04:59:42 PM PDT 24
Peak memory 200676 kb
Host smart-34a3e98a-08e1-4610-a71b-c151e4884fb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3607374890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.3607374890
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.1966352036
Short name T812
Test name
Test status
Simulation time 4219324615 ps
CPU time 8.37 seconds
Started Jun 21 04:44:51 PM PDT 24
Finished Jun 21 04:45:03 PM PDT 24
Peak memory 199012 kb
Host smart-b397fdd7-a607-4838-9bae-366a890b36a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1966352036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.1966352036
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.24159181
Short name T1082
Test name
Test status
Simulation time 28986953538 ps
CPU time 19.72 seconds
Started Jun 21 04:44:41 PM PDT 24
Finished Jun 21 04:45:02 PM PDT 24
Peak memory 198492 kb
Host smart-05ac0916-e52f-4682-8b22-296a3cb1964f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24159181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.24159181
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.3329173797
Short name T725
Test name
Test status
Simulation time 27252357770 ps
CPU time 39.22 seconds
Started Jun 21 04:44:44 PM PDT 24
Finished Jun 21 04:45:27 PM PDT 24
Peak memory 197416 kb
Host smart-8ddadd67-6a36-464a-893e-dd2d102e4023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329173797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.3329173797
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.1898092012
Short name T272
Test name
Test status
Simulation time 5693000208 ps
CPU time 16.29 seconds
Started Jun 21 04:44:50 PM PDT 24
Finished Jun 21 04:45:10 PM PDT 24
Peak memory 200464 kb
Host smart-0278c598-ffb7-428a-bd2e-00a495e83b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898092012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.1898092012
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.261278973
Short name T789
Test name
Test status
Simulation time 1458640843 ps
CPU time 2.76 seconds
Started Jun 21 04:44:39 PM PDT 24
Finished Jun 21 04:44:44 PM PDT 24
Peak memory 199484 kb
Host smart-793bfc83-0899-47c1-8792-17283a8873f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261278973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.261278973
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.4062713840
Short name T995
Test name
Test status
Simulation time 116038783055 ps
CPU time 65.25 seconds
Started Jun 21 04:44:55 PM PDT 24
Finished Jun 21 04:46:04 PM PDT 24
Peak memory 200668 kb
Host smart-bb2341b9-51c7-442f-a6c7-837eff575759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062713840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.4062713840
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.1101768898
Short name T19
Test name
Test status
Simulation time 159474805781 ps
CPU time 45.79 seconds
Started Jun 21 04:47:20 PM PDT 24
Finished Jun 21 04:48:10 PM PDT 24
Peak memory 200684 kb
Host smart-d0e28e04-0b35-4eb5-809d-6c6bf95b8213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101768898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.1101768898
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.4013653145
Short name T685
Test name
Test status
Simulation time 29427197186 ps
CPU time 598.34 seconds
Started Jun 21 04:47:18 PM PDT 24
Finished Jun 21 04:57:19 PM PDT 24
Peak memory 216044 kb
Host smart-86bbb466-4f2a-4abb-a8a9-66bbe0d405e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013653145 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.4013653145
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.3172802064
Short name T159
Test name
Test status
Simulation time 94682621886 ps
CPU time 14.82 seconds
Started Jun 21 04:47:18 PM PDT 24
Finished Jun 21 04:47:34 PM PDT 24
Peak memory 200176 kb
Host smart-1f51cab4-2a6e-4520-a22d-9fa2989a8b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172802064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.3172802064
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.1569313810
Short name T319
Test name
Test status
Simulation time 360404732473 ps
CPU time 931.14 seconds
Started Jun 21 04:47:17 PM PDT 24
Finished Jun 21 05:02:51 PM PDT 24
Peak memory 217124 kb
Host smart-48712a10-851e-4ad6-926e-54af86560596
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569313810 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.1569313810
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.4009350509
Short name T673
Test name
Test status
Simulation time 6903669984 ps
CPU time 6.47 seconds
Started Jun 21 04:47:23 PM PDT 24
Finished Jun 21 04:47:35 PM PDT 24
Peak memory 200660 kb
Host smart-35c412bc-91ad-4793-9165-575508fbdc7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009350509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.4009350509
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.209486668
Short name T517
Test name
Test status
Simulation time 79795289606 ps
CPU time 183.48 seconds
Started Jun 21 04:47:25 PM PDT 24
Finished Jun 21 04:50:36 PM PDT 24
Peak memory 200568 kb
Host smart-0e9e9e14-8de2-41eb-8ec1-81d33347fbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209486668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.209486668
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.2855333145
Short name T927
Test name
Test status
Simulation time 240307235768 ps
CPU time 103.23 seconds
Started Jun 21 04:47:23 PM PDT 24
Finished Jun 21 04:49:12 PM PDT 24
Peak memory 200524 kb
Host smart-1ce80fc5-49fb-4af8-86ff-9d8dfacf54ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855333145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.2855333145
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.962727034
Short name T877
Test name
Test status
Simulation time 103144264150 ps
CPU time 74.36 seconds
Started Jun 21 04:47:21 PM PDT 24
Finished Jun 21 04:48:40 PM PDT 24
Peak memory 200484 kb
Host smart-0a5c288e-83ac-4f1d-a2cf-8be5cf0c8e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962727034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.962727034
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.330252828
Short name T861
Test name
Test status
Simulation time 29979130157 ps
CPU time 337.58 seconds
Started Jun 21 04:47:26 PM PDT 24
Finished Jun 21 04:53:11 PM PDT 24
Peak memory 215936 kb
Host smart-f7000e8a-b4e1-4d2c-843d-882147d8d1a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330252828 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.330252828
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.1137865991
Short name T875
Test name
Test status
Simulation time 22004895902 ps
CPU time 9.57 seconds
Started Jun 21 04:47:21 PM PDT 24
Finished Jun 21 04:47:36 PM PDT 24
Peak memory 200632 kb
Host smart-a5c81095-b08b-48de-b15b-6cadfe88deaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137865991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.1137865991
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.3125516640
Short name T121
Test name
Test status
Simulation time 75822968884 ps
CPU time 814.35 seconds
Started Jun 21 04:47:23 PM PDT 24
Finished Jun 21 05:01:05 PM PDT 24
Peak memory 216988 kb
Host smart-38ebf45d-d7ed-48d1-91c9-b421fdfe2b8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125516640 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.3125516640
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.2488135823
Short name T688
Test name
Test status
Simulation time 8022112233 ps
CPU time 13.69 seconds
Started Jun 21 04:47:22 PM PDT 24
Finished Jun 21 04:47:40 PM PDT 24
Peak memory 200632 kb
Host smart-42d5fb78-a2b1-426a-860f-73938e6ee222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488135823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.2488135823
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.1260348299
Short name T936
Test name
Test status
Simulation time 95246381632 ps
CPU time 345.33 seconds
Started Jun 21 04:47:26 PM PDT 24
Finished Jun 21 04:53:19 PM PDT 24
Peak memory 217088 kb
Host smart-fc3807a3-7648-4734-aaf7-b0526e651151
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260348299 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.1260348299
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.498697030
Short name T724
Test name
Test status
Simulation time 25635280418 ps
CPU time 46.45 seconds
Started Jun 21 04:47:23 PM PDT 24
Finished Jun 21 04:48:15 PM PDT 24
Peak memory 200584 kb
Host smart-b8af9b4c-516a-4cf2-abf4-b06cc280159b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498697030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.498697030
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.1230407637
Short name T72
Test name
Test status
Simulation time 292315805868 ps
CPU time 638.98 seconds
Started Jun 21 04:47:22 PM PDT 24
Finished Jun 21 04:58:06 PM PDT 24
Peak memory 217044 kb
Host smart-49b1b93a-5e4d-4be5-a372-79d1d82a0ec4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230407637 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.1230407637
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.1468581248
Short name T591
Test name
Test status
Simulation time 51466548975 ps
CPU time 73.85 seconds
Started Jun 21 04:47:24 PM PDT 24
Finished Jun 21 04:48:45 PM PDT 24
Peak memory 200580 kb
Host smart-d7546e6d-3a7d-4627-8334-f38711e7db6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468581248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.1468581248
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.2288269866
Short name T67
Test name
Test status
Simulation time 99713372709 ps
CPU time 1768.96 seconds
Started Jun 21 04:47:22 PM PDT 24
Finished Jun 21 05:16:57 PM PDT 24
Peak memory 216968 kb
Host smart-4dd940b3-78b6-49f1-94cb-50283d25148d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288269866 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.2288269866
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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