Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99609	1			T1	25		T2	58		T3	1
all_values[1]	99609	1			T1	25		T2	58		T3	1
all_values[2]	99609	1			T1	25		T2	58		T3	1
all_values[3]	99609	1			T1	25		T2	58		T3	1
all_values[4]	99609	1			T1	25		T2	58		T3	1
all_values[5]	99609	1			T1	25		T2	58		T3	1
all_values[6]	99609	1			T1	25		T2	58		T3	1
all_values[7]	99609	1			T1	25		T2	58		T3	1
all_values[8]	99609	1			T1	25		T2	58		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

448363

1

T1

163

T2

244

T3

4

auto[1]

448118

1

T1

62

T2

278

T3

5

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

818838

1

T1

165

T2

435

T3

7

auto[1]

77643

1

T1

60

T2

87

T3

2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	31005	1			T5	4		T15	8		T145	2
all_values[0]	auto[0]	auto[1]	19780	1			T1	13		T2	46		T3	1
all_values[0]	auto[1]	auto[0]	29285	1			T2	2		T7	15		T8	25
all_values[0]	auto[1]	auto[1]	19539	1			T1	12		T2	10		T5	2
all_values[1]	auto[0]	auto[0]	50250	1			T1	23		T2	40		T3	1
all_values[1]	auto[0]	auto[1]	1430	1			T1	2		T5	2		T13	6
all_values[1]	auto[1]	auto[0]	46590	1			T2	18		T5	11		T6	6
all_values[1]	auto[1]	auto[1]	1339	1			T146	2		T45	3		T150	6
all_values[2]	auto[0]	auto[0]	45182	1			T1	25		T2	49		T4	1
all_values[2]	auto[0]	auto[1]	2163	1			T2	9		T4	1		T5	5
all_values[2]	auto[1]	auto[0]	50199	1			T3	1		T5	2		T6	6
all_values[2]	auto[1]	auto[1]	2065	1			T6	2		T7	3		T103	2
all_values[3]	auto[0]	auto[0]	52966	1			T1	24		T2	11		T4	2
all_values[3]	auto[0]	auto[1]	257	1			T1	1		T6	1		T13	1
all_values[3]	auto[1]	auto[0]	46105	1			T2	47		T3	1		T5	11
all_values[3]	auto[1]	auto[1]	281	1			T15	1		T27	2		T273	2
all_values[4]	auto[0]	auto[0]	50224	1			T1	18		T2	13		T4	2
all_values[4]	auto[0]	auto[1]	416	1			T1	7		T15	1		T27	2
all_values[4]	auto[1]	auto[0]	48593	1			T2	45		T3	1		T5	20
all_values[4]	auto[1]	auto[1]	376	1			T13	3		T15	2		T27	3
all_values[5]	auto[0]	auto[0]	47381	1			T1	13		T2	42		T3	1
all_values[5]	auto[0]	auto[1]	163	1			T15	3		T35	3		T36	1
all_values[5]	auto[1]	auto[0]	51934	1			T1	12		T2	16		T5	20
all_values[5]	auto[1]	auto[1]	131	1			T15	2		T27	1		T35	2
all_values[6]	auto[0]	auto[0]	49863	1			T1	25		T2	5		T4	2
all_values[6]	auto[0]	auto[1]	128	1			T15	3		T27	1		T35	1
all_values[6]	auto[1]	auto[0]	49487	1			T2	53		T3	1		T5	2
all_values[6]	auto[1]	auto[1]	131	1			T15	2		T27	3		T35	2
all_values[7]	auto[0]	auto[0]	49435	1			T1	12		T2	11		T3	1
all_values[7]	auto[0]	auto[1]	358	1			T2	5		T15	3		T145	1
all_values[7]	auto[1]	auto[0]	49526	1			T1	13		T2	41		T5	2
all_values[7]	auto[1]	auto[1]	290	1			T2	1		T13	3		T15	2
all_values[8]	auto[0]	auto[0]	33847	1			T2	2		T5	7		T8	25
all_values[8]	auto[0]	auto[1]	13515	1			T2	11		T4	2		T5	4
all_values[8]	auto[1]	auto[0]	36966	1			T2	40		T5	2		T6	6
all_values[8]	auto[1]	auto[1]	15281	1			T1	25		T2	5		T3	1