Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg
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Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv



Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 13 0 13 100.00
Crosses 22 0 22 100.00


Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dir 2 0 2 100.00 100 1 1 0
cp_rst_pos 11 0 11 100.00 100 1 1 0


Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
uart_reset_cg_cc 22 0 22 100.00 100 1 1 0


Summary for Variable cp_dir

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_dir

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[UartTx] 2125 1 T1 1 T2 1 T3 1
auto[UartRx] 2125 1 T1 1 T2 1 T3 1



Summary for Variable cp_rst_pos

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 11 0 11 100.00


User Defined Bins for cp_rst_pos

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 3884 1 T1 2 T2 2 T3 2
values[1] 31 1 T28 1 T35 1 T39 1
values[2] 34 1 T36 1 T38 1 T298 1
values[3] 18 1 T27 2 T35 1 T41 1
values[4] 36 1 T27 1 T35 1 T39 1
values[5] 38 1 T28 1 T37 1 T38 1
values[6] 40 1 T36 1 T40 1 T318 1
values[7] 42 1 T25 1 T39 1 T40 2
values[8] 32 1 T37 1 T38 2 T41 1
values[9] 36 1 T28 1 T25 2 T298 1
values[10] 37 1 T27 1 T28 1 T36 1



Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 22 0 22 100.00


Automatically Generated Cross Bins for uart_reset_cg_cc

Bins
cp_dircp_rst_posCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[UartTx] values[0] 1999 1 T1 1 T2 1 T3 1
auto[UartTx] values[1] 9 1 T28 1 T331 1 T346 1
auto[UartTx] values[2] 10 1 T38 1 T298 1 T346 1
auto[UartTx] values[3] 8 1 T27 1 T35 1 T237 1
auto[UartTx] values[4] 7 1 T40 1 T347 2 T348 1
auto[UartTx] values[5] 11 1 T28 1 T41 1 T349 1
auto[UartTx] values[6] 16 1 T350 1 T351 1 T183 1
auto[UartTx] values[7] 15 1 T39 1 T127 1 T237 1
auto[UartTx] values[8] 18 1 T37 1 T318 1 T346 1
auto[UartTx] values[9] 9 1 T237 1 T352 1 T73 2
auto[UartTx] values[10] 15 1 T27 1 T28 1 T36 1
auto[UartRx] values[0] 1885 1 T1 1 T2 1 T3 1
auto[UartRx] values[1] 22 1 T35 1 T39 1 T40 1
auto[UartRx] values[2] 24 1 T36 1 T91 1 T349 1
auto[UartRx] values[3] 10 1 T27 1 T41 1 T69 1
auto[UartRx] values[4] 29 1 T27 1 T35 1 T39 1
auto[UartRx] values[5] 27 1 T37 1 T38 1 T40 1
auto[UartRx] values[6] 24 1 T36 1 T40 1 T318 1
auto[UartRx] values[7] 27 1 T25 1 T40 2 T331 1
auto[UartRx] values[8] 14 1 T38 2 T41 1 T318 1
auto[UartRx] values[9] 27 1 T28 1 T25 2 T298 1
auto[UartRx] values[10] 22 1 T41 1 T318 2 T347 2

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