Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1949	1			T1	1		T2	1		T3	20
auto[BaudRate115200]	1549	1			T2	2		T5	1		T6	1
auto[BaudRate230400]	1602	1			T1	1		T5	1		T8	2
auto[BaudRate128Kbps]	1579	1			T4	1		T5	2		T8	2
auto[BaudRate256Kbps]	1664	1			T2	2		T4	1		T6	1
auto[BaudRate1Mbps]	1448	1			T6	2		T7	3		T8	1
auto[BaudRate1p5Mbps]	1033	1			T2	2		T5	1		T6	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1295	1			T6	6		T7	7		T8	10
freqs[25]	790	1			T3	20		T103	6		T27	15
freqs[48]	595	1			T10	2		T44	6		T150	10
freqs[50]	422	1			T145	7		T47	2		T300	2
freqs[100]	1007	1			T1	2		T2	7		T308	1

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	205	1			T6	1		T8	1		T14	17
auto[BaudRate9600]	freqs[25]	187	1			T3	20		T27	4		T148	1
auto[BaudRate9600]	freqs[48]	95	1			T44	1		T150	1		T302	1
auto[BaudRate9600]	freqs[50]	99	1			T145	1		T300	1		T126	3
auto[BaudRate9600]	freqs[100]	168	1			T1	1		T2	1		T308	1
auto[BaudRate115200]	freqs[24]	184	1			T6	1		T48	2		T282	2
auto[BaudRate115200]	freqs[25]	118	1			T27	2		T45	1		T148	1
auto[BaudRate115200]	freqs[48]	79	1			T150	1		T63	1		T330	1
auto[BaudRate115200]	freqs[50]	45	1			T145	1		T47	1		T300	1
auto[BaudRate115200]	freqs[100]	114	1			T2	2		T50	1		T21	1
auto[BaudRate230400]	freqs[24]	213	1			T8	2		T48	1		T159	2
auto[BaudRate230400]	freqs[25]	98	1			T103	2		T27	3		T45	3
auto[BaudRate230400]	freqs[48]	73	1			T44	1		T150	2		T302	1
auto[BaudRate230400]	freqs[50]	54	1			T145	1		T47	1		T126	2
auto[BaudRate230400]	freqs[100]	130	1			T1	1		T50	4		T21	2
auto[BaudRate128Kbps]	freqs[24]	187	1			T8	2		T48	1		T56	3
auto[BaudRate128Kbps]	freqs[25]	120	1			T103	3		T27	3		T45	1
auto[BaudRate128Kbps]	freqs[48]	89	1			T10	1		T150	2		T25	2
auto[BaudRate128Kbps]	freqs[50]	50	1			T145	1		T126	1		T138	3
auto[BaudRate128Kbps]	freqs[100]	134	1			T21	1		T296	1		T38	1
auto[BaudRate256Kbps]	freqs[24]	175	1			T6	1		T8	1		T48	1
auto[BaudRate256Kbps]	freqs[25]	114	1			T103	1		T45	2		T148	3
auto[BaudRate256Kbps]	freqs[48]	83	1			T44	3		T25	3		T353	4
auto[BaudRate256Kbps]	freqs[50]	48	1			T289	1		T303	1		T237	5
auto[BaudRate256Kbps]	freqs[100]	144	1			T2	2		T50	1		T296	1
auto[BaudRate1Mbps]	freqs[24]	207	1			T6	2		T7	3		T8	1
auto[BaudRate1Mbps]	freqs[25]	111	1			T27	2		T45	1		T148	1
auto[BaudRate1Mbps]	freqs[48]	92	1			T10	1		T44	1		T150	1
auto[BaudRate1Mbps]	freqs[50]	67	1			T145	1		T126	2		T289	1
auto[BaudRate1Mbps]	freqs[100]	145	1			T50	1		T296	1		T139	1
auto[BaudRate1p5Mbps]	freqs[25]	42	1			T27	1		T45	2		T123	1
auto[BaudRate1p5Mbps]	freqs[48]	84	1			T150	3		T25	2		T331	4
auto[BaudRate1p5Mbps]	freqs[50]	59	1			T145	2		T138	1		T289	3
auto[BaudRate1p5Mbps]	freqs[100]	172	1			T2	2		T296	1		T36	2

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded