Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.94	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	8	122	93.85

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	8	122	93.85	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	29347627	1			T1	19		T2	153		T3	1
all_levels[1]	158175	1			T6	1		T7	822		T8	3
all_levels[2]	1985	1			T5	2		T7	15		T8	8
all_levels[3]	896	1			T6	1		T8	10		T50	1
all_levels[4]	596	1			T5	1		T8	3		T103	1
all_levels[5]	414	1			T8	2		T52	1		T27	2
all_levels[6]	355	1			T5	2		T8	3		T9	2
all_levels[7]	284	1			T2	1		T8	3		T103	1
all_levels[8]	267	1			T8	2		T9	1		T103	1
all_levels[9]	227	1			T6	1		T8	1		T103	1
all_levels[10]	194	1			T8	1		T146	1		T51	1
all_levels[11]	176	1			T8	1		T103	1		T15	1
all_levels[12]	151	1			T2	1		T9	1		T148	2
all_levels[13]	132	1			T53	1		T44	1		T46	2
all_levels[14]	123	1			T2	1		T9	1		T44	1
all_levels[15]	104	1			T44	1		T55	3		T148	1
all_levels[16]	93	1			T9	1		T15	1		T46	2
all_levels[17]	119	1			T9	1		T26	4		T52	1
all_levels[18]	102	1			T145	1		T150	2		T157	1
all_levels[19]	91	1			T145	1		T158	1		T28	1
all_levels[20]	74	1			T2	1		T145	1		T158	1
all_levels[21]	64	1			T6	1		T9	2		T50	1
all_levels[22]	52	1			T9	1		T103	1		T15	1
all_levels[23]	48	1			T158	1		T147	1		T159	1
all_levels[24]	62	1			T8	1		T150	1		T55	1
all_levels[25]	42	1			T15	3		T44	1		T55	1
all_levels[26]	56	1			T146	1		T150	2		T158	1
all_levels[27]	52	1			T160	1		T161	2		T37	2
all_levels[28]	39	1			T16	1		T158	1		T162	1
all_levels[29]	46	1			T37	1		T163	1		T40	1
all_levels[30]	40	1			T17	2		T150	1		T157	1
all_levels[31]	33	1			T150	1		T164	4		T165	1
all_levels[32]	28	1			T166	1		T167	2		T168	1
all_levels[33]	28	1			T48	1		T138	1		T63	1
all_levels[34]	23	1			T146	1		T169	2		T170	1
all_levels[35]	22	1			T158	1		T121	2		T138	1
all_levels[36]	28	1			T44	1		T157	1		T171	4
all_levels[37]	26	1			T16	1		T148	1		T163	1
all_levels[38]	20	1			T48	2		T37	1		T153	2
all_levels[39]	26	1			T39	1		T172	1		T173	1
all_levels[40]	17	1			T158	1		T159	1		T138	1
all_levels[41]	20	1			T48	1		T174	1		T171	1
all_levels[42]	15	1			T175	1		T138	1		T166	1
all_levels[43]	6	1			T158	1		T159	1		T176	1
all_levels[44]	17	1			T44	1		T119	1		T159	1
all_levels[45]	11	1			T9	1		T160	1		T177	3
all_levels[46]	6	1			T60	1		T178	1		T179	1
all_levels[47]	12	1			T46	1		T148	1		T180	1
all_levels[48]	14	1			T181	3		T178	1		T182	1
all_levels[49]	8	1			T58	1		T182	1		T183	2
all_levels[50]	14	1			T175	1		T138	3		T184	1
all_levels[51]	5	1			T37	1		T185	1		T186	1
all_levels[52]	12	1			T125	1		T176	1		T187	1
all_levels[53]	11	1			T6	1		T150	1		T188	1
all_levels[54]	5	1			T189	2		T190	1		T191	1
all_levels[55]	10	1			T55	1		T192	1		T193	1
all_levels[56]	4	1			T158	1		T194	1		T71	1
all_levels[57]	12	1			T173	4		T195	1		T196	1
all_levels[58]	9	1			T58	1		T37	1		T197	2
all_levels[59]	13	1			T37	1		T188	1		T198	3
all_levels[60]	19	1			T173	1		T179	1		T129	2
all_levels[61]	6	1			T8	1		T86	1		T199	1
all_levels[62]	8	1			T46	1		T200	3		T201	2
all_levels[63]	7	1			T152	1		T178	1		T188	1
all_levels[64]	80	1			T6	1		T148	2		T160	3

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29508777

1

T2

157

T5

44

T6

21

auto[1]

4484

1

T1

19

T3

1

T5

5

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	8	122	93.85	8

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[43]]	[auto[1]]	0	1	1
[all_levels[46] , all_levels[47]]	[auto[1]]	--	--	2
[all_levels[51] , all_levels[52]]	[auto[1]]	--	--	2
[all_levels[56]]	[auto[1]]	0	1	1
[all_levels[61]]	[auto[1]]	0	1	1
[all_levels[63]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	29343594	1			T2	153		T5	40		T6	15
all_levels[0]	auto[1]	4033	1			T1	19		T3	1		T5	4
all_levels[1]	auto[0]	158094	1			T6	1		T7	822		T8	3
all_levels[1]	auto[1]	81	1			T44	1		T48	4		T147	1
all_levels[2]	auto[0]	1953	1			T5	2		T7	15		T8	8
all_levels[2]	auto[1]	32	1			T202	1		T203	1		T204	2
all_levels[3]	auto[0]	866	1			T6	1		T8	9		T50	1
all_levels[3]	auto[1]	30	1			T8	1		T157	1		T123	1
all_levels[4]	auto[0]	583	1			T5	1		T8	3		T103	1
all_levels[4]	auto[1]	13	1			T205	1		T206	1		T207	1
all_levels[5]	auto[0]	400	1			T8	2		T52	1		T27	2
all_levels[5]	auto[1]	14	1			T167	1		T169	1		T208	2
all_levels[6]	auto[0]	344	1			T5	1		T8	3		T9	2
all_levels[6]	auto[1]	11	1			T5	1		T147	1		T152	2
all_levels[7]	auto[0]	268	1			T2	1		T8	3		T103	1
all_levels[7]	auto[1]	16	1			T51	2		T209	1		T210	1
all_levels[8]	auto[0]	262	1			T8	2		T9	1		T103	1
all_levels[8]	auto[1]	5	1			T211	1		T212	1		T213	2
all_levels[9]	auto[0]	214	1			T6	1		T8	1		T103	1
all_levels[9]	auto[1]	13	1			T214	1		T215	1		T216	1
all_levels[10]	auto[0]	187	1			T8	1		T146	1		T51	1
all_levels[10]	auto[1]	7	1			T217	1		T172	1		T173	1
all_levels[11]	auto[0]	159	1			T8	1		T103	1		T15	1
all_levels[11]	auto[1]	17	1			T174	3		T119	1		T63	1
all_levels[12]	auto[0]	140	1			T2	1		T9	1		T148	2
all_levels[12]	auto[1]	11	1			T121	2		T218	1		T219	2
all_levels[13]	auto[0]	124	1			T53	1		T44	1		T46	2
all_levels[13]	auto[1]	8	1			T181	2		T168	2		T220	1
all_levels[14]	auto[0]	109	1			T2	1		T9	1		T44	1
all_levels[14]	auto[1]	14	1			T69	3		T210	1		T221	1
all_levels[15]	auto[0]	102	1			T44	1		T55	3		T148	1
all_levels[15]	auto[1]	2	1			T133	1		T222	1		-	-
all_levels[16]	auto[0]	87	1			T9	1		T15	1		T46	2
all_levels[16]	auto[1]	6	1			T223	1		T168	1		T206	1
all_levels[17]	auto[0]	101	1			T9	1		T26	1		T52	1
all_levels[17]	auto[1]	18	1			T26	3		T209	2		T223	1
all_levels[18]	auto[0]	91	1			T145	1		T150	2		T157	1
all_levels[18]	auto[1]	11	1			T40	1		T224	1		T225	2
all_levels[19]	auto[0]	84	1			T145	1		T158	1		T28	1
all_levels[19]	auto[1]	7	1			T138	1		T226	2		T227	1
all_levels[20]	auto[0]	62	1			T2	1		T145	1		T158	1
all_levels[20]	auto[1]	12	1			T140	3		T209	1		T228	1
all_levels[21]	auto[0]	54	1			T6	1		T9	2		T50	1
all_levels[21]	auto[1]	10	1			T229	3		T230	2		T212	1
all_levels[22]	auto[0]	50	1			T9	1		T103	1		T15	1
all_levels[22]	auto[1]	2	1			T231	2		-	-		-	-
all_levels[23]	auto[0]	46	1			T158	1		T147	1		T159	1
all_levels[23]	auto[1]	2	1			T232	1		T227	1		-	-
all_levels[24]	auto[0]	56	1			T8	1		T150	1		T55	1
all_levels[24]	auto[1]	6	1			T233	1		T234	2		T235	1
all_levels[25]	auto[0]	41	1			T15	3		T44	1		T55	1
all_levels[25]	auto[1]	1	1			T236	1		-	-		-	-
all_levels[26]	auto[0]	48	1			T146	1		T150	2		T158	1
all_levels[26]	auto[1]	8	1			T237	4		T238	1		T239	1
all_levels[27]	auto[0]	43	1			T160	1		T161	1		T37	2
all_levels[27]	auto[1]	9	1			T161	1		T208	1		T240	1
all_levels[28]	auto[0]	32	1			T16	1		T158	1		T162	1
all_levels[28]	auto[1]	7	1			T241	1		T74	4		T242	2
all_levels[29]	auto[0]	40	1			T37	1		T163	1		T40	1
all_levels[29]	auto[1]	6	1			T243	2		T244	1		T245	1
all_levels[30]	auto[0]	38	1			T17	2		T150	1		T157	1
all_levels[30]	auto[1]	2	1			T246	1		T247	1		-	-
all_levels[31]	auto[0]	29	1			T150	1		T164	2		T165	1
all_levels[31]	auto[1]	4	1			T164	2		T248	1		T249	1
all_levels[32]	auto[0]	23	1			T166	1		T167	2		T168	1
all_levels[32]	auto[1]	5	1			T250	2		T251	2		T252	1
all_levels[33]	auto[0]	25	1			T48	1		T138	1		T63	1
all_levels[33]	auto[1]	3	1			T253	1		T254	1		T255	1
all_levels[34]	auto[0]	20	1			T146	1		T169	1		T170	1
all_levels[34]	auto[1]	3	1			T169	1		T249	2		-	-
all_levels[35]	auto[0]	19	1			T158	1		T121	1		T138	1
all_levels[35]	auto[1]	3	1			T121	1		T256	2		-	-
all_levels[36]	auto[0]	24	1			T44	1		T157	1		T171	3
all_levels[36]	auto[1]	4	1			T171	1		T243	1		T257	1
all_levels[37]	auto[0]	23	1			T16	1		T148	1		T163	1
all_levels[37]	auto[1]	3	1			T258	1		T231	1		T259	1
all_levels[38]	auto[0]	17	1			T48	2		T37	1		T153	1
all_levels[38]	auto[1]	3	1			T153	1		T180	1		T260	1
all_levels[39]	auto[0]	23	1			T39	1		T172	1		T173	1
all_levels[39]	auto[1]	3	1			T261	1		T262	2		-	-
all_levels[40]	auto[0]	15	1			T158	1		T159	1		T138	1
all_levels[40]	auto[1]	2	1			T198	2		-	-		-	-
all_levels[41]	auto[0]	18	1			T48	1		T174	1		T171	1
all_levels[41]	auto[1]	2	1			T253	1		T263	1		-	-
all_levels[42]	auto[0]	14	1			T175	1		T138	1		T166	1
all_levels[42]	auto[1]	1	1			T173	1		-	-		-	-
all_levels[43]	auto[0]	6	1			T158	1		T159	1		T176	1
all_levels[44]	auto[0]	16	1			T44	1		T119	1		T159	1
all_levels[44]	auto[1]	1	1			T264	1		-	-		-	-
all_levels[45]	auto[0]	8	1			T9	1		T160	1		T177	1
all_levels[45]	auto[1]	3	1			T177	2		T265	1		-	-
all_levels[46]	auto[0]	6	1			T60	1		T178	1		T179	1
all_levels[47]	auto[0]	12	1			T46	1		T148	1		T180	1
all_levels[48]	auto[0]	12	1			T181	1		T178	1		T182	1
all_levels[48]	auto[1]	2	1			T181	2		-	-		-	-
all_levels[49]	auto[0]	7	1			T58	1		T182	1		T183	1
all_levels[49]	auto[1]	1	1			T183	1		-	-		-	-
all_levels[50]	auto[0]	11	1			T175	1		T138	2		T184	1
all_levels[50]	auto[1]	3	1			T138	1		T266	1		T267	1
all_levels[51]	auto[0]	5	1			T37	1		T185	1		T186	1
all_levels[52]	auto[0]	12	1			T125	1		T176	1		T187	1
all_levels[53]	auto[0]	10	1			T6	1		T150	1		T188	1
all_levels[53]	auto[1]	1	1			T268	1		-	-		-	-
all_levels[54]	auto[0]	4	1			T189	1		T190	1		T191	1
all_levels[54]	auto[1]	1	1			T189	1		-	-		-	-
all_levels[55]	auto[0]	9	1			T55	1		T192	1		T193	1
all_levels[55]	auto[1]	1	1			T221	1		-	-		-	-
all_levels[56]	auto[0]	4	1			T158	1		T194	1		T71	1
all_levels[57]	auto[0]	9	1			T173	1		T195	1		T196	1
all_levels[57]	auto[1]	3	1			T173	3		-	-		-	-
all_levels[58]	auto[0]	8	1			T58	1		T37	1		T197	1
all_levels[58]	auto[1]	1	1			T197	1		-	-		-	-
all_levels[59]	auto[0]	12	1			T37	1		T188	1		T198	3
all_levels[59]	auto[1]	1	1			T269	1		-	-		-	-
all_levels[60]	auto[0]	13	1			T173	1		T179	1		T129	2
all_levels[60]	auto[1]	6	1			T270	1		T271	5		-	-
all_levels[61]	auto[0]	6	1			T8	1		T86	1		T199	1
all_levels[62]	auto[0]	5	1			T46	1		T200	1		T201	1
all_levels[62]	auto[1]	3	1			T200	2		T201	1		-	-
all_levels[63]	auto[0]	7	1			T152	1		T178	1		T188	1
all_levels[64]	auto[0]	73	1			T6	1		T148	2		T160	3
all_levels[64]	auto[1]	7	1			T270	1		T269	1		T272	1