Group : uart_env_pkg::uart_env_cov::rx_watermark_cg
Summary for Group uart_env_pkg::uart_env_cov::rx_watermark_cg
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables |
8 |
1 |
7 |
87.50 |
Variables for Group uart_env_pkg::uart_env_cov::rx_watermark_cg
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_watermark_lvl |
8 |
1 |
7 |
87.50 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_watermark_lvl
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
1 |
7 |
87.50 |
User Defined Bins for cp_watermark_lvl
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
all_levels[7] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_levels[0] |
1083 |
1 |
|
|
T5 |
2 |
|
T15 |
2 |
|
T146 |
2 |
all_levels[1] |
637 |
1 |
|
|
T21 |
13 |
|
T147 |
4 |
|
T148 |
3 |
all_levels[2] |
365 |
1 |
|
|
T149 |
2 |
|
T28 |
20 |
|
T56 |
1 |
all_levels[3] |
272 |
1 |
|
|
T1 |
2 |
|
T150 |
6 |
|
T151 |
9 |
all_levels[4] |
204 |
1 |
|
|
T15 |
2 |
|
T152 |
2 |
|
T35 |
2 |
all_levels[5] |
157 |
1 |
|
|
T13 |
6 |
|
T153 |
14 |
|
T154 |
4 |
all_levels[6] |
47 |
1 |
|
|
T21 |
6 |
|
T104 |
4 |
|
T35 |
5 |
0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |