Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99609	1			T1	25		T2	58		T3	1
all_pins[1]	99609	1			T1	25		T2	58		T3	1
all_pins[2]	99609	1			T1	25		T2	58		T3	1
all_pins[3]	99609	1			T1	25		T2	58		T3	1
all_pins[4]	99609	1			T1	25		T2	58		T3	1
all_pins[5]	99609	1			T1	25		T2	58		T3	1
all_pins[6]	99609	1			T1	25		T2	58		T3	1
all_pins[7]	99609	1			T1	25		T2	58		T3	1
all_pins[8]	99609	1			T1	25		T2	58		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	856275	1			T1	187		T2	506		T3	8
values[0x1]	40206	1			T1	38		T2	16		T3	1
transitions[0x0=>0x1]	31965	1			T1	25		T2	16		T5	18
transitions[0x1=>0x0]	31755	1			T1	26		T2	16		T3	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	79989	1			T1	13		T2	48		T3	1
all_pins[0]	values[0x1]	19620	1			T1	12		T2	10		T5	2
all_pins[0]	transitions[0x0=>0x1]	19126	1			T1	12		T2	10		T5	2
all_pins[0]	transitions[0x1=>0x0]	845	1			T45	3		T150	6		T148	3
all_pins[1]	values[0x0]	98270	1			T1	25		T2	58		T3	1
all_pins[1]	values[0x1]	1339	1			T146	2		T45	3		T150	6
all_pins[1]	transitions[0x0=>0x1]	1247	1			T146	2		T45	3		T150	3
all_pins[1]	transitions[0x1=>0x0]	2030	1			T6	2		T7	3		T103	2
all_pins[2]	values[0x0]	97487	1			T1	25		T2	58		T3	1
all_pins[2]	values[0x1]	2122	1			T6	2		T7	3		T103	2
all_pins[2]	transitions[0x0=>0x1]	2064	1			T6	2		T7	3		T103	2
all_pins[2]	transitions[0x1=>0x0]	223	1			T15	1		T273	2		T160	1
all_pins[3]	values[0x0]	99328	1			T1	25		T2	58		T3	1
all_pins[3]	values[0x1]	281	1			T15	1		T27	2		T273	2
all_pins[3]	transitions[0x0=>0x1]	244	1			T15	1		T273	2		T160	1
all_pins[3]	transitions[0x1=>0x0]	338	1			T13	3		T15	2		T27	1
all_pins[4]	values[0x0]	99234	1			T1	25		T2	58		T3	1
all_pins[4]	values[0x1]	375	1			T13	3		T15	2		T27	3
all_pins[4]	transitions[0x0=>0x1]	318	1			T13	2		T27	3		T21	10
all_pins[4]	transitions[0x1=>0x0]	123	1			T1	1		T27	1		T151	2
all_pins[5]	values[0x0]	99429	1			T1	24		T2	58		T3	1
all_pins[5]	values[0x1]	180	1			T1	1		T13	1		T15	2
all_pins[5]	transitions[0x0=>0x1]	142	1			T1	1		T13	1		T15	2
all_pins[5]	transitions[0x1=>0x0]	591	1			T16	1		T15	2		T17	2
all_pins[6]	values[0x0]	98980	1			T1	25		T2	58		T3	1
all_pins[6]	values[0x1]	629	1			T16	1		T15	2		T17	2
all_pins[6]	transitions[0x0=>0x1]	590	1			T16	1		T15	1		T26	1
all_pins[6]	transitions[0x1=>0x0]	250	1			T2	1		T13	3		T15	1
all_pins[7]	values[0x0]	99320	1			T1	25		T2	57		T3	1
all_pins[7]	values[0x1]	289	1			T2	1		T13	3		T15	2
all_pins[7]	transitions[0x0=>0x1]	183	1			T2	1		T17	7		T27	1
all_pins[7]	transitions[0x1=>0x0]	15265	1			T1	25		T2	5		T3	1
all_pins[8]	values[0x0]	84238	1			T2	53		T4	2		T5	13
all_pins[8]	values[0x1]	15371	1			T1	25		T2	5		T3	1
all_pins[8]	transitions[0x0=>0x1]	8051	1			T1	12		T2	5		T5	16
all_pins[8]	transitions[0x1=>0x0]	12090	1			T2	10		T5	2		T6	6