Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	6581003	1			T1	18		T2	14		T5	25
all_levels[1]	1647271	1			T2	127		T6	2		T7	13
all_levels[2]	282030	1			T5	1		T7	7		T15	2
all_levels[3]	204246	1			T5	1		T7	14		T103	1
all_levels[4]	199470	1			T2	4		T5	1		T7	19
all_levels[5]	553039	1			T2	1		T7	10		T103	1
all_levels[6]	225271	1			T2	2		T7	15		T103	2
all_levels[7]	466636	1			T7	19		T15	1		T145	1
all_levels[8]	291844	1			T7	12		T15	7		T17	3
all_levels[9]	518517	1			T2	3		T5	2		T7	10
all_levels[10]	192662	1			T7	8		T15	1		T279	3
all_levels[11]	199357	1			T5	1		T7	13		T15	4
all_levels[12]	175501	1			T5	1		T7	9		T15	3
all_levels[13]	259586	1			T2	1		T7	13		T15	9
all_levels[14]	181839	1			T7	13		T9	2		T50	4
all_levels[15]	376856	1			T5	2		T7	10		T8	5
all_levels[16]	390087	1			T7	15		T15	2		T279	5
all_levels[17]	278652	1			T2	1		T5	1		T7	19
all_levels[18]	239464	1			T5	2		T7	11		T279	1
all_levels[19]	192427	1			T5	1		T7	12		T279	4
all_levels[20]	175267	1			T2	1		T7	11		T27	1
all_levels[21]	213537	1			T5	3		T7	15		T16	2
all_levels[22]	424126	1			T7	8		T16	1		T146	1
all_levels[23]	415685	1			T7	12		T9	1		T45	372
all_levels[24]	231903	1			T7	18		T17	1		T45	372
all_levels[25]	219275	1			T6	3		T7	13		T15	2
all_levels[26]	163572	1			T7	11		T8	5		T45	365
all_levels[27]	237267	1			T2	1		T5	1		T7	13
all_levels[28]	173792	1			T7	16		T15	3		T53	1
all_levels[29]	251383	1			T7	7		T52	7		T45	367
all_levels[30]	176672	1			T5	1		T7	14		T9	3
all_levels[31]	668257	1			T5	1		T7	483		T15	2
all_levels[32]	12706412	1			T2	3		T5	2		T6	2

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29508777

1

T2

157

T5

44

T6

21

auto[1]

4129

1

T1

18

T2

1

T5

2

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	6578577	1			T2	14		T5	23		T6	15
all_levels[0]	auto[1]	2426	1			T1	18		T5	2		T8	4
all_levels[1]	auto[0]	1646960	1			T2	127		T6	2		T7	13
all_levels[1]	auto[1]	311	1			T51	1		T284	1		T148	1
all_levels[2]	auto[0]	281999	1			T5	1		T7	7		T15	2
all_levels[2]	auto[1]	31	1			T279	1		T51	2		T218	1
all_levels[3]	auto[0]	204106	1			T5	1		T7	14		T103	1
all_levels[3]	auto[1]	140	1			T51	1		T293	1		T355	16
all_levels[4]	auto[0]	199454	1			T2	4		T5	1		T7	19
all_levels[4]	auto[1]	16	1			T16	1		T291	1		T206	1
all_levels[5]	auto[0]	553003	1			T2	1		T7	10		T103	1
all_levels[5]	auto[1]	36	1			T306	3		T214	1		T233	1
all_levels[6]	auto[0]	225252	1			T2	2		T7	15		T103	2
all_levels[6]	auto[1]	19	1			T172	1		T356	1		T237	1
all_levels[7]	auto[0]	466493	1			T7	19		T15	1		T145	1
all_levels[7]	auto[1]	143	1			T174	1		T126	1		T293	2
all_levels[8]	auto[0]	291822	1			T7	12		T15	7		T17	3
all_levels[8]	auto[1]	22	1			T147	1		T58	1		T138	1
all_levels[9]	auto[0]	518498	1			T2	3		T5	2		T7	10
all_levels[9]	auto[1]	19	1			T140	1		T63	1		T162	2
all_levels[10]	auto[0]	192638	1			T7	8		T15	1		T279	3
all_levels[10]	auto[1]	24	1			T306	4		T209	1		T233	2
all_levels[11]	auto[0]	199344	1			T5	1		T7	13		T15	4
all_levels[11]	auto[1]	13	1			T56	1		T291	1		T208	1
all_levels[12]	auto[0]	175480	1			T5	1		T7	9		T15	3
all_levels[12]	auto[1]	21	1			T357	1		T181	3		T320	2
all_levels[13]	auto[0]	259572	1			T2	1		T7	13		T15	9
all_levels[13]	auto[1]	14	1			T138	1		T358	1		T266	1
all_levels[14]	auto[0]	181810	1			T7	13		T9	2		T50	4
all_levels[14]	auto[1]	29	1			T44	2		T149	1		T58	1
all_levels[15]	auto[0]	376760	1			T5	2		T7	10		T8	2
all_levels[15]	auto[1]	96	1			T8	3		T44	1		T162	2
all_levels[16]	auto[0]	390054	1			T7	15		T15	2		T279	5
all_levels[16]	auto[1]	33	1			T126	1		T345	1		T356	1
all_levels[17]	auto[0]	278616	1			T2	1		T5	1		T7	19
all_levels[17]	auto[1]	36	1			T202	1		T281	2		T223	2
all_levels[18]	auto[0]	239437	1			T5	2		T7	11		T279	1
all_levels[18]	auto[1]	27	1			T273	1		T121	2		T228	1
all_levels[19]	auto[0]	192413	1			T5	1		T7	12		T279	4
all_levels[19]	auto[1]	14	1			T281	1		T358	1		T240	3
all_levels[20]	auto[0]	175259	1			T2	1		T7	11		T27	1
all_levels[20]	auto[1]	8	1			T240	1		T299	1		T201	1
all_levels[21]	auto[0]	213521	1			T5	3		T7	15		T16	1
all_levels[21]	auto[1]	16	1			T16	1		T359	1		T179	1
all_levels[22]	auto[0]	424110	1			T7	8		T16	1		T146	1
all_levels[22]	auto[1]	16	1			T277	1		T338	1		T171	1
all_levels[23]	auto[0]	415670	1			T7	12		T9	1		T45	372
all_levels[23]	auto[1]	15	1			T138	2		T243	1		T360	1
all_levels[24]	auto[0]	231883	1			T7	18		T17	1		T45	372
all_levels[24]	auto[1]	20	1			T234	2		T361	3		T362	3
all_levels[25]	auto[0]	219250	1			T6	2		T7	13		T15	2
all_levels[25]	auto[1]	25	1			T6	1		T291	1		T217	1
all_levels[26]	auto[0]	163558	1			T7	11		T8	4		T45	365
all_levels[26]	auto[1]	14	1			T8	1		T363	1		T364	1
all_levels[27]	auto[0]	237249	1			T2	1		T5	1		T7	13
all_levels[27]	auto[1]	18	1			T9	2		T122	1		T205	1
all_levels[28]	auto[0]	173780	1			T7	16		T15	3		T53	1
all_levels[28]	auto[1]	12	1			T164	2		T303	1		T365	1
all_levels[29]	auto[0]	251367	1			T7	7		T52	7		T45	367
all_levels[29]	auto[1]	16	1			T124	1		T37	1		T238	1
all_levels[30]	auto[0]	176660	1			T5	1		T7	14		T9	3
all_levels[30]	auto[1]	12	1			T56	1		T205	1		T232	1
all_levels[31]	auto[0]	668243	1			T5	1		T7	483		T15	2
all_levels[31]	auto[1]	14	1			T45	1		T297	1		T180	1
all_levels[32]	auto[0]	12705939	1			T2	2		T5	2		T6	2
all_levels[32]	auto[1]	473	1			T2	1		T8	1		T9	2