Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	642	1			T15	8		T27	7		T35	7
all_values[1]	642	1			T15	8		T27	7		T35	7
all_values[2]	642	1			T15	8		T27	7		T35	7
all_values[3]	642	1			T15	8		T27	7		T35	7
all_values[4]	642	1			T15	8		T27	7		T35	7
all_values[5]	642	1			T15	8		T27	7		T35	7
all_values[6]	642	1			T15	8		T27	7		T35	7
all_values[7]	642	1			T15	8		T27	7		T35	7
all_values[8]	642	1			T15	8		T27	7		T35	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3089

1

T15

41

T27

31

T35

29

auto[1]

2689

1

T15

31

T27

32

T35

34

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2038

1

T15

29

T27

21

T35

19

auto[1]

3740

1

T15

43

T27

42

T35

44

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3501

1

T15

47

T27

35

T35

39

auto[1]

2277

1

T15

25

T27

28

T35

24

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	199	1			T15	3		T27	1		T35	3
all_values[0]	auto[0]	auto[1]	auto[1]	178	1			T15	2		T27	1		T35	2
all_values[0]	auto[1]	auto[0]	auto[1]	160	1			T15	1		T27	3		T35	1
all_values[0]	auto[1]	auto[1]	auto[1]	105	1			T15	2		T27	2		T35	1
all_values[1]	auto[0]	auto[0]	auto[0]	224	1			T15	5		T27	4		T35	2
all_values[1]	auto[0]	auto[1]	auto[0]	189	1			T15	1		T27	2		T36	3
all_values[1]	auto[1]	auto[0]	auto[1]	128	1			T15	1		T27	1		T35	1
all_values[1]	auto[1]	auto[1]	auto[1]	101	1			T15	1		T35	4		T36	3
all_values[2]	auto[0]	auto[0]	auto[0]	146	1			T15	4		T35	1		T36	3
all_values[2]	auto[0]	auto[0]	auto[1]	72	1			T15	2		T27	1		T35	1
all_values[2]	auto[0]	auto[1]	auto[0]	120	1			T15	1		T35	3		T36	1
all_values[2]	auto[0]	auto[1]	auto[1]	62	1			T27	3		T36	1		T40	2
all_values[2]	auto[1]	auto[0]	auto[1]	137	1			T15	1		T27	2		T35	1
all_values[2]	auto[1]	auto[1]	auto[1]	105	1			T27	1		T35	1		T36	3
all_values[3]	auto[0]	auto[0]	auto[0]	132	1			T15	1		T27	2		T35	3
all_values[3]	auto[0]	auto[0]	auto[1]	57	1			T15	1		T35	1		T36	1
all_values[3]	auto[0]	auto[1]	auto[0]	125	1			T15	4		T27	3		T35	1
all_values[3]	auto[0]	auto[1]	auto[1]	74	1			T15	1		T27	1		T36	2
all_values[3]	auto[1]	auto[0]	auto[1]	134	1			T39	3		T40	4		T62	4
all_values[3]	auto[1]	auto[1]	auto[1]	120	1			T15	1		T27	1		T35	2
all_values[4]	auto[0]	auto[0]	auto[0]	166	1			T15	4		T27	1		T35	2
all_values[4]	auto[0]	auto[0]	auto[1]	40	1			T36	3		T40	2		T62	1
all_values[4]	auto[0]	auto[1]	auto[0]	108	1			T15	1		T35	2		T40	1
all_values[4]	auto[0]	auto[1]	auto[1]	66	1			T15	1		T27	1		T35	1
all_values[4]	auto[1]	auto[0]	auto[1]	123	1			T27	2		T35	1		T36	4
all_values[4]	auto[1]	auto[1]	auto[1]	139	1			T15	2		T27	3		T35	1
all_values[5]	auto[0]	auto[0]	auto[0]	134	1			T15	2		T27	5		T36	4
all_values[5]	auto[0]	auto[0]	auto[1]	71	1			T15	1		T35	1		T40	3
all_values[5]	auto[0]	auto[1]	auto[0]	126	1			T35	1		T36	1		T40	3
all_values[5]	auto[0]	auto[1]	auto[1]	68	1			T15	1		T35	2		T36	2
all_values[5]	auto[1]	auto[0]	auto[1]	139	1			T15	3		T35	2		T36	2
all_values[5]	auto[1]	auto[1]	auto[1]	104	1			T15	1		T27	2		T35	1
all_values[6]	auto[0]	auto[0]	auto[0]	155	1			T15	2		T27	1		T35	1
all_values[6]	auto[0]	auto[0]	auto[1]	56	1			T15	1		T40	1		T62	1
all_values[6]	auto[0]	auto[1]	auto[0]	132	1			T35	2		T40	3		T62	2
all_values[6]	auto[0]	auto[1]	auto[1]	51	1			T27	2		T35	1		T36	1
all_values[6]	auto[1]	auto[0]	auto[1]	134	1			T15	2		T27	2		T35	1
all_values[6]	auto[1]	auto[1]	auto[1]	114	1			T15	3		T27	2		T35	2
all_values[7]	auto[0]	auto[0]	auto[0]	176	1			T15	3		T27	1		T35	1
all_values[7]	auto[0]	auto[0]	auto[1]	51	1			T35	2		T36	2		T40	2
all_values[7]	auto[0]	auto[1]	auto[0]	105	1			T15	1		T27	2		T36	1
all_values[7]	auto[0]	auto[1]	auto[1]	55	1			T27	1		T35	1		T36	1
all_values[7]	auto[1]	auto[0]	auto[1]	133	1			T15	1		T27	2		T35	2
all_values[7]	auto[1]	auto[1]	auto[1]	122	1			T15	3		T27	1		T35	1
all_values[8]	auto[0]	auto[0]	auto[1]	168	1			T15	2		T27	1		T35	2
all_values[8]	auto[0]	auto[1]	auto[1]	195	1			T15	3		T27	2		T35	3
all_values[8]	auto[1]	auto[0]	auto[1]	154	1			T15	1		T27	2		T36	2
all_values[8]	auto[1]	auto[1]	auto[1]	125	1			T15	2		T27	2		T35	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal