Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.12 99.10 97.65 100.00 98.38 100.00 99.59


Total test records in report: 1224
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T1038 /workspace/coverage/default/71.uart_stress_all_with_rand_reset.1150458953 Jun 22 04:30:06 PM PDT 24 Jun 22 04:32:12 PM PDT 24 36693399560 ps
T1039 /workspace/coverage/default/49.uart_smoke.563550728 Jun 22 04:30:05 PM PDT 24 Jun 22 04:30:07 PM PDT 24 501023784 ps
T1040 /workspace/coverage/default/7.uart_intr.3774561273 Jun 22 04:28:02 PM PDT 24 Jun 22 04:28:11 PM PDT 24 17662727685 ps
T265 /workspace/coverage/default/248.uart_fifo_reset.2998965604 Jun 22 04:30:43 PM PDT 24 Jun 22 04:31:13 PM PDT 24 173589818879 ps
T1041 /workspace/coverage/default/35.uart_rx_start_bit_filter.1469923403 Jun 22 04:29:34 PM PDT 24 Jun 22 04:29:44 PM PDT 24 5546144741 ps
T1042 /workspace/coverage/default/8.uart_stress_all_with_rand_reset.1536774452 Jun 22 04:28:11 PM PDT 24 Jun 22 04:37:27 PM PDT 24 49283449808 ps
T1043 /workspace/coverage/default/34.uart_perf.3659868254 Jun 22 04:29:29 PM PDT 24 Jun 22 04:48:31 PM PDT 24 20302199884 ps
T1044 /workspace/coverage/default/23.uart_fifo_full.2779181616 Jun 22 04:28:43 PM PDT 24 Jun 22 04:30:48 PM PDT 24 256195023189 ps
T1045 /workspace/coverage/default/37.uart_tx_rx.3297807274 Jun 22 04:29:23 PM PDT 24 Jun 22 04:29:41 PM PDT 24 38051877470 ps
T1046 /workspace/coverage/default/45.uart_perf.964176969 Jun 22 04:29:46 PM PDT 24 Jun 22 04:30:31 PM PDT 24 3086525719 ps
T1047 /workspace/coverage/default/13.uart_smoke.2135613534 Jun 22 04:28:14 PM PDT 24 Jun 22 04:28:17 PM PDT 24 727951153 ps
T1048 /workspace/coverage/default/47.uart_smoke.2695148750 Jun 22 04:29:51 PM PDT 24 Jun 22 04:29:55 PM PDT 24 947016778 ps
T1049 /workspace/coverage/default/41.uart_perf.2699142857 Jun 22 04:29:37 PM PDT 24 Jun 22 04:33:22 PM PDT 24 14931667707 ps
T1050 /workspace/coverage/default/29.uart_perf.2182618635 Jun 22 04:29:00 PM PDT 24 Jun 22 04:47:09 PM PDT 24 20302697383 ps
T1051 /workspace/coverage/default/45.uart_noise_filter.1067768275 Jun 22 04:29:45 PM PDT 24 Jun 22 04:29:56 PM PDT 24 25555946908 ps
T1052 /workspace/coverage/default/2.uart_smoke.4289421212 Jun 22 04:27:57 PM PDT 24 Jun 22 04:27:59 PM PDT 24 652287344 ps
T1053 /workspace/coverage/default/286.uart_fifo_reset.2109510398 Jun 22 04:30:51 PM PDT 24 Jun 22 04:31:10 PM PDT 24 12764539767 ps
T1054 /workspace/coverage/default/156.uart_fifo_reset.984911612 Jun 22 04:30:32 PM PDT 24 Jun 22 04:31:00 PM PDT 24 37422366656 ps
T1055 /workspace/coverage/default/40.uart_loopback.1993507393 Jun 22 04:29:35 PM PDT 24 Jun 22 04:29:38 PM PDT 24 1282007432 ps
T1056 /workspace/coverage/default/13.uart_rx_start_bit_filter.287206184 Jun 22 04:28:14 PM PDT 24 Jun 22 04:28:39 PM PDT 24 32879415244 ps
T1057 /workspace/coverage/default/192.uart_fifo_reset.127224778 Jun 22 04:30:35 PM PDT 24 Jun 22 04:31:39 PM PDT 24 170679889244 ps
T255 /workspace/coverage/default/190.uart_fifo_reset.2119766150 Jun 22 04:30:47 PM PDT 24 Jun 22 04:31:21 PM PDT 24 46926746901 ps
T1058 /workspace/coverage/default/14.uart_rx_oversample.78568135 Jun 22 04:28:33 PM PDT 24 Jun 22 04:29:34 PM PDT 24 6829197055 ps
T1059 /workspace/coverage/default/44.uart_tx_rx.3982932493 Jun 22 04:29:44 PM PDT 24 Jun 22 04:30:13 PM PDT 24 76219726408 ps
T1060 /workspace/coverage/default/11.uart_intr.3213896376 Jun 22 04:28:16 PM PDT 24 Jun 22 04:30:05 PM PDT 24 216992824206 ps
T252 /workspace/coverage/default/204.uart_fifo_reset.747059844 Jun 22 04:30:47 PM PDT 24 Jun 22 04:32:07 PM PDT 24 113002991296 ps
T1061 /workspace/coverage/default/5.uart_loopback.990132739 Jun 22 04:27:58 PM PDT 24 Jun 22 04:28:06 PM PDT 24 4470628457 ps
T1062 /workspace/coverage/default/13.uart_stress_all.832681463 Jun 22 04:28:34 PM PDT 24 Jun 22 04:29:53 PM PDT 24 165674716606 ps
T1063 /workspace/coverage/default/98.uart_fifo_reset.3614200997 Jun 22 04:30:14 PM PDT 24 Jun 22 04:31:19 PM PDT 24 33234081188 ps
T1064 /workspace/coverage/default/36.uart_stress_all.721750520 Jun 22 04:29:20 PM PDT 24 Jun 22 04:31:32 PM PDT 24 244066423780 ps
T1065 /workspace/coverage/default/34.uart_fifo_full.2599650665 Jun 22 04:29:24 PM PDT 24 Jun 22 04:29:41 PM PDT 24 38582927390 ps
T1066 /workspace/coverage/default/28.uart_fifo_reset.1478179975 Jun 22 04:29:11 PM PDT 24 Jun 22 04:29:27 PM PDT 24 67501002149 ps
T1067 /workspace/coverage/default/71.uart_fifo_reset.2833619554 Jun 22 04:30:09 PM PDT 24 Jun 22 04:30:40 PM PDT 24 17332417970 ps
T1068 /workspace/coverage/default/0.uart_perf.264490678 Jun 22 04:28:00 PM PDT 24 Jun 22 04:30:01 PM PDT 24 4679649594 ps
T1069 /workspace/coverage/default/273.uart_fifo_reset.1672914285 Jun 22 04:30:50 PM PDT 24 Jun 22 04:34:50 PM PDT 24 81499017808 ps
T1070 /workspace/coverage/default/31.uart_rx_oversample.4267370956 Jun 22 04:29:11 PM PDT 24 Jun 22 04:29:31 PM PDT 24 2649520167 ps
T1071 /workspace/coverage/default/20.uart_tx_ovrd.3445868253 Jun 22 04:28:30 PM PDT 24 Jun 22 04:28:32 PM PDT 24 2313697506 ps
T1072 /workspace/coverage/default/38.uart_long_xfer_wo_dly.3708330900 Jun 22 04:29:46 PM PDT 24 Jun 22 04:35:01 PM PDT 24 71819407321 ps
T1073 /workspace/coverage/default/42.uart_smoke.3716966403 Jun 22 04:29:41 PM PDT 24 Jun 22 04:29:43 PM PDT 24 305729383 ps
T1074 /workspace/coverage/default/37.uart_fifo_reset.2293660294 Jun 22 04:29:44 PM PDT 24 Jun 22 04:29:57 PM PDT 24 102152007403 ps
T1075 /workspace/coverage/default/4.uart_intr.2956818944 Jun 22 04:27:59 PM PDT 24 Jun 22 04:28:56 PM PDT 24 105579073027 ps
T1076 /workspace/coverage/default/11.uart_loopback.562251856 Jun 22 04:28:13 PM PDT 24 Jun 22 04:28:16 PM PDT 24 1479062214 ps
T1077 /workspace/coverage/default/144.uart_fifo_reset.4153399936 Jun 22 04:30:35 PM PDT 24 Jun 22 04:32:24 PM PDT 24 234777238352 ps
T1078 /workspace/coverage/default/48.uart_long_xfer_wo_dly.715959811 Jun 22 04:29:52 PM PDT 24 Jun 22 04:46:43 PM PDT 24 93295252517 ps
T1079 /workspace/coverage/default/38.uart_fifo_full.1497191706 Jun 22 04:29:33 PM PDT 24 Jun 22 04:30:57 PM PDT 24 100431374450 ps
T1080 /workspace/coverage/default/17.uart_rx_parity_err.3465313620 Jun 22 04:28:37 PM PDT 24 Jun 22 04:29:05 PM PDT 24 32183522888 ps
T1081 /workspace/coverage/default/12.uart_alert_test.1221884766 Jun 22 04:28:17 PM PDT 24 Jun 22 04:28:18 PM PDT 24 39568717 ps
T1082 /workspace/coverage/default/16.uart_rx_parity_err.1985079272 Jun 22 04:28:50 PM PDT 24 Jun 22 04:29:41 PM PDT 24 143611238307 ps
T1083 /workspace/coverage/default/33.uart_fifo_full.749716629 Jun 22 04:29:27 PM PDT 24 Jun 22 04:29:48 PM PDT 24 53261807019 ps
T1084 /workspace/coverage/default/22.uart_loopback.1465940079 Jun 22 04:28:50 PM PDT 24 Jun 22 04:28:52 PM PDT 24 777369575 ps
T1085 /workspace/coverage/default/19.uart_loopback.2265793204 Jun 22 04:28:50 PM PDT 24 Jun 22 04:28:52 PM PDT 24 1001991278 ps
T242 /workspace/coverage/default/195.uart_fifo_reset.2049946913 Jun 22 04:30:38 PM PDT 24 Jun 22 04:31:18 PM PDT 24 27838805777 ps
T75 /workspace/coverage/default/47.uart_stress_all_with_rand_reset.2375218064 Jun 22 04:29:52 PM PDT 24 Jun 22 04:33:15 PM PDT 24 50942742679 ps
T1086 /workspace/coverage/default/4.uart_loopback.998343802 Jun 22 04:27:59 PM PDT 24 Jun 22 04:28:13 PM PDT 24 6231447282 ps
T1087 /workspace/coverage/default/17.uart_rx_start_bit_filter.3072974503 Jun 22 04:28:25 PM PDT 24 Jun 22 04:28:27 PM PDT 24 682524625 ps
T1088 /workspace/coverage/default/14.uart_tx_ovrd.1310155638 Jun 22 04:28:36 PM PDT 24 Jun 22 04:28:40 PM PDT 24 1381281131 ps
T1089 /workspace/coverage/default/294.uart_fifo_reset.4231164798 Jun 22 04:31:01 PM PDT 24 Jun 22 04:31:42 PM PDT 24 42420097615 ps
T1090 /workspace/coverage/default/215.uart_fifo_reset.886445549 Jun 22 04:30:44 PM PDT 24 Jun 22 04:31:00 PM PDT 24 10307897158 ps
T1091 /workspace/coverage/default/34.uart_rx_oversample.1408701382 Jun 22 04:29:13 PM PDT 24 Jun 22 04:29:24 PM PDT 24 5450049002 ps
T1092 /workspace/coverage/cover_reg_top/14.uart_intr_test.1751629222 Jun 22 04:22:13 PM PDT 24 Jun 22 04:22:14 PM PDT 24 36722527 ps
T1093 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3098075916 Jun 22 04:17:38 PM PDT 24 Jun 22 04:17:39 PM PDT 24 40436998 ps
T1094 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3111649903 Jun 22 04:22:13 PM PDT 24 Jun 22 04:22:14 PM PDT 24 24690083 ps
T76 /workspace/coverage/cover_reg_top/17.uart_csr_rw.597072248 Jun 22 04:22:53 PM PDT 24 Jun 22 04:22:54 PM PDT 24 22311049 ps
T94 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3295422549 Jun 22 04:20:13 PM PDT 24 Jun 22 04:20:15 PM PDT 24 35077951 ps
T1095 /workspace/coverage/cover_reg_top/12.uart_intr_test.4219600565 Jun 22 04:18:55 PM PDT 24 Jun 22 04:18:56 PM PDT 24 44071464 ps
T1096 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.379355777 Jun 22 04:18:01 PM PDT 24 Jun 22 04:18:03 PM PDT 24 40304163 ps
T1097 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.583839801 Jun 22 04:17:58 PM PDT 24 Jun 22 04:18:00 PM PDT 24 20496454 ps
T1098 /workspace/coverage/cover_reg_top/17.uart_intr_test.1082677441 Jun 22 04:22:24 PM PDT 24 Jun 22 04:22:25 PM PDT 24 11312211 ps
T95 /workspace/coverage/cover_reg_top/2.uart_csr_rw.2177604733 Jun 22 04:18:11 PM PDT 24 Jun 22 04:18:12 PM PDT 24 17947101 ps
T1099 /workspace/coverage/cover_reg_top/21.uart_intr_test.494207488 Jun 22 04:20:36 PM PDT 24 Jun 22 04:20:37 PM PDT 24 63297625 ps
T1100 /workspace/coverage/cover_reg_top/0.uart_tl_errors.3076833994 Jun 22 04:18:01 PM PDT 24 Jun 22 04:18:04 PM PDT 24 481244210 ps
T105 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.4238558046 Jun 22 04:22:24 PM PDT 24 Jun 22 04:22:26 PM PDT 24 444667927 ps
T1101 /workspace/coverage/cover_reg_top/20.uart_intr_test.801968017 Jun 22 04:20:14 PM PDT 24 Jun 22 04:20:15 PM PDT 24 12254883 ps
T77 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.3556823237 Jun 22 04:22:35 PM PDT 24 Jun 22 04:22:36 PM PDT 24 24344561 ps
T1102 /workspace/coverage/cover_reg_top/11.uart_tl_errors.4061482949 Jun 22 04:20:13 PM PDT 24 Jun 22 04:20:15 PM PDT 24 156354700 ps
T106 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.2621461058 Jun 22 04:19:04 PM PDT 24 Jun 22 04:19:05 PM PDT 24 40023919 ps
T1103 /workspace/coverage/cover_reg_top/7.uart_tl_errors.4152488784 Jun 22 04:18:33 PM PDT 24 Jun 22 04:18:35 PM PDT 24 68871049 ps
T1104 /workspace/coverage/cover_reg_top/15.uart_intr_test.1242906255 Jun 22 04:22:47 PM PDT 24 Jun 22 04:22:47 PM PDT 24 31064748 ps
T1105 /workspace/coverage/cover_reg_top/35.uart_intr_test.1083109969 Jun 22 04:23:08 PM PDT 24 Jun 22 04:23:10 PM PDT 24 23282743 ps
T1106 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.752210679 Jun 22 04:18:01 PM PDT 24 Jun 22 04:18:03 PM PDT 24 57991866 ps
T78 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.2521713312 Jun 22 04:17:58 PM PDT 24 Jun 22 04:18:00 PM PDT 24 123806661 ps
T96 /workspace/coverage/cover_reg_top/3.uart_csr_rw.2287094717 Jun 22 04:17:42 PM PDT 24 Jun 22 04:17:43 PM PDT 24 15233303 ps
T107 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.2537589688 Jun 22 04:20:59 PM PDT 24 Jun 22 04:21:01 PM PDT 24 97846653 ps
T97 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.988503585 Jun 22 04:17:39 PM PDT 24 Jun 22 04:17:40 PM PDT 24 24179202 ps
T98 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3882621014 Jun 22 04:23:08 PM PDT 24 Jun 22 04:23:10 PM PDT 24 19048972 ps
T1107 /workspace/coverage/cover_reg_top/2.uart_tl_errors.2850939177 Jun 22 04:18:04 PM PDT 24 Jun 22 04:18:05 PM PDT 24 437295314 ps
T1108 /workspace/coverage/cover_reg_top/6.uart_tl_errors.2055350693 Jun 22 04:17:58 PM PDT 24 Jun 22 04:18:00 PM PDT 24 26706488 ps
T1109 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.1898890815 Jun 22 04:18:13 PM PDT 24 Jun 22 04:18:14 PM PDT 24 49850535 ps
T1110 /workspace/coverage/cover_reg_top/45.uart_intr_test.1561307782 Jun 22 04:19:21 PM PDT 24 Jun 22 04:19:22 PM PDT 24 23234200 ps
T99 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1758970183 Jun 22 04:18:30 PM PDT 24 Jun 22 04:18:31 PM PDT 24 99367699 ps
T1111 /workspace/coverage/cover_reg_top/13.uart_intr_test.415934953 Jun 22 04:22:25 PM PDT 24 Jun 22 04:22:26 PM PDT 24 15299657 ps
T1112 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.4163430583 Jun 22 04:18:31 PM PDT 24 Jun 22 04:18:32 PM PDT 24 158466125 ps
T1113 /workspace/coverage/cover_reg_top/9.uart_tl_errors.4127773862 Jun 22 04:17:36 PM PDT 24 Jun 22 04:17:38 PM PDT 24 111341535 ps
T1114 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.47839120 Jun 22 04:21:01 PM PDT 24 Jun 22 04:21:03 PM PDT 24 103973803 ps
T100 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2314045441 Jun 22 04:22:39 PM PDT 24 Jun 22 04:22:40 PM PDT 24 55598714 ps
T1115 /workspace/coverage/cover_reg_top/46.uart_intr_test.1694265750 Jun 22 04:18:43 PM PDT 24 Jun 22 04:18:43 PM PDT 24 61906253 ps
T115 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1020351768 Jun 22 04:22:53 PM PDT 24 Jun 22 04:22:55 PM PDT 24 177487525 ps
T1116 /workspace/coverage/cover_reg_top/15.uart_tl_errors.3980531307 Jun 22 04:18:49 PM PDT 24 Jun 22 04:18:52 PM PDT 24 119798044 ps
T1117 /workspace/coverage/cover_reg_top/22.uart_intr_test.1597887591 Jun 22 04:19:52 PM PDT 24 Jun 22 04:19:53 PM PDT 24 40034211 ps
T156 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.1296690527 Jun 22 04:18:31 PM PDT 24 Jun 22 04:18:33 PM PDT 24 254995408 ps
T101 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.4189888795 Jun 22 04:22:29 PM PDT 24 Jun 22 04:22:30 PM PDT 24 56338877 ps
T1118 /workspace/coverage/cover_reg_top/18.uart_intr_test.2958994984 Jun 22 04:20:08 PM PDT 24 Jun 22 04:20:08 PM PDT 24 16711138 ps
T102 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2912514151 Jun 22 04:22:53 PM PDT 24 Jun 22 04:22:54 PM PDT 24 37041350 ps
T1119 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3555719208 Jun 22 04:19:55 PM PDT 24 Jun 22 04:19:56 PM PDT 24 29089098 ps
T1120 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1026772139 Jun 22 04:22:13 PM PDT 24 Jun 22 04:22:15 PM PDT 24 32517506 ps
T116 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.1491489342 Jun 22 04:21:22 PM PDT 24 Jun 22 04:21:24 PM PDT 24 141254705 ps
T1121 /workspace/coverage/cover_reg_top/1.uart_tl_errors.3785903943 Jun 22 04:22:52 PM PDT 24 Jun 22 04:22:54 PM PDT 24 68646068 ps
T79 /workspace/coverage/cover_reg_top/9.uart_csr_rw.1229176827 Jun 22 04:18:32 PM PDT 24 Jun 22 04:18:34 PM PDT 24 42834366 ps
T113 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.828330487 Jun 22 04:18:37 PM PDT 24 Jun 22 04:18:39 PM PDT 24 141739629 ps
T114 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2477043359 Jun 22 04:17:41 PM PDT 24 Jun 22 04:17:43 PM PDT 24 161613582 ps
T1122 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.2741505593 Jun 22 04:22:52 PM PDT 24 Jun 22 04:22:53 PM PDT 24 123593691 ps
T110 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.4093469416 Jun 22 04:18:01 PM PDT 24 Jun 22 04:18:02 PM PDT 24 326588681 ps
T1123 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1466411197 Jun 22 04:20:14 PM PDT 24 Jun 22 04:20:16 PM PDT 24 31906020 ps
T1124 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1505291790 Jun 22 04:18:13 PM PDT 24 Jun 22 04:18:13 PM PDT 24 200191678 ps
T1125 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.648334559 Jun 22 04:19:22 PM PDT 24 Jun 22 04:19:23 PM PDT 24 12625959 ps
T1126 /workspace/coverage/cover_reg_top/7.uart_csr_rw.308069586 Jun 22 04:18:42 PM PDT 24 Jun 22 04:18:43 PM PDT 24 49866267 ps
T1127 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1874544002 Jun 22 04:17:58 PM PDT 24 Jun 22 04:18:00 PM PDT 24 57959279 ps
T1128 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.599382 Jun 22 04:17:17 PM PDT 24 Jun 22 04:17:18 PM PDT 24 42016570 ps
T1129 /workspace/coverage/cover_reg_top/44.uart_intr_test.806173210 Jun 22 04:17:40 PM PDT 24 Jun 22 04:17:41 PM PDT 24 15003317 ps
T1130 /workspace/coverage/cover_reg_top/3.uart_intr_test.3874511486 Jun 22 04:17:42 PM PDT 24 Jun 22 04:17:43 PM PDT 24 47223012 ps
T1131 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.328173762 Jun 22 04:19:21 PM PDT 24 Jun 22 04:19:22 PM PDT 24 18141066 ps
T1132 /workspace/coverage/cover_reg_top/10.uart_tl_errors.2962146476 Jun 22 04:22:40 PM PDT 24 Jun 22 04:22:42 PM PDT 24 94960751 ps
T1133 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.3927484525 Jun 22 04:18:52 PM PDT 24 Jun 22 04:18:53 PM PDT 24 81892798 ps
T1134 /workspace/coverage/cover_reg_top/16.uart_intr_test.4254482623 Jun 22 04:18:25 PM PDT 24 Jun 22 04:18:26 PM PDT 24 13146030 ps
T1135 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3801522980 Jun 22 04:22:52 PM PDT 24 Jun 22 04:22:52 PM PDT 24 16269138 ps
T1136 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.968677650 Jun 22 04:17:39 PM PDT 24 Jun 22 04:17:40 PM PDT 24 23207190 ps
T1137 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.2440961928 Jun 22 04:19:42 PM PDT 24 Jun 22 04:19:43 PM PDT 24 52252741 ps
T1138 /workspace/coverage/cover_reg_top/25.uart_intr_test.3437189428 Jun 22 04:20:22 PM PDT 24 Jun 22 04:20:23 PM PDT 24 137874084 ps
T1139 /workspace/coverage/cover_reg_top/9.uart_intr_test.1092191717 Jun 22 04:19:03 PM PDT 24 Jun 22 04:19:04 PM PDT 24 14462142 ps
T1140 /workspace/coverage/cover_reg_top/4.uart_tl_errors.3110854951 Jun 22 04:22:51 PM PDT 24 Jun 22 04:22:53 PM PDT 24 106769100 ps
T1141 /workspace/coverage/cover_reg_top/28.uart_intr_test.3661980056 Jun 22 04:19:55 PM PDT 24 Jun 22 04:19:56 PM PDT 24 108936420 ps
T1142 /workspace/coverage/cover_reg_top/12.uart_tl_errors.4033452682 Jun 22 04:22:14 PM PDT 24 Jun 22 04:22:16 PM PDT 24 505824105 ps
T1143 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1844827068 Jun 22 04:18:31 PM PDT 24 Jun 22 04:18:32 PM PDT 24 38099205 ps
T1144 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.2505898658 Jun 22 04:21:12 PM PDT 24 Jun 22 04:21:13 PM PDT 24 21135968 ps
T1145 /workspace/coverage/cover_reg_top/29.uart_intr_test.1167550079 Jun 22 04:20:14 PM PDT 24 Jun 22 04:20:15 PM PDT 24 26834064 ps
T1146 /workspace/coverage/cover_reg_top/19.uart_tl_errors.116061011 Jun 22 04:21:22 PM PDT 24 Jun 22 04:21:25 PM PDT 24 43294390 ps
T83 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.1596422502 Jun 22 04:18:01 PM PDT 24 Jun 22 04:18:02 PM PDT 24 38784707 ps
T1147 /workspace/coverage/cover_reg_top/8.uart_csr_rw.2180716553 Jun 22 04:18:30 PM PDT 24 Jun 22 04:18:31 PM PDT 24 14029217 ps
T111 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.2738163488 Jun 22 04:20:22 PM PDT 24 Jun 22 04:20:23 PM PDT 24 51052915 ps
T1148 /workspace/coverage/cover_reg_top/30.uart_intr_test.1568767896 Jun 22 04:18:37 PM PDT 24 Jun 22 04:18:38 PM PDT 24 12917831 ps
T1149 /workspace/coverage/cover_reg_top/36.uart_intr_test.1378572837 Jun 22 04:18:10 PM PDT 24 Jun 22 04:18:11 PM PDT 24 16269221 ps
T1150 /workspace/coverage/cover_reg_top/48.uart_intr_test.2073887220 Jun 22 04:18:42 PM PDT 24 Jun 22 04:18:43 PM PDT 24 16199965 ps
T1151 /workspace/coverage/cover_reg_top/32.uart_intr_test.1636377150 Jun 22 04:21:03 PM PDT 24 Jun 22 04:21:03 PM PDT 24 15532340 ps
T1152 /workspace/coverage/cover_reg_top/19.uart_intr_test.1273306214 Jun 22 04:19:06 PM PDT 24 Jun 22 04:19:07 PM PDT 24 63676935 ps
T1153 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.3340723246 Jun 22 04:18:20 PM PDT 24 Jun 22 04:18:23 PM PDT 24 191978684 ps
T1154 /workspace/coverage/cover_reg_top/4.uart_intr_test.1055812388 Jun 22 04:18:37 PM PDT 24 Jun 22 04:18:39 PM PDT 24 187979175 ps
T1155 /workspace/coverage/cover_reg_top/6.uart_csr_rw.3873424782 Jun 22 04:17:38 PM PDT 24 Jun 22 04:17:39 PM PDT 24 24294107 ps
T155 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2557366741 Jun 22 04:18:23 PM PDT 24 Jun 22 04:18:24 PM PDT 24 831038597 ps
T1156 /workspace/coverage/cover_reg_top/1.uart_intr_test.1967829767 Jun 22 04:22:37 PM PDT 24 Jun 22 04:22:39 PM PDT 24 13292951 ps
T112 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.3516950615 Jun 22 04:16:40 PM PDT 24 Jun 22 04:16:43 PM PDT 24 266420471 ps
T1157 /workspace/coverage/cover_reg_top/40.uart_intr_test.4277227350 Jun 22 04:21:03 PM PDT 24 Jun 22 04:21:04 PM PDT 24 44288805 ps
T1158 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.357604761 Jun 22 04:17:39 PM PDT 24 Jun 22 04:17:40 PM PDT 24 25561860 ps
T1159 /workspace/coverage/cover_reg_top/3.uart_tl_errors.3703773423 Jun 22 04:22:35 PM PDT 24 Jun 22 04:22:37 PM PDT 24 22833246 ps
T1160 /workspace/coverage/cover_reg_top/26.uart_intr_test.862130608 Jun 22 04:22:15 PM PDT 24 Jun 22 04:22:16 PM PDT 24 15748349 ps
T1161 /workspace/coverage/cover_reg_top/16.uart_csr_rw.1922443363 Jun 22 04:17:46 PM PDT 24 Jun 22 04:17:47 PM PDT 24 33535525 ps
T1162 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2355580149 Jun 22 04:22:55 PM PDT 24 Jun 22 04:22:56 PM PDT 24 48550763 ps
T1163 /workspace/coverage/cover_reg_top/10.uart_csr_rw.2206845835 Jun 22 04:22:48 PM PDT 24 Jun 22 04:22:49 PM PDT 24 17470999 ps
T1164 /workspace/coverage/cover_reg_top/13.uart_csr_rw.3808608478 Jun 22 04:23:08 PM PDT 24 Jun 22 04:23:10 PM PDT 24 12746401 ps
T93 /workspace/coverage/cover_reg_top/11.uart_csr_rw.892543270 Jun 22 04:18:31 PM PDT 24 Jun 22 04:18:32 PM PDT 24 49009889 ps
T1165 /workspace/coverage/cover_reg_top/5.uart_intr_test.434120748 Jun 22 04:18:13 PM PDT 24 Jun 22 04:18:14 PM PDT 24 19119856 ps
T1166 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1090765712 Jun 22 04:18:04 PM PDT 24 Jun 22 04:18:06 PM PDT 24 100698757 ps
T1167 /workspace/coverage/cover_reg_top/0.uart_intr_test.2478410962 Jun 22 04:17:18 PM PDT 24 Jun 22 04:17:19 PM PDT 24 12674738 ps
T80 /workspace/coverage/cover_reg_top/18.uart_csr_rw.403172442 Jun 22 04:22:53 PM PDT 24 Jun 22 04:22:54 PM PDT 24 42360737 ps
T1168 /workspace/coverage/cover_reg_top/12.uart_csr_rw.135359531 Jun 22 04:17:45 PM PDT 24 Jun 22 04:17:46 PM PDT 24 24169982 ps
T1169 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.894970527 Jun 22 04:21:22 PM PDT 24 Jun 22 04:21:24 PM PDT 24 70178888 ps
T1170 /workspace/coverage/cover_reg_top/34.uart_intr_test.1417998210 Jun 22 04:23:08 PM PDT 24 Jun 22 04:23:10 PM PDT 24 13895937 ps
T81 /workspace/coverage/cover_reg_top/15.uart_csr_rw.1394295063 Jun 22 04:17:40 PM PDT 24 Jun 22 04:17:41 PM PDT 24 24284461 ps
T1171 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.2862025300 Jun 22 04:17:58 PM PDT 24 Jun 22 04:18:01 PM PDT 24 84028535 ps
T1172 /workspace/coverage/cover_reg_top/7.uart_intr_test.973758197 Jun 22 04:19:14 PM PDT 24 Jun 22 04:19:14 PM PDT 24 41878633 ps
T1173 /workspace/coverage/cover_reg_top/49.uart_intr_test.1835517609 Jun 22 04:17:40 PM PDT 24 Jun 22 04:17:41 PM PDT 24 12536263 ps
T1174 /workspace/coverage/cover_reg_top/14.uart_csr_rw.1470238871 Jun 22 04:20:22 PM PDT 24 Jun 22 04:20:23 PM PDT 24 16732756 ps
T1175 /workspace/coverage/cover_reg_top/17.uart_tl_errors.2705038839 Jun 22 04:22:25 PM PDT 24 Jun 22 04:22:27 PM PDT 24 99946807 ps
T1176 /workspace/coverage/cover_reg_top/16.uart_tl_errors.3338685617 Jun 22 04:18:33 PM PDT 24 Jun 22 04:18:35 PM PDT 24 120727580 ps
T1177 /workspace/coverage/cover_reg_top/37.uart_intr_test.3316223608 Jun 22 04:18:27 PM PDT 24 Jun 22 04:18:28 PM PDT 24 36207495 ps
T1178 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.898015623 Jun 22 04:17:17 PM PDT 24 Jun 22 04:17:18 PM PDT 24 30968756 ps
T1179 /workspace/coverage/cover_reg_top/14.uart_tl_errors.5337231 Jun 22 04:22:13 PM PDT 24 Jun 22 04:22:15 PM PDT 24 449930637 ps
T1180 /workspace/coverage/cover_reg_top/1.uart_csr_rw.1394361356 Jun 22 04:22:52 PM PDT 24 Jun 22 04:22:52 PM PDT 24 39249843 ps
T1181 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.2942448793 Jun 22 04:18:45 PM PDT 24 Jun 22 04:18:46 PM PDT 24 195633395 ps
T1182 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2436752332 Jun 22 04:21:04 PM PDT 24 Jun 22 04:21:05 PM PDT 24 36517286 ps
T1183 /workspace/coverage/cover_reg_top/43.uart_intr_test.2845839781 Jun 22 04:17:42 PM PDT 24 Jun 22 04:17:43 PM PDT 24 21158991 ps
T1184 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2315498065 Jun 22 04:22:51 PM PDT 24 Jun 22 04:22:52 PM PDT 24 176679873 ps
T1185 /workspace/coverage/cover_reg_top/5.uart_tl_errors.1822891193 Jun 22 04:18:34 PM PDT 24 Jun 22 04:18:36 PM PDT 24 89714048 ps
T1186 /workspace/coverage/cover_reg_top/5.uart_csr_rw.1675263661 Jun 22 04:22:35 PM PDT 24 Jun 22 04:22:36 PM PDT 24 31477413 ps
T1187 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.3410007290 Jun 22 04:18:01 PM PDT 24 Jun 22 04:18:02 PM PDT 24 22524064 ps
T1188 /workspace/coverage/cover_reg_top/24.uart_intr_test.858513932 Jun 22 04:18:54 PM PDT 24 Jun 22 04:18:55 PM PDT 24 108386641 ps
T1189 /workspace/coverage/cover_reg_top/13.uart_tl_errors.1579956235 Jun 22 04:17:39 PM PDT 24 Jun 22 04:17:41 PM PDT 24 456800642 ps
T1190 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3888293265 Jun 22 04:17:51 PM PDT 24 Jun 22 04:17:53 PM PDT 24 39935389 ps
T1191 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.3410636063 Jun 22 04:19:23 PM PDT 24 Jun 22 04:19:24 PM PDT 24 15894106 ps
T1192 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.717471680 Jun 22 04:17:58 PM PDT 24 Jun 22 04:18:00 PM PDT 24 159188587 ps
T1193 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.1650119627 Jun 22 04:19:42 PM PDT 24 Jun 22 04:19:43 PM PDT 24 17722782 ps
T1194 /workspace/coverage/cover_reg_top/0.uart_csr_rw.3018241084 Jun 22 04:17:17 PM PDT 24 Jun 22 04:17:18 PM PDT 24 11581288 ps
T1195 /workspace/coverage/cover_reg_top/33.uart_intr_test.391261779 Jun 22 04:18:02 PM PDT 24 Jun 22 04:18:03 PM PDT 24 79595075 ps
T1196 /workspace/coverage/cover_reg_top/39.uart_intr_test.4173976885 Jun 22 04:17:49 PM PDT 24 Jun 22 04:17:50 PM PDT 24 24656887 ps
T1197 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1203271195 Jun 22 04:19:29 PM PDT 24 Jun 22 04:19:31 PM PDT 24 27522305 ps
T108 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.2398432112 Jun 22 04:20:08 PM PDT 24 Jun 22 04:20:09 PM PDT 24 776204557 ps
T1198 /workspace/coverage/cover_reg_top/38.uart_intr_test.1733858910 Jun 22 04:18:31 PM PDT 24 Jun 22 04:18:32 PM PDT 24 39543395 ps
T1199 /workspace/coverage/cover_reg_top/18.uart_tl_errors.2464760014 Jun 22 04:18:30 PM PDT 24 Jun 22 04:18:33 PM PDT 24 539016558 ps
T1200 /workspace/coverage/cover_reg_top/11.uart_intr_test.3767244352 Jun 22 04:22:10 PM PDT 24 Jun 22 04:22:12 PM PDT 24 18270818 ps
T1201 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3507432278 Jun 22 04:18:37 PM PDT 24 Jun 22 04:18:39 PM PDT 24 55338065 ps
T1202 /workspace/coverage/cover_reg_top/10.uart_intr_test.2585978264 Jun 22 04:21:41 PM PDT 24 Jun 22 04:21:41 PM PDT 24 14166137 ps
T1203 /workspace/coverage/cover_reg_top/27.uart_intr_test.2618318724 Jun 22 04:22:31 PM PDT 24 Jun 22 04:22:33 PM PDT 24 33761623 ps
T1204 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.4082994509 Jun 22 04:22:25 PM PDT 24 Jun 22 04:22:26 PM PDT 24 32292560 ps
T1205 /workspace/coverage/cover_reg_top/41.uart_intr_test.1791442530 Jun 22 04:21:04 PM PDT 24 Jun 22 04:21:05 PM PDT 24 29536595 ps
T1206 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.2124211350 Jun 22 04:18:55 PM PDT 24 Jun 22 04:18:56 PM PDT 24 91881426 ps
T1207 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2173893311 Jun 22 04:17:38 PM PDT 24 Jun 22 04:17:39 PM PDT 24 93298141 ps
T1208 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.1993063503 Jun 22 04:18:12 PM PDT 24 Jun 22 04:18:12 PM PDT 24 15889592 ps
T1209 /workspace/coverage/cover_reg_top/6.uart_intr_test.455556539 Jun 22 04:16:57 PM PDT 24 Jun 22 04:16:58 PM PDT 24 41576931 ps
T1210 /workspace/coverage/cover_reg_top/8.uart_tl_errors.88282708 Jun 22 04:18:32 PM PDT 24 Jun 22 04:18:33 PM PDT 24 54578881 ps
T82 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.3723177759 Jun 22 04:18:12 PM PDT 24 Jun 22 04:18:13 PM PDT 24 29239317 ps
T1211 /workspace/coverage/cover_reg_top/8.uart_intr_test.2159442170 Jun 22 04:18:30 PM PDT 24 Jun 22 04:18:31 PM PDT 24 52069787 ps
T1212 /workspace/coverage/cover_reg_top/47.uart_intr_test.3011578692 Jun 22 04:19:15 PM PDT 24 Jun 22 04:19:15 PM PDT 24 21519953 ps
T109 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3587767308 Jun 22 04:22:51 PM PDT 24 Jun 22 04:22:53 PM PDT 24 3739734844 ps
T1213 /workspace/coverage/cover_reg_top/2.uart_intr_test.1014683589 Jun 22 04:18:01 PM PDT 24 Jun 22 04:18:02 PM PDT 24 14129162 ps
T1214 /workspace/coverage/cover_reg_top/19.uart_csr_rw.1855883064 Jun 22 04:19:20 PM PDT 24 Jun 22 04:19:21 PM PDT 24 84272573 ps
T1215 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.298073603 Jun 22 04:18:15 PM PDT 24 Jun 22 04:18:17 PM PDT 24 326222169 ps
T1216 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3758047371 Jun 22 04:21:26 PM PDT 24 Jun 22 04:21:27 PM PDT 24 21576491 ps
T1217 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.283551 Jun 22 04:17:36 PM PDT 24 Jun 22 04:17:37 PM PDT 24 53576827 ps
T1218 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2685263818 Jun 22 04:18:01 PM PDT 24 Jun 22 04:18:03 PM PDT 24 28309888 ps
T1219 /workspace/coverage/cover_reg_top/31.uart_intr_test.1051998110 Jun 22 04:23:06 PM PDT 24 Jun 22 04:23:07 PM PDT 24 40916167 ps
T1220 /workspace/coverage/cover_reg_top/4.uart_csr_rw.1345175211 Jun 22 04:22:51 PM PDT 24 Jun 22 04:22:52 PM PDT 24 16722061 ps
T1221 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1879925109 Jun 22 04:17:37 PM PDT 24 Jun 22 04:17:38 PM PDT 24 28004450 ps
T1222 /workspace/coverage/cover_reg_top/23.uart_intr_test.2122915067 Jun 22 04:20:22 PM PDT 24 Jun 22 04:20:23 PM PDT 24 48595774 ps
T1223 /workspace/coverage/cover_reg_top/42.uart_intr_test.699317918 Jun 22 04:18:45 PM PDT 24 Jun 22 04:18:46 PM PDT 24 17144406 ps
T1224 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2070081802 Jun 22 04:19:23 PM PDT 24 Jun 22 04:19:24 PM PDT 24 167226968 ps

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.3796526748
Short name T7
Test name
Test status
Simulation time 53482420287 ps
CPU time 97.07 seconds
Started Jun 22 04:28:06 PM PDT 24
Finished Jun 22 04:29:44 PM PDT 24
Peak memory 200508 kb
Host smart-f1d1e47b-adf8-4f3d-b737-6c596c442307
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3796526748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.3796526748
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.3320826433
Short name T35
Test name
Test status
Simulation time 170890317074 ps
CPU time 619.22 seconds
Started Jun 22 04:28:14 PM PDT 24
Finished Jun 22 04:38:33 PM PDT 24
Peak memory 213628 kb
Host smart-ceb40b74-231d-440e-9bc5-f8b7ba34f83e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320826433 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.3320826433
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_stress_all.4159622994
Short name T160
Test name
Test status
Simulation time 243444790319 ps
CPU time 313.25 seconds
Started Jun 22 04:29:33 PM PDT 24
Finished Jun 22 04:34:48 PM PDT 24
Peak memory 200452 kb
Host smart-4ea34c86-9d1b-4485-bd2c-41187c98ffe8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159622994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.4159622994
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all.2413699292
Short name T15
Test name
Test status
Simulation time 62900053890 ps
CPU time 94.16 seconds
Started Jun 22 04:29:41 PM PDT 24
Finished Jun 22 04:31:16 PM PDT 24
Peak memory 200536 kb
Host smart-3c8bdbf2-316c-49b0-b92f-095ab485080f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413699292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.2413699292
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.1557620919
Short name T37
Test name
Test status
Simulation time 250258370334 ps
CPU time 396.44 seconds
Started Jun 22 04:28:32 PM PDT 24
Finished Jun 22 04:35:09 PM PDT 24
Peak memory 216968 kb
Host smart-40b436f4-4ee1-473f-aa6b-6d77f524b974
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557620919 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.1557620919
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_intr.923703495
Short name T1
Test name
Test status
Simulation time 272217344483 ps
CPU time 360.79 seconds
Started Jun 22 04:27:55 PM PDT 24
Finished Jun 22 04:33:56 PM PDT 24
Peak memory 197744 kb
Host smart-7319b0ef-8265-4462-9092-288192efa35b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923703495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.923703495
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.357601194
Short name T40
Test name
Test status
Simulation time 104156806872 ps
CPU time 1044.27 seconds
Started Jun 22 04:29:59 PM PDT 24
Finished Jun 22 04:47:24 PM PDT 24
Peak memory 225176 kb
Host smart-4d9825ae-8a69-4d46-b73d-972ea02c1ef6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357601194 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.357601194
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.347878888
Short name T57
Test name
Test status
Simulation time 157059100119 ps
CPU time 908.56 seconds
Started Jun 22 04:29:06 PM PDT 24
Finished Jun 22 04:44:16 PM PDT 24
Peak memory 200604 kb
Host smart-8c820618-56c2-4090-acba-55ce294d8dcd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=347878888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.347878888
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.1781039901
Short name T17
Test name
Test status
Simulation time 177978395017 ps
CPU time 37.79 seconds
Started Jun 22 04:28:15 PM PDT 24
Finished Jun 22 04:28:54 PM PDT 24
Peak memory 200348 kb
Host smart-7efd4419-76c8-43e7-923d-195ce0ffbcdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781039901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.1781039901
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_sec_cm.3866010468
Short name T29
Test name
Test status
Simulation time 293958149 ps
CPU time 0.78 seconds
Started Jun 22 04:27:59 PM PDT 24
Finished Jun 22 04:28:01 PM PDT 24
Peak memory 218736 kb
Host smart-ac507cdf-e2c3-4b6d-95eb-d90afbaff244
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866010468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.3866010468
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.2782408310
Short name T150
Test name
Test status
Simulation time 140377675377 ps
CPU time 121.73 seconds
Started Jun 22 04:29:13 PM PDT 24
Finished Jun 22 04:31:16 PM PDT 24
Peak memory 200556 kb
Host smart-1a13e228-44d3-400b-9df7-fc43c4fd4ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782408310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.2782408310
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.3497686125
Short name T175
Test name
Test status
Simulation time 119285488883 ps
CPU time 115.05 seconds
Started Jun 22 04:28:01 PM PDT 24
Finished Jun 22 04:29:58 PM PDT 24
Peak memory 200568 kb
Host smart-d6c1507d-dcb5-45b5-82a6-f4f0ecc12348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497686125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.3497686125
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_fifo_full.2121907348
Short name T46
Test name
Test status
Simulation time 324981873620 ps
CPU time 176.4 seconds
Started Jun 22 04:29:32 PM PDT 24
Finished Jun 22 04:32:29 PM PDT 24
Peak memory 200456 kb
Host smart-f0390c1a-b750-4027-8762-c9f734353d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121907348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.2121907348
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.838992031
Short name T273
Test name
Test status
Simulation time 86197970474 ps
CPU time 79.05 seconds
Started Jun 22 04:30:56 PM PDT 24
Finished Jun 22 04:32:16 PM PDT 24
Peak memory 200524 kb
Host smart-370819fc-d29b-4cb8-8a18-680ffd66ece8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838992031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.838992031
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.2693386681
Short name T27
Test name
Test status
Simulation time 64878254458 ps
CPU time 183.44 seconds
Started Jun 22 04:30:07 PM PDT 24
Finished Jun 22 04:33:11 PM PDT 24
Peak memory 216000 kb
Host smart-ca280d7a-44b4-4510-a5d4-0b73e0d39010
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693386681 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.2693386681
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.1991541689
Short name T218
Test name
Test status
Simulation time 143906568884 ps
CPU time 212.52 seconds
Started Jun 22 04:29:04 PM PDT 24
Finished Jun 22 04:32:37 PM PDT 24
Peak memory 200436 kb
Host smart-db91795f-d517-48d8-98fb-b77f9ab9bf8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991541689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.1991541689
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.870358578
Short name T138
Test name
Test status
Simulation time 48389190210 ps
CPU time 43.95 seconds
Started Jun 22 04:30:13 PM PDT 24
Finished Jun 22 04:30:58 PM PDT 24
Peak memory 200348 kb
Host smart-ae9054cd-3b5b-4991-987e-b404508a89ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870358578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.870358578
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.3678002608
Short name T202
Test name
Test status
Simulation time 21039908294 ps
CPU time 49.65 seconds
Started Jun 22 04:30:31 PM PDT 24
Finished Jun 22 04:31:22 PM PDT 24
Peak memory 200524 kb
Host smart-d7fe6601-8ec1-4c58-903d-106087e823e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678002608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.3678002608
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.287197266
Short name T214
Test name
Test status
Simulation time 136411026803 ps
CPU time 213.64 seconds
Started Jun 22 04:30:48 PM PDT 24
Finished Jun 22 04:34:22 PM PDT 24
Peak memory 200552 kb
Host smart-be063ec7-ac7d-42e5-aaee-51548bd6a264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287197266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.287197266
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.2738163488
Short name T111
Test name
Test status
Simulation time 51052915 ps
CPU time 0.91 seconds
Started Jun 22 04:20:22 PM PDT 24
Finished Jun 22 04:20:23 PM PDT 24
Peak memory 198856 kb
Host smart-2d19a675-bb03-4e04-9b9d-4e1e0239793a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738163488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.2738163488
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/default/30.uart_fifo_full.1399049415
Short name T178
Test name
Test status
Simulation time 306332816773 ps
CPU time 30.05 seconds
Started Jun 22 04:28:59 PM PDT 24
Finished Jun 22 04:29:30 PM PDT 24
Peak memory 200488 kb
Host smart-ceea5d4a-6582-441e-ae61-ba7c5432b5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399049415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.1399049415
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_alert_test.3309319928
Short name T384
Test name
Test status
Simulation time 12861061 ps
CPU time 0.55 seconds
Started Jun 22 04:27:59 PM PDT 24
Finished Jun 22 04:28:02 PM PDT 24
Peak memory 195256 kb
Host smart-edfea404-2b84-4f3a-aa9a-2df6332f55b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309319928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.3309319928
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.403172442
Short name T80
Test name
Test status
Simulation time 42360737 ps
CPU time 0.63 seconds
Started Jun 22 04:22:53 PM PDT 24
Finished Jun 22 04:22:54 PM PDT 24
Peak memory 193932 kb
Host smart-d18cd49e-f270-4ec0-a356-7342ba08e6b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403172442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.403172442
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/default/19.uart_stress_all.560901381
Short name T277
Test name
Test status
Simulation time 100347812395 ps
CPU time 77.95 seconds
Started Jun 22 04:28:53 PM PDT 24
Finished Jun 22 04:30:13 PM PDT 24
Peak memory 200540 kb
Host smart-0d7cd31a-fb7a-4f03-86b3-64c54d4a2e2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560901381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.560901381
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.530147014
Short name T16
Test name
Test status
Simulation time 18463005233 ps
CPU time 24 seconds
Started Jun 22 04:30:36 PM PDT 24
Finished Jun 22 04:31:02 PM PDT 24
Peak memory 200508 kb
Host smart-b491e116-3492-4c04-a482-329c3315b3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530147014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.530147014
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.3082137110
Short name T56
Test name
Test status
Simulation time 142413420057 ps
CPU time 67.98 seconds
Started Jun 22 04:30:34 PM PDT 24
Finished Jun 22 04:31:42 PM PDT 24
Peak memory 200484 kb
Host smart-3a947ba9-6776-4a05-89a4-b8cad7dbfb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082137110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.3082137110
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_fifo_full.870047502
Short name T53
Test name
Test status
Simulation time 204429022669 ps
CPU time 104.27 seconds
Started Jun 22 04:29:45 PM PDT 24
Finished Jun 22 04:31:31 PM PDT 24
Peak memory 200544 kb
Host smart-290add90-3d43-4c00-866c-7c4e1064c354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870047502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.870047502
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.3610356693
Short name T159
Test name
Test status
Simulation time 33872688978 ps
CPU time 15.04 seconds
Started Jun 22 04:29:07 PM PDT 24
Finished Jun 22 04:29:22 PM PDT 24
Peak memory 200512 kb
Host smart-f06fb28a-80ba-4ebd-a1aa-291a7def89fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610356693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.3610356693
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.11204254
Short name T173
Test name
Test status
Simulation time 98957728726 ps
CPU time 44.51 seconds
Started Jun 22 04:30:36 PM PDT 24
Finished Jun 22 04:31:22 PM PDT 24
Peak memory 200424 kb
Host smart-934f6cc8-ec83-4d71-b82f-0381982ae666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11204254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.11204254
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3295422549
Short name T94
Test name
Test status
Simulation time 35077951 ps
CPU time 0.78 seconds
Started Jun 22 04:20:13 PM PDT 24
Finished Jun 22 04:20:15 PM PDT 24
Peak memory 196932 kb
Host smart-14b2cdf5-cff7-4f55-a903-f0af659fd065
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295422549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.3295422549
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.317633920
Short name T127
Test name
Test status
Simulation time 111536000444 ps
CPU time 398.75 seconds
Started Jun 22 04:28:15 PM PDT 24
Finished Jun 22 04:34:55 PM PDT 24
Peak memory 216980 kb
Host smart-4ec7d464-90cf-4a0c-80a9-be6f96dc5ba5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317633920 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.317633920
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.2967346848
Short name T297
Test name
Test status
Simulation time 65957556290 ps
CPU time 133.25 seconds
Started Jun 22 04:30:36 PM PDT 24
Finished Jun 22 04:32:51 PM PDT 24
Peak memory 200536 kb
Host smart-b5005c93-1f1b-475a-9afa-0a77557a435c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967346848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.2967346848
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.4238558046
Short name T105
Test name
Test status
Simulation time 444667927 ps
CPU time 1.34 seconds
Started Jun 22 04:22:24 PM PDT 24
Finished Jun 22 04:22:26 PM PDT 24
Peak memory 197900 kb
Host smart-eaac9337-d026-4ac8-8550-a9c84c0102f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238558046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.4238558046
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.3904788213
Short name T130
Test name
Test status
Simulation time 388607343856 ps
CPU time 834.49 seconds
Started Jun 22 04:28:23 PM PDT 24
Finished Jun 22 04:42:19 PM PDT 24
Peak memory 225148 kb
Host smart-4bb580f3-d723-4c6f-9de4-f00ad08d7fb9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904788213 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.3904788213
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.3556795248
Short name T58
Test name
Test status
Simulation time 30921950871 ps
CPU time 30.22 seconds
Started Jun 22 04:30:30 PM PDT 24
Finished Jun 22 04:31:00 PM PDT 24
Peak memory 200528 kb
Host smart-f3167aaf-b231-4de7-a86e-a218bb29bdd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556795248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.3556795248
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.2393179503
Short name T171
Test name
Test status
Simulation time 39842535910 ps
CPU time 78.59 seconds
Started Jun 22 04:30:38 PM PDT 24
Finished Jun 22 04:31:58 PM PDT 24
Peak memory 200420 kb
Host smart-cbf0982d-8e86-4dc5-9167-5ea4c5e1d1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393179503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.2393179503
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_fifo_full.3898225153
Short name T192
Test name
Test status
Simulation time 105141592531 ps
CPU time 24.11 seconds
Started Jun 22 04:28:47 PM PDT 24
Finished Jun 22 04:29:12 PM PDT 24
Peak memory 200492 kb
Host smart-ec1ec6b0-55a4-4b10-b507-45bd0e930900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898225153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.3898225153
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.3628199198
Short name T281
Test name
Test status
Simulation time 256019653985 ps
CPU time 425.64 seconds
Started Jun 22 04:30:17 PM PDT 24
Finished Jun 22 04:37:23 PM PDT 24
Peak memory 200568 kb
Host smart-0e604504-2886-45ac-86fc-7186d46f1027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628199198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.3628199198
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.922596622
Short name T5
Test name
Test status
Simulation time 39298416405 ps
CPU time 71.72 seconds
Started Jun 22 04:30:55 PM PDT 24
Finished Jun 22 04:32:08 PM PDT 24
Peak memory 200524 kb
Host smart-4949abdb-c5c5-4612-b1a1-2870a89cfc56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922596622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.922596622
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.3521568958
Short name T197
Test name
Test status
Simulation time 222180721028 ps
CPU time 112.13 seconds
Started Jun 22 04:29:01 PM PDT 24
Finished Jun 22 04:30:54 PM PDT 24
Peak memory 200580 kb
Host smart-65b6f665-4f5c-4109-b8a4-b66ff52ceb51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521568958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.3521568958
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.2870127694
Short name T262
Test name
Test status
Simulation time 50056519720 ps
CPU time 14.55 seconds
Started Jun 22 04:30:20 PM PDT 24
Finished Jun 22 04:30:36 PM PDT 24
Peak memory 200500 kb
Host smart-606549ca-b320-4e5a-a7f3-d9a5d74e2872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870127694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.2870127694
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.2125480170
Short name T222
Test name
Test status
Simulation time 65132962834 ps
CPU time 294.34 seconds
Started Jun 22 04:28:16 PM PDT 24
Finished Jun 22 04:33:12 PM PDT 24
Peak memory 216952 kb
Host smart-95f3083b-db8b-4259-bd97-3641fe30f00a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125480170 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.2125480170
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.279012892
Short name T121
Test name
Test status
Simulation time 77419304605 ps
CPU time 28.06 seconds
Started Jun 22 04:30:37 PM PDT 24
Finished Jun 22 04:31:07 PM PDT 24
Peak memory 200880 kb
Host smart-6f9b5cee-3c3a-48eb-83cd-0d990dcb7ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279012892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.279012892
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.1560281908
Short name T295
Test name
Test status
Simulation time 183479999942 ps
CPU time 302.79 seconds
Started Jun 22 04:28:40 PM PDT 24
Finished Jun 22 04:33:43 PM PDT 24
Peak memory 200520 kb
Host smart-4963479b-bcbd-4679-8b39-766f4c0897ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560281908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.1560281908
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_tx_rx.3065507304
Short name T441
Test name
Test status
Simulation time 144756368343 ps
CPU time 230.74 seconds
Started Jun 22 04:28:15 PM PDT 24
Finished Jun 22 04:32:06 PM PDT 24
Peak memory 200928 kb
Host smart-54d5c3c7-fbd2-40ce-9109-9b7c7547dd98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065507304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.3065507304
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.2121800213
Short name T140
Test name
Test status
Simulation time 44200538212 ps
CPU time 25.7 seconds
Started Jun 22 04:30:43 PM PDT 24
Finished Jun 22 04:31:10 PM PDT 24
Peak memory 200508 kb
Host smart-90e877f6-1e31-478b-9c80-37115841ace1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121800213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.2121800213
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.40870831
Short name T9
Test name
Test status
Simulation time 40237223933 ps
CPU time 29.8 seconds
Started Jun 22 04:27:55 PM PDT 24
Finished Jun 22 04:28:26 PM PDT 24
Peak memory 200360 kb
Host smart-1c6f008d-a140-43d1-8132-9887dce02758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40870831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.40870831
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_stress_all.2407638076
Short name T62
Test name
Test status
Simulation time 217474509522 ps
CPU time 90.55 seconds
Started Jun 22 04:28:41 PM PDT 24
Finished Jun 22 04:30:12 PM PDT 24
Peak memory 200456 kb
Host smart-0435c57b-6140-48b5-a586-b0cbce923b77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407638076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.2407638076
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.1362819712
Short name T208
Test name
Test status
Simulation time 51513599075 ps
CPU time 39.26 seconds
Started Jun 22 04:28:26 PM PDT 24
Finished Jun 22 04:29:05 PM PDT 24
Peak memory 200596 kb
Host smart-b2d0976e-3fde-4d42-b3f5-518649e934f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362819712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.1362819712
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.1593698747
Short name T51
Test name
Test status
Simulation time 64055868992 ps
CPU time 116.99 seconds
Started Jun 22 04:30:46 PM PDT 24
Finished Jun 22 04:32:43 PM PDT 24
Peak memory 200484 kb
Host smart-c7eec858-3836-43eb-96db-290913648e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593698747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.1593698747
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.3311035182
Short name T189
Test name
Test status
Simulation time 31793447690 ps
CPU time 25.4 seconds
Started Jun 22 04:30:56 PM PDT 24
Finished Jun 22 04:31:22 PM PDT 24
Peak memory 200492 kb
Host smart-9bc475ba-793f-4f8b-b138-f8ae85433790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311035182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.3311035182
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.803305000
Short name T516
Test name
Test status
Simulation time 150640037275 ps
CPU time 304.8 seconds
Started Jun 22 04:28:52 PM PDT 24
Finished Jun 22 04:33:59 PM PDT 24
Peak memory 200520 kb
Host smart-2cd9e070-6d58-4477-8fb1-ede2784463af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803305000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.803305000
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_stress_all.1021664465
Short name T200
Test name
Test status
Simulation time 675965613251 ps
CPU time 1327.16 seconds
Started Jun 22 04:27:58 PM PDT 24
Finished Jun 22 04:50:06 PM PDT 24
Peak memory 200952 kb
Host smart-858a265b-a7e2-4d89-93dc-623bfad96864
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021664465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.1021664465
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.3211613041
Short name T271
Test name
Test status
Simulation time 130391175124 ps
CPU time 78.22 seconds
Started Jun 22 04:30:20 PM PDT 24
Finished Jun 22 04:31:39 PM PDT 24
Peak memory 200544 kb
Host smart-f46dfc7b-c18c-4846-b771-fb3ad5aaf47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211613041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.3211613041
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2477043359
Short name T114
Test name
Test status
Simulation time 161613582 ps
CPU time 1.35 seconds
Started Jun 22 04:17:41 PM PDT 24
Finished Jun 22 04:17:43 PM PDT 24
Peak memory 198952 kb
Host smart-3dc2f25d-e161-4b55-96ee-71a358077cc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477043359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.2477043359
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.2057794943
Short name T363
Test name
Test status
Simulation time 12242927086 ps
CPU time 18.38 seconds
Started Jun 22 04:30:26 PM PDT 24
Finished Jun 22 04:30:45 PM PDT 24
Peak memory 200468 kb
Host smart-e0aae0ac-f74f-413b-b217-d175e490e364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057794943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.2057794943
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.1406852420
Short name T168
Test name
Test status
Simulation time 34119185187 ps
CPU time 61.74 seconds
Started Jun 22 04:30:22 PM PDT 24
Finished Jun 22 04:31:25 PM PDT 24
Peak memory 200484 kb
Host smart-87454e36-a685-40ea-b2c8-9fc5b9ee6a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406852420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.1406852420
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.4071834585
Short name T249
Test name
Test status
Simulation time 39058574949 ps
CPU time 51.53 seconds
Started Jun 22 04:30:38 PM PDT 24
Finished Jun 22 04:31:31 PM PDT 24
Peak memory 200744 kb
Host smart-71b8825b-8930-41d2-80fc-e3b70cfc89f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071834585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.4071834585
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.2183081726
Short name T700
Test name
Test status
Simulation time 43168684852 ps
CPU time 16.15 seconds
Started Jun 22 04:30:41 PM PDT 24
Finished Jun 22 04:30:57 PM PDT 24
Peak memory 200380 kb
Host smart-7a7179be-d57d-4f71-8dae-9519ff745700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183081726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.2183081726
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.2211495251
Short name T91
Test name
Test status
Simulation time 18021461590 ps
CPU time 181.12 seconds
Started Jun 22 04:27:56 PM PDT 24
Finished Jun 22 04:30:58 PM PDT 24
Peak memory 216148 kb
Host smart-f254952d-b794-4271-ad3d-3e9fd8439e0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211495251 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.2211495251
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.506799728
Short name T212
Test name
Test status
Simulation time 132528627586 ps
CPU time 33.85 seconds
Started Jun 22 04:30:34 PM PDT 24
Finished Jun 22 04:31:08 PM PDT 24
Peak memory 200464 kb
Host smart-8ec5e5a3-cbe6-463e-930c-e8b25b954407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506799728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.506799728
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.1271262456
Short name T231
Test name
Test status
Simulation time 40610996336 ps
CPU time 29.57 seconds
Started Jun 22 04:30:38 PM PDT 24
Finished Jun 22 04:31:09 PM PDT 24
Peak memory 200524 kb
Host smart-b37f266a-6c6c-4f58-84cd-7cb8fd363708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271262456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.1271262456
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.3199133437
Short name T74
Test name
Test status
Simulation time 511866222095 ps
CPU time 835.65 seconds
Started Jun 22 04:28:54 PM PDT 24
Finished Jun 22 04:42:51 PM PDT 24
Peak memory 216948 kb
Host smart-f40b84cf-d1a6-40f7-8939-8afe772ec7b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199133437 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.3199133437
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.2313626545
Short name T194
Test name
Test status
Simulation time 46264713409 ps
CPU time 84.5 seconds
Started Jun 22 04:29:52 PM PDT 24
Finished Jun 22 04:31:17 PM PDT 24
Peak memory 200452 kb
Host smart-a674f085-3985-4120-9725-35a3096a9be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313626545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.2313626545
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.1314455513
Short name T253
Test name
Test status
Simulation time 68969237663 ps
CPU time 60.74 seconds
Started Jun 22 04:30:20 PM PDT 24
Finished Jun 22 04:31:22 PM PDT 24
Peak memory 200544 kb
Host smart-603d670d-2f54-41a4-a730-515ed2ea3d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314455513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.1314455513
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.3687179603
Short name T243
Test name
Test status
Simulation time 41923808292 ps
CPU time 70.23 seconds
Started Jun 22 04:30:20 PM PDT 24
Finished Jun 22 04:31:30 PM PDT 24
Peak memory 200544 kb
Host smart-8fd20dbe-644b-4186-a691-eccac15eaa78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687179603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.3687179603
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.2381511102
Short name T177
Test name
Test status
Simulation time 121871278069 ps
CPU time 26.65 seconds
Started Jun 22 04:30:22 PM PDT 24
Finished Jun 22 04:30:49 PM PDT 24
Peak memory 200480 kb
Host smart-8fc8910f-7d42-45c8-ae70-59cf323d74a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381511102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.2381511102
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.2706826423
Short name T180
Test name
Test status
Simulation time 47528287116 ps
CPU time 24.31 seconds
Started Jun 22 04:30:21 PM PDT 24
Finished Jun 22 04:30:46 PM PDT 24
Peak memory 200508 kb
Host smart-1f228e2f-563b-4731-95e6-69fe50f12053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706826423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.2706826423
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.1755960740
Short name T221
Test name
Test status
Simulation time 117496904900 ps
CPU time 153.1 seconds
Started Jun 22 04:30:37 PM PDT 24
Finished Jun 22 04:33:12 PM PDT 24
Peak memory 200604 kb
Host smart-ab639dc4-a0d3-4e21-bea5-b520b68e9fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755960740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.1755960740
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.2216728281
Short name T250
Test name
Test status
Simulation time 110576218045 ps
CPU time 22.47 seconds
Started Jun 22 04:30:31 PM PDT 24
Finished Jun 22 04:30:54 PM PDT 24
Peak memory 200520 kb
Host smart-79027b23-c13f-4a01-997f-267872e0bad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216728281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.2216728281
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.3753209138
Short name T227
Test name
Test status
Simulation time 122007988746 ps
CPU time 197.7 seconds
Started Jun 22 04:30:36 PM PDT 24
Finished Jun 22 04:33:55 PM PDT 24
Peak memory 200652 kb
Host smart-9b4ff542-0fb1-4c49-98b9-0ecb2258d977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753209138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.3753209138
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.4168063201
Short name T268
Test name
Test status
Simulation time 60090305989 ps
CPU time 110.58 seconds
Started Jun 22 04:30:38 PM PDT 24
Finished Jun 22 04:32:30 PM PDT 24
Peak memory 200488 kb
Host smart-4262c8f4-1d9f-4fb7-b7bd-23614e04d92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168063201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.4168063201
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.2523130137
Short name T246
Test name
Test status
Simulation time 29841599370 ps
CPU time 41.65 seconds
Started Jun 22 04:30:44 PM PDT 24
Finished Jun 22 04:31:26 PM PDT 24
Peak memory 200316 kb
Host smart-f9233947-70ca-4237-b086-efd230d53e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523130137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.2523130137
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.3947030217
Short name T198
Test name
Test status
Simulation time 213828386893 ps
CPU time 53.77 seconds
Started Jun 22 04:30:37 PM PDT 24
Finished Jun 22 04:31:33 PM PDT 24
Peak memory 200480 kb
Host smart-c0e8122f-547a-4ff4-a6eb-fdf7e47e9c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947030217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.3947030217
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.3105799203
Short name T181
Test name
Test status
Simulation time 44835149245 ps
CPU time 15.18 seconds
Started Jun 22 04:30:56 PM PDT 24
Finished Jun 22 04:31:12 PM PDT 24
Peak memory 200484 kb
Host smart-9bf4c1c9-2947-49ed-ae80-1440440cdc13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105799203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.3105799203
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.2090747037
Short name T238
Test name
Test status
Simulation time 33960034546 ps
CPU time 56.77 seconds
Started Jun 22 04:30:48 PM PDT 24
Finished Jun 22 04:31:46 PM PDT 24
Peak memory 200484 kb
Host smart-1ef844b2-1e70-47f1-9e8d-52d979009fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090747037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.2090747037
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.3437084025
Short name T236
Test name
Test status
Simulation time 13285529530 ps
CPU time 15.18 seconds
Started Jun 22 04:30:55 PM PDT 24
Finished Jun 22 04:31:11 PM PDT 24
Peak memory 200436 kb
Host smart-6175c17f-5dcc-4048-80aa-adb496006742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437084025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.3437084025
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.2548659575
Short name T269
Test name
Test status
Simulation time 146877585417 ps
CPU time 30.01 seconds
Started Jun 22 04:31:02 PM PDT 24
Finished Jun 22 04:31:33 PM PDT 24
Peak memory 200548 kb
Host smart-9713f1ff-ff7d-4a5c-be48-c043a06718cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548659575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.2548659575
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_stress_all.3591655382
Short name T264
Test name
Test status
Simulation time 125152575686 ps
CPU time 44 seconds
Started Jun 22 04:29:46 PM PDT 24
Finished Jun 22 04:30:31 PM PDT 24
Peak memory 200476 kb
Host smart-f0a0da2a-c2a0-465a-899c-a05d4ee87614
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591655382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.3591655382
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.1492536816
Short name T248
Test name
Test status
Simulation time 144697809854 ps
CPU time 89.38 seconds
Started Jun 22 04:29:45 PM PDT 24
Finished Jun 22 04:31:15 PM PDT 24
Peak memory 200532 kb
Host smart-2c2c2184-71e2-43c4-a9f6-10218e1fd921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492536816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.1492536816
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.2833350037
Short name T183
Test name
Test status
Simulation time 320550216315 ps
CPU time 1295.39 seconds
Started Jun 22 04:30:05 PM PDT 24
Finished Jun 22 04:51:41 PM PDT 24
Peak memory 225196 kb
Host smart-fb901ec4-59f3-4db3-bd32-e9e1a143177b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833350037 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.2833350037
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.2741505593
Short name T1122
Test name
Test status
Simulation time 123593691 ps
CPU time 0.76 seconds
Started Jun 22 04:22:52 PM PDT 24
Finished Jun 22 04:22:53 PM PDT 24
Peak memory 196104 kb
Host smart-8951f529-5c81-4b8f-b235-df0b312cca40
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741505593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.2741505593
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.3340723246
Short name T1153
Test name
Test status
Simulation time 191978684 ps
CPU time 2.68 seconds
Started Jun 22 04:18:20 PM PDT 24
Finished Jun 22 04:18:23 PM PDT 24
Peak memory 197856 kb
Host smart-71113999-5f89-4963-ba2c-c696bf729862
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340723246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.3340723246
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.3927484525
Short name T1133
Test name
Test status
Simulation time 81892798 ps
CPU time 0.62 seconds
Started Jun 22 04:18:52 PM PDT 24
Finished Jun 22 04:18:53 PM PDT 24
Peak memory 195240 kb
Host smart-ac7e104a-1c34-4972-9a99-d3ad854b137a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927484525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.3927484525
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3098075916
Short name T1093
Test name
Test status
Simulation time 40436998 ps
CPU time 0.73 seconds
Started Jun 22 04:17:38 PM PDT 24
Finished Jun 22 04:17:39 PM PDT 24
Peak memory 199092 kb
Host smart-1a16b73b-7eda-411c-9a60-7b22dd43df90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098075916 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.3098075916
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.3018241084
Short name T1194
Test name
Test status
Simulation time 11581288 ps
CPU time 0.61 seconds
Started Jun 22 04:17:17 PM PDT 24
Finished Jun 22 04:17:18 PM PDT 24
Peak memory 195260 kb
Host smart-4f721cec-e593-44b7-92b5-45c0a83ac486
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018241084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.3018241084
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.2478410962
Short name T1167
Test name
Test status
Simulation time 12674738 ps
CPU time 0.59 seconds
Started Jun 22 04:17:18 PM PDT 24
Finished Jun 22 04:17:19 PM PDT 24
Peak memory 194184 kb
Host smart-db5b8a5e-d73b-460d-bd6d-fcec19eb99ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478410962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.2478410962
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1505291790
Short name T1124
Test name
Test status
Simulation time 200191678 ps
CPU time 0.64 seconds
Started Jun 22 04:18:13 PM PDT 24
Finished Jun 22 04:18:13 PM PDT 24
Peak memory 195484 kb
Host smart-34c7a753-3c03-460d-8c54-7d7d2bdf3d48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505291790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.1505291790
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.3076833994
Short name T1100
Test name
Test status
Simulation time 481244210 ps
CPU time 2.18 seconds
Started Jun 22 04:18:01 PM PDT 24
Finished Jun 22 04:18:04 PM PDT 24
Peak memory 199800 kb
Host smart-844620ee-5a06-463b-bdcf-8086dd7433c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076833994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.3076833994
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.3516950615
Short name T112
Test name
Test status
Simulation time 266420471 ps
CPU time 1.31 seconds
Started Jun 22 04:16:40 PM PDT 24
Finished Jun 22 04:16:43 PM PDT 24
Peak memory 198332 kb
Host smart-ade080ab-c65c-45c6-933a-c5bce90c9dcd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516950615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.3516950615
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.1596422502
Short name T83
Test name
Test status
Simulation time 38784707 ps
CPU time 0.62 seconds
Started Jun 22 04:18:01 PM PDT 24
Finished Jun 22 04:18:02 PM PDT 24
Peak memory 195232 kb
Host smart-49a895cf-de37-4915-9101-ac006d79aed3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596422502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.1596422502
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3888293265
Short name T1190
Test name
Test status
Simulation time 39935389 ps
CPU time 1.47 seconds
Started Jun 22 04:17:51 PM PDT 24
Finished Jun 22 04:17:53 PM PDT 24
Peak memory 197556 kb
Host smart-70b7a0b3-0783-4997-8990-76012993941e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888293265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.3888293265
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3801522980
Short name T1135
Test name
Test status
Simulation time 16269138 ps
CPU time 0.59 seconds
Started Jun 22 04:22:52 PM PDT 24
Finished Jun 22 04:22:52 PM PDT 24
Peak memory 195220 kb
Host smart-a0b77c23-4b79-4860-8e07-d2c29cf15c66
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801522980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.3801522980
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.752210679
Short name T1106
Test name
Test status
Simulation time 57991866 ps
CPU time 0.84 seconds
Started Jun 22 04:18:01 PM PDT 24
Finished Jun 22 04:18:03 PM PDT 24
Peak memory 199648 kb
Host smart-0f37bda2-ac53-43f8-bf52-0712e3e27e60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752210679 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.752210679
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.1394361356
Short name T1180
Test name
Test status
Simulation time 39249843 ps
CPU time 0.59 seconds
Started Jun 22 04:22:52 PM PDT 24
Finished Jun 22 04:22:52 PM PDT 24
Peak memory 195388 kb
Host smart-c3fb95ee-1793-4118-88e3-514a85652d52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394361356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.1394361356
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.1967829767
Short name T1156
Test name
Test status
Simulation time 13292951 ps
CPU time 0.57 seconds
Started Jun 22 04:22:37 PM PDT 24
Finished Jun 22 04:22:39 PM PDT 24
Peak memory 193596 kb
Host smart-2bdbf287-2ec3-43ab-8b10-822d2a5a92d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967829767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.1967829767
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2685263818
Short name T1218
Test name
Test status
Simulation time 28309888 ps
CPU time 0.7 seconds
Started Jun 22 04:18:01 PM PDT 24
Finished Jun 22 04:18:03 PM PDT 24
Peak memory 196660 kb
Host smart-5238ebf0-3dbe-43bf-88c9-caffb89d2fac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685263818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.2685263818
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.3785903943
Short name T1121
Test name
Test status
Simulation time 68646068 ps
CPU time 1.42 seconds
Started Jun 22 04:22:52 PM PDT 24
Finished Jun 22 04:22:54 PM PDT 24
Peak memory 199836 kb
Host smart-a61607bd-f0d5-4227-bf99-dd5b2b01e7f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785903943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.3785903943
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.47839120
Short name T1114
Test name
Test status
Simulation time 103973803 ps
CPU time 1.43 seconds
Started Jun 22 04:21:01 PM PDT 24
Finished Jun 22 04:21:03 PM PDT 24
Peak memory 199860 kb
Host smart-94076ffc-9bea-4445-9628-1c25ccb312ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47839120 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.47839120
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.2206845835
Short name T1163
Test name
Test status
Simulation time 17470999 ps
CPU time 0.62 seconds
Started Jun 22 04:22:48 PM PDT 24
Finished Jun 22 04:22:49 PM PDT 24
Peak memory 194584 kb
Host smart-20f3e6c7-9850-429f-9c09-8e8e7d065e38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206845835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.2206845835
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.2585978264
Short name T1202
Test name
Test status
Simulation time 14166137 ps
CPU time 0.54 seconds
Started Jun 22 04:21:41 PM PDT 24
Finished Jun 22 04:21:41 PM PDT 24
Peak memory 194256 kb
Host smart-a91a2103-a2ad-43f6-9189-5219dbf6e371
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585978264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.2585978264
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.2505898658
Short name T1144
Test name
Test status
Simulation time 21135968 ps
CPU time 0.66 seconds
Started Jun 22 04:21:12 PM PDT 24
Finished Jun 22 04:21:13 PM PDT 24
Peak memory 195864 kb
Host smart-57c81d4c-e3e5-4390-bf34-3cea09188ef6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505898658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.2505898658
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.2962146476
Short name T1132
Test name
Test status
Simulation time 94960751 ps
CPU time 1.75 seconds
Started Jun 22 04:22:40 PM PDT 24
Finished Jun 22 04:22:42 PM PDT 24
Peak memory 199644 kb
Host smart-cc794a5b-96a5-459e-9af3-b803bf71c989
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962146476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.2962146476
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2557366741
Short name T155
Test name
Test status
Simulation time 831038597 ps
CPU time 0.91 seconds
Started Jun 22 04:18:23 PM PDT 24
Finished Jun 22 04:18:24 PM PDT 24
Peak memory 199008 kb
Host smart-a28f901e-48e2-41b8-8ef4-632f7b6c5bc6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557366741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.2557366741
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1203271195
Short name T1197
Test name
Test status
Simulation time 27522305 ps
CPU time 1.4 seconds
Started Jun 22 04:19:29 PM PDT 24
Finished Jun 22 04:19:31 PM PDT 24
Peak memory 200248 kb
Host smart-fb0d2edd-5691-41af-b403-e6428340bdce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203271195 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.1203271195
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.892543270
Short name T93
Test name
Test status
Simulation time 49009889 ps
CPU time 0.64 seconds
Started Jun 22 04:18:31 PM PDT 24
Finished Jun 22 04:18:32 PM PDT 24
Peak memory 195508 kb
Host smart-943f9563-7de1-400f-aea1-d13162ffcff3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892543270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.892543270
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.3767244352
Short name T1200
Test name
Test status
Simulation time 18270818 ps
CPU time 0.6 seconds
Started Jun 22 04:22:10 PM PDT 24
Finished Jun 22 04:22:12 PM PDT 24
Peak memory 193576 kb
Host smart-6ed00053-8ecc-452b-b347-0b2e9442aef9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767244352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.3767244352
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.4061482949
Short name T1102
Test name
Test status
Simulation time 156354700 ps
CPU time 2.02 seconds
Started Jun 22 04:20:13 PM PDT 24
Finished Jun 22 04:20:15 PM PDT 24
Peak memory 200160 kb
Host smart-a0d8a5b1-20a7-4b53-bea2-65c9014d2595
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061482949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.4061482949
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.1491489342
Short name T116
Test name
Test status
Simulation time 141254705 ps
CPU time 0.9 seconds
Started Jun 22 04:21:22 PM PDT 24
Finished Jun 22 04:21:24 PM PDT 24
Peak memory 197228 kb
Host smart-2f51e0f9-ac89-4086-af61-1cce36bc4fbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491489342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.1491489342
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3555719208
Short name T1119
Test name
Test status
Simulation time 29089098 ps
CPU time 0.85 seconds
Started Jun 22 04:19:55 PM PDT 24
Finished Jun 22 04:19:56 PM PDT 24
Peak memory 199076 kb
Host smart-3a897068-b392-44aa-a790-4d53dcd353db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555719208 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.3555719208
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.135359531
Short name T1168
Test name
Test status
Simulation time 24169982 ps
CPU time 0.61 seconds
Started Jun 22 04:17:45 PM PDT 24
Finished Jun 22 04:17:46 PM PDT 24
Peak memory 195528 kb
Host smart-62405890-a60b-4924-b855-6ccd239a64f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135359531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.135359531
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.4219600565
Short name T1095
Test name
Test status
Simulation time 44071464 ps
CPU time 0.56 seconds
Started Jun 22 04:18:55 PM PDT 24
Finished Jun 22 04:18:56 PM PDT 24
Peak memory 194284 kb
Host smart-1c2571c7-76ff-432c-80c0-9704dcf9e1b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219600565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.4219600565
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1026772139
Short name T1120
Test name
Test status
Simulation time 32517506 ps
CPU time 0.8 seconds
Started Jun 22 04:22:13 PM PDT 24
Finished Jun 22 04:22:15 PM PDT 24
Peak memory 195064 kb
Host smart-c5521319-aa13-49e9-a0fc-4502d810dbaa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026772139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.1026772139
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.4033452682
Short name T1142
Test name
Test status
Simulation time 505824105 ps
CPU time 1.4 seconds
Started Jun 22 04:22:14 PM PDT 24
Finished Jun 22 04:22:16 PM PDT 24
Peak memory 199160 kb
Host smart-e27fea26-bbad-4c3c-b47c-ba1687b72924
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033452682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.4033452682
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.2537589688
Short name T107
Test name
Test status
Simulation time 97846653 ps
CPU time 0.99 seconds
Started Jun 22 04:20:59 PM PDT 24
Finished Jun 22 04:21:01 PM PDT 24
Peak memory 198880 kb
Host smart-a1a373ac-2fa9-49e6-a9d7-c3397aed520a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537589688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.2537589688
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3111649903
Short name T1094
Test name
Test status
Simulation time 24690083 ps
CPU time 0.64 seconds
Started Jun 22 04:22:13 PM PDT 24
Finished Jun 22 04:22:14 PM PDT 24
Peak memory 197548 kb
Host smart-5d9b4ee9-0bf9-44da-8e41-eb51d8935fe0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111649903 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.3111649903
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.3808608478
Short name T1164
Test name
Test status
Simulation time 12746401 ps
CPU time 0.67 seconds
Started Jun 22 04:23:08 PM PDT 24
Finished Jun 22 04:23:10 PM PDT 24
Peak memory 192948 kb
Host smart-16a9f176-8e90-4861-8f04-2bb15561559e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808608478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.3808608478
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.415934953
Short name T1111
Test name
Test status
Simulation time 15299657 ps
CPU time 0.55 seconds
Started Jun 22 04:22:25 PM PDT 24
Finished Jun 22 04:22:26 PM PDT 24
Peak memory 194260 kb
Host smart-20f0d099-90c2-4709-bc18-db313aaac3d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415934953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.415934953
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3882621014
Short name T98
Test name
Test status
Simulation time 19048972 ps
CPU time 0.73 seconds
Started Jun 22 04:23:08 PM PDT 24
Finished Jun 22 04:23:10 PM PDT 24
Peak memory 193360 kb
Host smart-15ef1233-6d8b-4d56-a756-c18a29ef33e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882621014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.3882621014
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.1579956235
Short name T1189
Test name
Test status
Simulation time 456800642 ps
CPU time 2.49 seconds
Started Jun 22 04:17:39 PM PDT 24
Finished Jun 22 04:17:41 PM PDT 24
Peak memory 199848 kb
Host smart-0ae1e969-b2f9-447e-b9a7-f3084090c3e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579956235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.1579956235
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.2398432112
Short name T108
Test name
Test status
Simulation time 776204557 ps
CPU time 1.39 seconds
Started Jun 22 04:20:08 PM PDT 24
Finished Jun 22 04:20:09 PM PDT 24
Peak memory 199224 kb
Host smart-134a7465-eac7-446b-8404-9b626ad37b48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398432112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.2398432112
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2436752332
Short name T1182
Test name
Test status
Simulation time 36517286 ps
CPU time 0.7 seconds
Started Jun 22 04:21:04 PM PDT 24
Finished Jun 22 04:21:05 PM PDT 24
Peak memory 197672 kb
Host smart-412c1904-2082-4a50-bba6-a12d43f07568
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436752332 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.2436752332
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.1470238871
Short name T1174
Test name
Test status
Simulation time 16732756 ps
CPU time 0.6 seconds
Started Jun 22 04:20:22 PM PDT 24
Finished Jun 22 04:20:23 PM PDT 24
Peak memory 195408 kb
Host smart-ac58c16d-5d01-44b2-944f-3f6357410c62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470238871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.1470238871
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.1751629222
Short name T1092
Test name
Test status
Simulation time 36722527 ps
CPU time 0.55 seconds
Started Jun 22 04:22:13 PM PDT 24
Finished Jun 22 04:22:14 PM PDT 24
Peak memory 194092 kb
Host smart-62b5857d-2cf2-4b71-93da-9dce7bb28673
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751629222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.1751629222
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.4189888795
Short name T101
Test name
Test status
Simulation time 56338877 ps
CPU time 0.67 seconds
Started Jun 22 04:22:29 PM PDT 24
Finished Jun 22 04:22:30 PM PDT 24
Peak memory 196816 kb
Host smart-bd56de8c-7adc-4da3-96f4-6b95fc67b9fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189888795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.4189888795
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.5337231
Short name T1179
Test name
Test status
Simulation time 449930637 ps
CPU time 2.15 seconds
Started Jun 22 04:22:13 PM PDT 24
Finished Jun 22 04:22:15 PM PDT 24
Peak memory 199148 kb
Host smart-b12a22c0-c1df-498f-8c07-eb118cb0815a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5337231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.5337231
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.1296690527
Short name T156
Test name
Test status
Simulation time 254995408 ps
CPU time 1.3 seconds
Started Jun 22 04:18:31 PM PDT 24
Finished Jun 22 04:18:33 PM PDT 24
Peak memory 199216 kb
Host smart-556a29f6-8313-4012-9e7c-fbc1af39ae2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296690527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.1296690527
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3507432278
Short name T1201
Test name
Test status
Simulation time 55338065 ps
CPU time 0.67 seconds
Started Jun 22 04:18:37 PM PDT 24
Finished Jun 22 04:18:39 PM PDT 24
Peak memory 198140 kb
Host smart-01bd7669-61f8-4287-b470-12ffa1351a1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507432278 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.3507432278
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.1394295063
Short name T81
Test name
Test status
Simulation time 24284461 ps
CPU time 0.62 seconds
Started Jun 22 04:17:40 PM PDT 24
Finished Jun 22 04:17:41 PM PDT 24
Peak memory 195928 kb
Host smart-7d0a3683-6089-47f0-a856-4acc21ee1220
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394295063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.1394295063
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.1242906255
Short name T1104
Test name
Test status
Simulation time 31064748 ps
CPU time 0.55 seconds
Started Jun 22 04:22:47 PM PDT 24
Finished Jun 22 04:22:47 PM PDT 24
Peak memory 194236 kb
Host smart-aa4a511e-aa22-4f8f-9c6f-c306b239b0a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242906255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.1242906255
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.3410636063
Short name T1191
Test name
Test status
Simulation time 15894106 ps
CPU time 0.63 seconds
Started Jun 22 04:19:23 PM PDT 24
Finished Jun 22 04:19:24 PM PDT 24
Peak memory 196372 kb
Host smart-85f46c66-74f4-426f-995c-bde1f74178e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410636063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.3410636063
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.3980531307
Short name T1116
Test name
Test status
Simulation time 119798044 ps
CPU time 2.43 seconds
Started Jun 22 04:18:49 PM PDT 24
Finished Jun 22 04:18:52 PM PDT 24
Peak memory 199824 kb
Host smart-8d545589-768b-47d7-97e9-2b8c4e8ce334
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980531307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.3980531307
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2355580149
Short name T1162
Test name
Test status
Simulation time 48550763 ps
CPU time 0.99 seconds
Started Jun 22 04:22:55 PM PDT 24
Finished Jun 22 04:22:56 PM PDT 24
Peak memory 198200 kb
Host smart-2d72548c-847a-40d8-bb01-a9831b02092a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355580149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.2355580149
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.283551
Short name T1217
Test name
Test status
Simulation time 53576827 ps
CPU time 0.82 seconds
Started Jun 22 04:17:36 PM PDT 24
Finished Jun 22 04:17:37 PM PDT 24
Peak memory 199976 kb
Host smart-bf0c0571-d13f-4d44-988d-f2adb0938a98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283551 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.283551
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.1922443363
Short name T1161
Test name
Test status
Simulation time 33535525 ps
CPU time 0.56 seconds
Started Jun 22 04:17:46 PM PDT 24
Finished Jun 22 04:17:47 PM PDT 24
Peak memory 195224 kb
Host smart-5b082d96-e799-4b42-bdd9-0ca12d3c391e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922443363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.1922443363
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.4254482623
Short name T1134
Test name
Test status
Simulation time 13146030 ps
CPU time 0.58 seconds
Started Jun 22 04:18:25 PM PDT 24
Finished Jun 22 04:18:26 PM PDT 24
Peak memory 194276 kb
Host smart-f624359e-a64c-4663-8106-f1076a6a3979
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254482623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.4254482623
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1844827068
Short name T1143
Test name
Test status
Simulation time 38099205 ps
CPU time 0.64 seconds
Started Jun 22 04:18:31 PM PDT 24
Finished Jun 22 04:18:32 PM PDT 24
Peak memory 195784 kb
Host smart-b2e33d59-abb1-458c-b550-73055ff5dc7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844827068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.1844827068
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.3338685617
Short name T1176
Test name
Test status
Simulation time 120727580 ps
CPU time 1.86 seconds
Started Jun 22 04:18:33 PM PDT 24
Finished Jun 22 04:18:35 PM PDT 24
Peak memory 200244 kb
Host smart-8a1bb3a6-9a16-4492-97ee-85137d9e7894
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338685617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.3338685617
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.1650119627
Short name T1193
Test name
Test status
Simulation time 17722782 ps
CPU time 0.66 seconds
Started Jun 22 04:19:42 PM PDT 24
Finished Jun 22 04:19:43 PM PDT 24
Peak memory 197420 kb
Host smart-7cdf7640-ac5c-4486-bfdf-230cc44ff061
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650119627 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.1650119627
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.597072248
Short name T76
Test name
Test status
Simulation time 22311049 ps
CPU time 0.57 seconds
Started Jun 22 04:22:53 PM PDT 24
Finished Jun 22 04:22:54 PM PDT 24
Peak memory 194920 kb
Host smart-06bc5d10-7d25-4a81-a7ce-cb1f27cfae24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597072248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.597072248
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.1082677441
Short name T1098
Test name
Test status
Simulation time 11312211 ps
CPU time 0.59 seconds
Started Jun 22 04:22:24 PM PDT 24
Finished Jun 22 04:22:25 PM PDT 24
Peak memory 193028 kb
Host smart-f5c046dc-defc-4647-acc9-97a98a020f9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082677441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.1082677441
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2314045441
Short name T100
Test name
Test status
Simulation time 55598714 ps
CPU time 0.8 seconds
Started Jun 22 04:22:39 PM PDT 24
Finished Jun 22 04:22:40 PM PDT 24
Peak memory 196136 kb
Host smart-6cbdbed9-e910-4e57-b228-58321ab65395
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314045441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.2314045441
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.2705038839
Short name T1175
Test name
Test status
Simulation time 99946807 ps
CPU time 1.2 seconds
Started Jun 22 04:22:25 PM PDT 24
Finished Jun 22 04:22:27 PM PDT 24
Peak memory 199596 kb
Host smart-2201762c-ac0c-4ca3-8597-0af05237fa71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705038839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.2705038839
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.2124211350
Short name T1206
Test name
Test status
Simulation time 91881426 ps
CPU time 0.97 seconds
Started Jun 22 04:18:55 PM PDT 24
Finished Jun 22 04:18:56 PM PDT 24
Peak memory 198632 kb
Host smart-1517ac37-7468-4736-9fee-4033a6e46307
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124211350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.2124211350
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.4163430583
Short name T1112
Test name
Test status
Simulation time 158466125 ps
CPU time 0.78 seconds
Started Jun 22 04:18:31 PM PDT 24
Finished Jun 22 04:18:32 PM PDT 24
Peak memory 199216 kb
Host smart-492a1c4b-7d62-462e-b7c2-255ef667049f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163430583 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.4163430583
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.2958994984
Short name T1118
Test name
Test status
Simulation time 16711138 ps
CPU time 0.61 seconds
Started Jun 22 04:20:08 PM PDT 24
Finished Jun 22 04:20:08 PM PDT 24
Peak memory 194676 kb
Host smart-092e9f8b-de27-4c29-ab07-fedd2acccff7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958994984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.2958994984
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3758047371
Short name T1216
Test name
Test status
Simulation time 21576491 ps
CPU time 0.7 seconds
Started Jun 22 04:21:26 PM PDT 24
Finished Jun 22 04:21:27 PM PDT 24
Peak memory 195884 kb
Host smart-fc2d0444-a3e7-469b-9654-0a436acd28c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758047371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.3758047371
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.2464760014
Short name T1199
Test name
Test status
Simulation time 539016558 ps
CPU time 2.03 seconds
Started Jun 22 04:18:30 PM PDT 24
Finished Jun 22 04:18:33 PM PDT 24
Peak memory 199884 kb
Host smart-850a7df2-0696-438b-b48f-8d17e151023b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464760014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.2464760014
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.894970527
Short name T1169
Test name
Test status
Simulation time 70178888 ps
CPU time 0.92 seconds
Started Jun 22 04:21:22 PM PDT 24
Finished Jun 22 04:21:24 PM PDT 24
Peak memory 198352 kb
Host smart-04429847-925c-45bf-8cc0-a5950393dd55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894970527 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.894970527
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.1855883064
Short name T1214
Test name
Test status
Simulation time 84272573 ps
CPU time 0.71 seconds
Started Jun 22 04:19:20 PM PDT 24
Finished Jun 22 04:19:21 PM PDT 24
Peak memory 195628 kb
Host smart-22201bdb-3012-46c0-81c0-b6bdc58b7b9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855883064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.1855883064
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.1273306214
Short name T1152
Test name
Test status
Simulation time 63676935 ps
CPU time 0.61 seconds
Started Jun 22 04:19:06 PM PDT 24
Finished Jun 22 04:19:07 PM PDT 24
Peak memory 194212 kb
Host smart-5304e1e4-0a0e-4021-b948-766545bec3a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273306214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.1273306214
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.328173762
Short name T1131
Test name
Test status
Simulation time 18141066 ps
CPU time 0.65 seconds
Started Jun 22 04:19:21 PM PDT 24
Finished Jun 22 04:19:22 PM PDT 24
Peak memory 196292 kb
Host smart-6fdbdbd7-1c61-48a7-8346-568871245d67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328173762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_csr
_outstanding.328173762
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.116061011
Short name T1146
Test name
Test status
Simulation time 43294390 ps
CPU time 1.98 seconds
Started Jun 22 04:21:22 PM PDT 24
Finished Jun 22 04:21:25 PM PDT 24
Peak memory 198400 kb
Host smart-7cd6269b-e90c-4310-8ddf-c7e93c798adc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116061011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.116061011
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1020351768
Short name T115
Test name
Test status
Simulation time 177487525 ps
CPU time 1.23 seconds
Started Jun 22 04:22:53 PM PDT 24
Finished Jun 22 04:22:55 PM PDT 24
Peak memory 197624 kb
Host smart-1a668fdc-fb2c-40a5-b44d-3d6556f93b98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020351768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.1020351768
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.583839801
Short name T1097
Test name
Test status
Simulation time 20496454 ps
CPU time 0.7 seconds
Started Jun 22 04:17:58 PM PDT 24
Finished Jun 22 04:18:00 PM PDT 24
Peak memory 192584 kb
Host smart-5c7afb3d-0cb0-4875-8d51-68229e6a25f8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583839801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.583839801
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2173893311
Short name T1207
Test name
Test status
Simulation time 93298141 ps
CPU time 1.46 seconds
Started Jun 22 04:17:38 PM PDT 24
Finished Jun 22 04:17:39 PM PDT 24
Peak memory 197432 kb
Host smart-96450603-321d-4775-84c5-2841977a2de8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173893311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.2173893311
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.1993063503
Short name T1208
Test name
Test status
Simulation time 15889592 ps
CPU time 0.56 seconds
Started Jun 22 04:18:12 PM PDT 24
Finished Jun 22 04:18:12 PM PDT 24
Peak memory 195208 kb
Host smart-226c3c01-395d-4e0e-8cc6-b1066618065e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993063503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.1993063503
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.898015623
Short name T1178
Test name
Test status
Simulation time 30968756 ps
CPU time 0.66 seconds
Started Jun 22 04:17:17 PM PDT 24
Finished Jun 22 04:17:18 PM PDT 24
Peak memory 197612 kb
Host smart-c035fcc9-2101-42de-8519-802d2922dc92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898015623 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.898015623
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.2177604733
Short name T95
Test name
Test status
Simulation time 17947101 ps
CPU time 0.71 seconds
Started Jun 22 04:18:11 PM PDT 24
Finished Jun 22 04:18:12 PM PDT 24
Peak memory 195312 kb
Host smart-a6e920fb-2c48-47f1-b935-9668c0c28adb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177604733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.2177604733
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.1014683589
Short name T1213
Test name
Test status
Simulation time 14129162 ps
CPU time 0.55 seconds
Started Jun 22 04:18:01 PM PDT 24
Finished Jun 22 04:18:02 PM PDT 24
Peak memory 194160 kb
Host smart-53fc1fe0-4e9a-4717-8abc-2dc537377fe9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014683589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.1014683589
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.599382
Short name T1128
Test name
Test status
Simulation time 42016570 ps
CPU time 0.69 seconds
Started Jun 22 04:17:17 PM PDT 24
Finished Jun 22 04:17:18 PM PDT 24
Peak memory 195596 kb
Host smart-17a332dc-feb5-4448-b82a-711e35a82363
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr_out
standing.599382
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.2850939177
Short name T1107
Test name
Test status
Simulation time 437295314 ps
CPU time 1.43 seconds
Started Jun 22 04:18:04 PM PDT 24
Finished Jun 22 04:18:05 PM PDT 24
Peak memory 199852 kb
Host smart-d4e7d231-7b5e-45bf-85ca-4ac838762d4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850939177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.2850939177
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.4093469416
Short name T110
Test name
Test status
Simulation time 326588681 ps
CPU time 0.99 seconds
Started Jun 22 04:18:01 PM PDT 24
Finished Jun 22 04:18:02 PM PDT 24
Peak memory 198820 kb
Host smart-f5b0552b-cd35-407e-92e7-75bc916dfa31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093469416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.4093469416
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.801968017
Short name T1101
Test name
Test status
Simulation time 12254883 ps
CPU time 0.57 seconds
Started Jun 22 04:20:14 PM PDT 24
Finished Jun 22 04:20:15 PM PDT 24
Peak memory 194204 kb
Host smart-6736ce62-55de-4061-987b-888ad776b4b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801968017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.801968017
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.494207488
Short name T1099
Test name
Test status
Simulation time 63297625 ps
CPU time 0.62 seconds
Started Jun 22 04:20:36 PM PDT 24
Finished Jun 22 04:20:37 PM PDT 24
Peak memory 194676 kb
Host smart-20e4a1e9-6fa6-499d-94e0-f99e2725ef2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494207488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.494207488
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.1597887591
Short name T1117
Test name
Test status
Simulation time 40034211 ps
CPU time 0.6 seconds
Started Jun 22 04:19:52 PM PDT 24
Finished Jun 22 04:19:53 PM PDT 24
Peak memory 194212 kb
Host smart-5dc8e371-ed81-4360-b474-b4202dd8cc81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597887591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.1597887591
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.2122915067
Short name T1222
Test name
Test status
Simulation time 48595774 ps
CPU time 0.58 seconds
Started Jun 22 04:20:22 PM PDT 24
Finished Jun 22 04:20:23 PM PDT 24
Peak memory 194276 kb
Host smart-bcc98d4a-5f54-4a39-b93f-0cde2642ccc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122915067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.2122915067
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.858513932
Short name T1188
Test name
Test status
Simulation time 108386641 ps
CPU time 0.56 seconds
Started Jun 22 04:18:54 PM PDT 24
Finished Jun 22 04:18:55 PM PDT 24
Peak memory 194284 kb
Host smart-7e71b2ae-6731-4113-b2a9-57140e7882db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858513932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.858513932
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.3437189428
Short name T1138
Test name
Test status
Simulation time 137874084 ps
CPU time 0.65 seconds
Started Jun 22 04:20:22 PM PDT 24
Finished Jun 22 04:20:23 PM PDT 24
Peak memory 194212 kb
Host smart-2df80d6a-5e0a-46d2-9fd6-56a7a997127e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437189428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.3437189428
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.862130608
Short name T1160
Test name
Test status
Simulation time 15748349 ps
CPU time 0.55 seconds
Started Jun 22 04:22:15 PM PDT 24
Finished Jun 22 04:22:16 PM PDT 24
Peak memory 194012 kb
Host smart-3b444f40-b996-43ec-a434-3cc831b3c04d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862130608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.862130608
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.2618318724
Short name T1203
Test name
Test status
Simulation time 33761623 ps
CPU time 0.58 seconds
Started Jun 22 04:22:31 PM PDT 24
Finished Jun 22 04:22:33 PM PDT 24
Peak memory 193516 kb
Host smart-70489859-113d-4d0e-a3ad-5ba85e27bbfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618318724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.2618318724
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.3661980056
Short name T1141
Test name
Test status
Simulation time 108936420 ps
CPU time 0.63 seconds
Started Jun 22 04:19:55 PM PDT 24
Finished Jun 22 04:19:56 PM PDT 24
Peak memory 194236 kb
Host smart-9eda5b0b-9cf6-4da2-ba62-33f33902640a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661980056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.3661980056
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.1167550079
Short name T1145
Test name
Test status
Simulation time 26834064 ps
CPU time 0.59 seconds
Started Jun 22 04:20:14 PM PDT 24
Finished Jun 22 04:20:15 PM PDT 24
Peak memory 194580 kb
Host smart-cef6555a-cdba-4547-a914-717abb1d5d0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167550079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.1167550079
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.3556823237
Short name T77
Test name
Test status
Simulation time 24344561 ps
CPU time 0.7 seconds
Started Jun 22 04:22:35 PM PDT 24
Finished Jun 22 04:22:36 PM PDT 24
Peak memory 192872 kb
Host smart-c8564377-f9b2-485d-87b1-308a88922aa1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556823237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.3556823237
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.2862025300
Short name T1171
Test name
Test status
Simulation time 84028535 ps
CPU time 2.22 seconds
Started Jun 22 04:17:58 PM PDT 24
Finished Jun 22 04:18:01 PM PDT 24
Peak memory 195100 kb
Host smart-c77b07b7-84e7-46ec-a2ec-d3e191f06607
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862025300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.2862025300
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.1898890815
Short name T1109
Test name
Test status
Simulation time 49850535 ps
CPU time 0.6 seconds
Started Jun 22 04:18:13 PM PDT 24
Finished Jun 22 04:18:14 PM PDT 24
Peak memory 195208 kb
Host smart-9fca85f9-cc03-462d-8bf5-71ac83ea7286
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898890815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.1898890815
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1879925109
Short name T1221
Test name
Test status
Simulation time 28004450 ps
CPU time 0.77 seconds
Started Jun 22 04:17:37 PM PDT 24
Finished Jun 22 04:17:38 PM PDT 24
Peak memory 198880 kb
Host smart-89f51186-1b0b-4ddc-8992-717ecded7b77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879925109 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.1879925109
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.2287094717
Short name T96
Test name
Test status
Simulation time 15233303 ps
CPU time 0.57 seconds
Started Jun 22 04:17:42 PM PDT 24
Finished Jun 22 04:17:43 PM PDT 24
Peak memory 195272 kb
Host smart-7f999b47-78eb-4523-bd64-dd5d05b86a2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287094717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.2287094717
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.3874511486
Short name T1130
Test name
Test status
Simulation time 47223012 ps
CPU time 0.55 seconds
Started Jun 22 04:17:42 PM PDT 24
Finished Jun 22 04:17:43 PM PDT 24
Peak memory 194220 kb
Host smart-7770ae11-86b5-47c5-a2ff-36793d2b7b04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874511486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.3874511486
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.3410007290
Short name T1187
Test name
Test status
Simulation time 22524064 ps
CPU time 0.64 seconds
Started Jun 22 04:18:01 PM PDT 24
Finished Jun 22 04:18:02 PM PDT 24
Peak memory 195604 kb
Host smart-798bd79c-8b1d-453c-872f-394e69057553
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410007290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.3410007290
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.3703773423
Short name T1159
Test name
Test status
Simulation time 22833246 ps
CPU time 1.19 seconds
Started Jun 22 04:22:35 PM PDT 24
Finished Jun 22 04:22:37 PM PDT 24
Peak memory 197984 kb
Host smart-b32dae92-ae1f-4ffc-8cec-6ba830120e66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703773423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.3703773423
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.828330487
Short name T113
Test name
Test status
Simulation time 141739629 ps
CPU time 0.96 seconds
Started Jun 22 04:18:37 PM PDT 24
Finished Jun 22 04:18:39 PM PDT 24
Peak memory 199192 kb
Host smart-22463e90-8eb9-4335-aa9e-77a1bc5745ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828330487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.828330487
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.1568767896
Short name T1148
Test name
Test status
Simulation time 12917831 ps
CPU time 0.57 seconds
Started Jun 22 04:18:37 PM PDT 24
Finished Jun 22 04:18:38 PM PDT 24
Peak memory 194576 kb
Host smart-5712ba4f-bd27-425e-a207-e81ac3c7a09e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568767896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.1568767896
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.1051998110
Short name T1219
Test name
Test status
Simulation time 40916167 ps
CPU time 0.61 seconds
Started Jun 22 04:23:06 PM PDT 24
Finished Jun 22 04:23:07 PM PDT 24
Peak memory 193540 kb
Host smart-945cde10-b899-446b-8afd-e4fa5b14c227
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051998110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.1051998110
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.1636377150
Short name T1151
Test name
Test status
Simulation time 15532340 ps
CPU time 0.62 seconds
Started Jun 22 04:21:03 PM PDT 24
Finished Jun 22 04:21:03 PM PDT 24
Peak memory 194580 kb
Host smart-dd76ec16-77b9-45a1-9c6f-99f0d1662d88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636377150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.1636377150
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.391261779
Short name T1195
Test name
Test status
Simulation time 79595075 ps
CPU time 0.59 seconds
Started Jun 22 04:18:02 PM PDT 24
Finished Jun 22 04:18:03 PM PDT 24
Peak memory 194188 kb
Host smart-da1ffce6-6863-4e88-8f53-6663bc99c476
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391261779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.391261779
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.1417998210
Short name T1170
Test name
Test status
Simulation time 13895937 ps
CPU time 0.64 seconds
Started Jun 22 04:23:08 PM PDT 24
Finished Jun 22 04:23:10 PM PDT 24
Peak memory 191836 kb
Host smart-b8f44346-5396-4663-b1c4-b32c8bf4d402
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417998210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.1417998210
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.1083109969
Short name T1105
Test name
Test status
Simulation time 23282743 ps
CPU time 0.6 seconds
Started Jun 22 04:23:08 PM PDT 24
Finished Jun 22 04:23:10 PM PDT 24
Peak memory 191924 kb
Host smart-048b33d3-f20a-48ba-9a98-3a54dede7045
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083109969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.1083109969
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.1378572837
Short name T1149
Test name
Test status
Simulation time 16269221 ps
CPU time 0.58 seconds
Started Jun 22 04:18:10 PM PDT 24
Finished Jun 22 04:18:11 PM PDT 24
Peak memory 194304 kb
Host smart-7c5ede89-bd9e-4abb-8baa-c845815d4312
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378572837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.1378572837
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.3316223608
Short name T1177
Test name
Test status
Simulation time 36207495 ps
CPU time 0.57 seconds
Started Jun 22 04:18:27 PM PDT 24
Finished Jun 22 04:18:28 PM PDT 24
Peak memory 194216 kb
Host smart-645419ff-8e8a-4564-ada3-7094e76c2eb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316223608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.3316223608
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.1733858910
Short name T1198
Test name
Test status
Simulation time 39543395 ps
CPU time 0.58 seconds
Started Jun 22 04:18:31 PM PDT 24
Finished Jun 22 04:18:32 PM PDT 24
Peak memory 194680 kb
Host smart-220544ad-d230-400b-8da6-3f753dc18ea5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733858910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.1733858910
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.4173976885
Short name T1196
Test name
Test status
Simulation time 24656887 ps
CPU time 0.61 seconds
Started Jun 22 04:17:49 PM PDT 24
Finished Jun 22 04:17:50 PM PDT 24
Peak memory 194252 kb
Host smart-e8d69ae4-9d77-4fbe-a92c-7633f976ce4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173976885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.4173976885
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.3723177759
Short name T82
Test name
Test status
Simulation time 29239317 ps
CPU time 0.77 seconds
Started Jun 22 04:18:12 PM PDT 24
Finished Jun 22 04:18:13 PM PDT 24
Peak memory 196180 kb
Host smart-6e918e78-8a0d-4e65-a24e-2394f08034b0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723177759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.3723177759
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.2521713312
Short name T78
Test name
Test status
Simulation time 123806661 ps
CPU time 1.4 seconds
Started Jun 22 04:17:58 PM PDT 24
Finished Jun 22 04:18:00 PM PDT 24
Peak memory 195632 kb
Host smart-f60c6d4c-818c-48a4-a1dd-2f5c218f9a5f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521713312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.2521713312
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.379355777
Short name T1096
Test name
Test status
Simulation time 40304163 ps
CPU time 0.59 seconds
Started Jun 22 04:18:01 PM PDT 24
Finished Jun 22 04:18:03 PM PDT 24
Peak memory 195240 kb
Host smart-1b21e952-d01e-4ce3-9e15-2748e0124310
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379355777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.379355777
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.357604761
Short name T1158
Test name
Test status
Simulation time 25561860 ps
CPU time 0.73 seconds
Started Jun 22 04:17:39 PM PDT 24
Finished Jun 22 04:17:40 PM PDT 24
Peak memory 198664 kb
Host smart-69acc737-c62d-4c54-a6a6-8f4f9121cd96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357604761 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.357604761
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.1345175211
Short name T1220
Test name
Test status
Simulation time 16722061 ps
CPU time 0.61 seconds
Started Jun 22 04:22:51 PM PDT 24
Finished Jun 22 04:22:52 PM PDT 24
Peak memory 195472 kb
Host smart-860d86fe-cbc4-46ea-9f76-4b63a8a33a41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345175211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.1345175211
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.1055812388
Short name T1154
Test name
Test status
Simulation time 187979175 ps
CPU time 0.59 seconds
Started Jun 22 04:18:37 PM PDT 24
Finished Jun 22 04:18:39 PM PDT 24
Peak memory 194580 kb
Host smart-efe78aea-16d8-4d8e-8a5b-ae8b0c1beaa9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055812388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.1055812388
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.968677650
Short name T1136
Test name
Test status
Simulation time 23207190 ps
CPU time 0.72 seconds
Started Jun 22 04:17:39 PM PDT 24
Finished Jun 22 04:17:40 PM PDT 24
Peak memory 196768 kb
Host smart-b935d6be-804f-45d5-bcb3-24bafeb928d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968677650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_
outstanding.968677650
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.3110854951
Short name T1140
Test name
Test status
Simulation time 106769100 ps
CPU time 2.14 seconds
Started Jun 22 04:22:51 PM PDT 24
Finished Jun 22 04:22:53 PM PDT 24
Peak memory 199776 kb
Host smart-847bea82-d428-4438-bdf8-441505a982ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110854951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.3110854951
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2315498065
Short name T1184
Test name
Test status
Simulation time 176679873 ps
CPU time 0.93 seconds
Started Jun 22 04:22:51 PM PDT 24
Finished Jun 22 04:22:52 PM PDT 24
Peak memory 198800 kb
Host smart-087c334b-28a6-4aff-88c6-c22d19c28871
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315498065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.2315498065
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.4277227350
Short name T1157
Test name
Test status
Simulation time 44288805 ps
CPU time 0.59 seconds
Started Jun 22 04:21:03 PM PDT 24
Finished Jun 22 04:21:04 PM PDT 24
Peak memory 194216 kb
Host smart-24b58889-53f6-4da4-a7b1-2879d44f5e7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277227350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.4277227350
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.1791442530
Short name T1205
Test name
Test status
Simulation time 29536595 ps
CPU time 0.6 seconds
Started Jun 22 04:21:04 PM PDT 24
Finished Jun 22 04:21:05 PM PDT 24
Peak memory 194216 kb
Host smart-626c92ba-da37-4be1-befb-df86b889b88f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791442530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.1791442530
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.699317918
Short name T1223
Test name
Test status
Simulation time 17144406 ps
CPU time 0.58 seconds
Started Jun 22 04:18:45 PM PDT 24
Finished Jun 22 04:18:46 PM PDT 24
Peak memory 194256 kb
Host smart-cd73c912-cab9-4974-bdfa-324a001aa0df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699317918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.699317918
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.2845839781
Short name T1183
Test name
Test status
Simulation time 21158991 ps
CPU time 0.53 seconds
Started Jun 22 04:17:42 PM PDT 24
Finished Jun 22 04:17:43 PM PDT 24
Peak memory 194276 kb
Host smart-559c9822-2ccb-4585-817c-893b9240356d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845839781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.2845839781
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.806173210
Short name T1129
Test name
Test status
Simulation time 15003317 ps
CPU time 0.58 seconds
Started Jun 22 04:17:40 PM PDT 24
Finished Jun 22 04:17:41 PM PDT 24
Peak memory 194672 kb
Host smart-eee2963b-ac3e-46c2-8dc6-6cd984070f32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806173210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.806173210
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.1561307782
Short name T1110
Test name
Test status
Simulation time 23234200 ps
CPU time 0.62 seconds
Started Jun 22 04:19:21 PM PDT 24
Finished Jun 22 04:19:22 PM PDT 24
Peak memory 194612 kb
Host smart-72e41cb0-b3b6-458f-b272-58799b61a38c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561307782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.1561307782
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.1694265750
Short name T1115
Test name
Test status
Simulation time 61906253 ps
CPU time 0.59 seconds
Started Jun 22 04:18:43 PM PDT 24
Finished Jun 22 04:18:43 PM PDT 24
Peak memory 194232 kb
Host smart-28a39c2c-a015-491e-9c1e-8df69583506c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694265750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.1694265750
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.3011578692
Short name T1212
Test name
Test status
Simulation time 21519953 ps
CPU time 0.54 seconds
Started Jun 22 04:19:15 PM PDT 24
Finished Jun 22 04:19:15 PM PDT 24
Peak memory 194148 kb
Host smart-0585c79b-bd9d-471e-bdc6-3b3386ab8936
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011578692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.3011578692
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.2073887220
Short name T1150
Test name
Test status
Simulation time 16199965 ps
CPU time 0.62 seconds
Started Jun 22 04:18:42 PM PDT 24
Finished Jun 22 04:18:43 PM PDT 24
Peak memory 194164 kb
Host smart-f44111d6-f5bf-480d-8aba-eac271a72a8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073887220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.2073887220
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.1835517609
Short name T1173
Test name
Test status
Simulation time 12536263 ps
CPU time 0.59 seconds
Started Jun 22 04:17:40 PM PDT 24
Finished Jun 22 04:17:41 PM PDT 24
Peak memory 194216 kb
Host smart-592c26de-f0d7-46fb-999b-e2614050881d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835517609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.1835517609
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1874544002
Short name T1127
Test name
Test status
Simulation time 57959279 ps
CPU time 0.82 seconds
Started Jun 22 04:17:58 PM PDT 24
Finished Jun 22 04:18:00 PM PDT 24
Peak memory 198192 kb
Host smart-c26162e1-bab2-467f-b7c5-857d51584bde
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874544002 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.1874544002
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.1675263661
Short name T1186
Test name
Test status
Simulation time 31477413 ps
CPU time 0.65 seconds
Started Jun 22 04:22:35 PM PDT 24
Finished Jun 22 04:22:36 PM PDT 24
Peak memory 193792 kb
Host smart-59be0ff0-f410-455e-9bc7-ee7cc16d70b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675263661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.1675263661
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.434120748
Short name T1165
Test name
Test status
Simulation time 19119856 ps
CPU time 0.56 seconds
Started Jun 22 04:18:13 PM PDT 24
Finished Jun 22 04:18:14 PM PDT 24
Peak memory 194148 kb
Host smart-999826a7-5a85-4e40-8036-104b843be2d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434120748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.434120748
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.988503585
Short name T97
Test name
Test status
Simulation time 24179202 ps
CPU time 0.65 seconds
Started Jun 22 04:17:39 PM PDT 24
Finished Jun 22 04:17:40 PM PDT 24
Peak memory 195384 kb
Host smart-c39ce979-94d7-430e-8b02-46c3588a3a7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988503585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr_
outstanding.988503585
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.1822891193
Short name T1185
Test name
Test status
Simulation time 89714048 ps
CPU time 1.81 seconds
Started Jun 22 04:18:34 PM PDT 24
Finished Jun 22 04:18:36 PM PDT 24
Peak memory 200244 kb
Host smart-f675a844-57c8-4e7a-ab12-a749abd4ca02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822891193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.1822891193
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.717471680
Short name T1192
Test name
Test status
Simulation time 159188587 ps
CPU time 1.29 seconds
Started Jun 22 04:17:58 PM PDT 24
Finished Jun 22 04:18:00 PM PDT 24
Peak memory 197108 kb
Host smart-0de5fc67-e26d-47f7-a768-41c60a43be6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717471680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.717471680
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1090765712
Short name T1166
Test name
Test status
Simulation time 100698757 ps
CPU time 0.77 seconds
Started Jun 22 04:18:04 PM PDT 24
Finished Jun 22 04:18:06 PM PDT 24
Peak memory 198428 kb
Host smart-100988da-3519-4235-ac60-67e5517c4961
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090765712 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.1090765712
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.3873424782
Short name T1155
Test name
Test status
Simulation time 24294107 ps
CPU time 0.61 seconds
Started Jun 22 04:17:38 PM PDT 24
Finished Jun 22 04:17:39 PM PDT 24
Peak memory 195276 kb
Host smart-9f7a6e52-b2db-46c1-88a6-29145efc46c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873424782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.3873424782
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.455556539
Short name T1209
Test name
Test status
Simulation time 41576931 ps
CPU time 0.56 seconds
Started Jun 22 04:16:57 PM PDT 24
Finished Jun 22 04:16:58 PM PDT 24
Peak memory 194248 kb
Host smart-0d0c597d-78d0-41ba-8fd4-31f6ee4505f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455556539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.455556539
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.2942448793
Short name T1181
Test name
Test status
Simulation time 195633395 ps
CPU time 0.69 seconds
Started Jun 22 04:18:45 PM PDT 24
Finished Jun 22 04:18:46 PM PDT 24
Peak memory 195504 kb
Host smart-d686564a-cecd-4d14-be44-a7966c8d7e37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942448793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.2942448793
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.2055350693
Short name T1108
Test name
Test status
Simulation time 26706488 ps
CPU time 1.37 seconds
Started Jun 22 04:17:58 PM PDT 24
Finished Jun 22 04:18:00 PM PDT 24
Peak memory 198448 kb
Host smart-251e2512-739d-4b91-8b86-6aa6de846a81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055350693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.2055350693
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.298073603
Short name T1215
Test name
Test status
Simulation time 326222169 ps
CPU time 1.33 seconds
Started Jun 22 04:18:15 PM PDT 24
Finished Jun 22 04:18:17 PM PDT 24
Peak memory 198948 kb
Host smart-ce47ac20-e6cb-472f-b12b-9ee00f64bc58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298073603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.298073603
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1466411197
Short name T1123
Test name
Test status
Simulation time 31906020 ps
CPU time 0.83 seconds
Started Jun 22 04:20:14 PM PDT 24
Finished Jun 22 04:20:16 PM PDT 24
Peak memory 199656 kb
Host smart-614a760e-e583-41fb-9b97-aa83fffd54b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466411197 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.1466411197
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.308069586
Short name T1126
Test name
Test status
Simulation time 49866267 ps
CPU time 0.62 seconds
Started Jun 22 04:18:42 PM PDT 24
Finished Jun 22 04:18:43 PM PDT 24
Peak memory 195276 kb
Host smart-f6d4376a-3d98-4c80-94f5-702972014261
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308069586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.308069586
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.973758197
Short name T1172
Test name
Test status
Simulation time 41878633 ps
CPU time 0.6 seconds
Started Jun 22 04:19:14 PM PDT 24
Finished Jun 22 04:19:14 PM PDT 24
Peak memory 194672 kb
Host smart-217eaf34-bcb1-43d9-8154-4036084d05b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973758197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.973758197
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1758970183
Short name T99
Test name
Test status
Simulation time 99367699 ps
CPU time 0.63 seconds
Started Jun 22 04:18:30 PM PDT 24
Finished Jun 22 04:18:31 PM PDT 24
Peak memory 195596 kb
Host smart-95d801c6-79ec-48bd-a0ee-b95b722eed60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758970183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.1758970183
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.4152488784
Short name T1103
Test name
Test status
Simulation time 68871049 ps
CPU time 0.96 seconds
Started Jun 22 04:18:33 PM PDT 24
Finished Jun 22 04:18:35 PM PDT 24
Peak memory 199716 kb
Host smart-79b22136-fbe5-46e6-a799-6059580ccf40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152488784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.4152488784
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3587767308
Short name T109
Test name
Test status
Simulation time 3739734844 ps
CPU time 1.82 seconds
Started Jun 22 04:22:51 PM PDT 24
Finished Jun 22 04:22:53 PM PDT 24
Peak memory 199728 kb
Host smart-5fdd1370-5b8b-4f02-978b-2075be9d139d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587767308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.3587767308
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.4082994509
Short name T1204
Test name
Test status
Simulation time 32292560 ps
CPU time 0.84 seconds
Started Jun 22 04:22:25 PM PDT 24
Finished Jun 22 04:22:26 PM PDT 24
Peak memory 199420 kb
Host smart-5d875203-2335-496e-9bb6-fa9466505fe4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082994509 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.4082994509
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.2180716553
Short name T1147
Test name
Test status
Simulation time 14029217 ps
CPU time 0.6 seconds
Started Jun 22 04:18:30 PM PDT 24
Finished Jun 22 04:18:31 PM PDT 24
Peak memory 195260 kb
Host smart-c5455f8f-a1ca-4024-a01f-af4240c00325
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180716553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.2180716553
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.2159442170
Short name T1211
Test name
Test status
Simulation time 52069787 ps
CPU time 0.59 seconds
Started Jun 22 04:18:30 PM PDT 24
Finished Jun 22 04:18:31 PM PDT 24
Peak memory 194232 kb
Host smart-4f762ca0-cc1a-4e7f-8f46-a112578d5903
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159442170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.2159442170
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.648334559
Short name T1125
Test name
Test status
Simulation time 12625959 ps
CPU time 0.64 seconds
Started Jun 22 04:19:22 PM PDT 24
Finished Jun 22 04:19:23 PM PDT 24
Peak memory 195560 kb
Host smart-1f59bc5d-844f-4b9a-a0d9-f21b296af4ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648334559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr_
outstanding.648334559
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.88282708
Short name T1210
Test name
Test status
Simulation time 54578881 ps
CPU time 1.37 seconds
Started Jun 22 04:18:32 PM PDT 24
Finished Jun 22 04:18:33 PM PDT 24
Peak memory 199824 kb
Host smart-7df66571-0047-4b50-a620-fd3e71de0404
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88282708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.88282708
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2070081802
Short name T1224
Test name
Test status
Simulation time 167226968 ps
CPU time 0.93 seconds
Started Jun 22 04:19:23 PM PDT 24
Finished Jun 22 04:19:24 PM PDT 24
Peak memory 198856 kb
Host smart-8ea756e1-7c06-48a0-b11b-40694239cab2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070081802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.2070081802
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.2440961928
Short name T1137
Test name
Test status
Simulation time 52252741 ps
CPU time 0.78 seconds
Started Jun 22 04:19:42 PM PDT 24
Finished Jun 22 04:19:43 PM PDT 24
Peak memory 199664 kb
Host smart-20c40ae7-bf9d-4696-b60b-f5eb272da8ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440961928 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.2440961928
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.1229176827
Short name T79
Test name
Test status
Simulation time 42834366 ps
CPU time 0.62 seconds
Started Jun 22 04:18:32 PM PDT 24
Finished Jun 22 04:18:34 PM PDT 24
Peak memory 195684 kb
Host smart-a0e8c9a7-31bf-43fa-8a4a-2b67256da8ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229176827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.1229176827
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.1092191717
Short name T1139
Test name
Test status
Simulation time 14462142 ps
CPU time 0.6 seconds
Started Jun 22 04:19:03 PM PDT 24
Finished Jun 22 04:19:04 PM PDT 24
Peak memory 194176 kb
Host smart-f3096961-31a3-4b03-8516-b8ce44826f24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092191717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.1092191717
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2912514151
Short name T102
Test name
Test status
Simulation time 37041350 ps
CPU time 0.71 seconds
Started Jun 22 04:22:53 PM PDT 24
Finished Jun 22 04:22:54 PM PDT 24
Peak memory 194100 kb
Host smart-0a1356d0-c240-4772-8da6-c3905337ed8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912514151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.2912514151
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.4127773862
Short name T1113
Test name
Test status
Simulation time 111341535 ps
CPU time 2.4 seconds
Started Jun 22 04:17:36 PM PDT 24
Finished Jun 22 04:17:38 PM PDT 24
Peak memory 200252 kb
Host smart-0fdb569b-dbe8-4380-9ab2-7f5aa8a5e9cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127773862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.4127773862
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.2621461058
Short name T106
Test name
Test status
Simulation time 40023919 ps
CPU time 0.97 seconds
Started Jun 22 04:19:04 PM PDT 24
Finished Jun 22 04:19:05 PM PDT 24
Peak memory 198792 kb
Host smart-1584061e-c688-42ca-8ba6-9f8fdf74febf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621461058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.2621461058
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_fifo_full.3252238692
Short name T730
Test name
Test status
Simulation time 203146016242 ps
CPU time 394.38 seconds
Started Jun 22 04:27:50 PM PDT 24
Finished Jun 22 04:34:25 PM PDT 24
Peak memory 200844 kb
Host smart-c227d473-60c4-46ad-ba0b-c60ce67f30d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252238692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.3252238692
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.1251231802
Short name T624
Test name
Test status
Simulation time 24760163937 ps
CPU time 43.26 seconds
Started Jun 22 04:27:53 PM PDT 24
Finished Jun 22 04:28:37 PM PDT 24
Peak memory 200456 kb
Host smart-9865665f-c0a1-4536-8e96-82f5564952f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251231802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.1251231802
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.2058520348
Short name T754
Test name
Test status
Simulation time 99991775398 ps
CPU time 168.85 seconds
Started Jun 22 04:27:47 PM PDT 24
Finished Jun 22 04:30:36 PM PDT 24
Peak memory 200528 kb
Host smart-5e848f2e-7bc0-4e12-8c66-9c3686906552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058520348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.2058520348
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.484608434
Short name T668
Test name
Test status
Simulation time 12828619407 ps
CPU time 5.94 seconds
Started Jun 22 04:27:55 PM PDT 24
Finished Jun 22 04:28:02 PM PDT 24
Peak memory 196800 kb
Host smart-d9451778-d610-4f6f-978f-d129cfec259b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484608434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.484608434
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.3287610424
Short name T464
Test name
Test status
Simulation time 226884923449 ps
CPU time 1240.09 seconds
Started Jun 22 04:27:49 PM PDT 24
Finished Jun 22 04:48:30 PM PDT 24
Peak memory 200492 kb
Host smart-b6c829b6-2a72-4411-8887-1de1da9a4441
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3287610424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.3287610424
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.1019191636
Short name T418
Test name
Test status
Simulation time 11368680943 ps
CPU time 24.01 seconds
Started Jun 22 04:27:59 PM PDT 24
Finished Jun 22 04:28:24 PM PDT 24
Peak memory 200276 kb
Host smart-1505ff6c-e3a2-4fef-bcf4-346775f7001c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019191636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.1019191636
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_perf.264490678
Short name T1068
Test name
Test status
Simulation time 4679649594 ps
CPU time 118.69 seconds
Started Jun 22 04:28:00 PM PDT 24
Finished Jun 22 04:30:01 PM PDT 24
Peak memory 200432 kb
Host smart-81840347-cd42-49cc-96b8-58c86e592201
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=264490678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.264490678
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.2599725641
Short name T1000
Test name
Test status
Simulation time 1272993215 ps
CPU time 2.65 seconds
Started Jun 22 04:27:54 PM PDT 24
Finished Jun 22 04:27:58 PM PDT 24
Peak memory 198500 kb
Host smart-7fd37519-a66d-474e-965e-d9e968f52020
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2599725641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.2599725641
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.3008125314
Short name T283
Test name
Test status
Simulation time 85618962549 ps
CPU time 34.3 seconds
Started Jun 22 04:27:53 PM PDT 24
Finished Jun 22 04:28:29 PM PDT 24
Peak memory 199940 kb
Host smart-8d1c1737-b58b-45d3-be26-94b456128c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008125314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.3008125314
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.720670470
Short name T533
Test name
Test status
Simulation time 3507991874 ps
CPU time 2.08 seconds
Started Jun 22 04:27:52 PM PDT 24
Finished Jun 22 04:27:55 PM PDT 24
Peak memory 196592 kb
Host smart-54740db1-bda3-48fb-bceb-c2ab628121da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720670470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.720670470
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_sec_cm.1823602611
Short name T34
Test name
Test status
Simulation time 59885035 ps
CPU time 0.83 seconds
Started Jun 22 04:27:53 PM PDT 24
Finished Jun 22 04:27:55 PM PDT 24
Peak memory 218916 kb
Host smart-381f597b-6359-4765-844e-1faaaaf23cdb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823602611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.1823602611
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/0.uart_smoke.4035779210
Short name T934
Test name
Test status
Simulation time 5284277236 ps
CPU time 11.94 seconds
Started Jun 22 04:27:49 PM PDT 24
Finished Jun 22 04:28:01 PM PDT 24
Peak memory 200480 kb
Host smart-dda5eb06-739b-462f-b0a6-f5a1b8c359e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035779210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.4035779210
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.1602739239
Short name T978
Test name
Test status
Simulation time 320377227448 ps
CPU time 653.99 seconds
Started Jun 22 04:28:04 PM PDT 24
Finished Jun 22 04:39:00 PM PDT 24
Peak memory 200868 kb
Host smart-fba7d6cf-3a04-462e-973a-9cd666fa6bdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602739239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.1602739239
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.3088519135
Short name T545
Test name
Test status
Simulation time 1155976293 ps
CPU time 4.39 seconds
Started Jun 22 04:27:46 PM PDT 24
Finished Jun 22 04:27:51 PM PDT 24
Peak memory 199312 kb
Host smart-813ffcf7-2a01-4803-84e6-a93e038209fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088519135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.3088519135
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.833313491
Short name T645
Test name
Test status
Simulation time 101530746415 ps
CPU time 8.26 seconds
Started Jun 22 04:27:57 PM PDT 24
Finished Jun 22 04:28:07 PM PDT 24
Peak memory 198244 kb
Host smart-428e4e7a-eeac-4600-986c-71ef480eb70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833313491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.833313491
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.4186816297
Short name T881
Test name
Test status
Simulation time 14407884 ps
CPU time 0.54 seconds
Started Jun 22 04:27:57 PM PDT 24
Finished Jun 22 04:27:59 PM PDT 24
Peak memory 195860 kb
Host smart-baa7c9ac-d48b-4bd8-a2b5-0de0ab1d798f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186816297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.4186816297
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.482041132
Short name T736
Test name
Test status
Simulation time 64469248572 ps
CPU time 49.61 seconds
Started Jun 22 04:27:43 PM PDT 24
Finished Jun 22 04:28:33 PM PDT 24
Peak memory 200464 kb
Host smart-4a22b411-e7ca-4cfc-a242-4ab5ebe8ac3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482041132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.482041132
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.495202019
Short name T842
Test name
Test status
Simulation time 104530639561 ps
CPU time 159.78 seconds
Started Jun 22 04:27:53 PM PDT 24
Finished Jun 22 04:30:34 PM PDT 24
Peak memory 200488 kb
Host smart-e4125673-2b3d-45c8-b562-72c6a2b63503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495202019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.495202019
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_intr.1298188335
Short name T459
Test name
Test status
Simulation time 70278047291 ps
CPU time 101.89 seconds
Started Jun 22 04:27:56 PM PDT 24
Finished Jun 22 04:29:39 PM PDT 24
Peak memory 200372 kb
Host smart-01f1cc6d-6ad1-4eaa-867a-ca81bb0597f0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298188335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.1298188335
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.1767149673
Short name T749
Test name
Test status
Simulation time 75082296141 ps
CPU time 351.71 seconds
Started Jun 22 04:27:57 PM PDT 24
Finished Jun 22 04:33:50 PM PDT 24
Peak memory 200920 kb
Host smart-9ca84a6f-4557-4ab6-a86e-9626c38ef652
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1767149673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.1767149673
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.3563875435
Short name T497
Test name
Test status
Simulation time 3799985270 ps
CPU time 3.16 seconds
Started Jun 22 04:27:57 PM PDT 24
Finished Jun 22 04:28:02 PM PDT 24
Peak memory 199736 kb
Host smart-dbb6daa7-c511-449d-b416-8d93f2a871f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563875435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.3563875435
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_perf.1167836800
Short name T1011
Test name
Test status
Simulation time 10693061028 ps
CPU time 519.15 seconds
Started Jun 22 04:27:55 PM PDT 24
Finished Jun 22 04:36:36 PM PDT 24
Peak memory 200576 kb
Host smart-c72ec56f-b033-4974-9a1d-c6eda8017de4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1167836800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.1167836800
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.793268862
Short name T536
Test name
Test status
Simulation time 1616468633 ps
CPU time 1.59 seconds
Started Jun 22 04:27:59 PM PDT 24
Finished Jun 22 04:28:02 PM PDT 24
Peak memory 198564 kb
Host smart-06a9716c-9018-499b-a9ee-ab354bb57460
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=793268862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.793268862
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.2728842182
Short name T405
Test name
Test status
Simulation time 49796434918 ps
CPU time 39.33 seconds
Started Jun 22 04:27:49 PM PDT 24
Finished Jun 22 04:28:29 PM PDT 24
Peak memory 200436 kb
Host smart-8dfd47e2-f21e-466f-9117-4e2d0abcab2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728842182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.2728842182
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.540884651
Short name T767
Test name
Test status
Simulation time 3682186720 ps
CPU time 2.27 seconds
Started Jun 22 04:27:49 PM PDT 24
Finished Jun 22 04:27:52 PM PDT 24
Peak memory 197040 kb
Host smart-01f6bdeb-a89f-4a1c-9370-431c5b91a200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540884651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.540884651
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.1953812140
Short name T118
Test name
Test status
Simulation time 78241107 ps
CPU time 0.89 seconds
Started Jun 22 04:27:49 PM PDT 24
Finished Jun 22 04:27:51 PM PDT 24
Peak memory 219032 kb
Host smart-f99b9f33-b5fe-4b39-a837-c5a0573a57c7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953812140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.1953812140
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.2087136872
Short name T728
Test name
Test status
Simulation time 543328692 ps
CPU time 1.26 seconds
Started Jun 22 04:27:56 PM PDT 24
Finished Jun 22 04:27:58 PM PDT 24
Peak memory 198848 kb
Host smart-b0e07b36-db8f-4315-93d4-914b66f65834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087136872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.2087136872
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.2496457355
Short name T20
Test name
Test status
Simulation time 649527412 ps
CPU time 2.37 seconds
Started Jun 22 04:27:51 PM PDT 24
Finished Jun 22 04:27:54 PM PDT 24
Peak memory 199244 kb
Host smart-91d67a7b-d581-423f-8277-cb44acc21830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496457355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.2496457355
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.23307030
Short name T970
Test name
Test status
Simulation time 19674369478 ps
CPU time 7.95 seconds
Started Jun 22 04:27:51 PM PDT 24
Finished Jun 22 04:28:00 PM PDT 24
Peak memory 199044 kb
Host smart-5dc2766f-17bf-4248-a817-e33a0c8585e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23307030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.23307030
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.2145498118
Short name T1029
Test name
Test status
Simulation time 13066027 ps
CPU time 0.56 seconds
Started Jun 22 04:28:34 PM PDT 24
Finished Jun 22 04:28:35 PM PDT 24
Peak memory 195884 kb
Host smart-30b27873-0e0b-494d-b3ba-50271298b668
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145498118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.2145498118
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.2774669895
Short name T963
Test name
Test status
Simulation time 76448753506 ps
CPU time 79.41 seconds
Started Jun 22 04:28:28 PM PDT 24
Finished Jun 22 04:29:48 PM PDT 24
Peak memory 200512 kb
Host smart-820f743a-928e-43de-8271-ea16d3243e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774669895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.2774669895
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.457861490
Short name T122
Test name
Test status
Simulation time 19668087658 ps
CPU time 18.97 seconds
Started Jun 22 04:28:07 PM PDT 24
Finished Jun 22 04:28:26 PM PDT 24
Peak memory 200620 kb
Host smart-be76d695-89bb-4968-aecd-09af99e0ec8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457861490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.457861490
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.824359543
Short name T543
Test name
Test status
Simulation time 18402071918 ps
CPU time 26.59 seconds
Started Jun 22 04:28:11 PM PDT 24
Finished Jun 22 04:28:39 PM PDT 24
Peak memory 200332 kb
Host smart-26156e02-c863-43aa-9dcc-ba7b0c80a6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824359543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.824359543
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.1997518437
Short name T425
Test name
Test status
Simulation time 41744033855 ps
CPU time 36.73 seconds
Started Jun 22 04:28:07 PM PDT 24
Finished Jun 22 04:28:44 PM PDT 24
Peak memory 200576 kb
Host smart-e5be19ab-1b40-4af2-a233-f163af7eaa08
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997518437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.1997518437
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.1014818710
Short name T723
Test name
Test status
Simulation time 122459504758 ps
CPU time 373.12 seconds
Started Jun 22 04:28:22 PM PDT 24
Finished Jun 22 04:34:36 PM PDT 24
Peak memory 200512 kb
Host smart-36eff324-a850-4660-af52-570e68c625a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1014818710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.1014818710
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.1345446981
Short name T385
Test name
Test status
Simulation time 5454854085 ps
CPU time 8.47 seconds
Started Jun 22 04:28:31 PM PDT 24
Finished Jun 22 04:28:40 PM PDT 24
Peak memory 200560 kb
Host smart-8e0c4e03-4571-4306-83d0-424fa85a5382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345446981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.1345446981
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_perf.3758729153
Short name T969
Test name
Test status
Simulation time 15390524140 ps
CPU time 195.07 seconds
Started Jun 22 04:28:15 PM PDT 24
Finished Jun 22 04:31:32 PM PDT 24
Peak memory 200512 kb
Host smart-7ecfbc3a-70f5-4de6-8ad0-9dee6f9212ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3758729153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.3758729153
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.3981289754
Short name T369
Test name
Test status
Simulation time 4849540526 ps
CPU time 9.65 seconds
Started Jun 22 04:28:29 PM PDT 24
Finished Jun 22 04:28:39 PM PDT 24
Peak memory 199740 kb
Host smart-89ef5b4f-1fa6-4ac7-9fb4-ced03a0a408e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3981289754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.3981289754
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.3497587340
Short name T501
Test name
Test status
Simulation time 104176004985 ps
CPU time 11.81 seconds
Started Jun 22 04:28:17 PM PDT 24
Finished Jun 22 04:28:29 PM PDT 24
Peak memory 200260 kb
Host smart-bb72b268-1f92-4e3b-8dc1-a9f7cd9b5500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497587340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.3497587340
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.612659726
Short name T701
Test name
Test status
Simulation time 41487698595 ps
CPU time 15.89 seconds
Started Jun 22 04:28:27 PM PDT 24
Finished Jun 22 04:28:44 PM PDT 24
Peak memory 196280 kb
Host smart-65ee074e-4a42-4fa5-bac0-936a5a911f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612659726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.612659726
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.2239986126
Short name T623
Test name
Test status
Simulation time 491044069 ps
CPU time 1.98 seconds
Started Jun 22 04:28:08 PM PDT 24
Finished Jun 22 04:28:11 PM PDT 24
Peak memory 200796 kb
Host smart-3cf75103-ccf9-46a8-b4aa-9f5ac2ae0e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239986126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.2239986126
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.1167116845
Short name T1031
Test name
Test status
Simulation time 277908267117 ps
CPU time 490.66 seconds
Started Jun 22 04:28:29 PM PDT 24
Finished Jun 22 04:36:40 PM PDT 24
Peak memory 200516 kb
Host smart-74d46450-d7e5-4ace-95f6-4a2ede6a1aca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167116845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.1167116845
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.2256638422
Short name T399
Test name
Test status
Simulation time 1690455513 ps
CPU time 2.23 seconds
Started Jun 22 04:28:13 PM PDT 24
Finished Jun 22 04:28:16 PM PDT 24
Peak memory 199292 kb
Host smart-d17e6a33-1ced-45c3-82d2-ec0385a1df60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256638422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.2256638422
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.4073622470
Short name T627
Test name
Test status
Simulation time 42626909344 ps
CPU time 13.9 seconds
Started Jun 22 04:28:24 PM PDT 24
Finished Jun 22 04:28:39 PM PDT 24
Peak memory 200436 kb
Host smart-0618cbb5-f8e5-44e4-becc-eafa398825a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073622470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.4073622470
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.3961846430
Short name T555
Test name
Test status
Simulation time 17429560447 ps
CPU time 28.32 seconds
Started Jun 22 04:30:26 PM PDT 24
Finished Jun 22 04:30:55 PM PDT 24
Peak memory 200448 kb
Host smart-8b533b54-a766-4b1b-ad04-f5c96f7a9284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961846430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3961846430
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.2431575790
Short name T362
Test name
Test status
Simulation time 27439325972 ps
CPU time 13.62 seconds
Started Jun 22 04:30:20 PM PDT 24
Finished Jun 22 04:30:35 PM PDT 24
Peak memory 200572 kb
Host smart-a818be17-47ba-43ee-8060-007f17991412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431575790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.2431575790
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.723433542
Short name T816
Test name
Test status
Simulation time 69895225478 ps
CPU time 54.05 seconds
Started Jun 22 04:30:32 PM PDT 24
Finished Jun 22 04:31:27 PM PDT 24
Peak memory 200532 kb
Host smart-33546821-c96a-4d11-9440-2f3621839ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723433542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.723433542
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.723582558
Short name T263
Test name
Test status
Simulation time 89225341083 ps
CPU time 134.75 seconds
Started Jun 22 04:30:22 PM PDT 24
Finished Jun 22 04:32:37 PM PDT 24
Peak memory 200600 kb
Host smart-949ff124-03e1-484d-9447-d184b37f9f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723582558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.723582558
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.1023607809
Short name T1001
Test name
Test status
Simulation time 152304022540 ps
CPU time 57.54 seconds
Started Jun 22 04:30:29 PM PDT 24
Finished Jun 22 04:31:27 PM PDT 24
Peak memory 200752 kb
Host smart-758276d2-c32b-4fd3-a46e-f265665cf8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023607809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.1023607809
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.3684530617
Short name T559
Test name
Test status
Simulation time 96326805644 ps
CPU time 149.9 seconds
Started Jun 22 04:30:21 PM PDT 24
Finished Jun 22 04:32:52 PM PDT 24
Peak memory 200508 kb
Host smart-ede31f97-47ce-48d5-bc7e-4ef63f23a161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684530617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.3684530617
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.3975579853
Short name T475
Test name
Test status
Simulation time 124120173221 ps
CPU time 59.67 seconds
Started Jun 22 04:30:33 PM PDT 24
Finished Jun 22 04:31:33 PM PDT 24
Peak memory 200592 kb
Host smart-4ada40f3-e13b-4a4c-af81-4f3708a742a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975579853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.3975579853
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.1240062938
Short name T633
Test name
Test status
Simulation time 20821599439 ps
CPU time 41.43 seconds
Started Jun 22 04:30:28 PM PDT 24
Finished Jun 22 04:31:09 PM PDT 24
Peak memory 200284 kb
Host smart-6dd63289-f7a7-490d-b48e-a9344e61a29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240062938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.1240062938
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.1029940284
Short name T573
Test name
Test status
Simulation time 157983835307 ps
CPU time 56.8 seconds
Started Jun 22 04:30:20 PM PDT 24
Finished Jun 22 04:31:17 PM PDT 24
Peak memory 200348 kb
Host smart-58652f88-3802-49cb-8e72-20a84e1fade5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029940284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.1029940284
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.3306472824
Short name T761
Test name
Test status
Simulation time 38432418 ps
CPU time 0.53 seconds
Started Jun 22 04:28:22 PM PDT 24
Finished Jun 22 04:28:23 PM PDT 24
Peak memory 195316 kb
Host smart-16472462-557a-4fa2-a4d7-9d61cdc67224
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306472824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.3306472824
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.3865339124
Short name T566
Test name
Test status
Simulation time 131326323224 ps
CPU time 369.7 seconds
Started Jun 22 04:28:13 PM PDT 24
Finished Jun 22 04:34:23 PM PDT 24
Peak memory 200468 kb
Host smart-2858adf2-7852-490e-a5b0-90d2883a5049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865339124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.3865339124
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.193445521
Short name T60
Test name
Test status
Simulation time 103290719796 ps
CPU time 96.3 seconds
Started Jun 22 04:28:11 PM PDT 24
Finished Jun 22 04:29:48 PM PDT 24
Peak memory 200436 kb
Host smart-cb5ef4cb-b9e3-4d28-9546-517db92e59b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193445521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.193445521
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.3760476864
Short name T206
Test name
Test status
Simulation time 18225177403 ps
CPU time 15.68 seconds
Started Jun 22 04:28:16 PM PDT 24
Finished Jun 22 04:28:33 PM PDT 24
Peak memory 200508 kb
Host smart-35b2a7b2-4969-4052-9521-e14b392f4a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760476864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.3760476864
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.3213896376
Short name T1060
Test name
Test status
Simulation time 216992824206 ps
CPU time 107.51 seconds
Started Jun 22 04:28:16 PM PDT 24
Finished Jun 22 04:30:05 PM PDT 24
Peak memory 200428 kb
Host smart-d00412f3-d49a-4cc9-9096-5a61f46ba576
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213896376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.3213896376
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.2576566749
Short name T614
Test name
Test status
Simulation time 69050753705 ps
CPU time 329.97 seconds
Started Jun 22 04:28:15 PM PDT 24
Finished Jun 22 04:33:46 PM PDT 24
Peak memory 200396 kb
Host smart-3c2976c1-9e52-42b9-a325-8479b1e855d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2576566749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.2576566749
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.562251856
Short name T1076
Test name
Test status
Simulation time 1479062214 ps
CPU time 1.9 seconds
Started Jun 22 04:28:13 PM PDT 24
Finished Jun 22 04:28:16 PM PDT 24
Peak memory 198116 kb
Host smart-a9e3c120-faa8-4ffe-b390-77b327abb01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562251856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.562251856
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_perf.2408389239
Short name T450
Test name
Test status
Simulation time 17558172052 ps
CPU time 226.78 seconds
Started Jun 22 04:28:09 PM PDT 24
Finished Jun 22 04:31:57 PM PDT 24
Peak memory 200452 kb
Host smart-4f505505-fd50-4f6e-ab78-e1b08d47ebd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2408389239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.2408389239
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.1964903676
Short name T381
Test name
Test status
Simulation time 3515589023 ps
CPU time 7.84 seconds
Started Jun 22 04:28:14 PM PDT 24
Finished Jun 22 04:28:23 PM PDT 24
Peak memory 199564 kb
Host smart-95febc47-ffc3-4786-ae62-1148d65793bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1964903676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.1964903676
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.2107376651
Short name T906
Test name
Test status
Simulation time 15956976444 ps
CPU time 26.31 seconds
Started Jun 22 04:28:07 PM PDT 24
Finished Jun 22 04:28:34 PM PDT 24
Peak memory 200508 kb
Host smart-7aebe6b7-b6f5-4768-b270-724eb06bed2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107376651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.2107376651
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.2655614046
Short name T12
Test name
Test status
Simulation time 1641869215 ps
CPU time 1.49 seconds
Started Jun 22 04:28:14 PM PDT 24
Finished Jun 22 04:28:16 PM PDT 24
Peak memory 196144 kb
Host smart-8e1ca1ea-51f6-4c19-a0ba-ff57ef8a0918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655614046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.2655614046
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.2597294436
Short name T710
Test name
Test status
Simulation time 11588257323 ps
CPU time 19.43 seconds
Started Jun 22 04:28:28 PM PDT 24
Finished Jun 22 04:28:47 PM PDT 24
Peak memory 200412 kb
Host smart-2f513e10-a723-4247-bedf-1c9427a6b8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597294436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.2597294436
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.3295060596
Short name T659
Test name
Test status
Simulation time 77703557337 ps
CPU time 90.02 seconds
Started Jun 22 04:28:24 PM PDT 24
Finished Jun 22 04:29:55 PM PDT 24
Peak memory 200428 kb
Host smart-23c94cd9-4597-4641-a98c-3dcdd14353d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295060596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.3295060596
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.1139003677
Short name T688
Test name
Test status
Simulation time 515967195 ps
CPU time 1.3 seconds
Started Jun 22 04:28:16 PM PDT 24
Finished Jun 22 04:28:18 PM PDT 24
Peak memory 198728 kb
Host smart-3cd9901c-d5f5-4ef1-a49e-480ee200f664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139003677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.1139003677
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.3097175557
Short name T215
Test name
Test status
Simulation time 33798316067 ps
CPU time 64.44 seconds
Started Jun 22 04:30:23 PM PDT 24
Finished Jun 22 04:31:28 PM PDT 24
Peak memory 200544 kb
Host smart-0ace5450-46ef-4b7a-bcfd-cbd50957d69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097175557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.3097175557
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.3767996728
Short name T755
Test name
Test status
Simulation time 28789110363 ps
CPU time 52.53 seconds
Started Jun 22 04:30:26 PM PDT 24
Finished Jun 22 04:31:19 PM PDT 24
Peak memory 200392 kb
Host smart-23b79375-07c0-400a-8bb3-7c3bd247b9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767996728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.3767996728
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.220321852
Short name T147
Test name
Test status
Simulation time 8330457058 ps
CPU time 13.31 seconds
Started Jun 22 04:30:22 PM PDT 24
Finished Jun 22 04:30:36 PM PDT 24
Peak memory 200508 kb
Host smart-72a95897-5632-468d-9e6c-732fa96cb278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220321852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.220321852
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.883246028
Short name T341
Test name
Test status
Simulation time 85680301430 ps
CPU time 45.7 seconds
Started Jun 22 04:30:21 PM PDT 24
Finished Jun 22 04:31:07 PM PDT 24
Peak memory 200524 kb
Host smart-f7a84650-4e6d-44d3-b61d-05ae31dea55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883246028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.883246028
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.2425076598
Short name T729
Test name
Test status
Simulation time 25173165204 ps
CPU time 23.92 seconds
Started Jun 22 04:30:20 PM PDT 24
Finished Jun 22 04:30:45 PM PDT 24
Peak memory 200616 kb
Host smart-eb39d4b3-1b3b-4658-a2b3-62de20c3d734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425076598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.2425076598
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.2872516123
Short name T89
Test name
Test status
Simulation time 56745815121 ps
CPU time 20.36 seconds
Started Jun 22 04:30:29 PM PDT 24
Finished Jun 22 04:30:50 PM PDT 24
Peak memory 200256 kb
Host smart-7f9ad6ba-eeab-4e55-a379-f4a89c41d652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872516123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.2872516123
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.2567355133
Short name T780
Test name
Test status
Simulation time 73308946822 ps
CPU time 44.1 seconds
Started Jun 22 04:31:22 PM PDT 24
Finished Jun 22 04:32:07 PM PDT 24
Peak memory 200592 kb
Host smart-0a3324da-c4c6-4c7e-bff4-76b8639ed115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567355133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.2567355133
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.3309565358
Short name T279
Test name
Test status
Simulation time 83971958847 ps
CPU time 75.37 seconds
Started Jun 22 04:30:22 PM PDT 24
Finished Jun 22 04:31:38 PM PDT 24
Peak memory 200168 kb
Host smart-262dc415-a644-4950-b401-d9ba3ce357af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309565358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.3309565358
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.1221884766
Short name T1081
Test name
Test status
Simulation time 39568717 ps
CPU time 0.56 seconds
Started Jun 22 04:28:17 PM PDT 24
Finished Jun 22 04:28:18 PM PDT 24
Peak memory 195864 kb
Host smart-0d1567b5-29ac-4119-94a7-8894e20cc846
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221884766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.1221884766
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.3654207869
Short name T496
Test name
Test status
Simulation time 83363589605 ps
CPU time 140.85 seconds
Started Jun 22 04:28:28 PM PDT 24
Finished Jun 22 04:30:49 PM PDT 24
Peak memory 200548 kb
Host smart-ee0f0d4f-8d17-455e-a59a-48f510284fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654207869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.3654207869
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.3344371179
Short name T676
Test name
Test status
Simulation time 27801595327 ps
CPU time 42.01 seconds
Started Jun 22 04:28:25 PM PDT 24
Finished Jun 22 04:29:07 PM PDT 24
Peak memory 200460 kb
Host smart-d0c548d3-8744-4e60-ba53-f0559deb88f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344371179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.3344371179
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.1577962287
Short name T48
Test name
Test status
Simulation time 82604804028 ps
CPU time 42.79 seconds
Started Jun 22 04:28:13 PM PDT 24
Finished Jun 22 04:28:57 PM PDT 24
Peak memory 200916 kb
Host smart-9f80a395-dc82-441f-806d-b4c6b0d9b15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577962287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.1577962287
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.742960151
Short name T824
Test name
Test status
Simulation time 46667865185 ps
CPU time 91.87 seconds
Started Jun 22 04:28:07 PM PDT 24
Finished Jun 22 04:29:39 PM PDT 24
Peak memory 200472 kb
Host smart-4faba7de-f362-4713-bf8f-5617f668fe2b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742960151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.742960151
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.1519796723
Short name T565
Test name
Test status
Simulation time 228228757650 ps
CPU time 302.92 seconds
Started Jun 22 04:28:24 PM PDT 24
Finished Jun 22 04:33:27 PM PDT 24
Peak memory 200416 kb
Host smart-31f84ff3-b0dd-46aa-84f1-7ef9a968bef5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1519796723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.1519796723
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.2716022716
Short name T136
Test name
Test status
Simulation time 5411379356 ps
CPU time 12.43 seconds
Started Jun 22 04:28:10 PM PDT 24
Finished Jun 22 04:28:23 PM PDT 24
Peak memory 200184 kb
Host smart-bde9aaed-7e79-4c66-b636-1cee8faae0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716022716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.2716022716
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_perf.1363062411
Short name T796
Test name
Test status
Simulation time 23212898667 ps
CPU time 1065.3 seconds
Started Jun 22 04:28:27 PM PDT 24
Finished Jun 22 04:46:13 PM PDT 24
Peak memory 200512 kb
Host smart-c22bbde0-a385-41ae-b9b4-3c6bf87885f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1363062411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.1363062411
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.1838120478
Short name T510
Test name
Test status
Simulation time 1916463180 ps
CPU time 5.86 seconds
Started Jun 22 04:28:10 PM PDT 24
Finished Jun 22 04:28:16 PM PDT 24
Peak memory 199472 kb
Host smart-a7b6748b-4713-4b69-b437-06dbde07b594
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1838120478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.1838120478
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.1595068037
Short name T415
Test name
Test status
Simulation time 14986385120 ps
CPU time 24.92 seconds
Started Jun 22 04:28:09 PM PDT 24
Finished Jun 22 04:28:34 PM PDT 24
Peak memory 200460 kb
Host smart-21041cbd-cb76-480c-bebb-19e36c052646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595068037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.1595068037
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.3512168589
Short name T720
Test name
Test status
Simulation time 2809445258 ps
CPU time 1.59 seconds
Started Jun 22 04:28:23 PM PDT 24
Finished Jun 22 04:28:25 PM PDT 24
Peak memory 196468 kb
Host smart-c538327e-2139-471b-9071-fa19bfd34639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512168589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.3512168589
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.1744321287
Short name T709
Test name
Test status
Simulation time 938762126 ps
CPU time 3 seconds
Started Jun 22 04:28:25 PM PDT 24
Finished Jun 22 04:28:29 PM PDT 24
Peak memory 200472 kb
Host smart-c4ee59ed-2901-4e02-b00a-02693e0676c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744321287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.1744321287
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.3173537055
Short name T276
Test name
Test status
Simulation time 176950300887 ps
CPU time 235.49 seconds
Started Jun 22 04:28:28 PM PDT 24
Finished Jun 22 04:32:24 PM PDT 24
Peak memory 200456 kb
Host smart-4d493037-706f-47a3-956f-906708e238a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173537055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.3173537055
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.4015223429
Short name T394
Test name
Test status
Simulation time 6447768918 ps
CPU time 44.83 seconds
Started Jun 22 04:28:15 PM PDT 24
Finished Jun 22 04:29:01 PM PDT 24
Peak memory 200256 kb
Host smart-ed3d0d1d-0f9c-4fe4-b6a6-12824bea5da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015223429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.4015223429
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.70479937
Short name T943
Test name
Test status
Simulation time 51727526760 ps
CPU time 85.86 seconds
Started Jun 22 04:28:28 PM PDT 24
Finished Jun 22 04:29:55 PM PDT 24
Peak memory 200480 kb
Host smart-fb7c45a2-7a04-428b-9e6e-10eb650910d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70479937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.70479937
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.4283960560
Short name T781
Test name
Test status
Simulation time 36467716140 ps
CPU time 31.71 seconds
Started Jun 22 04:30:18 PM PDT 24
Finished Jun 22 04:30:50 PM PDT 24
Peak memory 200544 kb
Host smart-e7aa422d-aa68-421f-b7de-276c2852d2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283960560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.4283960560
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.3911699684
Short name T530
Test name
Test status
Simulation time 51138541393 ps
CPU time 21.96 seconds
Started Jun 22 04:30:33 PM PDT 24
Finished Jun 22 04:30:55 PM PDT 24
Peak memory 200616 kb
Host smart-d0509cb4-ca66-41a0-a7d7-20bbe5019f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911699684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.3911699684
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.2776769167
Short name T912
Test name
Test status
Simulation time 39762974741 ps
CPU time 17.57 seconds
Started Jun 22 04:30:19 PM PDT 24
Finished Jun 22 04:30:37 PM PDT 24
Peak memory 200556 kb
Host smart-586f3a28-7381-420d-9326-f72209b3bea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776769167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.2776769167
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.1285569245
Short name T353
Test name
Test status
Simulation time 26559745843 ps
CPU time 26.98 seconds
Started Jun 22 04:30:31 PM PDT 24
Finished Jun 22 04:30:59 PM PDT 24
Peak memory 200484 kb
Host smart-d9ce309b-a0ea-4c2f-bd7a-de0d8fd73ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285569245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.1285569245
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.2210746849
Short name T514
Test name
Test status
Simulation time 30490025023 ps
CPU time 41.55 seconds
Started Jun 22 04:30:22 PM PDT 24
Finished Jun 22 04:31:04 PM PDT 24
Peak memory 200464 kb
Host smart-44c8c6ba-33a7-45a9-9797-e504fbb824df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210746849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.2210746849
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.120008065
Short name T873
Test name
Test status
Simulation time 32450423924 ps
CPU time 57.9 seconds
Started Jun 22 04:30:20 PM PDT 24
Finished Jun 22 04:31:18 PM PDT 24
Peak memory 200536 kb
Host smart-5157ae45-818a-4319-ac01-084b0a4b89d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120008065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.120008065
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.931335177
Short name T864
Test name
Test status
Simulation time 61436621307 ps
CPU time 241.81 seconds
Started Jun 22 04:30:33 PM PDT 24
Finished Jun 22 04:34:35 PM PDT 24
Peak memory 200456 kb
Host smart-ac926b88-8d90-4a08-a0ae-2aad55f0a286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931335177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.931335177
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.2504677311
Short name T240
Test name
Test status
Simulation time 63451822270 ps
CPU time 117.09 seconds
Started Jun 22 04:30:21 PM PDT 24
Finished Jun 22 04:32:19 PM PDT 24
Peak memory 200576 kb
Host smart-1bc706e0-a518-49d6-8aa4-9e7072ef795a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504677311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.2504677311
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.154529422
Short name T836
Test name
Test status
Simulation time 13949341 ps
CPU time 0.55 seconds
Started Jun 22 04:28:40 PM PDT 24
Finished Jun 22 04:28:42 PM PDT 24
Peak memory 195828 kb
Host smart-97660d39-bf3f-415d-960e-47c09aa75a84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154529422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.154529422
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.1965090548
Short name T163
Test name
Test status
Simulation time 80330795607 ps
CPU time 40.33 seconds
Started Jun 22 04:28:11 PM PDT 24
Finished Jun 22 04:28:52 PM PDT 24
Peak memory 200528 kb
Host smart-93d5a2ab-6122-4b21-b517-895543fe88c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965090548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.1965090548
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.169829121
Short name T849
Test name
Test status
Simulation time 64066948516 ps
CPU time 47.35 seconds
Started Jun 22 04:28:14 PM PDT 24
Finished Jun 22 04:29:03 PM PDT 24
Peak memory 200548 kb
Host smart-156e7144-2205-4d33-ae46-67bd3eb9af43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169829121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.169829121
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.2703464756
Short name T654
Test name
Test status
Simulation time 25816823270 ps
CPU time 55.22 seconds
Started Jun 22 04:28:15 PM PDT 24
Finished Jun 22 04:29:11 PM PDT 24
Peak memory 200468 kb
Host smart-bff3471a-c1fe-4b54-8ddd-1f65ddb3b9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703464756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.2703464756
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.396555992
Short name T151
Test name
Test status
Simulation time 40039145950 ps
CPU time 28.07 seconds
Started Jun 22 04:28:16 PM PDT 24
Finished Jun 22 04:28:45 PM PDT 24
Peak memory 199972 kb
Host smart-0c364832-0ffd-4bca-9582-8a89f6a83152
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396555992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.396555992
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.4224575779
Short name T635
Test name
Test status
Simulation time 52843544856 ps
CPU time 73.44 seconds
Started Jun 22 04:28:15 PM PDT 24
Finished Jun 22 04:29:30 PM PDT 24
Peak memory 200420 kb
Host smart-3eaa5a38-e12e-4957-a623-ffa8659de422
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4224575779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.4224575779
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.1725546362
Short name T417
Test name
Test status
Simulation time 8269703589 ps
CPU time 16.68 seconds
Started Jun 22 04:28:27 PM PDT 24
Finished Jun 22 04:28:44 PM PDT 24
Peak memory 200560 kb
Host smart-4c846934-716d-4e28-bd43-4c34af06e801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725546362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.1725546362
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.3260863290
Short name T662
Test name
Test status
Simulation time 110876803375 ps
CPU time 55.54 seconds
Started Jun 22 04:28:26 PM PDT 24
Finished Jun 22 04:29:22 PM PDT 24
Peak memory 200548 kb
Host smart-b4512027-916f-4d27-b917-e5ef669e5420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260863290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.3260863290
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.566007583
Short name T570
Test name
Test status
Simulation time 20523848400 ps
CPU time 268.58 seconds
Started Jun 22 04:28:31 PM PDT 24
Finished Jun 22 04:33:00 PM PDT 24
Peak memory 200476 kb
Host smart-24ff71f9-f826-4ac0-a4e6-7d17eb0cc9da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=566007583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.566007583
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.3502033972
Short name T856
Test name
Test status
Simulation time 4613788188 ps
CPU time 36.88 seconds
Started Jun 22 04:28:28 PM PDT 24
Finished Jun 22 04:29:06 PM PDT 24
Peak memory 199820 kb
Host smart-5eb5025e-4a4d-498f-b60d-d7fb91d7de42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3502033972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.3502033972
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.2237915864
Short name T548
Test name
Test status
Simulation time 13855811580 ps
CPU time 22.16 seconds
Started Jun 22 04:28:18 PM PDT 24
Finished Jun 22 04:28:41 PM PDT 24
Peak memory 200432 kb
Host smart-388611f9-e3e0-46bf-a115-00fcca0937e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237915864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.2237915864
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.287206184
Short name T1056
Test name
Test status
Simulation time 32879415244 ps
CPU time 23.49 seconds
Started Jun 22 04:28:14 PM PDT 24
Finished Jun 22 04:28:39 PM PDT 24
Peak memory 196252 kb
Host smart-fe1a3d94-17bb-4c43-b0d8-cbf992c59afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287206184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.287206184
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.2135613534
Short name T1047
Test name
Test status
Simulation time 727951153 ps
CPU time 1.46 seconds
Started Jun 22 04:28:14 PM PDT 24
Finished Jun 22 04:28:17 PM PDT 24
Peak memory 199296 kb
Host smart-dc80c62f-fa34-45dc-8396-470ea67a3dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135613534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.2135613534
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.832681463
Short name T1062
Test name
Test status
Simulation time 165674716606 ps
CPU time 78.43 seconds
Started Jun 22 04:28:34 PM PDT 24
Finished Jun 22 04:29:53 PM PDT 24
Peak memory 200436 kb
Host smart-b2a008c3-da31-4abc-9dec-a883c30ee17b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832681463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.832681463
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.764609037
Short name T831
Test name
Test status
Simulation time 2177986994 ps
CPU time 2.45 seconds
Started Jun 22 04:28:40 PM PDT 24
Finished Jun 22 04:28:43 PM PDT 24
Peak memory 199004 kb
Host smart-2354f0de-a0be-4b1f-b577-42356d65701f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764609037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.764609037
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.3298147746
Short name T919
Test name
Test status
Simulation time 17978114221 ps
CPU time 25.86 seconds
Started Jun 22 04:28:23 PM PDT 24
Finished Jun 22 04:28:50 PM PDT 24
Peak memory 200440 kb
Host smart-535b515f-f723-41bc-8505-c4755720b8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298147746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.3298147746
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.2878560264
Short name T500
Test name
Test status
Simulation time 146079010223 ps
CPU time 16.34 seconds
Started Jun 22 04:30:20 PM PDT 24
Finished Jun 22 04:30:38 PM PDT 24
Peak memory 200288 kb
Host smart-936d0d54-980c-49bf-bc9e-f699efc59685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878560264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.2878560264
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.1129800095
Short name T936
Test name
Test status
Simulation time 148976094402 ps
CPU time 23.42 seconds
Started Jun 22 04:30:34 PM PDT 24
Finished Jun 22 04:30:58 PM PDT 24
Peak memory 200352 kb
Host smart-026b565c-76b1-464e-bacc-4ceab85feeeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129800095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.1129800095
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.2531987484
Short name T303
Test name
Test status
Simulation time 102870130518 ps
CPU time 95.24 seconds
Started Jun 22 04:30:30 PM PDT 24
Finished Jun 22 04:32:06 PM PDT 24
Peak memory 200484 kb
Host smart-dc83597a-44df-4818-a9d8-994d3a64e556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531987484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.2531987484
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.1838515487
Short name T226
Test name
Test status
Simulation time 19089896287 ps
CPU time 40.81 seconds
Started Jun 22 04:30:30 PM PDT 24
Finished Jun 22 04:31:11 PM PDT 24
Peak memory 200912 kb
Host smart-ec656d46-6765-4210-a228-835112cfebf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838515487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.1838515487
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.2665106677
Short name T550
Test name
Test status
Simulation time 183579988301 ps
CPU time 42.44 seconds
Started Jun 22 04:30:20 PM PDT 24
Finished Jun 22 04:31:03 PM PDT 24
Peak memory 200600 kb
Host smart-60f3dcc7-bc6b-42e5-be0a-b4fec27b1b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665106677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.2665106677
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.3099035316
Short name T712
Test name
Test status
Simulation time 11092268945 ps
CPU time 17.01 seconds
Started Jun 22 04:30:30 PM PDT 24
Finished Jun 22 04:30:48 PM PDT 24
Peak memory 200372 kb
Host smart-02a474b1-1427-482a-a3fc-d3c2625da306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099035316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.3099035316
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.815616167
Short name T820
Test name
Test status
Simulation time 107482473169 ps
CPU time 164.38 seconds
Started Jun 22 04:30:30 PM PDT 24
Finished Jun 22 04:33:15 PM PDT 24
Peak memory 200540 kb
Host smart-84fa538d-99d2-4f3a-a657-9b252d8d797a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815616167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.815616167
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.2034862761
Short name T437
Test name
Test status
Simulation time 40931603 ps
CPU time 0.62 seconds
Started Jun 22 04:28:18 PM PDT 24
Finished Jun 22 04:28:19 PM PDT 24
Peak memory 196152 kb
Host smart-806332b5-e896-4c24-b564-a56512c65b34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034862761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.2034862761
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.105806772
Short name T926
Test name
Test status
Simulation time 64305831344 ps
CPU time 57.19 seconds
Started Jun 22 04:28:15 PM PDT 24
Finished Jun 22 04:29:13 PM PDT 24
Peak memory 200524 kb
Host smart-97a49ae1-9e6a-4d01-8467-182de1ce64d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105806772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.105806772
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.3165543273
Short name T778
Test name
Test status
Simulation time 22428348084 ps
CPU time 33.11 seconds
Started Jun 22 04:28:46 PM PDT 24
Finished Jun 22 04:29:20 PM PDT 24
Peak memory 200520 kb
Host smart-965e4ade-36f1-419a-a618-ce98ccabbf8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165543273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.3165543273
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.1168322725
Short name T1016
Test name
Test status
Simulation time 166983505856 ps
CPU time 133.54 seconds
Started Jun 22 04:28:23 PM PDT 24
Finished Jun 22 04:30:38 PM PDT 24
Peak memory 200492 kb
Host smart-cbb3d82b-0190-4698-93e7-051c2eff82d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168322725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.1168322725
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.2005054328
Short name T355
Test name
Test status
Simulation time 49466418892 ps
CPU time 46.87 seconds
Started Jun 22 04:28:15 PM PDT 24
Finished Jun 22 04:29:03 PM PDT 24
Peak memory 200532 kb
Host smart-c2d0282b-dd78-48ad-9101-1670d933f769
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005054328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.2005054328
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.2962651143
Short name T617
Test name
Test status
Simulation time 212155078611 ps
CPU time 317.63 seconds
Started Jun 22 04:28:29 PM PDT 24
Finished Jun 22 04:33:52 PM PDT 24
Peak memory 200424 kb
Host smart-236e2fdc-8c72-4f1d-b5aa-69beb89cc6c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2962651143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.2962651143
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.204750082
Short name T22
Test name
Test status
Simulation time 6251418407 ps
CPU time 6.68 seconds
Started Jun 22 04:28:19 PM PDT 24
Finished Jun 22 04:28:26 PM PDT 24
Peak memory 199976 kb
Host smart-c3e0ba67-1500-4ac1-8cb2-bf2fffe5ef40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204750082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.204750082
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_perf.971113926
Short name T583
Test name
Test status
Simulation time 20106067087 ps
CPU time 923.94 seconds
Started Jun 22 04:28:42 PM PDT 24
Finished Jun 22 04:44:06 PM PDT 24
Peak memory 200544 kb
Host smart-10d6ce73-7cad-4484-91f2-636de05e2159
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=971113926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.971113926
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.78568135
Short name T1058
Test name
Test status
Simulation time 6829197055 ps
CPU time 59.83 seconds
Started Jun 22 04:28:33 PM PDT 24
Finished Jun 22 04:29:34 PM PDT 24
Peak memory 199136 kb
Host smart-8d44508b-f9cb-4e89-a5da-3c819ac36cbd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=78568135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.78568135
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.1887401115
Short name T608
Test name
Test status
Simulation time 194327616417 ps
CPU time 127.02 seconds
Started Jun 22 04:28:40 PM PDT 24
Finished Jun 22 04:30:48 PM PDT 24
Peak memory 200536 kb
Host smart-3e0248ee-93b1-477f-ba49-3ac46de60860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887401115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.1887401115
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.2583489263
Short name T587
Test name
Test status
Simulation time 3555413893 ps
CPU time 3.53 seconds
Started Jun 22 04:28:39 PM PDT 24
Finished Jun 22 04:28:43 PM PDT 24
Peak memory 196824 kb
Host smart-febc5da2-77df-439f-bc92-693a2a564973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583489263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.2583489263
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.3896928066
Short name T706
Test name
Test status
Simulation time 266322972 ps
CPU time 1.52 seconds
Started Jun 22 04:28:15 PM PDT 24
Finished Jun 22 04:28:18 PM PDT 24
Peak memory 199424 kb
Host smart-c021669c-97be-47f9-92d2-68f2c99ebb5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896928066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.3896928066
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.3929730342
Short name T144
Test name
Test status
Simulation time 274056423882 ps
CPU time 100.03 seconds
Started Jun 22 04:28:17 PM PDT 24
Finished Jun 22 04:29:58 PM PDT 24
Peak memory 200520 kb
Host smart-8b034acd-d4b4-41c6-a198-83e332291d05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929730342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.3929730342
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.1310155638
Short name T1088
Test name
Test status
Simulation time 1381281131 ps
CPU time 3.44 seconds
Started Jun 22 04:28:36 PM PDT 24
Finished Jun 22 04:28:40 PM PDT 24
Peak memory 199156 kb
Host smart-f5807d0a-baa5-43d0-aba1-4d9b9daf73df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310155638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.1310155638
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.3442715148
Short name T913
Test name
Test status
Simulation time 274716161073 ps
CPU time 25.73 seconds
Started Jun 22 04:28:17 PM PDT 24
Finished Jun 22 04:28:43 PM PDT 24
Peak memory 200548 kb
Host smart-462e9fa8-2061-4517-91ae-535433b3e916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442715148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.3442715148
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.2095554916
Short name T179
Test name
Test status
Simulation time 75683389911 ps
CPU time 37.91 seconds
Started Jun 22 04:30:27 PM PDT 24
Finished Jun 22 04:31:05 PM PDT 24
Peak memory 200544 kb
Host smart-95925d83-c532-4963-96ff-f3106829d331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095554916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.2095554916
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.2223954289
Short name T502
Test name
Test status
Simulation time 6050540525 ps
CPU time 12.7 seconds
Started Jun 22 04:30:21 PM PDT 24
Finished Jun 22 04:30:35 PM PDT 24
Peak memory 200544 kb
Host smart-7c3ec571-dc65-4206-9fd0-8caedb7be25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223954289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.2223954289
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.2088692383
Short name T872
Test name
Test status
Simulation time 135028819884 ps
CPU time 56.56 seconds
Started Jun 22 04:30:30 PM PDT 24
Finished Jun 22 04:31:27 PM PDT 24
Peak memory 200200 kb
Host smart-af8aa5a4-1b72-491f-b8dd-0c4706f8c094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088692383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.2088692383
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.4153399936
Short name T1077
Test name
Test status
Simulation time 234777238352 ps
CPU time 107.75 seconds
Started Jun 22 04:30:35 PM PDT 24
Finished Jun 22 04:32:24 PM PDT 24
Peak memory 200512 kb
Host smart-0edfdc88-6e65-4e27-b8da-b73ce7a37327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153399936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.4153399936
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.3352758251
Short name T488
Test name
Test status
Simulation time 159230017463 ps
CPU time 41.9 seconds
Started Jun 22 04:30:35 PM PDT 24
Finished Jun 22 04:31:18 PM PDT 24
Peak memory 200464 kb
Host smart-b434056d-4eef-432e-8ad2-98eeb61c19fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352758251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.3352758251
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.1700735475
Short name T1025
Test name
Test status
Simulation time 136972651724 ps
CPU time 36.1 seconds
Started Jun 22 04:30:37 PM PDT 24
Finished Jun 22 04:31:15 PM PDT 24
Peak memory 200544 kb
Host smart-43cfaf91-0af0-404e-86b6-dac0b2f01847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700735475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.1700735475
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.3094318644
Short name T513
Test name
Test status
Simulation time 144411110201 ps
CPU time 16.13 seconds
Started Jun 22 04:30:36 PM PDT 24
Finished Jun 22 04:30:55 PM PDT 24
Peak memory 200468 kb
Host smart-10fb503b-9d5e-420b-bd50-9e584a0720d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094318644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.3094318644
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.3644648689
Short name T225
Test name
Test status
Simulation time 22130507135 ps
CPU time 48.57 seconds
Started Jun 22 04:30:31 PM PDT 24
Finished Jun 22 04:31:20 PM PDT 24
Peak memory 200444 kb
Host smart-4bd69f24-66db-4b37-a365-b4307690d299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644648689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.3644648689
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.3557308084
Short name T738
Test name
Test status
Simulation time 12080734 ps
CPU time 0.56 seconds
Started Jun 22 04:28:23 PM PDT 24
Finished Jun 22 04:28:24 PM PDT 24
Peak memory 195316 kb
Host smart-1e205a07-24d4-4f15-8e15-147f89f273ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557308084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.3557308084
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.2938512586
Short name T589
Test name
Test status
Simulation time 24378048877 ps
CPU time 51.5 seconds
Started Jun 22 04:28:30 PM PDT 24
Finished Jun 22 04:29:22 PM PDT 24
Peak memory 200528 kb
Host smart-00a5a37c-b33e-41c9-8a65-9cdbbdbfdf4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938512586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.2938512586
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.1836461786
Short name T309
Test name
Test status
Simulation time 524847254575 ps
CPU time 125.8 seconds
Started Jun 22 04:28:16 PM PDT 24
Finished Jun 22 04:30:23 PM PDT 24
Peak memory 200460 kb
Host smart-471eeb7f-ca40-4e36-bedd-f6489cb5051b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836461786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.1836461786
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.139279229
Short name T590
Test name
Test status
Simulation time 101525776518 ps
CPU time 159.52 seconds
Started Jun 22 04:28:19 PM PDT 24
Finished Jun 22 04:30:59 PM PDT 24
Peak memory 200484 kb
Host smart-9a6e5fab-cf09-4024-b126-f3f019f9360d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139279229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.139279229
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.2196495685
Short name T575
Test name
Test status
Simulation time 76161627559 ps
CPU time 113.05 seconds
Started Jun 22 04:28:47 PM PDT 24
Finished Jun 22 04:30:41 PM PDT 24
Peak memory 200444 kb
Host smart-d509d4cc-25fd-4db8-8583-f5f3982d15ad
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196495685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.2196495685
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.514530694
Short name T827
Test name
Test status
Simulation time 82867956506 ps
CPU time 514.43 seconds
Started Jun 22 04:28:27 PM PDT 24
Finished Jun 22 04:37:02 PM PDT 24
Peak memory 200540 kb
Host smart-c27d8376-25dc-4586-91fe-1380ec47ee8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=514530694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.514530694
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.1307778273
Short name T429
Test name
Test status
Simulation time 7385048351 ps
CPU time 4 seconds
Started Jun 22 04:28:36 PM PDT 24
Finished Jun 22 04:28:41 PM PDT 24
Peak memory 200100 kb
Host smart-a5d6f97e-f54c-48e5-a173-f82c2ff7434a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307778273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.1307778273
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_perf.1622724183
Short name T870
Test name
Test status
Simulation time 22522368666 ps
CPU time 1101.02 seconds
Started Jun 22 04:28:14 PM PDT 24
Finished Jun 22 04:46:36 PM PDT 24
Peak memory 200608 kb
Host smart-fc604dc2-3c9a-49b2-bcee-c405ac09a290
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1622724183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.1622724183
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.1929877888
Short name T473
Test name
Test status
Simulation time 6701907375 ps
CPU time 62.96 seconds
Started Jun 22 04:28:18 PM PDT 24
Finished Jun 22 04:29:21 PM PDT 24
Peak memory 199796 kb
Host smart-9d674af2-bfe8-44d4-a6b9-cefb6a6a4b6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1929877888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.1929877888
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.2646958785
Short name T908
Test name
Test status
Simulation time 1729411910 ps
CPU time 2.01 seconds
Started Jun 22 04:28:17 PM PDT 24
Finished Jun 22 04:28:20 PM PDT 24
Peak memory 196148 kb
Host smart-a7de319a-3de0-4400-a231-088a139e7225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646958785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.2646958785
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.1963772776
Short name T961
Test name
Test status
Simulation time 687547128 ps
CPU time 1.7 seconds
Started Jun 22 04:28:40 PM PDT 24
Finished Jun 22 04:28:42 PM PDT 24
Peak memory 200008 kb
Host smart-cd2c0b5e-47a2-4493-96a0-69282377a0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963772776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.1963772776
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.3420594991
Short name T41
Test name
Test status
Simulation time 7073234384 ps
CPU time 59.47 seconds
Started Jun 22 04:28:24 PM PDT 24
Finished Jun 22 04:29:24 PM PDT 24
Peak memory 216220 kb
Host smart-36f3da87-ab87-42d1-a4c5-bc0462bcc072
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420594991 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.3420594991
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.565188850
Short name T504
Test name
Test status
Simulation time 1029817749 ps
CPU time 1.47 seconds
Started Jun 22 04:28:15 PM PDT 24
Finished Jun 22 04:28:18 PM PDT 24
Peak memory 197520 kb
Host smart-441b1826-38eb-4364-ae3a-5e4dfa5ba42b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565188850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.565188850
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.3174216180
Short name T317
Test name
Test status
Simulation time 17520034220 ps
CPU time 27.47 seconds
Started Jun 22 04:28:42 PM PDT 24
Finished Jun 22 04:29:11 PM PDT 24
Peak memory 200532 kb
Host smart-402d35ac-c1c3-4bf4-9c13-f058bbb05f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174216180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.3174216180
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.248393871
Short name T260
Test name
Test status
Simulation time 396990367906 ps
CPU time 131.17 seconds
Started Jun 22 04:30:31 PM PDT 24
Finished Jun 22 04:32:43 PM PDT 24
Peak memory 200940 kb
Host smart-c5e8f39c-16cb-4ff3-ab98-ba7b8eb71ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248393871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.248393871
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.2205858475
Short name T591
Test name
Test status
Simulation time 26682305972 ps
CPU time 39.91 seconds
Started Jun 22 04:30:36 PM PDT 24
Finished Jun 22 04:31:18 PM PDT 24
Peak memory 200388 kb
Host smart-3e7bf1f9-87b3-483f-99ef-41024bb3c613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205858475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.2205858475
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.1826591864
Short name T665
Test name
Test status
Simulation time 82714964792 ps
CPU time 22.62 seconds
Started Jun 22 04:30:37 PM PDT 24
Finished Jun 22 04:31:02 PM PDT 24
Peak memory 200524 kb
Host smart-da8ba721-c74a-4f06-94e0-9d7d87ad35c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826591864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.1826591864
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.3082907311
Short name T716
Test name
Test status
Simulation time 199669738631 ps
CPU time 20.4 seconds
Started Jun 22 04:30:30 PM PDT 24
Finished Jun 22 04:30:51 PM PDT 24
Peak memory 200536 kb
Host smart-8415c39b-df20-47ab-a9cf-e8f7463aa037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082907311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.3082907311
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.3968433982
Short name T266
Test name
Test status
Simulation time 22523665388 ps
CPU time 40.55 seconds
Started Jun 22 04:30:33 PM PDT 24
Finished Jun 22 04:31:14 PM PDT 24
Peak memory 200532 kb
Host smart-4e89dd1a-17ed-4a07-9ec4-45dfc938d301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968433982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.3968433982
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.3369214627
Short name T433
Test name
Test status
Simulation time 106961401534 ps
CPU time 51.81 seconds
Started Jun 22 04:30:43 PM PDT 24
Finished Jun 22 04:31:35 PM PDT 24
Peak memory 200456 kb
Host smart-3a5dec6b-3857-45bc-ab86-ca2865b8b3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369214627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.3369214627
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.984911612
Short name T1054
Test name
Test status
Simulation time 37422366656 ps
CPU time 27.55 seconds
Started Jun 22 04:30:32 PM PDT 24
Finished Jun 22 04:31:00 PM PDT 24
Peak memory 200580 kb
Host smart-646ad640-d9a5-458d-9e93-c7cca9628b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984911612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.984911612
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.1007856242
Short name T812
Test name
Test status
Simulation time 87582222219 ps
CPU time 55.86 seconds
Started Jun 22 04:30:41 PM PDT 24
Finished Jun 22 04:31:37 PM PDT 24
Peak memory 200484 kb
Host smart-a7eec851-1f13-4956-8da5-1e4059a46926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007856242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.1007856242
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.38056146
Short name T256
Test name
Test status
Simulation time 48060057647 ps
CPU time 22.88 seconds
Started Jun 22 04:30:36 PM PDT 24
Finished Jun 22 04:31:01 PM PDT 24
Peak memory 200368 kb
Host smart-056fb3ec-715a-4b05-850d-a0dc208ef040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38056146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.38056146
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.2554526235
Short name T1032
Test name
Test status
Simulation time 25074631443 ps
CPU time 43.75 seconds
Started Jun 22 04:30:35 PM PDT 24
Finished Jun 22 04:31:20 PM PDT 24
Peak memory 200456 kb
Host smart-8b48b4e9-8047-45ce-8c46-67b268a0b9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554526235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.2554526235
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.1811064567
Short name T1007
Test name
Test status
Simulation time 11257780 ps
CPU time 0.56 seconds
Started Jun 22 04:28:26 PM PDT 24
Finished Jun 22 04:28:27 PM PDT 24
Peak memory 195952 kb
Host smart-d1fcf169-369e-4344-96a8-ea079f30c073
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811064567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.1811064567
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.386903269
Short name T52
Test name
Test status
Simulation time 45091017142 ps
CPU time 79.49 seconds
Started Jun 22 04:28:39 PM PDT 24
Finished Jun 22 04:29:59 PM PDT 24
Peak memory 200524 kb
Host smart-849ca0c3-51f5-4762-9b68-5c96bfef3166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386903269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.386903269
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.1617550273
Short name T176
Test name
Test status
Simulation time 19549758559 ps
CPU time 19.19 seconds
Started Jun 22 04:28:40 PM PDT 24
Finished Jun 22 04:29:00 PM PDT 24
Peak memory 200612 kb
Host smart-af3407f1-29c6-4d9b-aebb-48053a7fbbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617550273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.1617550273
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.2591028117
Short name T358
Test name
Test status
Simulation time 53655855834 ps
CPU time 83.03 seconds
Started Jun 22 04:28:46 PM PDT 24
Finished Jun 22 04:30:10 PM PDT 24
Peak memory 200452 kb
Host smart-2e0ea464-e688-466d-8635-9529768d83ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591028117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.2591028117
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.1599730023
Short name T941
Test name
Test status
Simulation time 262077130748 ps
CPU time 69.78 seconds
Started Jun 22 04:28:24 PM PDT 24
Finished Jun 22 04:29:35 PM PDT 24
Peak memory 200092 kb
Host smart-3e42dd9b-d409-413b-b8b2-20906e4fb06e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599730023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.1599730023
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.4217251890
Short name T455
Test name
Test status
Simulation time 38815844908 ps
CPU time 105.57 seconds
Started Jun 22 04:28:39 PM PDT 24
Finished Jun 22 04:30:25 PM PDT 24
Peak memory 200448 kb
Host smart-e289f446-4c81-402e-8af7-d11502180e57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4217251890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.4217251890
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.3893250683
Short name T506
Test name
Test status
Simulation time 7297551356 ps
CPU time 13.53 seconds
Started Jun 22 04:28:25 PM PDT 24
Finished Jun 22 04:28:39 PM PDT 24
Peak memory 200908 kb
Host smart-902323b0-4c04-4454-92e6-aa9371b557ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893250683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.3893250683
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_perf.983779975
Short name T45
Test name
Test status
Simulation time 21862232283 ps
CPU time 334.54 seconds
Started Jun 22 04:28:45 PM PDT 24
Finished Jun 22 04:34:21 PM PDT 24
Peak memory 200848 kb
Host smart-e8aacf03-a56f-469c-b523-1927d06919b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=983779975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.983779975
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.2675293384
Short name T889
Test name
Test status
Simulation time 3090965629 ps
CPU time 3.67 seconds
Started Jun 22 04:28:26 PM PDT 24
Finished Jun 22 04:28:30 PM PDT 24
Peak memory 199588 kb
Host smart-2bf0769c-20ea-42a4-9825-488e1d2158df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2675293384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.2675293384
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.1985079272
Short name T1082
Test name
Test status
Simulation time 143611238307 ps
CPU time 49.04 seconds
Started Jun 22 04:28:50 PM PDT 24
Finished Jun 22 04:29:41 PM PDT 24
Peak memory 200492 kb
Host smart-a4c1e8cb-664c-487b-9b54-ab9e36753387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985079272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.1985079272
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.2517244653
Short name T300
Test name
Test status
Simulation time 39179697652 ps
CPU time 31.12 seconds
Started Jun 22 04:28:24 PM PDT 24
Finished Jun 22 04:28:56 PM PDT 24
Peak memory 196300 kb
Host smart-cc4f8fc9-4373-48e3-b381-159290fb2121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517244653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.2517244653
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.772047092
Short name T10
Test name
Test status
Simulation time 518036602 ps
CPU time 2.04 seconds
Started Jun 22 04:28:23 PM PDT 24
Finished Jun 22 04:28:26 PM PDT 24
Peak memory 198868 kb
Host smart-e7aac5d7-5dcb-45c0-831d-e18550824c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772047092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.772047092
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.4040622578
Short name T84
Test name
Test status
Simulation time 7186850478 ps
CPU time 8.32 seconds
Started Jun 22 04:28:24 PM PDT 24
Finished Jun 22 04:28:33 PM PDT 24
Peak memory 200328 kb
Host smart-c576bad2-f9aa-4666-8a2b-c90444a975d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040622578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.4040622578
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.3104807096
Short name T879
Test name
Test status
Simulation time 25860352048 ps
CPU time 10.96 seconds
Started Jun 22 04:28:23 PM PDT 24
Finished Jun 22 04:28:35 PM PDT 24
Peak memory 200180 kb
Host smart-39dc213c-270d-4dd3-8e40-d5900987c3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104807096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.3104807096
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.1032762776
Short name T911
Test name
Test status
Simulation time 31147737502 ps
CPU time 27.8 seconds
Started Jun 22 04:30:36 PM PDT 24
Finished Jun 22 04:31:06 PM PDT 24
Peak memory 200304 kb
Host smart-5c775847-7467-4afd-86e8-238ada6d2e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032762776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.1032762776
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.2796084689
Short name T270
Test name
Test status
Simulation time 353623459723 ps
CPU time 98.68 seconds
Started Jun 22 04:30:32 PM PDT 24
Finished Jun 22 04:32:11 PM PDT 24
Peak memory 200544 kb
Host smart-b1b98751-004e-4a5c-827c-859c905523ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796084689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.2796084689
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.3747147378
Short name T365
Test name
Test status
Simulation time 136704033233 ps
CPU time 104.49 seconds
Started Jun 22 04:30:34 PM PDT 24
Finished Jun 22 04:32:19 PM PDT 24
Peak memory 200544 kb
Host smart-30f5f404-7b30-4407-9439-fe067c7762c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747147378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.3747147378
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.2596198205
Short name T776
Test name
Test status
Simulation time 66377947515 ps
CPU time 25.22 seconds
Started Jun 22 04:30:36 PM PDT 24
Finished Jun 22 04:31:03 PM PDT 24
Peak memory 200520 kb
Host smart-e4d294a0-75c8-426d-b0d4-d97669f735c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596198205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.2596198205
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.1089968475
Short name T940
Test name
Test status
Simulation time 55465019417 ps
CPU time 82.45 seconds
Started Jun 22 04:30:29 PM PDT 24
Finished Jun 22 04:31:52 PM PDT 24
Peak memory 200464 kb
Host smart-26aec192-81f4-434c-8beb-e881c04ec140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089968475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.1089968475
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.78900148
Short name T172
Test name
Test status
Simulation time 22618613918 ps
CPU time 20.93 seconds
Started Jun 22 04:30:40 PM PDT 24
Finished Jun 22 04:31:02 PM PDT 24
Peak memory 200416 kb
Host smart-cface22a-e99e-4f3f-bc28-b2d6d121ce24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78900148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.78900148
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.1288740604
Short name T432
Test name
Test status
Simulation time 180281706325 ps
CPU time 129.85 seconds
Started Jun 22 04:30:38 PM PDT 24
Finished Jun 22 04:32:49 PM PDT 24
Peak memory 200468 kb
Host smart-480d8f5b-99e8-4924-a30f-b021909dd37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288740604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.1288740604
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.2240380636
Short name T1005
Test name
Test status
Simulation time 120896762376 ps
CPU time 12.68 seconds
Started Jun 22 04:30:33 PM PDT 24
Finished Jun 22 04:30:46 PM PDT 24
Peak memory 200568 kb
Host smart-72fc24c7-1730-4aa9-abc0-b334762edb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240380636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.2240380636
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.2534524869
Short name T261
Test name
Test status
Simulation time 55750613466 ps
CPU time 44.25 seconds
Started Jun 22 04:30:31 PM PDT 24
Finished Jun 22 04:31:17 PM PDT 24
Peak memory 200520 kb
Host smart-a8d37d6d-e9c9-4ca1-8525-7b8ed12fb350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534524869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.2534524869
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.3646142578
Short name T529
Test name
Test status
Simulation time 19042174 ps
CPU time 0.56 seconds
Started Jun 22 04:28:47 PM PDT 24
Finished Jun 22 04:28:49 PM PDT 24
Peak memory 195824 kb
Host smart-62f9e43e-ca2e-46cc-9a89-0e5e6bc2ee4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646142578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.3646142578
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.712393556
Short name T416
Test name
Test status
Simulation time 89539840364 ps
CPU time 14.58 seconds
Started Jun 22 04:28:23 PM PDT 24
Finished Jun 22 04:28:38 PM PDT 24
Peak memory 200524 kb
Host smart-47dd7275-d3c5-44f5-9e56-8c786eb64ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712393556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.712393556
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.1554442763
Short name T360
Test name
Test status
Simulation time 51739518122 ps
CPU time 40.08 seconds
Started Jun 22 04:28:27 PM PDT 24
Finished Jun 22 04:29:07 PM PDT 24
Peak memory 200928 kb
Host smart-4ab2438e-44ce-4b33-9e21-29ad021ff693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554442763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.1554442763
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_intr.2579242432
Short name T925
Test name
Test status
Simulation time 5123600102 ps
CPU time 6.57 seconds
Started Jun 22 04:28:25 PM PDT 24
Finished Jun 22 04:28:32 PM PDT 24
Peak memory 197408 kb
Host smart-b7098eaf-f0e6-402d-8a1d-3630cb42c4ec
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579242432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.2579242432
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.461469778
Short name T290
Test name
Test status
Simulation time 112167327246 ps
CPU time 572.72 seconds
Started Jun 22 04:29:39 PM PDT 24
Finished Jun 22 04:39:13 PM PDT 24
Peak memory 200448 kb
Host smart-7357a06a-5ac4-472d-9d54-d49970af733f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=461469778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.461469778
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.4291484900
Short name T24
Test name
Test status
Simulation time 2900555077 ps
CPU time 2.89 seconds
Started Jun 22 04:28:47 PM PDT 24
Finished Jun 22 04:28:51 PM PDT 24
Peak memory 196320 kb
Host smart-cf35f80d-68c2-4c02-a7ae-46442cc2a183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291484900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.4291484900
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_perf.2865837639
Short name T54
Test name
Test status
Simulation time 7197392810 ps
CPU time 64.14 seconds
Started Jun 22 04:28:23 PM PDT 24
Finished Jun 22 04:29:33 PM PDT 24
Peak memory 200508 kb
Host smart-d565ebf3-6cce-4395-ad77-84da738a9030
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2865837639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.2865837639
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.604275438
Short name T616
Test name
Test status
Simulation time 4924400715 ps
CPU time 36.13 seconds
Started Jun 22 04:28:21 PM PDT 24
Finished Jun 22 04:28:58 PM PDT 24
Peak memory 198688 kb
Host smart-378950c6-2d71-456f-9219-9d2738caf945
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=604275438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.604275438
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.3465313620
Short name T1080
Test name
Test status
Simulation time 32183522888 ps
CPU time 27.52 seconds
Started Jun 22 04:28:37 PM PDT 24
Finished Jun 22 04:29:05 PM PDT 24
Peak memory 200276 kb
Host smart-aec0a865-b80f-4197-abde-0aee32d3338d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465313620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.3465313620
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.3072974503
Short name T1087
Test name
Test status
Simulation time 682524625 ps
CPU time 0.94 seconds
Started Jun 22 04:28:25 PM PDT 24
Finished Jun 22 04:28:27 PM PDT 24
Peak memory 196152 kb
Host smart-ffbe9d5a-3966-4d84-afa3-8f24bcbaa6ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072974503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.3072974503
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.1941878061
Short name T487
Test name
Test status
Simulation time 5901135588 ps
CPU time 9.72 seconds
Started Jun 22 04:28:40 PM PDT 24
Finished Jun 22 04:28:50 PM PDT 24
Peak memory 200464 kb
Host smart-9f0faf86-18cd-4f11-9f2e-ccb8b8fd1fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941878061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.1941878061
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.1417588407
Short name T962
Test name
Test status
Simulation time 776538242 ps
CPU time 1.8 seconds
Started Jun 22 04:28:45 PM PDT 24
Finished Jun 22 04:28:48 PM PDT 24
Peak memory 200380 kb
Host smart-c1cdc750-0df4-4304-a9a2-fca19268a40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417588407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.1417588407
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.3690825993
Short name T275
Test name
Test status
Simulation time 24151025048 ps
CPU time 4.21 seconds
Started Jun 22 04:28:46 PM PDT 24
Finished Jun 22 04:28:51 PM PDT 24
Peak memory 199800 kb
Host smart-ac6862eb-b027-42ac-8ecd-587e6e242761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690825993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.3690825993
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.925366335
Short name T950
Test name
Test status
Simulation time 151891684233 ps
CPU time 279.98 seconds
Started Jun 22 04:30:36 PM PDT 24
Finished Jun 22 04:35:17 PM PDT 24
Peak memory 200544 kb
Host smart-c9a8e59d-089b-44ca-95d9-92471b687cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925366335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.925366335
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.3611562949
Short name T338
Test name
Test status
Simulation time 113604559007 ps
CPU time 158.93 seconds
Started Jun 22 04:30:37 PM PDT 24
Finished Jun 22 04:33:18 PM PDT 24
Peak memory 200148 kb
Host smart-87b10ef8-5b27-4a56-ad01-e6507a493503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611562949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.3611562949
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.466595644
Short name T897
Test name
Test status
Simulation time 21000570308 ps
CPU time 32.76 seconds
Started Jun 22 04:30:34 PM PDT 24
Finished Jun 22 04:31:08 PM PDT 24
Peak memory 200532 kb
Host smart-37b7f739-1c43-42bb-8b53-c18dc9773d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466595644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.466595644
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.2011834248
Short name T86
Test name
Test status
Simulation time 113108243197 ps
CPU time 193.89 seconds
Started Jun 22 04:30:36 PM PDT 24
Finished Jun 22 04:33:51 PM PDT 24
Peak memory 200356 kb
Host smart-8067a577-ef32-41e8-844a-1ec7c7305c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011834248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.2011834248
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.3337947492
Short name T90
Test name
Test status
Simulation time 15313203389 ps
CPU time 16.9 seconds
Started Jun 22 04:30:35 PM PDT 24
Finished Jun 22 04:30:53 PM PDT 24
Peak memory 200588 kb
Host smart-1157513e-2b01-4b3d-8bca-6bbe7d1b5256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337947492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.3337947492
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.2769476935
Short name T356
Test name
Test status
Simulation time 37004781573 ps
CPU time 73.03 seconds
Started Jun 22 04:30:32 PM PDT 24
Finished Jun 22 04:31:46 PM PDT 24
Peak memory 200536 kb
Host smart-186c4b07-b839-44a6-9643-3cad0c46ca27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769476935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.2769476935
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.4178043637
Short name T880
Test name
Test status
Simulation time 28324847561 ps
CPU time 44.44 seconds
Started Jun 22 04:30:30 PM PDT 24
Finished Jun 22 04:31:16 PM PDT 24
Peak memory 200364 kb
Host smart-57b01f7c-2dca-42a5-99a5-b8a08cc7ee0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178043637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.4178043637
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.586471206
Short name T123
Test name
Test status
Simulation time 56550745988 ps
CPU time 22.54 seconds
Started Jun 22 04:30:36 PM PDT 24
Finished Jun 22 04:31:01 PM PDT 24
Peak memory 200464 kb
Host smart-29ca9b09-7d10-4c67-8e3c-bae2e66a4204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586471206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.586471206
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.1879396964
Short name T63
Test name
Test status
Simulation time 17555432666 ps
CPU time 16.74 seconds
Started Jun 22 04:30:47 PM PDT 24
Finished Jun 22 04:31:04 PM PDT 24
Peak memory 200616 kb
Host smart-58700884-d163-43bd-b660-dd6cc5d079f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879396964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.1879396964
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.2110225500
Short name T490
Test name
Test status
Simulation time 18884730 ps
CPU time 0.55 seconds
Started Jun 22 04:28:52 PM PDT 24
Finished Jun 22 04:28:54 PM PDT 24
Peak memory 195864 kb
Host smart-7aea35b9-7984-4da2-b2be-b10ebe1a6815
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110225500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.2110225500
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.3427030991
Short name T1008
Test name
Test status
Simulation time 39699041916 ps
CPU time 35.33 seconds
Started Jun 22 04:28:48 PM PDT 24
Finished Jun 22 04:29:24 PM PDT 24
Peak memory 200448 kb
Host smart-c7847a16-5088-4df2-9f40-ad35026fe9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427030991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.3427030991
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.2983809115
Short name T188
Test name
Test status
Simulation time 92332565171 ps
CPU time 64.11 seconds
Started Jun 22 04:28:23 PM PDT 24
Finished Jun 22 04:29:28 PM PDT 24
Peak memory 200352 kb
Host smart-b2a68a96-8cdc-4028-a471-acdccc68ef1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983809115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.2983809115
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.4225390434
Short name T646
Test name
Test status
Simulation time 94705959641 ps
CPU time 77.4 seconds
Started Jun 22 04:28:47 PM PDT 24
Finished Jun 22 04:30:05 PM PDT 24
Peak memory 200648 kb
Host smart-8fe16de5-3e31-48ed-a54d-0385f545a8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225390434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.4225390434
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.959735557
Short name T1023
Test name
Test status
Simulation time 249453289078 ps
CPU time 183.61 seconds
Started Jun 22 04:28:23 PM PDT 24
Finished Jun 22 04:31:27 PM PDT 24
Peak memory 200332 kb
Host smart-001942f5-ae16-4bd7-97fc-8ad0772530e7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959735557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.959735557
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.3624353840
Short name T567
Test name
Test status
Simulation time 95199111813 ps
CPU time 383.79 seconds
Started Jun 22 04:28:32 PM PDT 24
Finished Jun 22 04:34:57 PM PDT 24
Peak memory 200588 kb
Host smart-99953359-c736-44f8-9cb9-d07d852c2539
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3624353840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.3624353840
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.1310261968
Short name T777
Test name
Test status
Simulation time 6505480257 ps
CPU time 12.25 seconds
Started Jun 22 04:28:49 PM PDT 24
Finished Jun 22 04:29:02 PM PDT 24
Peak memory 199516 kb
Host smart-cc018491-fe2c-46f4-9a2e-b79fe2897392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310261968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.1310261968
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.2153219664
Short name T649
Test name
Test status
Simulation time 7143087135 ps
CPU time 11.23 seconds
Started Jun 22 04:28:45 PM PDT 24
Finished Jun 22 04:28:57 PM PDT 24
Peak memory 197792 kb
Host smart-6660fa13-c4d3-40cf-a922-33add78acb92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153219664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.2153219664
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.1678468671
Short name T304
Test name
Test status
Simulation time 16509227165 ps
CPU time 232.62 seconds
Started Jun 22 04:28:34 PM PDT 24
Finished Jun 22 04:32:27 PM PDT 24
Peak memory 200508 kb
Host smart-3ef5f453-907a-434c-878b-5a6f930510cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1678468671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.1678468671
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.3530429582
Short name T619
Test name
Test status
Simulation time 5802707795 ps
CPU time 12.25 seconds
Started Jun 22 04:28:44 PM PDT 24
Finished Jun 22 04:28:57 PM PDT 24
Peak memory 199220 kb
Host smart-7c326270-069a-414a-9b57-55bd1e6c575e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3530429582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.3530429582
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.2839259878
Short name T49
Test name
Test status
Simulation time 26322054594 ps
CPU time 20.65 seconds
Started Jun 22 04:28:23 PM PDT 24
Finished Jun 22 04:28:45 PM PDT 24
Peak memory 200516 kb
Host smart-949c61ae-e883-471e-97cb-cf0a8fab2ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839259878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.2839259878
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.3649685135
Short name T984
Test name
Test status
Simulation time 4051116573 ps
CPU time 2.03 seconds
Started Jun 22 04:28:45 PM PDT 24
Finished Jun 22 04:28:48 PM PDT 24
Peak memory 196728 kb
Host smart-4fc6cd9c-7bcf-4094-a07a-91ee9ea6be1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649685135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.3649685135
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.4156057338
Short name T340
Test name
Test status
Simulation time 6117278337 ps
CPU time 5.85 seconds
Started Jun 22 04:28:25 PM PDT 24
Finished Jun 22 04:28:32 PM PDT 24
Peak memory 200376 kb
Host smart-0861c833-3fdb-4d3c-8232-46679671839a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156057338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.4156057338
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.906691758
Short name T342
Test name
Test status
Simulation time 652122257299 ps
CPU time 304.5 seconds
Started Jun 22 04:28:31 PM PDT 24
Finished Jun 22 04:33:36 PM PDT 24
Peak memory 200460 kb
Host smart-6182a148-52cc-4c39-acd8-36f3b44fa6df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906691758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.906691758
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.86472221
Short name T444
Test name
Test status
Simulation time 592696721 ps
CPU time 1.96 seconds
Started Jun 22 04:28:49 PM PDT 24
Finished Jun 22 04:28:52 PM PDT 24
Peak memory 198944 kb
Host smart-aa1dfb85-2304-486e-8706-f09df3b9c984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86472221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.86472221
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.1244444926
Short name T357
Test name
Test status
Simulation time 56313211349 ps
CPU time 22.23 seconds
Started Jun 22 04:28:25 PM PDT 24
Finished Jun 22 04:28:48 PM PDT 24
Peak memory 200532 kb
Host smart-0cff4d99-d753-4d18-a89b-d9c35bc9a240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244444926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.1244444926
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.105050410
Short name T153
Test name
Test status
Simulation time 283047631301 ps
CPU time 60.2 seconds
Started Jun 22 04:30:37 PM PDT 24
Finished Jun 22 04:31:39 PM PDT 24
Peak memory 200404 kb
Host smart-212bc016-0331-4201-b15c-33101177bf21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105050410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.105050410
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.293420122
Short name T467
Test name
Test status
Simulation time 98490519610 ps
CPU time 160.48 seconds
Started Jun 22 04:30:49 PM PDT 24
Finished Jun 22 04:33:29 PM PDT 24
Peak memory 200528 kb
Host smart-03701290-b427-4dfe-9931-d5864b69f0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293420122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.293420122
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.688103317
Short name T361
Test name
Test status
Simulation time 124753068942 ps
CPU time 105.21 seconds
Started Jun 22 04:30:37 PM PDT 24
Finished Jun 22 04:32:24 PM PDT 24
Peak memory 200564 kb
Host smart-29d44e50-6e8d-486f-ab3e-33666c487cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688103317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.688103317
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.3296672684
Short name T476
Test name
Test status
Simulation time 17938040426 ps
CPU time 30.5 seconds
Started Jun 22 04:31:46 PM PDT 24
Finished Jun 22 04:32:18 PM PDT 24
Peak memory 200532 kb
Host smart-ba3bf0b9-5436-4b40-be6a-0cdb3e211366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296672684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.3296672684
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.1569383441
Short name T209
Test name
Test status
Simulation time 121993793269 ps
CPU time 47.32 seconds
Started Jun 22 04:30:38 PM PDT 24
Finished Jun 22 04:31:27 PM PDT 24
Peak memory 200396 kb
Host smart-9d731947-3b4d-43fe-bdae-666f6d826de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569383441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.1569383441
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.3974683573
Short name T315
Test name
Test status
Simulation time 77487199074 ps
CPU time 35.3 seconds
Started Jun 22 04:30:47 PM PDT 24
Finished Jun 22 04:31:23 PM PDT 24
Peak memory 200524 kb
Host smart-5726d8ec-87d0-4101-9c45-0a0fea1a310d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974683573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.3974683573
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.55005488
Short name T791
Test name
Test status
Simulation time 41425915 ps
CPU time 0.57 seconds
Started Jun 22 04:28:31 PM PDT 24
Finished Jun 22 04:28:31 PM PDT 24
Peak memory 195864 kb
Host smart-34619724-c79e-44e3-a814-f01a3fdb7b60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55005488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.55005488
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.4061203938
Short name T404
Test name
Test status
Simulation time 102439649753 ps
CPU time 157.01 seconds
Started Jun 22 04:28:53 PM PDT 24
Finished Jun 22 04:31:31 PM PDT 24
Peak memory 200528 kb
Host smart-18b47c0e-fb23-4729-9305-6873f7484e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061203938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.4061203938
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.1165138523
Short name T386
Test name
Test status
Simulation time 17035551153 ps
CPU time 27.54 seconds
Started Jun 22 04:28:45 PM PDT 24
Finished Jun 22 04:29:14 PM PDT 24
Peak memory 200460 kb
Host smart-f6507409-b08f-4991-a466-26d929c43ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165138523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.1165138523
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.252725844
Short name T1037
Test name
Test status
Simulation time 63987665211 ps
CPU time 26.97 seconds
Started Jun 22 04:28:33 PM PDT 24
Finished Jun 22 04:29:00 PM PDT 24
Peak memory 200524 kb
Host smart-1ef989a8-8675-4113-a116-7de5fc1fc11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252725844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.252725844
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.1884881895
Short name T660
Test name
Test status
Simulation time 64937990793 ps
CPU time 93.71 seconds
Started Jun 22 04:28:29 PM PDT 24
Finished Jun 22 04:30:03 PM PDT 24
Peak memory 200108 kb
Host smart-b4367c24-4fcd-407b-933f-5d48e07034a0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884881895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.1884881895
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.2264765618
Short name T977
Test name
Test status
Simulation time 157298045474 ps
CPU time 1484.96 seconds
Started Jun 22 04:28:32 PM PDT 24
Finished Jun 22 04:53:17 PM PDT 24
Peak memory 200604 kb
Host smart-3b454b4a-13a1-4f4b-b731-316c126a7e50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2264765618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.2264765618
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.2265793204
Short name T1085
Test name
Test status
Simulation time 1001991278 ps
CPU time 0.82 seconds
Started Jun 22 04:28:50 PM PDT 24
Finished Jun 22 04:28:52 PM PDT 24
Peak memory 197468 kb
Host smart-18ce34b9-66f7-4ae5-ad70-e76c8ca34ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265793204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.2265793204
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_perf.3241120167
Short name T493
Test name
Test status
Simulation time 1984007505 ps
CPU time 89.96 seconds
Started Jun 22 04:28:30 PM PDT 24
Finished Jun 22 04:30:00 PM PDT 24
Peak memory 200476 kb
Host smart-2a3c53fd-490b-4371-bfac-7f252874f790
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3241120167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.3241120167
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.1448737177
Short name T996
Test name
Test status
Simulation time 2541278103 ps
CPU time 4.42 seconds
Started Jun 22 04:28:45 PM PDT 24
Finished Jun 22 04:28:51 PM PDT 24
Peak memory 198788 kb
Host smart-dff72c88-6828-4f39-af99-fe602aaf4989
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1448737177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.1448737177
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.1716088365
Short name T482
Test name
Test status
Simulation time 163988440935 ps
CPU time 336.23 seconds
Started Jun 22 04:28:33 PM PDT 24
Finished Jun 22 04:34:10 PM PDT 24
Peak memory 200340 kb
Host smart-70dbab27-a85f-4097-b4b3-861f876ebca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716088365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.1716088365
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.3708459339
Short name T789
Test name
Test status
Simulation time 86028800611 ps
CPU time 144.72 seconds
Started Jun 22 04:28:51 PM PDT 24
Finished Jun 22 04:31:17 PM PDT 24
Peak memory 196456 kb
Host smart-ba98d7f8-a52f-4f12-b618-cfbdb39ca120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708459339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.3708459339
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.467162145
Short name T139
Test name
Test status
Simulation time 290962002 ps
CPU time 1.37 seconds
Started Jun 22 04:28:53 PM PDT 24
Finished Jun 22 04:28:56 PM PDT 24
Peak memory 199116 kb
Host smart-c109bcf4-166e-4a9b-8f18-f671b6204153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467162145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.467162145
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.2781586162
Short name T731
Test name
Test status
Simulation time 119423925508 ps
CPU time 2099.03 seconds
Started Jun 22 04:28:30 PM PDT 24
Finished Jun 22 05:03:30 PM PDT 24
Peak memory 224112 kb
Host smart-0ceb9054-724d-493a-9cd9-8939d6b06529
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781586162 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.2781586162
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.1775249663
Short name T558
Test name
Test status
Simulation time 808856661 ps
CPU time 3.48 seconds
Started Jun 22 04:28:51 PM PDT 24
Finished Jun 22 04:28:56 PM PDT 24
Peak memory 198900 kb
Host smart-98ea0b89-43ad-4c35-911d-bd843473a607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775249663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.1775249663
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.3108098366
Short name T655
Test name
Test status
Simulation time 28637831630 ps
CPU time 10.96 seconds
Started Jun 22 04:28:51 PM PDT 24
Finished Jun 22 04:29:03 PM PDT 24
Peak memory 200552 kb
Host smart-c4568e16-fc92-4f15-accd-38af5bb6e051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108098366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.3108098366
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.2119766150
Short name T255
Test name
Test status
Simulation time 46926746901 ps
CPU time 34.65 seconds
Started Jun 22 04:30:47 PM PDT 24
Finished Jun 22 04:31:21 PM PDT 24
Peak memory 200484 kb
Host smart-e616f4dd-8308-406b-9c3d-de9f6fe86326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119766150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.2119766150
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.497416690
Short name T119
Test name
Test status
Simulation time 86036538586 ps
CPU time 13.1 seconds
Started Jun 22 04:30:39 PM PDT 24
Finished Jun 22 04:30:53 PM PDT 24
Peak memory 200464 kb
Host smart-f5527170-564d-4370-b19b-001875d22fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497416690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.497416690
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.127224778
Short name T1057
Test name
Test status
Simulation time 170679889244 ps
CPU time 63.37 seconds
Started Jun 22 04:30:35 PM PDT 24
Finished Jun 22 04:31:39 PM PDT 24
Peak memory 200548 kb
Host smart-be8f9eae-7c0d-4d0c-ac3d-b3549560ad23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127224778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.127224778
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.3512105166
Short name T216
Test name
Test status
Simulation time 77822709956 ps
CPU time 31.94 seconds
Started Jun 22 04:30:44 PM PDT 24
Finished Jun 22 04:31:17 PM PDT 24
Peak memory 200564 kb
Host smart-39e9235c-3a0f-4368-ab2a-880b14a89fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512105166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.3512105166
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.2049946913
Short name T242
Test name
Test status
Simulation time 27838805777 ps
CPU time 38.37 seconds
Started Jun 22 04:30:38 PM PDT 24
Finished Jun 22 04:31:18 PM PDT 24
Peak memory 200400 kb
Host smart-b9df5a05-dda0-4c26-a33d-05b9b2af5879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049946913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.2049946913
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.3250734289
Short name T174
Test name
Test status
Simulation time 108183325956 ps
CPU time 103.78 seconds
Started Jun 22 04:30:41 PM PDT 24
Finished Jun 22 04:32:25 PM PDT 24
Peak memory 200484 kb
Host smart-b3797253-3806-4b77-afc5-bd5b97c5fe6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250734289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.3250734289
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.1297910652
Short name T344
Test name
Test status
Simulation time 186068791318 ps
CPU time 72.61 seconds
Started Jun 22 04:30:36 PM PDT 24
Finished Jun 22 04:31:50 PM PDT 24
Peak memory 200512 kb
Host smart-1d6106c8-c00c-402f-8406-ec8fa2170aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297910652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.1297910652
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.3435776302
Short name T272
Test name
Test status
Simulation time 343298225497 ps
CPU time 93.2 seconds
Started Jun 22 04:30:38 PM PDT 24
Finished Jun 22 04:32:13 PM PDT 24
Peak memory 200524 kb
Host smart-98ae8641-03d7-46c6-abfa-17fbe27d4695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435776302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.3435776302
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.3616450840
Short name T400
Test name
Test status
Simulation time 62206806 ps
CPU time 0.53 seconds
Started Jun 22 04:28:02 PM PDT 24
Finished Jun 22 04:28:05 PM PDT 24
Peak memory 195960 kb
Host smart-ca0dac29-0e5e-4ece-957b-e6146c64ab1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616450840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.3616450840
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.2946938205
Short name T187
Test name
Test status
Simulation time 158842321310 ps
CPU time 20.93 seconds
Started Jun 22 04:27:53 PM PDT 24
Finished Jun 22 04:28:16 PM PDT 24
Peak memory 200376 kb
Host smart-7b413eba-1c38-4ee6-a3bd-563227940022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946938205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.2946938205
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.664418505
Short name T751
Test name
Test status
Simulation time 209504843751 ps
CPU time 471.59 seconds
Started Jun 22 04:27:59 PM PDT 24
Finished Jun 22 04:35:52 PM PDT 24
Peak memory 200580 kb
Host smart-28708014-0d26-4a65-aa81-071872792d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664418505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.664418505
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.1306747116
Short name T998
Test name
Test status
Simulation time 108832059341 ps
CPU time 107.33 seconds
Started Jun 22 04:27:59 PM PDT 24
Finished Jun 22 04:29:48 PM PDT 24
Peak memory 200516 kb
Host smart-cfa7fd2e-ca10-42af-9dec-643191016712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306747116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.1306747116
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.1083595735
Short name T765
Test name
Test status
Simulation time 105196002349 ps
CPU time 317.83 seconds
Started Jun 22 04:28:04 PM PDT 24
Finished Jun 22 04:33:23 PM PDT 24
Peak memory 200436 kb
Host smart-556f15e6-9be1-4493-9a09-96cfd6d55b2e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083595735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.1083595735
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.55323983
Short name T756
Test name
Test status
Simulation time 91598425256 ps
CPU time 709.97 seconds
Started Jun 22 04:28:02 PM PDT 24
Finished Jun 22 04:39:54 PM PDT 24
Peak memory 200608 kb
Host smart-25bb14c5-4fa2-44d7-9553-26db7f0916b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=55323983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.55323983
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.892098577
Short name T708
Test name
Test status
Simulation time 82527626 ps
CPU time 0.63 seconds
Started Jun 22 04:28:04 PM PDT 24
Finished Jun 22 04:28:07 PM PDT 24
Peak memory 196408 kb
Host smart-4296f0e2-f475-4565-8d1a-e4fa5ee8e10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892098577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.892098577
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_perf.2225902823
Short name T760
Test name
Test status
Simulation time 33332656598 ps
CPU time 176.52 seconds
Started Jun 22 04:28:01 PM PDT 24
Finished Jun 22 04:31:00 PM PDT 24
Peak memory 200556 kb
Host smart-8e9c6e09-c63d-4cff-97f7-5278fd7a631c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2225902823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.2225902823
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.528515888
Short name T699
Test name
Test status
Simulation time 1997678694 ps
CPU time 6.22 seconds
Started Jun 22 04:28:00 PM PDT 24
Finished Jun 22 04:28:08 PM PDT 24
Peak memory 198668 kb
Host smart-89eba19e-d6e1-4a61-8751-d7d0cab9da66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=528515888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.528515888
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.1057922066
Short name T42
Test name
Test status
Simulation time 5830632028 ps
CPU time 10.34 seconds
Started Jun 22 04:27:57 PM PDT 24
Finished Jun 22 04:28:08 PM PDT 24
Peak memory 197312 kb
Host smart-c7a5be44-a3ea-4686-a7d3-bb95c8506474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057922066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.1057922066
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.814651426
Short name T117
Test name
Test status
Simulation time 141025930 ps
CPU time 0.82 seconds
Started Jun 22 04:27:55 PM PDT 24
Finished Jun 22 04:27:57 PM PDT 24
Peak memory 219140 kb
Host smart-41adb3ee-54f0-4541-a7d4-d4f2643b7afd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814651426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.814651426
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.4289421212
Short name T1052
Test name
Test status
Simulation time 652287344 ps
CPU time 1.35 seconds
Started Jun 22 04:27:57 PM PDT 24
Finished Jun 22 04:27:59 PM PDT 24
Peak memory 198916 kb
Host smart-dd399c0c-59c5-49cb-860b-a0471584c3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289421212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.4289421212
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.3432893576
Short name T478
Test name
Test status
Simulation time 55037775706 ps
CPU time 113.26 seconds
Started Jun 22 04:27:57 PM PDT 24
Finished Jun 22 04:29:52 PM PDT 24
Peak memory 200452 kb
Host smart-a662e425-5b0a-4abe-8532-75368f53f3c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432893576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.3432893576
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.329224399
Short name T422
Test name
Test status
Simulation time 959381485 ps
CPU time 2.5 seconds
Started Jun 22 04:28:02 PM PDT 24
Finished Jun 22 04:28:06 PM PDT 24
Peak memory 199028 kb
Host smart-9e7d219b-b110-4c95-a1c2-787c425ae212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329224399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.329224399
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.1894878583
Short name T673
Test name
Test status
Simulation time 68526855158 ps
CPU time 103.25 seconds
Started Jun 22 04:27:53 PM PDT 24
Finished Jun 22 04:29:38 PM PDT 24
Peak memory 200500 kb
Host smart-37d710a2-15fd-4af9-82ad-278236b48c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894878583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.1894878583
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.2567093670
Short name T974
Test name
Test status
Simulation time 35347936 ps
CPU time 0.57 seconds
Started Jun 22 04:29:54 PM PDT 24
Finished Jun 22 04:29:55 PM PDT 24
Peak memory 195864 kb
Host smart-a873e6a8-504c-4ee5-98de-93d5e88e3b1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567093670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.2567093670
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.3911629028
Short name T184
Test name
Test status
Simulation time 61766939562 ps
CPU time 26.33 seconds
Started Jun 22 04:28:44 PM PDT 24
Finished Jun 22 04:29:11 PM PDT 24
Peak memory 200532 kb
Host smart-14fb66d6-e5d8-40e6-8a82-e167c6b648d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911629028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.3911629028
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.842767949
Short name T680
Test name
Test status
Simulation time 27562060630 ps
CPU time 48.89 seconds
Started Jun 22 04:28:48 PM PDT 24
Finished Jun 22 04:29:38 PM PDT 24
Peak memory 200532 kb
Host smart-ad27ec2d-a297-4b2e-8505-565dd253f4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842767949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.842767949
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.2060565502
Short name T847
Test name
Test status
Simulation time 33774116374 ps
CPU time 13.5 seconds
Started Jun 22 04:28:47 PM PDT 24
Finished Jun 22 04:29:01 PM PDT 24
Peak memory 200452 kb
Host smart-00063541-1d1b-4491-9e93-66359ce1b40b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060565502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.2060565502
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.4248582353
Short name T470
Test name
Test status
Simulation time 6484716582 ps
CPU time 5.89 seconds
Started Jun 22 04:28:32 PM PDT 24
Finished Jun 22 04:28:39 PM PDT 24
Peak memory 197144 kb
Host smart-94d5860c-5e5f-4d6c-9946-f0767474a8c0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248582353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.4248582353
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.3504677374
Short name T280
Test name
Test status
Simulation time 42391833918 ps
CPU time 99.55 seconds
Started Jun 22 04:28:48 PM PDT 24
Finished Jun 22 04:30:29 PM PDT 24
Peak memory 200524 kb
Host smart-b01aa981-003e-4005-81a7-366c5015ad03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3504677374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.3504677374
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.4098787496
Short name T367
Test name
Test status
Simulation time 635888375 ps
CPU time 0.95 seconds
Started Jun 22 04:28:52 PM PDT 24
Finished Jun 22 04:28:54 PM PDT 24
Peak memory 197424 kb
Host smart-9329a866-30bb-4b3f-835d-5de5730db808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098787496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.4098787496
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_perf.3068364486
Short name T463
Test name
Test status
Simulation time 11067775308 ps
CPU time 165.61 seconds
Started Jun 22 04:28:45 PM PDT 24
Finished Jun 22 04:31:32 PM PDT 24
Peak memory 200508 kb
Host smart-967aae77-5dc9-482d-a620-1e18b80b2931
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3068364486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.3068364486
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.1787308290
Short name T431
Test name
Test status
Simulation time 2874734034 ps
CPU time 6.1 seconds
Started Jun 22 04:28:31 PM PDT 24
Finished Jun 22 04:28:37 PM PDT 24
Peak memory 198504 kb
Host smart-f5c7382e-df53-4f9c-bdd2-62e63a875dd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1787308290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.1787308290
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.548619635
Short name T498
Test name
Test status
Simulation time 29089845738 ps
CPU time 74.42 seconds
Started Jun 22 04:28:32 PM PDT 24
Finished Jun 22 04:29:46 PM PDT 24
Peak memory 200600 kb
Host smart-2eae53b3-73f9-4989-b2d6-90b6d273d0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548619635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.548619635
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.1147615267
Short name T862
Test name
Test status
Simulation time 89368286130 ps
CPU time 66.66 seconds
Started Jun 22 04:28:47 PM PDT 24
Finished Jun 22 04:29:55 PM PDT 24
Peak memory 196600 kb
Host smart-68733c15-29c9-438a-89e8-c59ac5808aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147615267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.1147615267
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.1820539807
Short name T923
Test name
Test status
Simulation time 641579148 ps
CPU time 1.92 seconds
Started Jun 22 04:28:51 PM PDT 24
Finished Jun 22 04:28:55 PM PDT 24
Peak memory 198852 kb
Host smart-25fabfcf-87e0-4064-8408-71cc034bc954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820539807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.1820539807
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.142378571
Short name T349
Test name
Test status
Simulation time 147633255136 ps
CPU time 414.25 seconds
Started Jun 22 04:28:52 PM PDT 24
Finished Jun 22 04:35:48 PM PDT 24
Peak memory 216908 kb
Host smart-67f45ae0-7e65-486b-82a3-2f4bb89d903d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142378571 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.142378571
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.3445868253
Short name T1071
Test name
Test status
Simulation time 2313697506 ps
CPU time 1.87 seconds
Started Jun 22 04:28:30 PM PDT 24
Finished Jun 22 04:28:32 PM PDT 24
Peak memory 199460 kb
Host smart-8db1fad8-4133-4cd6-ab30-33155c50c808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445868253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.3445868253
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.406787909
Short name T989
Test name
Test status
Simulation time 80483509574 ps
CPU time 151.34 seconds
Started Jun 22 04:28:46 PM PDT 24
Finished Jun 22 04:31:18 PM PDT 24
Peak memory 200508 kb
Host smart-001a304a-5df2-4ecf-b125-432a1eddb473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406787909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.406787909
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.434765584
Short name T819
Test name
Test status
Simulation time 30718481509 ps
CPU time 59.16 seconds
Started Jun 22 04:30:37 PM PDT 24
Finished Jun 22 04:31:38 PM PDT 24
Peak memory 200552 kb
Host smart-11e2992c-e7fa-4040-9f17-619604072054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434765584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.434765584
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.747059844
Short name T252
Test name
Test status
Simulation time 113002991296 ps
CPU time 78.59 seconds
Started Jun 22 04:30:47 PM PDT 24
Finished Jun 22 04:32:07 PM PDT 24
Peak memory 200552 kb
Host smart-f33f3ebc-5068-41ce-9744-fe24bee24061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747059844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.747059844
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.1779901714
Short name T714
Test name
Test status
Simulation time 21353105893 ps
CPU time 37.18 seconds
Started Jun 22 04:30:36 PM PDT 24
Finished Jun 22 04:31:16 PM PDT 24
Peak memory 200396 kb
Host smart-3b04e780-7a0a-4090-bbf2-9b30915c0815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779901714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.1779901714
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.2533440876
Short name T254
Test name
Test status
Simulation time 145167102410 ps
CPU time 41.31 seconds
Started Jun 22 04:30:49 PM PDT 24
Finished Jun 22 04:31:30 PM PDT 24
Peak memory 200512 kb
Host smart-c75f787c-da9e-4cbc-a53e-2b18b15de3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533440876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.2533440876
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.3600256379
Short name T954
Test name
Test status
Simulation time 104329919118 ps
CPU time 252.97 seconds
Started Jun 22 04:30:35 PM PDT 24
Finished Jun 22 04:34:49 PM PDT 24
Peak memory 200540 kb
Host smart-87dcc3aa-d8b1-4721-b851-cd2f407f3a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600256379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.3600256379
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.4106925689
Short name T244
Test name
Test status
Simulation time 48873626892 ps
CPU time 23.02 seconds
Started Jun 22 04:30:37 PM PDT 24
Finished Jun 22 04:31:02 PM PDT 24
Peak memory 200620 kb
Host smart-025b7ed7-e824-4f83-9a59-acb848a79bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106925689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.4106925689
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.1937747992
Short name T1021
Test name
Test status
Simulation time 33500483 ps
CPU time 0.56 seconds
Started Jun 22 04:28:53 PM PDT 24
Finished Jun 22 04:28:55 PM PDT 24
Peak memory 194936 kb
Host smart-762d1a2c-8437-4073-b88a-26748dd389db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937747992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.1937747992
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.239165704
Short name T494
Test name
Test status
Simulation time 33670336302 ps
CPU time 61.15 seconds
Started Jun 22 04:28:54 PM PDT 24
Finished Jun 22 04:29:57 PM PDT 24
Peak memory 200560 kb
Host smart-c49ae111-2655-4239-8f16-f29d261ada9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239165704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.239165704
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.173063738
Short name T421
Test name
Test status
Simulation time 17965156371 ps
CPU time 7.73 seconds
Started Jun 22 04:28:29 PM PDT 24
Finished Jun 22 04:28:37 PM PDT 24
Peak memory 198908 kb
Host smart-6d3cc8a1-ec1e-4f6d-8961-348d42945420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173063738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.173063738
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.3822689687
Short name T182
Test name
Test status
Simulation time 144073586786 ps
CPU time 40.26 seconds
Started Jun 22 04:28:49 PM PDT 24
Finished Jun 22 04:29:30 PM PDT 24
Peak memory 200560 kb
Host smart-555e8a45-bc9f-4b7c-a73e-1b0cb6ccc06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822689687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.3822689687
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.3107440626
Short name T13
Test name
Test status
Simulation time 160489531232 ps
CPU time 36.65 seconds
Started Jun 22 04:28:51 PM PDT 24
Finished Jun 22 04:29:29 PM PDT 24
Peak memory 196700 kb
Host smart-327616f9-ba40-4048-a769-8f1c3c316dee
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107440626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.3107440626
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.2838721483
Short name T960
Test name
Test status
Simulation time 110824840558 ps
CPU time 664.85 seconds
Started Jun 22 04:28:53 PM PDT 24
Finished Jun 22 04:40:00 PM PDT 24
Peak memory 200472 kb
Host smart-bd5609f6-99a9-4a78-a0db-5f14437cd9d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2838721483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.2838721483
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.348253325
Short name T641
Test name
Test status
Simulation time 1706736680 ps
CPU time 2.64 seconds
Started Jun 22 04:28:51 PM PDT 24
Finished Jun 22 04:28:55 PM PDT 24
Peak memory 198188 kb
Host smart-12c57888-5e10-4f83-8c2f-aa4527a4a888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348253325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.348253325
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_perf.2467459926
Short name T409
Test name
Test status
Simulation time 5724045234 ps
CPU time 172.73 seconds
Started Jun 22 04:28:51 PM PDT 24
Finished Jun 22 04:31:45 PM PDT 24
Peak memory 200464 kb
Host smart-ff17ea37-9373-407c-9e87-c39d498e6ecb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2467459926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.2467459926
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.158333507
Short name T917
Test name
Test status
Simulation time 1276613366 ps
CPU time 2.96 seconds
Started Jun 22 04:28:52 PM PDT 24
Finished Jun 22 04:28:57 PM PDT 24
Peak memory 198752 kb
Host smart-1f107e2d-3806-4cc3-a669-419d63754c81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=158333507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.158333507
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.2169618171
Short name T696
Test name
Test status
Simulation time 3032699107 ps
CPU time 5.71 seconds
Started Jun 22 04:28:47 PM PDT 24
Finished Jun 22 04:28:54 PM PDT 24
Peak memory 196392 kb
Host smart-d9d3eb60-5d13-462d-bcc1-5b849f566bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169618171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.2169618171
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.2170653751
Short name T920
Test name
Test status
Simulation time 5811182566 ps
CPU time 7.51 seconds
Started Jun 22 04:28:50 PM PDT 24
Finished Jun 22 04:28:59 PM PDT 24
Peak memory 200328 kb
Host smart-d675c12d-f3fe-46c4-b434-227f3575b713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170653751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.2170653751
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.1608271546
Short name T133
Test name
Test status
Simulation time 61112109520 ps
CPU time 588.94 seconds
Started Jun 22 04:28:44 PM PDT 24
Finished Jun 22 04:38:33 PM PDT 24
Peak memory 217056 kb
Host smart-66721fed-d463-41cf-a990-d2d47368eeae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608271546 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.1608271546
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.2607530594
Short name T375
Test name
Test status
Simulation time 8557407190 ps
CPU time 10.46 seconds
Started Jun 22 04:28:42 PM PDT 24
Finished Jun 22 04:28:53 PM PDT 24
Peak memory 200416 kb
Host smart-d567a178-44d2-418b-b477-8f9a29f9b3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607530594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.2607530594
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.1282361641
Short name T679
Test name
Test status
Simulation time 180174715616 ps
CPU time 100.04 seconds
Started Jun 22 04:28:46 PM PDT 24
Finished Jun 22 04:30:27 PM PDT 24
Peak memory 200564 kb
Host smart-2d7986d2-7b40-4d44-8e1d-ad1cf2f526ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282361641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.1282361641
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.2947179064
Short name T486
Test name
Test status
Simulation time 58247321567 ps
CPU time 95.83 seconds
Started Jun 22 04:30:47 PM PDT 24
Finished Jun 22 04:32:23 PM PDT 24
Peak memory 200464 kb
Host smart-47a70569-aece-484f-b263-e5bdfd449096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947179064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.2947179064
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.3806145668
Short name T719
Test name
Test status
Simulation time 146308941266 ps
CPU time 287.32 seconds
Started Jun 22 04:30:37 PM PDT 24
Finished Jun 22 04:35:26 PM PDT 24
Peak memory 200524 kb
Host smart-c6c599fb-6173-4e4e-9f86-da38571184cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806145668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.3806145668
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.263656286
Short name T152
Test name
Test status
Simulation time 11198759787 ps
CPU time 19.74 seconds
Started Jun 22 04:30:36 PM PDT 24
Finished Jun 22 04:30:57 PM PDT 24
Peak memory 200556 kb
Host smart-d66add9f-0105-48b8-aed3-9327991c9b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263656286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.263656286
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.966875062
Short name T162
Test name
Test status
Simulation time 16138369297 ps
CPU time 10.22 seconds
Started Jun 22 04:30:45 PM PDT 24
Finished Jun 22 04:30:55 PM PDT 24
Peak memory 200572 kb
Host smart-d809ede8-2f80-4e81-b414-8690f106927a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966875062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.966875062
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.886445549
Short name T1090
Test name
Test status
Simulation time 10307897158 ps
CPU time 15.17 seconds
Started Jun 22 04:30:44 PM PDT 24
Finished Jun 22 04:31:00 PM PDT 24
Peak memory 200484 kb
Host smart-3ce2d759-02bc-401c-90f1-b983965708a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886445549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.886445549
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.3235412627
Short name T201
Test name
Test status
Simulation time 166567226772 ps
CPU time 15.94 seconds
Started Jun 22 04:30:42 PM PDT 24
Finished Jun 22 04:30:58 PM PDT 24
Peak memory 200196 kb
Host smart-868e58a4-390c-4254-8836-4e266ea07d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235412627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.3235412627
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.169369279
Short name T164
Test name
Test status
Simulation time 126327953839 ps
CPU time 68.75 seconds
Started Jun 22 04:30:36 PM PDT 24
Finished Jun 22 04:31:47 PM PDT 24
Peak memory 200500 kb
Host smart-2fc091cc-33f8-4a63-908a-5f27fe59b268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169369279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.169369279
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.3681903923
Short name T466
Test name
Test status
Simulation time 116907446924 ps
CPU time 167.45 seconds
Started Jun 22 04:30:48 PM PDT 24
Finished Jun 22 04:33:36 PM PDT 24
Peak memory 200532 kb
Host smart-24fb2e7f-7657-4ac9-9db2-08c6c046a860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681903923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.3681903923
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.3097874190
Short name T30
Test name
Test status
Simulation time 44541811 ps
CPU time 0.54 seconds
Started Jun 22 04:28:47 PM PDT 24
Finished Jun 22 04:28:48 PM PDT 24
Peak memory 195864 kb
Host smart-5812bd18-b469-4bfc-b992-1905f15253d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097874190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.3097874190
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.553776404
Short name T55
Test name
Test status
Simulation time 145842921988 ps
CPU time 48.02 seconds
Started Jun 22 04:28:45 PM PDT 24
Finished Jun 22 04:29:34 PM PDT 24
Peak memory 200464 kb
Host smart-e5ee5cf8-f0cb-4e07-9bf8-34588f5d4237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553776404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.553776404
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.3672563922
Short name T491
Test name
Test status
Simulation time 66594327639 ps
CPU time 28.93 seconds
Started Jun 22 04:28:59 PM PDT 24
Finished Jun 22 04:29:29 PM PDT 24
Peak memory 200456 kb
Host smart-e33c0831-4b0e-49fc-b700-7637bf9ca892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672563922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.3672563922
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.1945739750
Short name T257
Test name
Test status
Simulation time 37606336237 ps
CPU time 64.38 seconds
Started Jun 22 04:28:54 PM PDT 24
Finished Jun 22 04:30:00 PM PDT 24
Peak memory 200556 kb
Host smart-73621f68-da5a-4653-ac66-6ba79b4adc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945739750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.1945739750
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.3163188978
Short name T631
Test name
Test status
Simulation time 7098412659 ps
CPU time 11.57 seconds
Started Jun 22 04:28:44 PM PDT 24
Finished Jun 22 04:28:56 PM PDT 24
Peak memory 197428 kb
Host smart-3022fcd2-e6bf-47a1-9a78-bc4f2ad105fa
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163188978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.3163188978
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.633655112
Short name T1013
Test name
Test status
Simulation time 92336687114 ps
CPU time 583.59 seconds
Started Jun 22 04:28:53 PM PDT 24
Finished Jun 22 04:38:38 PM PDT 24
Peak memory 200484 kb
Host smart-fbddfc65-64e2-4a87-9e81-60ae3578f28e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=633655112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.633655112
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.1465940079
Short name T1084
Test name
Test status
Simulation time 777369575 ps
CPU time 0.95 seconds
Started Jun 22 04:28:50 PM PDT 24
Finished Jun 22 04:28:52 PM PDT 24
Peak memory 196436 kb
Host smart-e7492e65-e6c6-43b6-bc9e-7ed3aae21d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465940079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.1465940079
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_perf.2195878750
Short name T967
Test name
Test status
Simulation time 7636949191 ps
CPU time 385.19 seconds
Started Jun 22 04:28:42 PM PDT 24
Finished Jun 22 04:35:07 PM PDT 24
Peak memory 200452 kb
Host smart-331aea4b-47aa-4866-b1c4-5a637688d8a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2195878750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.2195878750
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.645377067
Short name T834
Test name
Test status
Simulation time 6652891105 ps
CPU time 28.98 seconds
Started Jun 22 04:28:55 PM PDT 24
Finished Jun 22 04:29:25 PM PDT 24
Peak memory 198744 kb
Host smart-5df52cb4-9c6f-4592-8f23-926793b85cc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=645377067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.645377067
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.1394032951
Short name T508
Test name
Test status
Simulation time 21383977300 ps
CPU time 9.25 seconds
Started Jun 22 04:28:50 PM PDT 24
Finished Jun 22 04:29:00 PM PDT 24
Peak memory 199524 kb
Host smart-cf926e71-74e8-4dae-9844-4e0b85d4afb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394032951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.1394032951
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.3587263765
Short name T622
Test name
Test status
Simulation time 4926002341 ps
CPU time 3.86 seconds
Started Jun 22 04:28:49 PM PDT 24
Finished Jun 22 04:28:54 PM PDT 24
Peak memory 196548 kb
Host smart-835b9f14-3ca1-4a99-ae2d-b81c9a31f524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587263765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.3587263765
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.2088349460
Short name T876
Test name
Test status
Simulation time 5529359403 ps
CPU time 7.77 seconds
Started Jun 22 04:28:41 PM PDT 24
Finished Jun 22 04:28:49 PM PDT 24
Peak memory 200388 kb
Host smart-01c9ff31-ab43-4817-9e37-6534c05589fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088349460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.2088349460
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.1877793177
Short name T557
Test name
Test status
Simulation time 210563394232 ps
CPU time 207.46 seconds
Started Jun 22 04:29:56 PM PDT 24
Finished Jun 22 04:33:24 PM PDT 24
Peak memory 200460 kb
Host smart-3247050a-2229-4323-ab80-2a884a595ba1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877793177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.1877793177
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.2219408920
Short name T72
Test name
Test status
Simulation time 81886600681 ps
CPU time 232.46 seconds
Started Jun 22 04:28:40 PM PDT 24
Finished Jun 22 04:32:33 PM PDT 24
Peak memory 217072 kb
Host smart-15eed60a-a988-469e-bcf1-875c7686e7c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219408920 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.2219408920
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.1547426114
Short name T609
Test name
Test status
Simulation time 2482045950 ps
CPU time 2.48 seconds
Started Jun 22 04:28:49 PM PDT 24
Finished Jun 22 04:28:52 PM PDT 24
Peak memory 199028 kb
Host smart-b1d8bb34-de08-46b9-8f02-3e64b74d49e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547426114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.1547426114
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.2824122525
Short name T801
Test name
Test status
Simulation time 53413518060 ps
CPU time 34.75 seconds
Started Jun 22 04:28:50 PM PDT 24
Finished Jun 22 04:29:26 PM PDT 24
Peak memory 200628 kb
Host smart-441cf0a8-ab83-4352-b5d6-860fd4977055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824122525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.2824122525
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.3956774146
Short name T205
Test name
Test status
Simulation time 310128170626 ps
CPU time 141.92 seconds
Started Jun 22 04:30:38 PM PDT 24
Finished Jun 22 04:33:01 PM PDT 24
Peak memory 200540 kb
Host smart-5fb0ea98-5c25-4e8e-987a-2a778c91ed0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956774146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.3956774146
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.2052646189
Short name T241
Test name
Test status
Simulation time 45708760475 ps
CPU time 70.08 seconds
Started Jun 22 04:30:40 PM PDT 24
Finished Jun 22 04:31:51 PM PDT 24
Peak memory 200484 kb
Host smart-fdb7f0c4-12bb-4ec0-b3ac-44facd4524bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052646189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.2052646189
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.2729334415
Short name T211
Test name
Test status
Simulation time 118954808019 ps
CPU time 159.74 seconds
Started Jun 22 04:30:37 PM PDT 24
Finished Jun 22 04:33:18 PM PDT 24
Peak memory 200588 kb
Host smart-6be8588f-7dfb-4717-99b5-a719a8992ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729334415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.2729334415
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.3116082633
Short name T990
Test name
Test status
Simulation time 161416739776 ps
CPU time 243.98 seconds
Started Jun 22 04:30:44 PM PDT 24
Finished Jun 22 04:34:49 PM PDT 24
Peak memory 200484 kb
Host smart-40a5438e-e3d9-4d9b-8fb6-c7722f2cbd93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116082633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.3116082633
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.2914072119
Short name T620
Test name
Test status
Simulation time 32230779720 ps
CPU time 64.95 seconds
Started Jun 22 04:30:47 PM PDT 24
Finished Jun 22 04:31:53 PM PDT 24
Peak memory 200556 kb
Host smart-364abd84-5b77-40f6-899b-4b2e93f967a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914072119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.2914072119
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.632446074
Short name T735
Test name
Test status
Simulation time 148172440793 ps
CPU time 22.09 seconds
Started Jun 22 04:30:48 PM PDT 24
Finished Jun 22 04:31:11 PM PDT 24
Peak memory 200556 kb
Host smart-3730b94d-4df9-4221-859d-1785ac9647fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632446074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.632446074
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.2391021886
Short name T453
Test name
Test status
Simulation time 22515238684 ps
CPU time 40.22 seconds
Started Jun 22 04:30:41 PM PDT 24
Finished Jun 22 04:31:22 PM PDT 24
Peak memory 200516 kb
Host smart-2e33b2e1-c2a9-40bd-8d0f-968e204c1c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391021886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.2391021886
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.2420260798
Short name T576
Test name
Test status
Simulation time 97112912594 ps
CPU time 158.26 seconds
Started Jun 22 04:30:48 PM PDT 24
Finished Jun 22 04:33:27 PM PDT 24
Peak memory 200616 kb
Host smart-a15ae90e-e54a-4c46-845a-e8a13a89c41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420260798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.2420260798
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.555270284
Short name T830
Test name
Test status
Simulation time 22174214641 ps
CPU time 13.04 seconds
Started Jun 22 04:30:47 PM PDT 24
Finished Jun 22 04:31:01 PM PDT 24
Peak memory 200556 kb
Host smart-42327b48-c3c2-4423-b885-7a414a505111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555270284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.555270284
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.1551604914
Short name T434
Test name
Test status
Simulation time 11276746 ps
CPU time 0.55 seconds
Started Jun 22 04:28:57 PM PDT 24
Finished Jun 22 04:28:58 PM PDT 24
Peak memory 195316 kb
Host smart-6f87b981-a95d-4a71-b7e1-4ed558df8876
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551604914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.1551604914
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.2779181616
Short name T1044
Test name
Test status
Simulation time 256195023189 ps
CPU time 124.75 seconds
Started Jun 22 04:28:43 PM PDT 24
Finished Jun 22 04:30:48 PM PDT 24
Peak memory 200564 kb
Host smart-74c7d2d3-e38b-4fc9-9558-da39ec246886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779181616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.2779181616
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.3240086458
Short name T931
Test name
Test status
Simulation time 56055190437 ps
CPU time 50.23 seconds
Started Jun 22 04:28:39 PM PDT 24
Finished Jun 22 04:29:29 PM PDT 24
Peak memory 200460 kb
Host smart-34147c05-6746-422c-a583-9c324e803272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240086458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.3240086458
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.3510045402
Short name T170
Test name
Test status
Simulation time 61774053798 ps
CPU time 61.3 seconds
Started Jun 22 04:28:50 PM PDT 24
Finished Jun 22 04:29:52 PM PDT 24
Peak memory 200476 kb
Host smart-7bcc08be-46a6-435f-b4bc-677bc4e25629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510045402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.3510045402
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.737363282
Short name T695
Test name
Test status
Simulation time 10092971085 ps
CPU time 17.34 seconds
Started Jun 22 04:28:48 PM PDT 24
Finished Jun 22 04:29:07 PM PDT 24
Peak memory 200040 kb
Host smart-1d8120f2-8459-4976-ae0f-e7fb1be1c760
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737363282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.737363282
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.322000251
Short name T1034
Test name
Test status
Simulation time 164148479382 ps
CPU time 675.28 seconds
Started Jun 22 04:28:50 PM PDT 24
Finished Jun 22 04:40:07 PM PDT 24
Peak memory 200496 kb
Host smart-397fdddb-5009-46d0-80d9-0b03858b4282
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=322000251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.322000251
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.2882380282
Short name T689
Test name
Test status
Simulation time 14106841552 ps
CPU time 9.61 seconds
Started Jun 22 04:28:49 PM PDT 24
Finished Jun 22 04:29:00 PM PDT 24
Peak memory 200280 kb
Host smart-6184403a-6165-4af4-a654-9a82db0e8d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882380282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.2882380282
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_perf.1535376136
Short name T392
Test name
Test status
Simulation time 5665001581 ps
CPU time 295.67 seconds
Started Jun 22 04:28:47 PM PDT 24
Finished Jun 22 04:33:44 PM PDT 24
Peak memory 200540 kb
Host smart-f6bb14f8-4072-45ed-9ead-ec047174a55d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1535376136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.1535376136
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.384273366
Short name T370
Test name
Test status
Simulation time 5601051251 ps
CPU time 53.04 seconds
Started Jun 22 04:28:48 PM PDT 24
Finished Jun 22 04:29:42 PM PDT 24
Peak memory 198916 kb
Host smart-ebf7dc3f-56f4-48b7-b8d3-e4f5cb1c0526
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=384273366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.384273366
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.3755089888
Short name T329
Test name
Test status
Simulation time 106246838329 ps
CPU time 82.58 seconds
Started Jun 22 04:28:52 PM PDT 24
Finished Jun 22 04:30:16 PM PDT 24
Peak memory 200184 kb
Host smart-527211bc-8c2d-4904-8bb1-0b28b2a2a186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755089888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.3755089888
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.1536662417
Short name T522
Test name
Test status
Simulation time 4570016350 ps
CPU time 2.48 seconds
Started Jun 22 04:28:47 PM PDT 24
Finished Jun 22 04:28:51 PM PDT 24
Peak memory 196620 kb
Host smart-5493174f-9615-491a-afe0-c2cd6e04bd7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536662417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.1536662417
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.2244759836
Short name T427
Test name
Test status
Simulation time 645709282 ps
CPU time 2.82 seconds
Started Jun 22 04:28:39 PM PDT 24
Finished Jun 22 04:28:43 PM PDT 24
Peak memory 199336 kb
Host smart-4e798bab-cce4-4053-a941-4c12d800a22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244759836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.2244759836
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.635740747
Short name T957
Test name
Test status
Simulation time 119453228477 ps
CPU time 97.25 seconds
Started Jun 22 04:28:53 PM PDT 24
Finished Jun 22 04:30:32 PM PDT 24
Peak memory 200472 kb
Host smart-684620a2-2990-412f-b5ac-ac9406c23f00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635740747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.635740747
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.4225866038
Short name T600
Test name
Test status
Simulation time 833600738 ps
CPU time 2.66 seconds
Started Jun 22 04:28:52 PM PDT 24
Finished Jun 22 04:28:56 PM PDT 24
Peak memory 199832 kb
Host smart-fdf07d9f-70c2-4eb9-9bf0-1bd9443e49a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225866038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.4225866038
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.1223819013
Short name T1020
Test name
Test status
Simulation time 27609337187 ps
CPU time 11.27 seconds
Started Jun 22 04:28:42 PM PDT 24
Finished Jun 22 04:28:54 PM PDT 24
Peak memory 198012 kb
Host smart-efee6a9e-7fa1-4e8d-abb8-ecc15e702e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223819013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.1223819013
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.1651810251
Short name T992
Test name
Test status
Simulation time 33102596562 ps
CPU time 14.3 seconds
Started Jun 22 04:30:45 PM PDT 24
Finished Jun 22 04:31:00 PM PDT 24
Peak memory 200572 kb
Host smart-92066469-e63c-4d69-b393-01601f9d70fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651810251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.1651810251
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.1154523170
Short name T499
Test name
Test status
Simulation time 94248354029 ps
CPU time 32.7 seconds
Started Jun 22 04:30:47 PM PDT 24
Finished Jun 22 04:31:20 PM PDT 24
Peak memory 200596 kb
Host smart-10455d2f-1dd1-49f2-8777-8cd3186ab6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154523170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.1154523170
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.1755284122
Short name T232
Test name
Test status
Simulation time 72277962813 ps
CPU time 33.99 seconds
Started Jun 22 04:30:47 PM PDT 24
Finished Jun 22 04:31:22 PM PDT 24
Peak memory 200852 kb
Host smart-d0bb4abb-1e77-43fe-8e47-e1ef0daa8252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755284122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.1755284122
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.2085398440
Short name T258
Test name
Test status
Simulation time 35229517940 ps
CPU time 55.41 seconds
Started Jun 22 04:30:36 PM PDT 24
Finished Jun 22 04:31:33 PM PDT 24
Peak memory 200440 kb
Host smart-77ea2752-bd65-444b-bc00-38be98f62a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085398440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.2085398440
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.285890814
Short name T220
Test name
Test status
Simulation time 52984398636 ps
CPU time 73.04 seconds
Started Jun 22 04:30:46 PM PDT 24
Finished Jun 22 04:31:59 PM PDT 24
Peak memory 200536 kb
Host smart-38ab9dd7-2fa5-43e5-84de-3e37cb1f9694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285890814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.285890814
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.142249358
Short name T210
Test name
Test status
Simulation time 42262503542 ps
CPU time 16.53 seconds
Started Jun 22 04:30:54 PM PDT 24
Finished Jun 22 04:31:11 PM PDT 24
Peak memory 200444 kb
Host smart-d18bdb3b-4a1d-40d5-8c4f-5e868234cbac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142249358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.142249358
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.2745130193
Short name T540
Test name
Test status
Simulation time 39249698973 ps
CPU time 44.23 seconds
Started Jun 22 04:30:47 PM PDT 24
Finished Jun 22 04:31:32 PM PDT 24
Peak memory 200560 kb
Host smart-63604f29-d9de-4a2a-9965-eb1f5732aab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745130193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.2745130193
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.2861934307
Short name T746
Test name
Test status
Simulation time 80752218413 ps
CPU time 166.16 seconds
Started Jun 22 04:30:42 PM PDT 24
Finished Jun 22 04:33:29 PM PDT 24
Peak memory 200476 kb
Host smart-c3ccd5b4-43d3-4fbe-893f-81119296f777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861934307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.2861934307
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.644302247
Short name T642
Test name
Test status
Simulation time 33090407781 ps
CPU time 57.59 seconds
Started Jun 22 04:30:36 PM PDT 24
Finished Jun 22 04:31:36 PM PDT 24
Peak memory 200556 kb
Host smart-370075ad-dd45-46cc-a1fa-ba7eeb86f78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644302247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.644302247
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.1340434765
Short name T442
Test name
Test status
Simulation time 33456659 ps
CPU time 0.58 seconds
Started Jun 22 04:29:14 PM PDT 24
Finished Jun 22 04:29:16 PM PDT 24
Peak memory 194860 kb
Host smart-c925d27b-690b-42eb-ab4b-022861932b57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340434765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.1340434765
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.1636602735
Short name T6
Test name
Test status
Simulation time 64435175420 ps
CPU time 34.5 seconds
Started Jun 22 04:28:45 PM PDT 24
Finished Jun 22 04:29:21 PM PDT 24
Peak memory 200452 kb
Host smart-2dfcff02-d236-48fe-9bd5-eebcac562187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636602735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.1636602735
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.3928724948
Short name T769
Test name
Test status
Simulation time 26926092471 ps
CPU time 43.44 seconds
Started Jun 22 04:28:53 PM PDT 24
Finished Jun 22 04:29:38 PM PDT 24
Peak memory 200560 kb
Host smart-6f5195f7-862a-4171-8499-984a8bd00a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928724948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.3928724948
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.3366553721
Short name T354
Test name
Test status
Simulation time 24157101072 ps
CPU time 8.48 seconds
Started Jun 22 04:28:54 PM PDT 24
Finished Jun 22 04:29:04 PM PDT 24
Peak memory 199928 kb
Host smart-1a79904c-d4f0-4625-af5d-e43c0910153d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366553721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.3366553721
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.3800328923
Short name T525
Test name
Test status
Simulation time 46404038060 ps
CPU time 237.39 seconds
Started Jun 22 04:28:58 PM PDT 24
Finished Jun 22 04:32:56 PM PDT 24
Peak memory 200464 kb
Host smart-b3c5ef02-b84d-4466-b47a-443867f4f98e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3800328923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.3800328923
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.3594061850
Short name T886
Test name
Test status
Simulation time 2783505893 ps
CPU time 2.11 seconds
Started Jun 22 04:28:45 PM PDT 24
Finished Jun 22 04:28:48 PM PDT 24
Peak memory 197000 kb
Host smart-a36629a5-0335-4484-a60d-747a1ffea885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594061850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.3594061850
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.2424018719
Short name T933
Test name
Test status
Simulation time 39895319546 ps
CPU time 75.12 seconds
Started Jun 22 04:28:42 PM PDT 24
Finished Jun 22 04:29:58 PM PDT 24
Peak memory 200620 kb
Host smart-aad045c4-c856-4a76-93e7-525d4bba6a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424018719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.2424018719
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.3921948570
Short name T885
Test name
Test status
Simulation time 13782492523 ps
CPU time 391.11 seconds
Started Jun 22 04:28:51 PM PDT 24
Finished Jun 22 04:35:23 PM PDT 24
Peak memory 200532 kb
Host smart-f8fcf38b-c46f-4563-a837-9264212dd562
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3921948570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.3921948570
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.669360007
Short name T975
Test name
Test status
Simulation time 5719993076 ps
CPU time 46.99 seconds
Started Jun 22 04:28:39 PM PDT 24
Finished Jun 22 04:29:27 PM PDT 24
Peak memory 198724 kb
Host smart-eba1dffe-606f-4a84-b80d-3d0e849539cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=669360007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.669360007
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.1228957376
Short name T733
Test name
Test status
Simulation time 13992406429 ps
CPU time 22.55 seconds
Started Jun 22 04:28:47 PM PDT 24
Finished Jun 22 04:29:10 PM PDT 24
Peak memory 200616 kb
Host smart-6b27fb2d-85fb-4b9d-8d4b-f2a9e6114c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228957376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.1228957376
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.3631396077
Short name T648
Test name
Test status
Simulation time 3603756778 ps
CPU time 3.51 seconds
Started Jun 22 04:28:53 PM PDT 24
Finished Jun 22 04:28:58 PM PDT 24
Peak memory 196824 kb
Host smart-f2701351-2320-490b-af9a-ae455de2887a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631396077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.3631396077
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.1215262431
Short name T274
Test name
Test status
Simulation time 5716223423 ps
CPU time 11.17 seconds
Started Jun 22 04:28:56 PM PDT 24
Finished Jun 22 04:29:08 PM PDT 24
Peak memory 199704 kb
Host smart-227736a3-b631-4fc3-9f58-f38be6921e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215262431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.1215262431
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.655350096
Short name T625
Test name
Test status
Simulation time 18746206253 ps
CPU time 221.05 seconds
Started Jun 22 04:28:52 PM PDT 24
Finished Jun 22 04:32:35 PM PDT 24
Peak memory 216828 kb
Host smart-fc1b5d54-1b69-48e7-94d8-19c87d037e88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655350096 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.655350096
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.3729452299
Short name T382
Test name
Test status
Simulation time 535866776 ps
CPU time 1.93 seconds
Started Jun 22 04:28:45 PM PDT 24
Finished Jun 22 04:28:48 PM PDT 24
Peak memory 199236 kb
Host smart-466ae8ec-8a81-4f02-911a-a76bb034bbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729452299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.3729452299
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.3858207026
Short name T725
Test name
Test status
Simulation time 101802570919 ps
CPU time 60.43 seconds
Started Jun 22 04:28:50 PM PDT 24
Finished Jun 22 04:29:51 PM PDT 24
Peak memory 200492 kb
Host smart-0283ac2a-04bb-4f58-965f-6df3a50fe671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858207026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.3858207026
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.1232469288
Short name T793
Test name
Test status
Simulation time 12645557806 ps
CPU time 9.26 seconds
Started Jun 22 04:30:48 PM PDT 24
Finished Jun 22 04:30:58 PM PDT 24
Peak memory 200456 kb
Host smart-d9647269-cea0-460d-b3d3-6466a1d297dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232469288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.1232469288
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.847098024
Short name T779
Test name
Test status
Simulation time 13348078164 ps
CPU time 5.98 seconds
Started Jun 22 04:30:57 PM PDT 24
Finished Jun 22 04:31:04 PM PDT 24
Peak memory 200412 kb
Host smart-3b7cda26-55ec-4e7f-8276-103aa01b75d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847098024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.847098024
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.686042343
Short name T332
Test name
Test status
Simulation time 101294493167 ps
CPU time 181.8 seconds
Started Jun 22 04:30:45 PM PDT 24
Finished Jun 22 04:33:48 PM PDT 24
Peak memory 200564 kb
Host smart-283de835-33e5-41a2-8b8f-5c252bcd7fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686042343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.686042343
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.1658149968
Short name T652
Test name
Test status
Simulation time 42039915062 ps
CPU time 65.51 seconds
Started Jun 22 04:30:46 PM PDT 24
Finished Jun 22 04:31:52 PM PDT 24
Peak memory 200544 kb
Host smart-d496ff8f-8a2d-4672-a6fe-220858c99deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658149968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.1658149968
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.2998965604
Short name T265
Test name
Test status
Simulation time 173589818879 ps
CPU time 28.99 seconds
Started Jun 22 04:30:43 PM PDT 24
Finished Jun 22 04:31:13 PM PDT 24
Peak memory 200572 kb
Host smart-9a67af89-e1c8-479b-acd0-5c964b36db4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998965604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.2998965604
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.3032106621
Short name T935
Test name
Test status
Simulation time 12710990737 ps
CPU time 22.59 seconds
Started Jun 22 04:30:45 PM PDT 24
Finished Jun 22 04:31:08 PM PDT 24
Peak memory 200504 kb
Host smart-94086f37-80cb-4885-bfdd-080d7120f92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032106621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.3032106621
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.443546807
Short name T531
Test name
Test status
Simulation time 13008338 ps
CPU time 0.53 seconds
Started Jun 22 04:28:54 PM PDT 24
Finished Jun 22 04:28:56 PM PDT 24
Peak memory 194932 kb
Host smart-45b269eb-8a61-4435-8a81-13be3652615d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443546807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.443546807
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.2900511597
Short name T556
Test name
Test status
Simulation time 275721651933 ps
CPU time 204.14 seconds
Started Jun 22 04:28:46 PM PDT 24
Finished Jun 22 04:32:11 PM PDT 24
Peak memory 200528 kb
Host smart-353e27e1-71ad-4288-b027-e7d07c12a856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900511597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.2900511597
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.2290939436
Short name T983
Test name
Test status
Simulation time 257541348085 ps
CPU time 38.06 seconds
Started Jun 22 04:28:49 PM PDT 24
Finished Jun 22 04:29:28 PM PDT 24
Peak memory 200516 kb
Host smart-909e32c7-5ac4-4d9f-88ac-5215e19c715e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290939436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.2290939436
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_intr.4279095049
Short name T515
Test name
Test status
Simulation time 31058041540 ps
CPU time 13.8 seconds
Started Jun 22 04:28:48 PM PDT 24
Finished Jun 22 04:29:03 PM PDT 24
Peak memory 200540 kb
Host smart-bf791eec-2c9f-4352-8d21-d3f2063e1a55
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279095049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.4279095049
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.1396212514
Short name T579
Test name
Test status
Simulation time 168093829812 ps
CPU time 289.19 seconds
Started Jun 22 04:28:53 PM PDT 24
Finished Jun 22 04:33:44 PM PDT 24
Peak memory 200464 kb
Host smart-f442b12b-045e-46e9-b696-4b64f96d888a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1396212514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.1396212514
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.1982506622
Short name T861
Test name
Test status
Simulation time 348821637 ps
CPU time 0.77 seconds
Started Jun 22 04:28:57 PM PDT 24
Finished Jun 22 04:28:59 PM PDT 24
Peak memory 195964 kb
Host smart-7f0155d3-5507-4b86-bddd-52a385414015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982506622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.1982506622
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.2720532951
Short name T968
Test name
Test status
Simulation time 35899950773 ps
CPU time 64.94 seconds
Started Jun 22 04:28:53 PM PDT 24
Finished Jun 22 04:29:59 PM PDT 24
Peak memory 200516 kb
Host smart-bfc4690f-03c9-442e-bbdb-94ca8be857fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720532951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.2720532951
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.586873000
Short name T480
Test name
Test status
Simulation time 13505280923 ps
CPU time 199.33 seconds
Started Jun 22 04:28:51 PM PDT 24
Finished Jun 22 04:32:11 PM PDT 24
Peak memory 200504 kb
Host smart-3598b3db-181b-490a-8e4a-8a3132350f43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=586873000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.586873000
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.4084383370
Short name T366
Test name
Test status
Simulation time 6064783468 ps
CPU time 48.59 seconds
Started Jun 22 04:29:08 PM PDT 24
Finished Jun 22 04:29:57 PM PDT 24
Peak memory 199968 kb
Host smart-312f00db-2a35-490d-938a-1210d88caf5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4084383370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.4084383370
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.1746765801
Short name T773
Test name
Test status
Simulation time 21417559480 ps
CPU time 24.83 seconds
Started Jun 22 04:28:47 PM PDT 24
Finished Jun 22 04:29:13 PM PDT 24
Peak memory 200460 kb
Host smart-6beaa45e-33d2-42b3-bda4-38c4e470dbb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746765801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.1746765801
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.820572516
Short name T505
Test name
Test status
Simulation time 3496331160 ps
CPU time 1.95 seconds
Started Jun 22 04:28:46 PM PDT 24
Finished Jun 22 04:28:49 PM PDT 24
Peak memory 196364 kb
Host smart-170108ae-1205-47db-a763-c85b69fcb800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820572516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.820572516
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.3821743194
Short name T945
Test name
Test status
Simulation time 485644925 ps
CPU time 2.29 seconds
Started Jun 22 04:29:17 PM PDT 24
Finished Jun 22 04:29:20 PM PDT 24
Peak memory 200480 kb
Host smart-91818224-70a9-442d-8e29-9554ea40feee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821743194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.3821743194
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.3469283135
Short name T845
Test name
Test status
Simulation time 201384772926 ps
CPU time 409.77 seconds
Started Jun 22 04:28:46 PM PDT 24
Finished Jun 22 04:35:36 PM PDT 24
Peak memory 200456 kb
Host smart-0161ba57-0a31-4bb0-b2c9-572c7385305b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469283135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.3469283135
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.4136088387
Short name T19
Test name
Test status
Simulation time 11536167453 ps
CPU time 6.75 seconds
Started Jun 22 04:28:56 PM PDT 24
Finished Jun 22 04:29:04 PM PDT 24
Peak memory 200528 kb
Host smart-41862c6b-fe4b-403c-b0bf-6df9e9e0df4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136088387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.4136088387
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.78264156
Short name T333
Test name
Test status
Simulation time 114264698499 ps
CPU time 74.97 seconds
Started Jun 22 04:29:17 PM PDT 24
Finished Jun 22 04:30:33 PM PDT 24
Peak memory 200472 kb
Host smart-d4f103f1-9f14-42ee-85df-3b675c471338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78264156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.78264156
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.236555841
Short name T742
Test name
Test status
Simulation time 168808820254 ps
CPU time 17.4 seconds
Started Jun 22 04:30:48 PM PDT 24
Finished Jun 22 04:31:06 PM PDT 24
Peak memory 200484 kb
Host smart-cc21a763-591e-4f81-b0b9-73914aeef5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236555841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.236555841
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.2281067718
Short name T26
Test name
Test status
Simulation time 33195597652 ps
CPU time 28.05 seconds
Started Jun 22 04:30:49 PM PDT 24
Finished Jun 22 04:31:17 PM PDT 24
Peak memory 200484 kb
Host smart-7cecf82c-a35c-4900-92b9-b5fa8b5e098f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281067718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.2281067718
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.76846124
Short name T871
Test name
Test status
Simulation time 87196381657 ps
CPU time 80.16 seconds
Started Jun 22 04:30:48 PM PDT 24
Finished Jun 22 04:32:09 PM PDT 24
Peak memory 200484 kb
Host smart-f6e72874-2756-41c9-8060-cdc317e0afde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76846124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.76846124
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.2717872865
Short name T612
Test name
Test status
Simulation time 247834630449 ps
CPU time 26.48 seconds
Started Jun 22 04:30:43 PM PDT 24
Finished Jun 22 04:31:10 PM PDT 24
Peak memory 200560 kb
Host smart-5d12418a-fade-4c59-a554-b25b90c48d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717872865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.2717872865
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.2889267486
Short name T859
Test name
Test status
Simulation time 68822833014 ps
CPU time 107.1 seconds
Started Jun 22 04:30:44 PM PDT 24
Finished Jun 22 04:32:31 PM PDT 24
Peak memory 200540 kb
Host smart-8499baad-0069-46ba-bb56-291c4afa1316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889267486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.2889267486
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.1941578604
Short name T686
Test name
Test status
Simulation time 168573709754 ps
CPU time 66.49 seconds
Started Jun 22 04:30:46 PM PDT 24
Finished Jun 22 04:31:53 PM PDT 24
Peak memory 200844 kb
Host smart-5efd2f62-d947-462a-838e-a282ee35fe16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941578604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.1941578604
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.1589305966
Short name T397
Test name
Test status
Simulation time 12103918580 ps
CPU time 16.16 seconds
Started Jun 22 04:30:47 PM PDT 24
Finished Jun 22 04:31:04 PM PDT 24
Peak memory 200436 kb
Host smart-68c6511f-6118-441d-85ba-170942f45e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589305966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.1589305966
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.3239315876
Short name T337
Test name
Test status
Simulation time 92725114043 ps
CPU time 147.6 seconds
Started Jun 22 04:30:56 PM PDT 24
Finished Jun 22 04:33:24 PM PDT 24
Peak memory 200524 kb
Host smart-ec402f95-b92f-48d3-93f4-1d85d1197f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239315876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.3239315876
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.4281248802
Short name T766
Test name
Test status
Simulation time 11678400 ps
CPU time 0.57 seconds
Started Jun 22 04:28:54 PM PDT 24
Finished Jun 22 04:28:56 PM PDT 24
Peak memory 195388 kb
Host smart-f850df78-ad28-436f-82ce-9d04cd767edb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281248802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.4281248802
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.455973207
Short name T704
Test name
Test status
Simulation time 121511631397 ps
CPU time 30.69 seconds
Started Jun 22 04:28:55 PM PDT 24
Finished Jun 22 04:29:26 PM PDT 24
Peak memory 200528 kb
Host smart-b1854c62-1831-4c01-838d-e7a50873de08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455973207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.455973207
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.3760330050
Short name T474
Test name
Test status
Simulation time 179005852784 ps
CPU time 29.7 seconds
Started Jun 22 04:28:48 PM PDT 24
Finished Jun 22 04:29:19 PM PDT 24
Peak memory 200524 kb
Host smart-d3e2a618-f207-4e2b-b94c-bcde4efdc23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760330050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.3760330050
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.3381680466
Short name T299
Test name
Test status
Simulation time 200579716059 ps
CPU time 92.12 seconds
Started Jun 22 04:28:53 PM PDT 24
Finished Jun 22 04:30:27 PM PDT 24
Peak memory 200544 kb
Host smart-4bf0d434-05f9-4919-9b88-7df3fafa926a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381680466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.3381680466
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.1637050822
Short name T782
Test name
Test status
Simulation time 6206311170 ps
CPU time 13.73 seconds
Started Jun 22 04:28:52 PM PDT 24
Finished Jun 22 04:29:08 PM PDT 24
Peak memory 200428 kb
Host smart-ecaccd37-c7f6-4dda-9568-8573f86f2b13
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637050822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.1637050822
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.1646591392
Short name T323
Test name
Test status
Simulation time 31358207022 ps
CPU time 75.9 seconds
Started Jun 22 04:28:48 PM PDT 24
Finished Jun 22 04:30:05 PM PDT 24
Peak memory 200944 kb
Host smart-328ddc41-ed43-48a5-9920-334d5a160af0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1646591392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.1646591392
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.520897799
Short name T389
Test name
Test status
Simulation time 8494876454 ps
CPU time 2.81 seconds
Started Jun 22 04:28:49 PM PDT 24
Finished Jun 22 04:28:53 PM PDT 24
Peak memory 200164 kb
Host smart-d88aa554-9eea-4589-87d3-d87ae99a3733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520897799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.520897799
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_perf.1772407115
Short name T694
Test name
Test status
Simulation time 25624778309 ps
CPU time 589.46 seconds
Started Jun 22 04:28:51 PM PDT 24
Finished Jun 22 04:38:42 PM PDT 24
Peak memory 200476 kb
Host smart-da61879d-e665-4647-a62d-134f0d0fa1e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1772407115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.1772407115
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.3101111165
Short name T454
Test name
Test status
Simulation time 5181912633 ps
CPU time 23.76 seconds
Started Jun 22 04:29:12 PM PDT 24
Finished Jun 22 04:29:37 PM PDT 24
Peak memory 199984 kb
Host smart-0ef9e6a0-7b1b-4f95-9bff-0d8c2b46f1ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3101111165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.3101111165
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.209697137
Short name T787
Test name
Test status
Simulation time 98779186428 ps
CPU time 74.97 seconds
Started Jun 22 04:28:58 PM PDT 24
Finished Jun 22 04:30:14 PM PDT 24
Peak memory 200504 kb
Host smart-c5b294bd-1143-467e-8058-391d61d0e89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209697137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.209697137
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.304192427
Short name T302
Test name
Test status
Simulation time 44683776422 ps
CPU time 31.46 seconds
Started Jun 22 04:28:53 PM PDT 24
Finished Jun 22 04:29:26 PM PDT 24
Peak memory 196272 kb
Host smart-8530df9f-bd29-4fd1-a942-64f0187b62dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304192427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.304192427
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.3481545428
Short name T783
Test name
Test status
Simulation time 666071612 ps
CPU time 1.54 seconds
Started Jun 22 04:29:09 PM PDT 24
Finished Jun 22 04:29:11 PM PDT 24
Peak memory 198876 kb
Host smart-7906b76a-3eb5-40a8-81e8-47ef652370c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481545428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.3481545428
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.4004228781
Short name T976
Test name
Test status
Simulation time 75595729157 ps
CPU time 105.4 seconds
Started Jun 22 04:28:51 PM PDT 24
Finished Jun 22 04:30:38 PM PDT 24
Peak memory 200444 kb
Host smart-d3c6d40e-c32a-45a7-ae43-0492f98ad6d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004228781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.4004228781
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.1163577783
Short name T762
Test name
Test status
Simulation time 680287485 ps
CPU time 1.61 seconds
Started Jun 22 04:28:55 PM PDT 24
Finished Jun 22 04:28:58 PM PDT 24
Peak memory 199184 kb
Host smart-909bc583-5970-4ab6-a74a-a9ef958b6a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163577783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.1163577783
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.1899677800
Short name T521
Test name
Test status
Simulation time 32448547835 ps
CPU time 16.83 seconds
Started Jun 22 04:28:55 PM PDT 24
Finished Jun 22 04:29:13 PM PDT 24
Peak memory 200528 kb
Host smart-694ae430-1840-4bac-8dd0-a243ddb2c079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899677800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.1899677800
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.1004971704
Short name T717
Test name
Test status
Simulation time 103479986123 ps
CPU time 46.49 seconds
Started Jun 22 04:30:49 PM PDT 24
Finished Jun 22 04:31:36 PM PDT 24
Peak memory 200636 kb
Host smart-a5be2025-0c84-4d05-8b27-4bf668808678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004971704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.1004971704
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.723231163
Short name T628
Test name
Test status
Simulation time 40471691069 ps
CPU time 19.12 seconds
Started Jun 22 04:30:43 PM PDT 24
Finished Jun 22 04:31:02 PM PDT 24
Peak memory 200544 kb
Host smart-276bacfb-301d-4f8d-ad05-7905211898b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723231163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.723231163
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.3694251427
Short name T1004
Test name
Test status
Simulation time 61177232918 ps
CPU time 106.53 seconds
Started Jun 22 04:30:45 PM PDT 24
Finished Jun 22 04:32:32 PM PDT 24
Peak memory 200488 kb
Host smart-93212170-52a0-4bc2-80de-bf12cc938cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694251427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.3694251427
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.607437570
Short name T495
Test name
Test status
Simulation time 59822306124 ps
CPU time 25.94 seconds
Started Jun 22 04:30:46 PM PDT 24
Finished Jun 22 04:31:12 PM PDT 24
Peak memory 200484 kb
Host smart-268a1bf1-cb99-4eba-a678-adf8c8b4de3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607437570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.607437570
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.856000735
Short name T868
Test name
Test status
Simulation time 29085987109 ps
CPU time 12.34 seconds
Started Jun 22 04:30:45 PM PDT 24
Finished Jun 22 04:30:58 PM PDT 24
Peak memory 200604 kb
Host smart-b5495faf-2415-4fba-ba73-eccc076dfec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856000735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.856000735
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.354814341
Short name T790
Test name
Test status
Simulation time 12994565867 ps
CPU time 24.42 seconds
Started Jun 22 04:30:43 PM PDT 24
Finished Jun 22 04:31:08 PM PDT 24
Peak memory 200620 kb
Host smart-95e21891-864b-48fe-8c18-3f41c58f2641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354814341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.354814341
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.4091000281
Short name T245
Test name
Test status
Simulation time 61636161589 ps
CPU time 24.01 seconds
Started Jun 22 04:30:43 PM PDT 24
Finished Jun 22 04:31:08 PM PDT 24
Peak memory 200460 kb
Host smart-9d498cc3-2da4-4dd8-8c92-beb2aaa0e629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091000281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.4091000281
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.2130782144
Short name T8
Test name
Test status
Simulation time 114494711444 ps
CPU time 48.82 seconds
Started Jun 22 04:30:44 PM PDT 24
Finished Jun 22 04:31:33 PM PDT 24
Peak memory 200460 kb
Host smart-b8838683-91e4-4bc4-9569-712e67e8ccda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130782144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.2130782144
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.620608135
Short name T66
Test name
Test status
Simulation time 28710507102 ps
CPU time 29.53 seconds
Started Jun 22 04:30:52 PM PDT 24
Finished Jun 22 04:31:22 PM PDT 24
Peak memory 200524 kb
Host smart-9edc453e-fb64-4502-b5ca-a86bcf46b9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620608135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.620608135
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.4294763848
Short name T456
Test name
Test status
Simulation time 38814607 ps
CPU time 0.53 seconds
Started Jun 22 04:29:07 PM PDT 24
Finished Jun 22 04:29:08 PM PDT 24
Peak memory 195928 kb
Host smart-a36b7f46-c16c-4ae3-86c5-87b0b8292c0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294763848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.4294763848
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.3209547791
Short name T103
Test name
Test status
Simulation time 61166927883 ps
CPU time 21.74 seconds
Started Jun 22 04:28:58 PM PDT 24
Finished Jun 22 04:29:21 PM PDT 24
Peak memory 200552 kb
Host smart-9005b5c4-0e36-4c16-a308-0617a950434e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209547791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.3209547791
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.2187227940
Short name T727
Test name
Test status
Simulation time 21197405356 ps
CPU time 32.56 seconds
Started Jun 22 04:28:53 PM PDT 24
Finished Jun 22 04:29:27 PM PDT 24
Peak memory 200536 kb
Host smart-8d34c32a-c4f9-400d-ab28-0aa6d8be939a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187227940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.2187227940
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.4018812054
Short name T851
Test name
Test status
Simulation time 17420856066 ps
CPU time 32.39 seconds
Started Jun 22 04:28:48 PM PDT 24
Finished Jun 22 04:29:21 PM PDT 24
Peak memory 200416 kb
Host smart-a16c6267-d642-4817-b6c2-1d5c1bacc002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018812054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.4018812054
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.3090296432
Short name T807
Test name
Test status
Simulation time 57600455452 ps
CPU time 25.06 seconds
Started Jun 22 04:29:11 PM PDT 24
Finished Jun 22 04:29:38 PM PDT 24
Peak memory 200472 kb
Host smart-b017da04-612d-46d3-9eb9-fe3ae679a10e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090296432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.3090296432
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.1493011930
Short name T278
Test name
Test status
Simulation time 342681509201 ps
CPU time 480.53 seconds
Started Jun 22 04:29:12 PM PDT 24
Finished Jun 22 04:37:14 PM PDT 24
Peak memory 200524 kb
Host smart-65750902-3641-4e3f-a400-1378368a2bc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1493011930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.1493011930
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.1712625977
Short name T902
Test name
Test status
Simulation time 10167275002 ps
CPU time 15.31 seconds
Started Jun 22 04:29:02 PM PDT 24
Finished Jun 22 04:29:18 PM PDT 24
Peak memory 200304 kb
Host smart-51d032dd-6ead-4e51-92fb-fdcc424135d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712625977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.1712625977
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.1481553093
Short name T345
Test name
Test status
Simulation time 21790330450 ps
CPU time 35.13 seconds
Started Jun 22 04:28:48 PM PDT 24
Finished Jun 22 04:29:24 PM PDT 24
Peak memory 200348 kb
Host smart-b7ad8acc-3578-4462-8459-14835c7bc4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481553093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.1481553093
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.1343720557
Short name T681
Test name
Test status
Simulation time 13373279985 ps
CPU time 289.24 seconds
Started Jun 22 04:29:23 PM PDT 24
Finished Jun 22 04:34:13 PM PDT 24
Peak memory 200472 kb
Host smart-4c718460-a38e-4142-b7fa-fa717aabc5ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1343720557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.1343720557
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.484240546
Short name T511
Test name
Test status
Simulation time 4831563691 ps
CPU time 39.44 seconds
Started Jun 22 04:28:51 PM PDT 24
Finished Jun 22 04:29:31 PM PDT 24
Peak memory 198484 kb
Host smart-1c00a088-466e-4f06-88c1-042188c1b3be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=484240546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.484240546
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.1556647457
Short name T829
Test name
Test status
Simulation time 94715667976 ps
CPU time 25.24 seconds
Started Jun 22 04:29:00 PM PDT 24
Finished Jun 22 04:29:26 PM PDT 24
Peak memory 200616 kb
Host smart-65baed09-db81-4435-bbca-a06f9196759f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556647457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.1556647457
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.3028610710
Short name T924
Test name
Test status
Simulation time 1473664023 ps
CPU time 3.13 seconds
Started Jun 22 04:28:46 PM PDT 24
Finished Jun 22 04:28:50 PM PDT 24
Peak memory 195960 kb
Host smart-82721219-07db-4584-b740-236f109b5d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028610710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.3028610710
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.3279663850
Short name T594
Test name
Test status
Simulation time 6013519767 ps
CPU time 12.01 seconds
Started Jun 22 04:29:05 PM PDT 24
Finished Jun 22 04:29:18 PM PDT 24
Peak memory 200284 kb
Host smart-f737c6a2-c011-4156-8467-d83f92ca0792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279663850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.3279663850
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.1045274181
Short name T848
Test name
Test status
Simulation time 213317664869 ps
CPU time 1293.67 seconds
Started Jun 22 04:28:56 PM PDT 24
Finished Jun 22 04:50:31 PM PDT 24
Peak memory 200396 kb
Host smart-d706b092-0c4a-41e6-9c8c-0ce60cf53b58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045274181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.1045274181
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.2972271244
Short name T915
Test name
Test status
Simulation time 715534787 ps
CPU time 2.33 seconds
Started Jun 22 04:28:57 PM PDT 24
Finished Jun 22 04:29:00 PM PDT 24
Peak memory 200080 kb
Host smart-d64b1a6d-401b-4db7-8ea4-9da76b37186a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972271244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.2972271244
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.3281903808
Short name T149
Test name
Test status
Simulation time 162576853009 ps
CPU time 65.77 seconds
Started Jun 22 04:29:10 PM PDT 24
Finished Jun 22 04:30:17 PM PDT 24
Peak memory 200532 kb
Host smart-1866cb8f-b20f-49a3-bcb7-5bfa25deafd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281903808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.3281903808
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.3725603698
Short name T939
Test name
Test status
Simulation time 24798132016 ps
CPU time 56.11 seconds
Started Jun 22 04:30:51 PM PDT 24
Finished Jun 22 04:31:48 PM PDT 24
Peak memory 200484 kb
Host smart-345a05d2-01b1-4de6-80fd-25d51d426a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725603698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.3725603698
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.2913062258
Short name T372
Test name
Test status
Simulation time 47142474395 ps
CPU time 17.76 seconds
Started Jun 22 04:30:51 PM PDT 24
Finished Jun 22 04:31:10 PM PDT 24
Peak memory 200316 kb
Host smart-0c0d9b1c-65b8-4b6b-a1ba-a8e483ea9845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913062258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.2913062258
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.923795440
Short name T44
Test name
Test status
Simulation time 53343903506 ps
CPU time 37.03 seconds
Started Jun 22 04:30:52 PM PDT 24
Finished Jun 22 04:31:30 PM PDT 24
Peak memory 200320 kb
Host smart-becd3e05-53fd-45de-af92-85b27e183f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923795440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.923795440
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.1672914285
Short name T1069
Test name
Test status
Simulation time 81499017808 ps
CPU time 239.71 seconds
Started Jun 22 04:30:50 PM PDT 24
Finished Jun 22 04:34:50 PM PDT 24
Peak memory 200492 kb
Host smart-597d3939-fffe-4ba0-ace8-35bc41e93034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672914285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.1672914285
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.4073250707
Short name T899
Test name
Test status
Simulation time 55266330312 ps
CPU time 81.75 seconds
Started Jun 22 04:30:52 PM PDT 24
Finished Jun 22 04:32:14 PM PDT 24
Peak memory 200484 kb
Host smart-a2ee3167-f46f-4824-af1d-1c8937a075e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073250707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.4073250707
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.4166998561
Short name T305
Test name
Test status
Simulation time 41613463016 ps
CPU time 20.8 seconds
Started Jun 22 04:30:51 PM PDT 24
Finished Jun 22 04:31:12 PM PDT 24
Peak memory 200484 kb
Host smart-ab2ee6da-47d3-40a5-b771-016c72235587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166998561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.4166998561
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.66644071
Short name T606
Test name
Test status
Simulation time 86248480320 ps
CPU time 142.33 seconds
Started Jun 22 04:30:52 PM PDT 24
Finished Jun 22 04:33:15 PM PDT 24
Peak memory 200540 kb
Host smart-c201078a-f5dc-4b17-8c36-8bd9c1246f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66644071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.66644071
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.1970352868
Short name T858
Test name
Test status
Simulation time 36536219438 ps
CPU time 26.39 seconds
Started Jun 22 04:30:51 PM PDT 24
Finished Jun 22 04:31:18 PM PDT 24
Peak memory 200508 kb
Host smart-b57c5a9a-a1a5-45d1-993c-2a12dfeb7891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970352868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.1970352868
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.3656238275
Short name T805
Test name
Test status
Simulation time 151459554290 ps
CPU time 239.51 seconds
Started Jun 22 04:30:50 PM PDT 24
Finished Jun 22 04:34:50 PM PDT 24
Peak memory 200492 kb
Host smart-df670eac-98ae-46a7-8811-963bb779be11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656238275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.3656238275
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.3576692861
Short name T203
Test name
Test status
Simulation time 67112967296 ps
CPU time 92.77 seconds
Started Jun 22 04:30:51 PM PDT 24
Finished Jun 22 04:32:24 PM PDT 24
Peak memory 200544 kb
Host smart-a0161fe0-44fe-4a09-9858-f67b02821cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576692861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.3576692861
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.2450793669
Short name T909
Test name
Test status
Simulation time 46041154 ps
CPU time 0.57 seconds
Started Jun 22 04:29:13 PM PDT 24
Finished Jun 22 04:29:15 PM PDT 24
Peak memory 195976 kb
Host smart-78631815-76b3-4975-aa9a-f5fd51539937
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450793669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.2450793669
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.2071453080
Short name T1028
Test name
Test status
Simulation time 86197538523 ps
CPU time 145.14 seconds
Started Jun 22 04:29:06 PM PDT 24
Finished Jun 22 04:31:32 PM PDT 24
Peak memory 200488 kb
Host smart-45612b98-7e2d-4d32-9c28-d1577a6d6426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071453080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.2071453080
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.4084104635
Short name T997
Test name
Test status
Simulation time 144487686538 ps
CPU time 102.89 seconds
Started Jun 22 04:28:58 PM PDT 24
Finished Jun 22 04:30:42 PM PDT 24
Peak memory 200528 kb
Host smart-859580a9-5508-4ec7-98a7-82fc7dd091fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084104635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.4084104635
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.1478179975
Short name T1066
Test name
Test status
Simulation time 67501002149 ps
CPU time 14.66 seconds
Started Jun 22 04:29:11 PM PDT 24
Finished Jun 22 04:29:27 PM PDT 24
Peak memory 200440 kb
Host smart-f2463d69-7869-4e6a-bee8-cac5c7a31ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478179975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.1478179975
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.3863817765
Short name T884
Test name
Test status
Simulation time 24162662832 ps
CPU time 7.24 seconds
Started Jun 22 04:28:58 PM PDT 24
Finished Jun 22 04:29:06 PM PDT 24
Peak memory 200456 kb
Host smart-22a06210-d9c5-469b-9479-45dd8f977605
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863817765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.3863817765
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.2351903185
Short name T319
Test name
Test status
Simulation time 110299504293 ps
CPU time 231.36 seconds
Started Jun 22 04:28:58 PM PDT 24
Finished Jun 22 04:32:50 PM PDT 24
Peak memory 200476 kb
Host smart-70273f4e-86cd-4dce-8d8f-44871d043e25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2351903185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.2351903185
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.2316233798
Short name T903
Test name
Test status
Simulation time 6220583215 ps
CPU time 10.22 seconds
Started Jun 22 04:28:55 PM PDT 24
Finished Jun 22 04:29:06 PM PDT 24
Peak memory 200264 kb
Host smart-5f1f90cc-3dab-4cd3-b5b9-242296fdb1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316233798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.2316233798
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_perf.285807394
Short name T339
Test name
Test status
Simulation time 12267589990 ps
CPU time 687.08 seconds
Started Jun 22 04:28:57 PM PDT 24
Finished Jun 22 04:40:25 PM PDT 24
Peak memory 200540 kb
Host smart-57ea0c7c-062a-4e72-99ef-62837a38f5cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=285807394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.285807394
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.3270086674
Short name T373
Test name
Test status
Simulation time 5322830239 ps
CPU time 12.49 seconds
Started Jun 22 04:28:59 PM PDT 24
Finished Jun 22 04:29:12 PM PDT 24
Peak memory 199848 kb
Host smart-f13c79c8-604d-41f5-bf53-5f79b7c66610
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3270086674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.3270086674
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.204249303
Short name T120
Test name
Test status
Simulation time 80965759256 ps
CPU time 8.98 seconds
Started Jun 22 04:28:58 PM PDT 24
Finished Jun 22 04:29:08 PM PDT 24
Peak memory 196372 kb
Host smart-9e4886b9-7785-4e97-b2c8-dd18c5fbcd42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204249303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.204249303
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.864471871
Short name T632
Test name
Test status
Simulation time 640599150 ps
CPU time 1.49 seconds
Started Jun 22 04:28:55 PM PDT 24
Finished Jun 22 04:28:58 PM PDT 24
Peak memory 200292 kb
Host smart-be23c91f-929b-4e7f-8ad9-c4a5e59ccb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864471871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.864471871
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.4105175810
Short name T537
Test name
Test status
Simulation time 21886533639 ps
CPU time 427.19 seconds
Started Jun 22 04:29:03 PM PDT 24
Finished Jun 22 04:36:11 PM PDT 24
Peak memory 216248 kb
Host smart-f5433769-0d7b-47f2-a905-e47bf22dc1fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105175810 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.4105175810
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.3141103458
Short name T18
Test name
Test status
Simulation time 1373349723 ps
CPU time 1.67 seconds
Started Jun 22 04:29:18 PM PDT 24
Finished Jun 22 04:29:20 PM PDT 24
Peak memory 199324 kb
Host smart-ca03915f-db48-4bfa-b3de-c795a6357de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141103458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.3141103458
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.2582032725
Short name T763
Test name
Test status
Simulation time 70840663674 ps
CPU time 114.48 seconds
Started Jun 22 04:29:14 PM PDT 24
Finished Jun 22 04:31:10 PM PDT 24
Peak memory 200596 kb
Host smart-6cbdaafb-b328-4f52-b816-6100b6a8d787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582032725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.2582032725
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.130432311
Short name T771
Test name
Test status
Simulation time 162427713479 ps
CPU time 71.16 seconds
Started Jun 22 04:30:52 PM PDT 24
Finished Jun 22 04:32:04 PM PDT 24
Peak memory 200484 kb
Host smart-5bb51a94-9612-48cc-bf38-d7d7bb366927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130432311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.130432311
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.379423802
Short name T703
Test name
Test status
Simulation time 81757001103 ps
CPU time 154.95 seconds
Started Jun 22 04:30:54 PM PDT 24
Finished Jun 22 04:33:29 PM PDT 24
Peak memory 200552 kb
Host smart-4de6ac22-f99d-41d9-aba9-031b2674fba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379423802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.379423802
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.1247888680
Short name T893
Test name
Test status
Simulation time 11905798926 ps
CPU time 9.39 seconds
Started Jun 22 04:30:52 PM PDT 24
Finished Jun 22 04:31:02 PM PDT 24
Peak memory 200576 kb
Host smart-6c23456a-f2c0-4407-b661-97ee5b423691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247888680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.1247888680
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.1579256751
Short name T126
Test name
Test status
Simulation time 80550508058 ps
CPU time 59.77 seconds
Started Jun 22 04:30:52 PM PDT 24
Finished Jun 22 04:31:52 PM PDT 24
Peak memory 200372 kb
Host smart-4a899093-62ff-4403-83e6-283dffa12a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579256751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.1579256751
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.2188620427
Short name T803
Test name
Test status
Simulation time 82852259761 ps
CPU time 13.85 seconds
Started Jun 22 04:30:51 PM PDT 24
Finished Jun 22 04:31:06 PM PDT 24
Peak memory 200528 kb
Host smart-b9539d22-1eee-4c67-bec2-44f71addf36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188620427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.2188620427
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.237867480
Short name T157
Test name
Test status
Simulation time 101759085340 ps
CPU time 43.65 seconds
Started Jun 22 04:30:50 PM PDT 24
Finished Jun 22 04:31:34 PM PDT 24
Peak memory 200468 kb
Host smart-6f32cac5-7c65-4d6a-994f-eefad0855179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237867480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.237867480
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.2109510398
Short name T1053
Test name
Test status
Simulation time 12764539767 ps
CPU time 18.24 seconds
Started Jun 22 04:30:51 PM PDT 24
Finished Jun 22 04:31:10 PM PDT 24
Peak memory 200500 kb
Host smart-cb545285-3382-46b4-99f4-06d8ea243105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109510398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.2109510398
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.538633285
Short name T228
Test name
Test status
Simulation time 43283846344 ps
CPU time 17.39 seconds
Started Jun 22 04:30:57 PM PDT 24
Finished Jun 22 04:31:14 PM PDT 24
Peak memory 200464 kb
Host smart-1e3a5120-1aab-4810-986e-e6d932998abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538633285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.538633285
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.2089427889
Short name T887
Test name
Test status
Simulation time 55010654730 ps
CPU time 45.31 seconds
Started Jun 22 04:30:52 PM PDT 24
Finished Jun 22 04:31:38 PM PDT 24
Peak memory 200512 kb
Host smart-54785cde-9b50-4fec-97c0-2f618ea9bc30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089427889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.2089427889
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.2568148317
Short name T865
Test name
Test status
Simulation time 16417184795 ps
CPU time 27.04 seconds
Started Jun 22 04:30:58 PM PDT 24
Finished Jun 22 04:31:26 PM PDT 24
Peak memory 200488 kb
Host smart-da98c214-4021-461b-9aea-6a89452280a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568148317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.2568148317
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.1263856761
Short name T461
Test name
Test status
Simulation time 41098855 ps
CPU time 0.56 seconds
Started Jun 22 04:29:11 PM PDT 24
Finished Jun 22 04:29:13 PM PDT 24
Peak memory 195864 kb
Host smart-443d2cd4-b5f1-4dc9-b0de-eb9819695d0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263856761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.1263856761
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.65649941
Short name T544
Test name
Test status
Simulation time 58547935186 ps
CPU time 55.06 seconds
Started Jun 22 04:29:06 PM PDT 24
Finished Jun 22 04:30:01 PM PDT 24
Peak memory 200528 kb
Host smart-f9e7ca16-454d-4475-ac6c-39a88d7772e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65649941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.65649941
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.1255714517
Short name T907
Test name
Test status
Simulation time 14719665978 ps
CPU time 25.58 seconds
Started Jun 22 04:28:55 PM PDT 24
Finished Jun 22 04:29:21 PM PDT 24
Peak memory 200576 kb
Host smart-1fae01de-e912-47d7-abce-7b22a2961832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255714517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.1255714517
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.2443283896
Short name T852
Test name
Test status
Simulation time 15284574486 ps
CPU time 54.75 seconds
Started Jun 22 04:29:03 PM PDT 24
Finished Jun 22 04:29:59 PM PDT 24
Peak memory 200568 kb
Host smart-f4cd7f06-8086-4489-a915-636044c7ba06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443283896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.2443283896
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.2676545224
Short name T534
Test name
Test status
Simulation time 45030240341 ps
CPU time 85.3 seconds
Started Jun 22 04:28:58 PM PDT 24
Finished Jun 22 04:30:25 PM PDT 24
Peak memory 200548 kb
Host smart-6f43f13a-97b0-4195-a7bc-363aa35b221d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676545224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.2676545224
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.274252145
Short name T687
Test name
Test status
Simulation time 118928937681 ps
CPU time 350.54 seconds
Started Jun 22 04:29:01 PM PDT 24
Finished Jun 22 04:34:53 PM PDT 24
Peak memory 200504 kb
Host smart-c96fc193-559d-4990-b363-847dc9793da4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=274252145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.274252145
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.315146582
Short name T798
Test name
Test status
Simulation time 7689289730 ps
CPU time 12.72 seconds
Started Jun 22 04:29:11 PM PDT 24
Finished Jun 22 04:29:25 PM PDT 24
Peak memory 200048 kb
Host smart-bb9d0a2b-899f-4adc-a499-9b2ba9dd84a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315146582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.315146582
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_perf.2182618635
Short name T1050
Test name
Test status
Simulation time 20302697383 ps
CPU time 1087.88 seconds
Started Jun 22 04:29:00 PM PDT 24
Finished Jun 22 04:47:09 PM PDT 24
Peak memory 200576 kb
Host smart-c0268521-5657-4849-bb40-315ef4c5ec49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2182618635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.2182618635
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.1291168160
Short name T371
Test name
Test status
Simulation time 3265613671 ps
CPU time 11.86 seconds
Started Jun 22 04:30:06 PM PDT 24
Finished Jun 22 04:30:19 PM PDT 24
Peak memory 199536 kb
Host smart-f4d45a82-3749-4a72-ad26-c52352aed84c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1291168160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.1291168160
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.2218323716
Short name T894
Test name
Test status
Simulation time 129652761370 ps
CPU time 39.77 seconds
Started Jun 22 04:29:05 PM PDT 24
Finished Jun 22 04:29:45 PM PDT 24
Peak memory 200452 kb
Host smart-d363a4e4-e670-41a6-ae09-f904f6d3453d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218323716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.2218323716
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.2356560457
Short name T411
Test name
Test status
Simulation time 2167915642 ps
CPU time 4.06 seconds
Started Jun 22 04:29:00 PM PDT 24
Finished Jun 22 04:29:05 PM PDT 24
Peak memory 196084 kb
Host smart-f80f2c39-a69a-4162-a945-80b08c1b5ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356560457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.2356560457
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.2772683966
Short name T669
Test name
Test status
Simulation time 6246968877 ps
CPU time 18.16 seconds
Started Jun 22 04:28:56 PM PDT 24
Finished Jun 22 04:29:15 PM PDT 24
Peak memory 200264 kb
Host smart-bebfceea-3b20-4b93-ac8a-2352c5251fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772683966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.2772683966
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.59889605
Short name T626
Test name
Test status
Simulation time 12280482938 ps
CPU time 361.83 seconds
Started Jun 22 04:28:58 PM PDT 24
Finished Jun 22 04:35:01 PM PDT 24
Peak memory 216312 kb
Host smart-5c89180e-4831-4c53-951d-46a553c36c51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59889605 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.59889605
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.1559495420
Short name T383
Test name
Test status
Simulation time 8190115292 ps
CPU time 9.67 seconds
Started Jun 22 04:29:03 PM PDT 24
Finished Jun 22 04:29:14 PM PDT 24
Peak memory 200288 kb
Host smart-d518f368-8939-4c6a-89a5-b7290d594d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559495420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.1559495420
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.1830005523
Short name T993
Test name
Test status
Simulation time 57925099757 ps
CPU time 84.59 seconds
Started Jun 22 04:28:56 PM PDT 24
Finished Jun 22 04:30:22 PM PDT 24
Peak memory 200472 kb
Host smart-dac9a079-68ee-4a56-91cb-ac9968cff952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830005523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.1830005523
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.3826670892
Short name T539
Test name
Test status
Simulation time 163207697138 ps
CPU time 392.84 seconds
Started Jun 22 04:30:51 PM PDT 24
Finished Jun 22 04:37:25 PM PDT 24
Peak memory 200544 kb
Host smart-01bfecdb-93b2-47b8-bb97-03b45eb5600e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826670892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.3826670892
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.3285370796
Short name T1018
Test name
Test status
Simulation time 52759847382 ps
CPU time 49.12 seconds
Started Jun 22 04:30:59 PM PDT 24
Finished Jun 22 04:31:49 PM PDT 24
Peak memory 200472 kb
Host smart-51c83ead-910d-4c56-9b4d-70051cccf093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285370796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.3285370796
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.3965448703
Short name T921
Test name
Test status
Simulation time 56492001708 ps
CPU time 40.57 seconds
Started Jun 22 04:31:01 PM PDT 24
Finished Jun 22 04:31:42 PM PDT 24
Peak memory 200464 kb
Host smart-911da812-7b9d-4f27-b4b0-a869c73c0246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965448703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.3965448703
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.3051284557
Short name T595
Test name
Test status
Simulation time 139251491664 ps
CPU time 85.9 seconds
Started Jun 22 04:30:59 PM PDT 24
Finished Jun 22 04:32:25 PM PDT 24
Peak memory 200528 kb
Host smart-8cd0eecc-9537-4089-89c7-a46d06b18463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051284557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.3051284557
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.4231164798
Short name T1089
Test name
Test status
Simulation time 42420097615 ps
CPU time 40.12 seconds
Started Jun 22 04:31:01 PM PDT 24
Finished Jun 22 04:31:42 PM PDT 24
Peak memory 200552 kb
Host smart-8297659a-b896-493d-8528-b159749b79f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231164798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.4231164798
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.2242760769
Short name T951
Test name
Test status
Simulation time 28309099380 ps
CPU time 42.77 seconds
Started Jun 22 04:30:57 PM PDT 24
Finished Jun 22 04:31:40 PM PDT 24
Peak memory 200220 kb
Host smart-1a424987-2f58-4c4a-adad-8d2344925b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242760769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.2242760769
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.699340420
Short name T657
Test name
Test status
Simulation time 151361234171 ps
CPU time 85.95 seconds
Started Jun 22 04:30:59 PM PDT 24
Finished Jun 22 04:32:26 PM PDT 24
Peak memory 200564 kb
Host smart-afde99b9-75ca-4178-ba1b-f30e903b2909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699340420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.699340420
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.2339067993
Short name T794
Test name
Test status
Simulation time 13269146429 ps
CPU time 19.84 seconds
Started Jun 22 04:31:02 PM PDT 24
Finished Jun 22 04:31:22 PM PDT 24
Peak memory 200592 kb
Host smart-864252cd-76d0-4829-af6e-465e3f049d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339067993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.2339067993
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.1830095365
Short name T326
Test name
Test status
Simulation time 60539302622 ps
CPU time 52.75 seconds
Started Jun 22 04:30:58 PM PDT 24
Finished Jun 22 04:31:51 PM PDT 24
Peak memory 200456 kb
Host smart-e4e64616-6da4-42ea-8caf-888462d2e3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830095365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.1830095365
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.2903036900
Short name T477
Test name
Test status
Simulation time 13717207 ps
CPU time 0.54 seconds
Started Jun 22 04:27:55 PM PDT 24
Finished Jun 22 04:27:57 PM PDT 24
Peak memory 195860 kb
Host smart-4ba9d00e-3ebb-4fc3-88aa-71f38eb9046a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903036900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.2903036900
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.3333478724
Short name T190
Test name
Test status
Simulation time 297401095132 ps
CPU time 353.92 seconds
Started Jun 22 04:28:03 PM PDT 24
Finished Jun 22 04:33:59 PM PDT 24
Peak memory 200464 kb
Host smart-546d6345-18aa-4d62-b797-898c8b6d8cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333478724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.3333478724
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.2235214226
Short name T949
Test name
Test status
Simulation time 268878478628 ps
CPU time 81.83 seconds
Started Jun 22 04:27:56 PM PDT 24
Finished Jun 22 04:29:19 PM PDT 24
Peak memory 200524 kb
Host smart-11a5f7da-abe9-4f37-aaa8-9a7571b5d985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235214226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.2235214226
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.2903262187
Short name T320
Test name
Test status
Simulation time 113170289184 ps
CPU time 175.35 seconds
Started Jun 22 04:27:59 PM PDT 24
Finished Jun 22 04:30:56 PM PDT 24
Peak memory 200460 kb
Host smart-0d6cfc4a-dee5-4e23-956c-a8a04ccb30b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903262187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.2903262187
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.692818576
Short name T67
Test name
Test status
Simulation time 47252636881 ps
CPU time 387.87 seconds
Started Jun 22 04:28:15 PM PDT 24
Finished Jun 22 04:34:45 PM PDT 24
Peak memory 200480 kb
Host smart-ffb55f70-dabe-4f13-aaf7-0b2d63b940ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=692818576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.692818576
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.2553079014
Short name T965
Test name
Test status
Simulation time 5666333395 ps
CPU time 13.44 seconds
Started Jun 22 04:27:59 PM PDT 24
Finished Jun 22 04:28:14 PM PDT 24
Peak memory 200284 kb
Host smart-a1c2cdb8-41e3-43ac-99b0-a4d60ee509fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553079014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.2553079014
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_perf.2357392997
Short name T285
Test name
Test status
Simulation time 11208859503 ps
CPU time 440.61 seconds
Started Jun 22 04:28:03 PM PDT 24
Finished Jun 22 04:35:25 PM PDT 24
Peak memory 200440 kb
Host smart-5553745b-e666-40e7-9e0f-0dbb1df22ca3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2357392997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.2357392997
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.3680298606
Short name T61
Test name
Test status
Simulation time 2631263752 ps
CPU time 9.81 seconds
Started Jun 22 04:27:56 PM PDT 24
Finished Jun 22 04:28:07 PM PDT 24
Peak memory 198724 kb
Host smart-3f34237e-59e8-4f9c-8e3b-80e9550f868e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3680298606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3680298606
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.4047635533
Short name T959
Test name
Test status
Simulation time 121036692787 ps
CPU time 102.8 seconds
Started Jun 22 04:28:06 PM PDT 24
Finished Jun 22 04:29:50 PM PDT 24
Peak memory 200492 kb
Host smart-db7822a0-3696-4c43-b592-5e8f02f07da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047635533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.4047635533
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.1389925260
Short name T376
Test name
Test status
Simulation time 34931878943 ps
CPU time 26.12 seconds
Started Jun 22 04:27:51 PM PDT 24
Finished Jun 22 04:28:18 PM PDT 24
Peak memory 196780 kb
Host smart-487af5ac-bf72-4c35-928f-2c9e23520d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389925260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.1389925260
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_smoke.4100894868
Short name T768
Test name
Test status
Simulation time 5978500067 ps
CPU time 11.29 seconds
Started Jun 22 04:28:01 PM PDT 24
Finished Jun 22 04:28:15 PM PDT 24
Peak memory 200280 kb
Host smart-eb97f4c9-ec61-4003-b010-ab6997060a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100894868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.4100894868
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.2611116057
Short name T702
Test name
Test status
Simulation time 20520255529 ps
CPU time 251.04 seconds
Started Jun 22 04:27:56 PM PDT 24
Finished Jun 22 04:32:08 PM PDT 24
Peak memory 216440 kb
Host smart-d3a96f38-51db-4df5-aa2c-94d8d0dd6745
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611116057 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.2611116057
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.286254869
Short name T672
Test name
Test status
Simulation time 1460159986 ps
CPU time 2.19 seconds
Started Jun 22 04:28:02 PM PDT 24
Finished Jun 22 04:28:06 PM PDT 24
Peak memory 199576 kb
Host smart-c600722b-52d7-4a9c-8812-eb1fcbc570b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286254869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.286254869
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.1859723279
Short name T775
Test name
Test status
Simulation time 34922871230 ps
CPU time 16.01 seconds
Started Jun 22 04:27:56 PM PDT 24
Finished Jun 22 04:28:13 PM PDT 24
Peak memory 200440 kb
Host smart-26d159d0-452d-4ed2-935e-59b54ae28519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859723279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.1859723279
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.1719700923
Short name T621
Test name
Test status
Simulation time 12552675 ps
CPU time 0.56 seconds
Started Jun 22 04:28:58 PM PDT 24
Finished Jun 22 04:28:59 PM PDT 24
Peak memory 195864 kb
Host smart-f8097842-52f9-4937-b0c6-ee4cc6f9141f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719700923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.1719700923
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.2571594387
Short name T618
Test name
Test status
Simulation time 138768264851 ps
CPU time 192.02 seconds
Started Jun 22 04:29:14 PM PDT 24
Finished Jun 22 04:32:28 PM PDT 24
Peak memory 200452 kb
Host smart-d58615f8-fd2e-4835-8c9a-5a522c7c48ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571594387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.2571594387
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_intr.1380925085
Short name T721
Test name
Test status
Simulation time 11296897641 ps
CPU time 4.65 seconds
Started Jun 22 04:28:59 PM PDT 24
Finished Jun 22 04:29:04 PM PDT 24
Peak memory 197844 kb
Host smart-6b1fd680-f5e2-4bc7-ba71-31e026b98c97
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380925085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.1380925085
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.1690238180
Short name T707
Test name
Test status
Simulation time 114520479619 ps
CPU time 411.97 seconds
Started Jun 22 04:28:59 PM PDT 24
Finished Jun 22 04:35:52 PM PDT 24
Peak memory 200496 kb
Host smart-aa2d8a70-0f5a-41f0-9224-b2c22a400720
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1690238180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.1690238180
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.1716902202
Short name T896
Test name
Test status
Simulation time 5964685033 ps
CPU time 4.66 seconds
Started Jun 22 04:28:57 PM PDT 24
Finished Jun 22 04:29:03 PM PDT 24
Peak memory 200268 kb
Host smart-10a5995c-32e6-43b0-80a2-87cf35ddefcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716902202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.1716902202
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_perf.1198750282
Short name T457
Test name
Test status
Simulation time 7153011143 ps
CPU time 416.95 seconds
Started Jun 22 04:29:01 PM PDT 24
Finished Jun 22 04:35:59 PM PDT 24
Peak memory 200532 kb
Host smart-d0780ef4-4dc9-4d17-9a9f-3fde43dda044
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1198750282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.1198750282
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.2341273707
Short name T904
Test name
Test status
Simulation time 3282490636 ps
CPU time 1.82 seconds
Started Jun 22 04:29:00 PM PDT 24
Finished Jun 22 04:29:03 PM PDT 24
Peak memory 198968 kb
Host smart-3425619c-2512-410e-bfeb-775db9cd57d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2341273707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.2341273707
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.3450031175
Short name T979
Test name
Test status
Simulation time 82724245857 ps
CPU time 142.78 seconds
Started Jun 22 04:29:03 PM PDT 24
Finished Jun 22 04:31:27 PM PDT 24
Peak memory 200540 kb
Host smart-f807d098-060c-4971-a5a2-4bf7f6c11bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450031175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.3450031175
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.721128840
Short name T840
Test name
Test status
Simulation time 3391223896 ps
CPU time 3.3 seconds
Started Jun 22 04:28:56 PM PDT 24
Finished Jun 22 04:29:00 PM PDT 24
Peak memory 196588 kb
Host smart-f64b4af4-25b6-454f-9420-5e1e028fc7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721128840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.721128840
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.896563747
Short name T663
Test name
Test status
Simulation time 681003409 ps
CPU time 1.37 seconds
Started Jun 22 04:29:11 PM PDT 24
Finished Jun 22 04:29:14 PM PDT 24
Peak memory 199008 kb
Host smart-6c65ee50-49a3-4845-adcf-bce26f343a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896563747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.896563747
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.3482204805
Short name T196
Test name
Test status
Simulation time 384590407584 ps
CPU time 275.91 seconds
Started Jun 22 04:29:12 PM PDT 24
Finished Jun 22 04:33:50 PM PDT 24
Peak memory 200560 kb
Host smart-37d453b7-c283-48c8-97f8-9ea1565c13a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482204805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.3482204805
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.1527338583
Short name T1014
Test name
Test status
Simulation time 428774091 ps
CPU time 2.06 seconds
Started Jun 22 04:28:56 PM PDT 24
Finished Jun 22 04:28:59 PM PDT 24
Peak memory 200168 kb
Host smart-064bd1c1-f7b1-41d9-b5e6-079c0ef87816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527338583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.1527338583
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.3503417795
Short name T956
Test name
Test status
Simulation time 99320884807 ps
CPU time 111.4 seconds
Started Jun 22 04:29:12 PM PDT 24
Finished Jun 22 04:31:05 PM PDT 24
Peak memory 200492 kb
Host smart-d31a8727-b587-4288-bd6a-bafa8952e19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503417795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.3503417795
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.3465919064
Short name T869
Test name
Test status
Simulation time 72790407 ps
CPU time 0.55 seconds
Started Jun 22 04:29:18 PM PDT 24
Finished Jun 22 04:29:19 PM PDT 24
Peak memory 195864 kb
Host smart-f45891fc-97e0-4b5d-babe-080ae6d79988
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465919064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.3465919064
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.615536757
Short name T451
Test name
Test status
Simulation time 54082844662 ps
CPU time 20.89 seconds
Started Jun 22 04:28:58 PM PDT 24
Finished Jun 22 04:29:20 PM PDT 24
Peak memory 200544 kb
Host smart-52000ca5-0e37-42cf-8eca-09f67b7bd7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615536757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.615536757
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.399498864
Short name T734
Test name
Test status
Simulation time 54931823589 ps
CPU time 35.98 seconds
Started Jun 22 04:29:24 PM PDT 24
Finished Jun 22 04:30:01 PM PDT 24
Peak memory 200484 kb
Host smart-3212fca6-6da8-4d96-a814-c011a27bee78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399498864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.399498864
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_intr.791822976
Short name T982
Test name
Test status
Simulation time 52039193248 ps
CPU time 22.37 seconds
Started Jun 22 04:29:33 PM PDT 24
Finished Jun 22 04:29:57 PM PDT 24
Peak memory 200488 kb
Host smart-421133ab-14e9-44fe-adb5-5667844eb00f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791822976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.791822976
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_loopback.2105484480
Short name T932
Test name
Test status
Simulation time 8480105050 ps
CPU time 15.01 seconds
Started Jun 22 04:29:16 PM PDT 24
Finished Jun 22 04:29:32 PM PDT 24
Peak memory 200336 kb
Host smart-46304b5d-7406-4c1c-a3f0-06532e720637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105484480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.2105484480
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_perf.3323690089
Short name T958
Test name
Test status
Simulation time 12737428870 ps
CPU time 422.12 seconds
Started Jun 22 04:29:10 PM PDT 24
Finished Jun 22 04:36:13 PM PDT 24
Peak memory 200540 kb
Host smart-e4eb9e8c-a0fb-4cfd-9e1c-8d4f31a8456e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3323690089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.3323690089
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.4267370956
Short name T1070
Test name
Test status
Simulation time 2649520167 ps
CPU time 19.08 seconds
Started Jun 22 04:29:11 PM PDT 24
Finished Jun 22 04:29:31 PM PDT 24
Peak memory 198788 kb
Host smart-76611114-d54c-40b9-ad06-dc27be4c257a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4267370956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.4267370956
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.3711299206
Short name T603
Test name
Test status
Simulation time 201041961164 ps
CPU time 122.05 seconds
Started Jun 22 04:29:10 PM PDT 24
Finished Jun 22 04:31:13 PM PDT 24
Peak memory 200456 kb
Host smart-35f8270e-2a22-43a8-a2e0-d43adc83029a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711299206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.3711299206
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.883152744
Short name T11
Test name
Test status
Simulation time 40079732901 ps
CPU time 13.78 seconds
Started Jun 22 04:29:10 PM PDT 24
Finished Jun 22 04:29:25 PM PDT 24
Peak memory 196296 kb
Host smart-77380e59-3e53-45ae-83d2-878441e2725d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883152744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.883152744
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.2898082943
Short name T374
Test name
Test status
Simulation time 106576992 ps
CPU time 0.87 seconds
Started Jun 22 04:29:11 PM PDT 24
Finished Jun 22 04:29:14 PM PDT 24
Peak memory 197712 kb
Host smart-30fb634b-1a2f-449f-a3ab-e705bef26332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898082943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.2898082943
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.3018913766
Short name T350
Test name
Test status
Simulation time 48501429219 ps
CPU time 754.28 seconds
Started Jun 22 04:29:06 PM PDT 24
Finished Jun 22 04:41:42 PM PDT 24
Peak memory 213112 kb
Host smart-ec70f7f2-e1f3-4a7a-9534-c8f2df46d35f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018913766 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.3018913766
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.221367258
Short name T867
Test name
Test status
Simulation time 1161889107 ps
CPU time 1.77 seconds
Started Jun 22 04:29:06 PM PDT 24
Finished Jun 22 04:29:09 PM PDT 24
Peak memory 198772 kb
Host smart-0f1ca816-03c4-439a-9a8f-71b1f0f0e307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221367258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.221367258
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.2057036811
Short name T698
Test name
Test status
Simulation time 33247943207 ps
CPU time 13.81 seconds
Started Jun 22 04:29:17 PM PDT 24
Finished Jun 22 04:29:31 PM PDT 24
Peak memory 200332 kb
Host smart-c87ac71e-66c1-4f1f-8015-8e153b0c87a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057036811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.2057036811
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.524090072
Short name T806
Test name
Test status
Simulation time 42856752 ps
CPU time 0.54 seconds
Started Jun 22 04:29:10 PM PDT 24
Finished Jun 22 04:29:12 PM PDT 24
Peak memory 195880 kb
Host smart-9b623ce1-c597-42f8-8c31-936e93d9a668
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524090072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.524090072
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.1878425305
Short name T737
Test name
Test status
Simulation time 163765513429 ps
CPU time 15.12 seconds
Started Jun 22 04:29:11 PM PDT 24
Finished Jun 22 04:29:28 PM PDT 24
Peak memory 200532 kb
Host smart-770c32ca-7d28-4f0b-8d0b-b16b5052e2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878425305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.1878425305
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.1235317951
Short name T1003
Test name
Test status
Simulation time 189805567370 ps
CPU time 30.17 seconds
Started Jun 22 04:29:13 PM PDT 24
Finished Jun 22 04:29:44 PM PDT 24
Peak memory 200404 kb
Host smart-60021003-3ed1-476a-bc1d-a0ca4fce2fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235317951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.1235317951
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.210339273
Short name T697
Test name
Test status
Simulation time 28015643398 ps
CPU time 22.18 seconds
Started Jun 22 04:29:13 PM PDT 24
Finished Jun 22 04:29:37 PM PDT 24
Peak memory 198696 kb
Host smart-2fc65f9b-8bc9-4ee4-aca6-7adedc9853ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210339273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.210339273
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.2831306283
Short name T795
Test name
Test status
Simulation time 48987571574 ps
CPU time 83.28 seconds
Started Jun 22 04:29:10 PM PDT 24
Finished Jun 22 04:30:35 PM PDT 24
Peak memory 200400 kb
Host smart-f59f2637-a1cf-4a33-950f-3216c96143e9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831306283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.2831306283
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.2964655092
Short name T571
Test name
Test status
Simulation time 40045188841 ps
CPU time 153.5 seconds
Started Jun 22 04:29:09 PM PDT 24
Finished Jun 22 04:31:43 PM PDT 24
Peak memory 200468 kb
Host smart-3d1be304-49f8-49d0-b4ee-b7819c57fd93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2964655092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.2964655092
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.3361700894
Short name T809
Test name
Test status
Simulation time 9075771779 ps
CPU time 21.18 seconds
Started Jun 22 04:29:14 PM PDT 24
Finished Jun 22 04:29:36 PM PDT 24
Peak memory 200268 kb
Host smart-1985cdd1-1b7e-4dac-bb2f-49f78b60d196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361700894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.3361700894
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_perf.344358500
Short name T577
Test name
Test status
Simulation time 27043141258 ps
CPU time 1498.42 seconds
Started Jun 22 04:29:06 PM PDT 24
Finished Jun 22 04:54:05 PM PDT 24
Peak memory 200452 kb
Host smart-6e0609d3-6d54-4aae-a837-6438063e6fbd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=344358500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.344358500
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.1606608704
Short name T860
Test name
Test status
Simulation time 3109864109 ps
CPU time 2.48 seconds
Started Jun 22 04:29:18 PM PDT 24
Finished Jun 22 04:29:21 PM PDT 24
Peak memory 198732 kb
Host smart-42613db4-a490-4211-b61f-7808ce33f8c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1606608704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.1606608704
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.2766005302
Short name T808
Test name
Test status
Simulation time 33480037324 ps
CPU time 15.34 seconds
Started Jun 22 04:29:12 PM PDT 24
Finished Jun 22 04:29:29 PM PDT 24
Peak memory 200492 kb
Host smart-e941cec2-9821-4ed3-9e16-219e1ed27397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766005302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.2766005302
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.3840441514
Short name T630
Test name
Test status
Simulation time 4831962863 ps
CPU time 2.4 seconds
Started Jun 22 04:29:10 PM PDT 24
Finished Jun 22 04:29:13 PM PDT 24
Peak memory 196584 kb
Host smart-ea52991c-ad4a-4eb1-a359-575ab7878398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840441514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.3840441514
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.3095102775
Short name T390
Test name
Test status
Simulation time 6025474000 ps
CPU time 14.3 seconds
Started Jun 22 04:29:06 PM PDT 24
Finished Jun 22 04:29:21 PM PDT 24
Peak memory 200360 kb
Host smart-fd8042e4-46df-48ce-b8cf-a435f01ec627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095102775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.3095102775
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.663374202
Short name T592
Test name
Test status
Simulation time 2262067127 ps
CPU time 2.08 seconds
Started Jun 22 04:29:06 PM PDT 24
Finished Jun 22 04:29:09 PM PDT 24
Peak memory 200524 kb
Host smart-90da6564-f05e-476d-a4ca-bb7483677103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663374202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.663374202
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.514596173
Short name T877
Test name
Test status
Simulation time 36867977497 ps
CPU time 26.46 seconds
Started Jun 22 04:29:17 PM PDT 24
Finished Jun 22 04:29:44 PM PDT 24
Peak memory 200436 kb
Host smart-522333c7-026d-4afc-837e-7c5db9688ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514596173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.514596173
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.2456584151
Short name T844
Test name
Test status
Simulation time 19767114 ps
CPU time 0.6 seconds
Started Jun 22 04:29:15 PM PDT 24
Finished Jun 22 04:29:17 PM PDT 24
Peak memory 195884 kb
Host smart-cefcc27e-3aff-47e4-9203-83bf7cbfcf10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456584151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.2456584151
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.749716629
Short name T1083
Test name
Test status
Simulation time 53261807019 ps
CPU time 20.24 seconds
Started Jun 22 04:29:27 PM PDT 24
Finished Jun 22 04:29:48 PM PDT 24
Peak memory 200292 kb
Host smart-1a8f6113-5262-4b5b-9c41-f5a6b66816f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749716629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.749716629
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.1840771533
Short name T185
Test name
Test status
Simulation time 11499309361 ps
CPU time 13 seconds
Started Jun 22 04:29:06 PM PDT 24
Finished Jun 22 04:29:20 PM PDT 24
Peak memory 200020 kb
Host smart-a571581a-df1c-41b7-9ef0-7295bc667f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840771533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.1840771533
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.279851462
Short name T229
Test name
Test status
Simulation time 42887927150 ps
CPU time 15.31 seconds
Started Jun 22 04:29:10 PM PDT 24
Finished Jun 22 04:29:25 PM PDT 24
Peak memory 200160 kb
Host smart-4709b06f-fefa-42ff-ac29-ade97fc41765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279851462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.279851462
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.298738994
Short name T770
Test name
Test status
Simulation time 52251693530 ps
CPU time 11 seconds
Started Jun 22 04:29:12 PM PDT 24
Finished Jun 22 04:29:24 PM PDT 24
Peak memory 200544 kb
Host smart-adb5f8fd-5f87-44d2-a5de-33d1e15b2ca9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298738994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.298738994
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.455212292
Short name T312
Test name
Test status
Simulation time 72602874028 ps
CPU time 266.23 seconds
Started Jun 22 04:30:26 PM PDT 24
Finished Jun 22 04:34:53 PM PDT 24
Peak memory 200448 kb
Host smart-fe378bb5-3513-44d1-bd0a-a81eb534fb59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=455212292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.455212292
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.1764350134
Short name T715
Test name
Test status
Simulation time 9858001978 ps
CPU time 10.32 seconds
Started Jun 22 04:29:29 PM PDT 24
Finished Jun 22 04:29:41 PM PDT 24
Peak memory 200360 kb
Host smart-972dabe2-bc01-4be0-ae41-3ea06faa8bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764350134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.1764350134
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_perf.1313155669
Short name T784
Test name
Test status
Simulation time 31552341636 ps
CPU time 445.63 seconds
Started Jun 22 04:29:15 PM PDT 24
Finished Jun 22 04:36:42 PM PDT 24
Peak memory 200532 kb
Host smart-f21dfadc-df99-45f6-be14-5556bde022d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1313155669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.1313155669
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.3035674144
Short name T980
Test name
Test status
Simulation time 2982601618 ps
CPU time 5.41 seconds
Started Jun 22 04:29:13 PM PDT 24
Finished Jun 22 04:29:20 PM PDT 24
Peak memory 199552 kb
Host smart-222e7c43-2237-4570-9141-d02e127cfed2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3035674144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.3035674144
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.2702336164
Short name T485
Test name
Test status
Simulation time 30171155072 ps
CPU time 20.63 seconds
Started Jun 22 04:29:38 PM PDT 24
Finished Jun 22 04:29:59 PM PDT 24
Peak memory 200336 kb
Host smart-4494be97-2430-43c7-90d8-c35df9021666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702336164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.2702336164
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.3692647161
Short name T137
Test name
Test status
Simulation time 44382211682 ps
CPU time 68.86 seconds
Started Jun 22 04:29:06 PM PDT 24
Finished Jun 22 04:30:15 PM PDT 24
Peak memory 196656 kb
Host smart-03a1d4ea-e133-4046-b141-a874a1c81575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692647161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.3692647161
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.735757116
Short name T605
Test name
Test status
Simulation time 601734402 ps
CPU time 2.11 seconds
Started Jun 22 04:29:10 PM PDT 24
Finished Jun 22 04:29:13 PM PDT 24
Peak memory 198812 kb
Host smart-3cd7b17c-d08b-4a0d-96fe-86405450b389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735757116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.735757116
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.251565652
Short name T914
Test name
Test status
Simulation time 803510700 ps
CPU time 1.9 seconds
Started Jun 22 04:29:14 PM PDT 24
Finished Jun 22 04:29:18 PM PDT 24
Peak memory 199072 kb
Host smart-4e5900c8-8275-42d2-b5d0-2d7ebaa451bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251565652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.251565652
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.1080503603
Short name T313
Test name
Test status
Simulation time 2707463889 ps
CPU time 4.72 seconds
Started Jun 22 04:29:15 PM PDT 24
Finished Jun 22 04:29:21 PM PDT 24
Peak memory 199004 kb
Host smart-7ab96732-d627-48a6-a4c7-2132b6d382ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080503603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.1080503603
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.1607953577
Short name T815
Test name
Test status
Simulation time 30662845 ps
CPU time 0.58 seconds
Started Jun 22 04:29:14 PM PDT 24
Finished Jun 22 04:29:16 PM PDT 24
Peak memory 195832 kb
Host smart-004bb340-352d-479d-b17b-03cc6ba99e69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607953577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.1607953577
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.2599650665
Short name T1065
Test name
Test status
Simulation time 38582927390 ps
CPU time 15.94 seconds
Started Jun 22 04:29:24 PM PDT 24
Finished Jun 22 04:29:41 PM PDT 24
Peak memory 200552 kb
Host smart-9e93b207-c7c6-413c-ba10-8f7f59bb2dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599650665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.2599650665
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.3163043828
Short name T741
Test name
Test status
Simulation time 60442697112 ps
CPU time 47.98 seconds
Started Jun 22 04:29:25 PM PDT 24
Finished Jun 22 04:30:14 PM PDT 24
Peak memory 200452 kb
Host smart-618b260a-b980-442c-9bb2-6c467138dc1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163043828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.3163043828
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.505438005
Short name T207
Test name
Test status
Simulation time 286604461464 ps
CPU time 56.76 seconds
Started Jun 22 04:29:25 PM PDT 24
Finished Jun 22 04:30:22 PM PDT 24
Peak memory 200544 kb
Host smart-bee53e6b-34f5-4b1e-862f-20b1ff64ade4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505438005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.505438005
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.3597486972
Short name T472
Test name
Test status
Simulation time 72023712295 ps
CPU time 29.45 seconds
Started Jun 22 04:29:16 PM PDT 24
Finished Jun 22 04:29:46 PM PDT 24
Peak memory 200176 kb
Host smart-51acb961-f044-42c6-b42a-4bb6c93264ce
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597486972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.3597486972
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.2243037907
Short name T802
Test name
Test status
Simulation time 229931314248 ps
CPU time 634.43 seconds
Started Jun 22 04:29:14 PM PDT 24
Finished Jun 22 04:39:50 PM PDT 24
Peak memory 200072 kb
Host smart-e3f03d0d-5714-4147-b27a-08a59a013c1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2243037907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.2243037907
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.3991463878
Short name T882
Test name
Test status
Simulation time 5240864552 ps
CPU time 4.01 seconds
Started Jun 22 04:29:17 PM PDT 24
Finished Jun 22 04:29:22 PM PDT 24
Peak memory 198420 kb
Host smart-3b7a04b6-cc56-4b64-addf-da07178fd285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991463878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.3991463878
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_perf.3659868254
Short name T1043
Test name
Test status
Simulation time 20302199884 ps
CPU time 1141.31 seconds
Started Jun 22 04:29:29 PM PDT 24
Finished Jun 22 04:48:31 PM PDT 24
Peak memory 200532 kb
Host smart-c7a2483c-28d0-433c-88b5-ea3eb540d1b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3659868254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.3659868254
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.1408701382
Short name T1091
Test name
Test status
Simulation time 5450049002 ps
CPU time 9.39 seconds
Started Jun 22 04:29:13 PM PDT 24
Finished Jun 22 04:29:24 PM PDT 24
Peak memory 198732 kb
Host smart-9ea7bb9e-dadf-48a4-bb7e-71efe4fd5305
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1408701382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.1408701382
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.2898101122
Short name T406
Test name
Test status
Simulation time 107819817812 ps
CPU time 35.06 seconds
Started Jun 22 04:29:37 PM PDT 24
Finished Jun 22 04:30:13 PM PDT 24
Peak memory 200540 kb
Host smart-c387c216-43d7-4213-950f-67e6838f4bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898101122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.2898101122
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.3710289425
Short name T311
Test name
Test status
Simulation time 3484523363 ps
CPU time 3.29 seconds
Started Jun 22 04:29:14 PM PDT 24
Finished Jun 22 04:29:19 PM PDT 24
Peak memory 197284 kb
Host smart-6139e130-a329-4ba5-a4da-be04c4138893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710289425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.3710289425
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.2609828097
Short name T334
Test name
Test status
Simulation time 5557952665 ps
CPU time 6.65 seconds
Started Jun 22 04:29:14 PM PDT 24
Finished Jun 22 04:29:22 PM PDT 24
Peak memory 199868 kb
Host smart-f9b8434f-2ceb-4cbb-afde-0eb2faf66995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609828097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.2609828097
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.3194969129
Short name T546
Test name
Test status
Simulation time 6384520660 ps
CPU time 19.19 seconds
Started Jun 22 04:29:24 PM PDT 24
Finished Jun 22 04:29:44 PM PDT 24
Peak memory 200456 kb
Host smart-c3f08984-3b2d-4571-90da-100ec02680f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194969129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.3194969129
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.2972158667
Short name T597
Test name
Test status
Simulation time 40560780913 ps
CPU time 68.29 seconds
Started Jun 22 04:29:21 PM PDT 24
Finished Jun 22 04:30:30 PM PDT 24
Peak memory 200512 kb
Host smart-0c5e7cf9-bb50-49a0-a7a9-b1161f8eeb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972158667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.2972158667
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.2726383195
Short name T966
Test name
Test status
Simulation time 19458176 ps
CPU time 0.53 seconds
Started Jun 22 04:29:15 PM PDT 24
Finished Jun 22 04:29:17 PM PDT 24
Peak memory 195884 kb
Host smart-3f4dd612-ab25-4b35-b88f-eee9d310a819
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726383195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.2726383195
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.2861642124
Short name T148
Test name
Test status
Simulation time 104415843468 ps
CPU time 45.95 seconds
Started Jun 22 04:29:38 PM PDT 24
Finished Jun 22 04:30:25 PM PDT 24
Peak memory 200508 kb
Host smart-fda4878f-4e29-48be-9764-a86ceb28283a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861642124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.2861642124
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.2272981672
Short name T167
Test name
Test status
Simulation time 92656769811 ps
CPU time 77.24 seconds
Started Jun 22 04:29:16 PM PDT 24
Finished Jun 22 04:30:34 PM PDT 24
Peak memory 200424 kb
Host smart-66d094af-ab10-4b3b-a010-3025c390e83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272981672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.2272981672
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.2589983951
Short name T745
Test name
Test status
Simulation time 43995838419 ps
CPU time 17.29 seconds
Started Jun 22 04:29:16 PM PDT 24
Finished Jun 22 04:29:35 PM PDT 24
Peak memory 199940 kb
Host smart-08b0f530-8f06-47bd-9b11-6a7dd7d40a28
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589983951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.2589983951
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.914766887
Short name T678
Test name
Test status
Simulation time 64046173179 ps
CPU time 363.96 seconds
Started Jun 22 04:29:13 PM PDT 24
Finished Jun 22 04:35:19 PM PDT 24
Peak memory 200528 kb
Host smart-2dbed899-7d8d-42de-9ba8-af35830e1d25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=914766887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.914766887
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.1571603647
Short name T446
Test name
Test status
Simulation time 1464088168 ps
CPU time 1.51 seconds
Started Jun 22 04:29:12 PM PDT 24
Finished Jun 22 04:29:15 PM PDT 24
Peak memory 197964 kb
Host smart-ebe29f25-14a5-4cb2-a947-0827523b9800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571603647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.1571603647
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_perf.3097972127
Short name T292
Test name
Test status
Simulation time 15306206805 ps
CPU time 367.83 seconds
Started Jun 22 04:29:14 PM PDT 24
Finished Jun 22 04:35:23 PM PDT 24
Peak memory 200524 kb
Host smart-df58eb09-a45c-4537-968a-646eba1c675a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3097972127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.3097972127
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.2049751368
Short name T14
Test name
Test status
Simulation time 6453176004 ps
CPU time 13.8 seconds
Started Jun 22 04:29:34 PM PDT 24
Finished Jun 22 04:29:49 PM PDT 24
Peak memory 198720 kb
Host smart-47bb4560-e9ed-42b8-b1da-2b5f82005507
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2049751368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.2049751368
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.4281821975
Short name T705
Test name
Test status
Simulation time 15072525448 ps
CPU time 19.2 seconds
Started Jun 22 04:29:39 PM PDT 24
Finished Jun 22 04:29:59 PM PDT 24
Peak memory 200480 kb
Host smart-d1e57723-aebc-4931-b23d-b50b107dd05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281821975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.4281821975
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.1469923403
Short name T1041
Test name
Test status
Simulation time 5546144741 ps
CPU time 8.67 seconds
Started Jun 22 04:29:34 PM PDT 24
Finished Jun 22 04:29:44 PM PDT 24
Peak memory 196564 kb
Host smart-da89245f-a03c-4761-adad-5a7128ecdb73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469923403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.1469923403
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.2535027247
Short name T64
Test name
Test status
Simulation time 462001753 ps
CPU time 1.93 seconds
Started Jun 22 04:29:30 PM PDT 24
Finished Jun 22 04:29:33 PM PDT 24
Peak memory 199396 kb
Host smart-acdb522f-3e5b-41be-923b-3f893ddbbeae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535027247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.2535027247
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.2759865919
Short name T1033
Test name
Test status
Simulation time 162218198988 ps
CPU time 130.06 seconds
Started Jun 22 04:29:15 PM PDT 24
Finished Jun 22 04:31:26 PM PDT 24
Peak memory 200532 kb
Host smart-04e0093b-21ce-487f-97cf-be854a24a14f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759865919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.2759865919
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.2831984396
Short name T489
Test name
Test status
Simulation time 2968866959 ps
CPU time 1.5 seconds
Started Jun 22 04:29:25 PM PDT 24
Finished Jun 22 04:29:27 PM PDT 24
Peak memory 199528 kb
Host smart-ff8ccb6e-1112-4171-bf40-a1f1bb4d3862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831984396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.2831984396
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.202260474
Short name T359
Test name
Test status
Simulation time 66017640353 ps
CPU time 22.86 seconds
Started Jun 22 04:29:24 PM PDT 24
Finished Jun 22 04:29:48 PM PDT 24
Peak memory 200480 kb
Host smart-dd2831ba-f076-4997-8216-e74f3a8291d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202260474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.202260474
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.2800816624
Short name T443
Test name
Test status
Simulation time 38177874 ps
CPU time 0.54 seconds
Started Jun 22 04:29:33 PM PDT 24
Finished Jun 22 04:29:35 PM PDT 24
Peak memory 196196 kb
Host smart-d6096e2f-5e2b-462b-9568-802421ebacd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800816624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.2800816624
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.3719113308
Short name T598
Test name
Test status
Simulation time 74908416261 ps
CPU time 242.19 seconds
Started Jun 22 04:29:23 PM PDT 24
Finished Jun 22 04:33:26 PM PDT 24
Peak memory 200572 kb
Host smart-f22677b5-e898-4409-ae26-81d0cd1bba79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719113308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.3719113308
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.3004274226
Short name T640
Test name
Test status
Simulation time 131425551707 ps
CPU time 173.63 seconds
Started Jun 22 04:29:34 PM PDT 24
Finished Jun 22 04:32:29 PM PDT 24
Peak memory 200544 kb
Host smart-f48da974-8fb7-42d9-b025-0cbf8f67ddc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004274226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.3004274226
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.1049131253
Short name T711
Test name
Test status
Simulation time 37620465365 ps
CPU time 33.66 seconds
Started Jun 22 04:29:21 PM PDT 24
Finished Jun 22 04:29:56 PM PDT 24
Peak memory 200940 kb
Host smart-6eb0063b-313a-49dc-b2e4-0cc7cddb2d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049131253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.1049131253
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.343114457
Short name T804
Test name
Test status
Simulation time 34941952238 ps
CPU time 16.78 seconds
Started Jun 22 04:29:23 PM PDT 24
Finished Jun 22 04:29:40 PM PDT 24
Peak memory 200556 kb
Host smart-3bb56f5e-3c84-4ae1-ad31-9797b77044eb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343114457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.343114457
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.3640598844
Short name T413
Test name
Test status
Simulation time 73906864065 ps
CPU time 152.03 seconds
Started Jun 22 04:29:23 PM PDT 24
Finished Jun 22 04:31:56 PM PDT 24
Peak memory 200448 kb
Host smart-0cb9a9e7-f361-4117-b25e-9af47f88954c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3640598844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.3640598844
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.1669731238
Short name T863
Test name
Test status
Simulation time 7044589853 ps
CPU time 12.85 seconds
Started Jun 22 04:29:22 PM PDT 24
Finished Jun 22 04:29:36 PM PDT 24
Peak memory 200236 kb
Host smart-4411d320-a604-4af2-b848-a429611ad067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669731238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.1669731238
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_perf.4092373419
Short name T307
Test name
Test status
Simulation time 18978635948 ps
CPU time 218.34 seconds
Started Jun 22 04:29:34 PM PDT 24
Finished Jun 22 04:33:13 PM PDT 24
Peak memory 200440 kb
Host smart-4e506c3c-ca7d-4721-be68-085eb6820541
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4092373419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.4092373419
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.19282906
Short name T797
Test name
Test status
Simulation time 2820245968 ps
CPU time 10.71 seconds
Started Jun 22 04:29:33 PM PDT 24
Finished Jun 22 04:29:45 PM PDT 24
Peak memory 198540 kb
Host smart-7d7c34c1-38ae-466d-ab5f-61eb635d63b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=19282906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.19282906
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.358804758
Short name T947
Test name
Test status
Simulation time 225630259400 ps
CPU time 161.25 seconds
Started Jun 22 04:29:24 PM PDT 24
Finished Jun 22 04:32:06 PM PDT 24
Peak memory 200552 kb
Host smart-2d74b7ab-b674-43ba-b7be-13128a782800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358804758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.358804758
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.967054869
Short name T479
Test name
Test status
Simulation time 51310609865 ps
CPU time 67.48 seconds
Started Jun 22 04:29:21 PM PDT 24
Finished Jun 22 04:30:29 PM PDT 24
Peak memory 196276 kb
Host smart-e4f0ba1b-fa2d-4ef9-beb5-e81c4901e9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967054869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.967054869
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.3839507816
Short name T774
Test name
Test status
Simulation time 731854206 ps
CPU time 1.48 seconds
Started Jun 22 04:29:25 PM PDT 24
Finished Jun 22 04:29:27 PM PDT 24
Peak memory 200152 kb
Host smart-0b9efbe5-ab94-4c5c-8a87-5f010547dcdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839507816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.3839507816
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.721750520
Short name T1064
Test name
Test status
Simulation time 244066423780 ps
CPU time 130.95 seconds
Started Jun 22 04:29:20 PM PDT 24
Finished Jun 22 04:31:32 PM PDT 24
Peak memory 200596 kb
Host smart-4d7aae38-340b-4f0b-ab98-2805c185b484
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721750520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.721750520
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.1865263858
Short name T683
Test name
Test status
Simulation time 1486205157 ps
CPU time 2.01 seconds
Started Jun 22 04:29:23 PM PDT 24
Finished Jun 22 04:29:26 PM PDT 24
Peak memory 199296 kb
Host smart-7ea221f1-5cb6-4231-8931-d0a642334f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865263858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.1865263858
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.630695704
Short name T388
Test name
Test status
Simulation time 24458656509 ps
CPU time 21.9 seconds
Started Jun 22 04:29:15 PM PDT 24
Finished Jun 22 04:29:38 PM PDT 24
Peak memory 200476 kb
Host smart-de8df0c7-2cb4-43e7-9acc-8fdb668ffcdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630695704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.630695704
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.3241445405
Short name T585
Test name
Test status
Simulation time 41064999 ps
CPU time 0.55 seconds
Started Jun 22 04:29:37 PM PDT 24
Finished Jun 22 04:29:39 PM PDT 24
Peak memory 195868 kb
Host smart-f23e774a-a471-48c6-b22c-dc6013e4eca6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241445405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.3241445405
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.2687449218
Short name T551
Test name
Test status
Simulation time 109528055083 ps
CPU time 196.69 seconds
Started Jun 22 04:29:42 PM PDT 24
Finished Jun 22 04:32:59 PM PDT 24
Peak memory 200528 kb
Host smart-74ba3e0c-f3ab-4920-be50-db7062b32158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687449218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.2687449218
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.3803144195
Short name T134
Test name
Test status
Simulation time 134708444099 ps
CPU time 114.93 seconds
Started Jun 22 04:29:30 PM PDT 24
Finished Jun 22 04:31:25 PM PDT 24
Peak memory 200628 kb
Host smart-d83103c2-d38f-4307-bb5e-92cb95ef1463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803144195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.3803144195
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.2293660294
Short name T1074
Test name
Test status
Simulation time 102152007403 ps
CPU time 12.48 seconds
Started Jun 22 04:29:44 PM PDT 24
Finished Jun 22 04:29:57 PM PDT 24
Peak memory 200544 kb
Host smart-95490645-a821-4efd-a392-c46eab3c06e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293660294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.2293660294
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.739110641
Short name T314
Test name
Test status
Simulation time 15201005378 ps
CPU time 32.47 seconds
Started Jun 22 04:29:21 PM PDT 24
Finished Jun 22 04:29:54 PM PDT 24
Peak memory 200424 kb
Host smart-14238bc8-de60-49a4-8cb4-ca0988b8caa9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739110641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.739110641
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.1981345596
Short name T560
Test name
Test status
Simulation time 225522264057 ps
CPU time 446.03 seconds
Started Jun 22 04:29:21 PM PDT 24
Finished Jun 22 04:36:48 PM PDT 24
Peak memory 200632 kb
Host smart-38acaa70-aa2d-46a7-818e-b8caa517ff7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1981345596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.1981345596
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.3909314099
Short name T602
Test name
Test status
Simulation time 2418943787 ps
CPU time 1.6 seconds
Started Jun 22 04:29:24 PM PDT 24
Finished Jun 22 04:29:26 PM PDT 24
Peak memory 199136 kb
Host smart-430b0655-a53d-4877-9b57-ff3824870694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909314099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.3909314099
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_perf.3368422016
Short name T651
Test name
Test status
Simulation time 12308602161 ps
CPU time 315.61 seconds
Started Jun 22 04:29:40 PM PDT 24
Finished Jun 22 04:34:56 PM PDT 24
Peak memory 200464 kb
Host smart-aaff910d-dbeb-4228-b9ff-ec381b4b490c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3368422016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.3368422016
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.237265410
Short name T691
Test name
Test status
Simulation time 5930826606 ps
CPU time 52.02 seconds
Started Jun 22 04:29:22 PM PDT 24
Finished Jun 22 04:30:15 PM PDT 24
Peak memory 199856 kb
Host smart-49a57c9f-2d3d-4eaa-a9ee-ffd7be19cb97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=237265410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.237265410
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.218149213
Short name T638
Test name
Test status
Simulation time 12095124505 ps
CPU time 10.01 seconds
Started Jun 22 04:29:33 PM PDT 24
Finished Jun 22 04:29:44 PM PDT 24
Peak memory 200612 kb
Host smart-31786f9e-51f9-40f9-b1b7-d90c1db47a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218149213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.218149213
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.2191554708
Short name T4
Test name
Test status
Simulation time 4253658234 ps
CPU time 1.43 seconds
Started Jun 22 04:29:30 PM PDT 24
Finished Jun 22 04:29:33 PM PDT 24
Peak memory 196584 kb
Host smart-625c6ac9-7ae4-46eb-bbf0-7d40dbcefcaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191554708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.2191554708
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.3324033978
Short name T832
Test name
Test status
Simulation time 538304718 ps
CPU time 2.81 seconds
Started Jun 22 04:29:37 PM PDT 24
Finished Jun 22 04:29:41 PM PDT 24
Peak memory 200224 kb
Host smart-d14a7c0c-83cc-4792-8ab0-72b0f8a2c05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324033978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.3324033978
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.337059
Short name T128
Test name
Test status
Simulation time 304513674732 ps
CPU time 207.69 seconds
Started Jun 22 04:29:42 PM PDT 24
Finished Jun 22 04:33:10 PM PDT 24
Peak memory 216232 kb
Host smart-01f7c1de-2b01-477f-bbef-32e66d86afe7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337059 -assert nopostproc
+UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.337059
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.2053806695
Short name T141
Test name
Test status
Simulation time 838529889 ps
CPU time 2.73 seconds
Started Jun 22 04:29:20 PM PDT 24
Finished Jun 22 04:29:24 PM PDT 24
Peak memory 200180 kb
Host smart-f8cef899-414c-4e3d-89d0-8b8fc8cac1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053806695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.2053806695
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.3297807274
Short name T1045
Test name
Test status
Simulation time 38051877470 ps
CPU time 17.43 seconds
Started Jun 22 04:29:23 PM PDT 24
Finished Jun 22 04:29:41 PM PDT 24
Peak memory 200460 kb
Host smart-010f9e4d-351b-4cb3-a4ab-023de05f339a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297807274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.3297807274
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.4245432291
Short name T601
Test name
Test status
Simulation time 24870308 ps
CPU time 0.56 seconds
Started Jun 22 04:29:41 PM PDT 24
Finished Jun 22 04:29:42 PM PDT 24
Peak memory 195824 kb
Host smart-379ad39f-9623-48ee-8e6e-cd246a42fde0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245432291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.4245432291
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.1497191706
Short name T1079
Test name
Test status
Simulation time 100431374450 ps
CPU time 82.73 seconds
Started Jun 22 04:29:33 PM PDT 24
Finished Jun 22 04:30:57 PM PDT 24
Peak memory 200760 kb
Host smart-8adf1c51-e288-45f0-93b3-5e1f10dc10eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497191706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.1497191706
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.1320922790
Short name T552
Test name
Test status
Simulation time 45046205408 ps
CPU time 36.37 seconds
Started Jun 22 04:29:23 PM PDT 24
Finished Jun 22 04:30:01 PM PDT 24
Peak memory 200080 kb
Host smart-c336a14d-4a18-4e48-9744-4a8266161a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320922790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.1320922790
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.3346786647
Short name T471
Test name
Test status
Simulation time 28682568558 ps
CPU time 12.26 seconds
Started Jun 22 04:29:37 PM PDT 24
Finished Jun 22 04:29:51 PM PDT 24
Peak memory 200200 kb
Host smart-73f5c8ff-87f6-4e49-9cca-bf47bf4974bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346786647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.3346786647
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.419280342
Short name T713
Test name
Test status
Simulation time 32620574857 ps
CPU time 13.52 seconds
Started Jun 22 04:29:24 PM PDT 24
Finished Jun 22 04:29:38 PM PDT 24
Peak memory 200452 kb
Host smart-c78234c4-a484-4a7a-9d15-f94c1a8582a2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419280342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.419280342
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.3708330900
Short name T1072
Test name
Test status
Simulation time 71819407321 ps
CPU time 313.98 seconds
Started Jun 22 04:29:46 PM PDT 24
Finished Jun 22 04:35:01 PM PDT 24
Peak memory 200476 kb
Host smart-40541f64-b2fe-4d20-a851-ce0ac1c8f0bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3708330900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.3708330900
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.1238354875
Short name T527
Test name
Test status
Simulation time 5312725209 ps
CPU time 9.19 seconds
Started Jun 22 04:29:44 PM PDT 24
Finished Jun 22 04:29:54 PM PDT 24
Peak memory 199592 kb
Host smart-c90e0db9-cc44-405a-bc88-3073de7025ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238354875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.1238354875
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_perf.1605952729
Short name T328
Test name
Test status
Simulation time 18836228659 ps
CPU time 281.98 seconds
Started Jun 22 04:29:36 PM PDT 24
Finished Jun 22 04:34:20 PM PDT 24
Peak memory 200516 kb
Host smart-ded8eec8-3c5b-415d-bd25-ecae59da919b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1605952729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.1605952729
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.3348071566
Short name T629
Test name
Test status
Simulation time 4589643037 ps
CPU time 10.65 seconds
Started Jun 22 04:29:24 PM PDT 24
Finished Jun 22 04:29:35 PM PDT 24
Peak memory 198744 kb
Host smart-bdc4e9f6-f493-4922-b1f6-5a8639b457b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3348071566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.3348071566
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.314940617
Short name T739
Test name
Test status
Simulation time 102730059987 ps
CPU time 124.87 seconds
Started Jun 22 04:29:30 PM PDT 24
Finished Jun 22 04:31:35 PM PDT 24
Peak memory 200472 kb
Host smart-3de024a2-037d-43b0-b04b-907da99d15d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314940617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.314940617
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.3208724048
Short name T327
Test name
Test status
Simulation time 4219491131 ps
CPU time 1.83 seconds
Started Jun 22 04:29:23 PM PDT 24
Finished Jun 22 04:29:26 PM PDT 24
Peak memory 197336 kb
Host smart-71ce84d2-81c3-446a-a1cf-23505939052d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208724048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.3208724048
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.1898618999
Short name T562
Test name
Test status
Simulation time 698798245 ps
CPU time 1.5 seconds
Started Jun 22 04:29:40 PM PDT 24
Finished Jun 22 04:29:42 PM PDT 24
Peak memory 199412 kb
Host smart-0aab2aff-acf7-43c5-88bf-b2d3dde8351d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898618999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.1898618999
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.2154556491
Short name T615
Test name
Test status
Simulation time 145656629186 ps
CPU time 1124.49 seconds
Started Jun 22 04:29:41 PM PDT 24
Finished Jun 22 04:48:27 PM PDT 24
Peak memory 200544 kb
Host smart-f4f2df07-91fb-463f-b3bd-d04c176a7531
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154556491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.2154556491
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.2914508554
Short name T930
Test name
Test status
Simulation time 7768540398 ps
CPU time 13.68 seconds
Started Jun 22 04:29:35 PM PDT 24
Finished Jun 22 04:29:49 PM PDT 24
Peak memory 200304 kb
Host smart-9f5a4e93-c50f-4b3a-9a19-9a864a94bfbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914508554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.2914508554
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.1938211780
Short name T682
Test name
Test status
Simulation time 82401824304 ps
CPU time 32.92 seconds
Started Jun 22 04:29:24 PM PDT 24
Finished Jun 22 04:29:58 PM PDT 24
Peak memory 200560 kb
Host smart-e8f90faa-c8b3-4e19-aaa5-274357423496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938211780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.1938211780
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.1902450856
Short name T584
Test name
Test status
Simulation time 12206451 ps
CPU time 0.55 seconds
Started Jun 22 04:29:29 PM PDT 24
Finished Jun 22 04:29:30 PM PDT 24
Peak memory 195960 kb
Host smart-2c94d81e-ec1b-4663-a206-26b0eba474c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902450856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.1902450856
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.314090165
Short name T395
Test name
Test status
Simulation time 34816579811 ps
CPU time 6.82 seconds
Started Jun 22 04:29:43 PM PDT 24
Finished Jun 22 04:29:50 PM PDT 24
Peak memory 200460 kb
Host smart-4c3af42f-95ac-4f21-9cd8-2843abf5d1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314090165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.314090165
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.2446057361
Short name T586
Test name
Test status
Simulation time 41390357828 ps
CPU time 18.68 seconds
Started Jun 22 04:29:42 PM PDT 24
Finished Jun 22 04:30:01 PM PDT 24
Peak memory 200832 kb
Host smart-cbfe5361-a26f-4b0d-a48e-2e9d37c6a69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446057361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.2446057361
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.289074000
Short name T1012
Test name
Test status
Simulation time 40390490243 ps
CPU time 32.84 seconds
Started Jun 22 04:29:40 PM PDT 24
Finished Jun 22 04:30:13 PM PDT 24
Peak memory 200564 kb
Host smart-8fc7c9c4-1e7c-4d85-9857-4435fec2ec38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289074000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.289074000
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.2439295525
Short name T759
Test name
Test status
Simulation time 47284144802 ps
CPU time 79.18 seconds
Started Jun 22 04:29:44 PM PDT 24
Finished Jun 22 04:31:04 PM PDT 24
Peak memory 200460 kb
Host smart-6281a69b-c61f-4612-ba19-fa27e66e9cf4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439295525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.2439295525
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.606718062
Short name T928
Test name
Test status
Simulation time 67751684900 ps
CPU time 341.99 seconds
Started Jun 22 04:29:43 PM PDT 24
Finished Jun 22 04:35:26 PM PDT 24
Peak memory 200496 kb
Host smart-60558165-a5b5-447e-a4e3-b42ace3eb0ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=606718062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.606718062
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.842306678
Short name T757
Test name
Test status
Simulation time 6855217563 ps
CPU time 15.89 seconds
Started Jun 22 04:29:44 PM PDT 24
Finished Jun 22 04:30:01 PM PDT 24
Peak memory 199352 kb
Host smart-55cef8dd-c826-42d0-a2a1-f765aacbe31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842306678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.842306678
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_perf.3075467649
Short name T407
Test name
Test status
Simulation time 13786097449 ps
CPU time 281.13 seconds
Started Jun 22 04:29:30 PM PDT 24
Finished Jun 22 04:34:12 PM PDT 24
Peak memory 200532 kb
Host smart-76a9856a-6d1d-4743-b8ce-c81c533da64f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3075467649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.3075467649
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.1393512069
Short name T368
Test name
Test status
Simulation time 5473527476 ps
CPU time 11.9 seconds
Started Jun 22 04:29:29 PM PDT 24
Finished Jun 22 04:29:41 PM PDT 24
Peak memory 199612 kb
Host smart-bb1c6000-cd0e-4831-a6ff-979623feb90f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1393512069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.1393512069
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.1346692998
Short name T324
Test name
Test status
Simulation time 65186702435 ps
CPU time 22.66 seconds
Started Jun 22 04:29:42 PM PDT 24
Finished Jun 22 04:30:05 PM PDT 24
Peak memory 199740 kb
Host smart-3e6d0ead-f2ca-41ff-899d-9c70be632f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346692998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.1346692998
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.3939922071
Short name T905
Test name
Test status
Simulation time 35212815888 ps
CPU time 15.61 seconds
Started Jun 22 04:29:44 PM PDT 24
Finished Jun 22 04:30:01 PM PDT 24
Peak memory 196600 kb
Host smart-f7a1c409-74ad-44e7-b9a3-1b1203cea943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939922071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.3939922071
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.2548325521
Short name T507
Test name
Test status
Simulation time 6268110430 ps
CPU time 7.38 seconds
Started Jun 22 04:29:30 PM PDT 24
Finished Jun 22 04:29:38 PM PDT 24
Peak memory 200600 kb
Host smart-74c2e518-8254-4a23-bed5-af2c5887d016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548325521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.2548325521
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.2508271497
Short name T549
Test name
Test status
Simulation time 763248946 ps
CPU time 2.48 seconds
Started Jun 22 04:29:41 PM PDT 24
Finished Jun 22 04:29:44 PM PDT 24
Peak memory 199036 kb
Host smart-303a224c-b045-4174-bf6d-b50b6d3db941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508271497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.2508271497
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.3814433570
Short name T512
Test name
Test status
Simulation time 5821234280 ps
CPU time 14.28 seconds
Started Jun 22 04:29:44 PM PDT 24
Finished Jun 22 04:30:00 PM PDT 24
Peak memory 200548 kb
Host smart-5b180dc5-b66a-40e9-83c2-69e5e1e95043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814433570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.3814433570
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.789805721
Short name T942
Test name
Test status
Simulation time 23860758 ps
CPU time 0.58 seconds
Started Jun 22 04:28:02 PM PDT 24
Finished Jun 22 04:28:04 PM PDT 24
Peak memory 195860 kb
Host smart-6b4ff92e-8a74-48f6-834d-42d387628ed0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789805721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.789805721
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.989339427
Short name T517
Test name
Test status
Simulation time 40312756485 ps
CPU time 19.33 seconds
Started Jun 22 04:28:02 PM PDT 24
Finished Jun 22 04:28:23 PM PDT 24
Peak memory 200592 kb
Host smart-ef46daab-21d9-4b3d-a663-5dcc7f128c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989339427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.989339427
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.3286913913
Short name T986
Test name
Test status
Simulation time 129286473155 ps
CPU time 97.46 seconds
Started Jun 22 04:27:59 PM PDT 24
Finished Jun 22 04:29:38 PM PDT 24
Peak memory 200460 kb
Host smart-2fa9f89d-2829-420c-8698-9695776eb575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286913913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.3286913913
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.171531494
Short name T588
Test name
Test status
Simulation time 39800769856 ps
CPU time 13.61 seconds
Started Jun 22 04:28:02 PM PDT 24
Finished Jun 22 04:28:17 PM PDT 24
Peak memory 200280 kb
Host smart-b1393bde-f35d-484d-9b63-6cec664121e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171531494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.171531494
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.2956818944
Short name T1075
Test name
Test status
Simulation time 105579073027 ps
CPU time 55.05 seconds
Started Jun 22 04:27:59 PM PDT 24
Finished Jun 22 04:28:56 PM PDT 24
Peak memory 200424 kb
Host smart-b2bd51de-0dbb-4d4c-85ff-533d14aec80e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956818944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.2956818944
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.2153534107
Short name T1019
Test name
Test status
Simulation time 77608848966 ps
CPU time 113.77 seconds
Started Jun 22 04:27:57 PM PDT 24
Finished Jun 22 04:29:53 PM PDT 24
Peak memory 200432 kb
Host smart-996905fc-2b78-46e6-91c2-a8b1de2d9ae2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2153534107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.2153534107
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.998343802
Short name T1086
Test name
Test status
Simulation time 6231447282 ps
CPU time 11.45 seconds
Started Jun 22 04:27:59 PM PDT 24
Finished Jun 22 04:28:13 PM PDT 24
Peak memory 199240 kb
Host smart-d96cb385-267e-426c-96f7-ad8c04660945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998343802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.998343802
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_perf.3723117837
Short name T59
Test name
Test status
Simulation time 24406932575 ps
CPU time 1249.06 seconds
Started Jun 22 04:27:54 PM PDT 24
Finished Jun 22 04:48:45 PM PDT 24
Peak memory 200512 kb
Host smart-090c6eef-d25d-4cb1-bcfe-6e7b50acc6e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3723117837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.3723117837
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.3482473471
Short name T524
Test name
Test status
Simulation time 3893754448 ps
CPU time 29.27 seconds
Started Jun 22 04:28:02 PM PDT 24
Finished Jun 22 04:28:33 PM PDT 24
Peak memory 198540 kb
Host smart-d63454a8-0333-4756-9787-b17c114d3c9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3482473471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.3482473471
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.3799710240
Short name T661
Test name
Test status
Simulation time 26320784655 ps
CPU time 42.86 seconds
Started Jun 22 04:27:54 PM PDT 24
Finished Jun 22 04:28:38 PM PDT 24
Peak memory 200520 kb
Host smart-2275d5b2-db0c-4092-bf3b-7521e72905e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799710240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.3799710240
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.1549988886
Short name T322
Test name
Test status
Simulation time 2164021615 ps
CPU time 3.97 seconds
Started Jun 22 04:28:00 PM PDT 24
Finished Jun 22 04:28:05 PM PDT 24
Peak memory 196236 kb
Host smart-54e9f8c3-65cf-4da5-82ad-1c59f11e0cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549988886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.1549988886
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.3897003380
Short name T33
Test name
Test status
Simulation time 70001331 ps
CPU time 0.83 seconds
Started Jun 22 04:27:56 PM PDT 24
Finished Jun 22 04:27:58 PM PDT 24
Peak memory 219368 kb
Host smart-d32f7bc6-5d61-49ec-abca-5a0f03e50ea0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897003380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.3897003380
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.4070700571
Short name T634
Test name
Test status
Simulation time 471158170 ps
CPU time 2.37 seconds
Started Jun 22 04:27:59 PM PDT 24
Finished Jun 22 04:28:03 PM PDT 24
Peak memory 199392 kb
Host smart-b3e6a299-4751-41a7-b62c-cb68361e0adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070700571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.4070700571
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.511417200
Short name T825
Test name
Test status
Simulation time 6641027512 ps
CPU time 40.73 seconds
Started Jun 22 04:27:59 PM PDT 24
Finished Jun 22 04:28:41 PM PDT 24
Peak memory 200352 kb
Host smart-777ef107-a721-4882-988a-36544ec184d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511417200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.511417200
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.3313589261
Short name T726
Test name
Test status
Simulation time 94566956067 ps
CPU time 148.76 seconds
Started Jun 22 04:27:59 PM PDT 24
Finished Jun 22 04:30:30 PM PDT 24
Peak memory 200544 kb
Host smart-c997c6c5-2347-4689-ae5e-7e6e799cfe7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313589261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.3313589261
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.308225242
Short name T428
Test name
Test status
Simulation time 22182107 ps
CPU time 0.55 seconds
Started Jun 22 04:29:32 PM PDT 24
Finished Jun 22 04:29:33 PM PDT 24
Peak memory 195332 kb
Host smart-bc975496-a95f-4bfa-9b7a-7442c5006a63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308225242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.308225242
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.903554814
Short name T748
Test name
Test status
Simulation time 208364715172 ps
CPU time 268.35 seconds
Started Jun 22 04:29:31 PM PDT 24
Finished Jun 22 04:34:00 PM PDT 24
Peak memory 200552 kb
Host smart-f1c2f9d6-fbd3-41e2-8e34-596ee3764a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903554814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.903554814
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.168916499
Short name T888
Test name
Test status
Simulation time 124973812940 ps
CPU time 50.39 seconds
Started Jun 22 04:29:30 PM PDT 24
Finished Jun 22 04:30:21 PM PDT 24
Peak memory 200492 kb
Host smart-b687ac3c-e824-45cd-8673-1da79cb0dea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168916499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.168916499
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.2732696241
Short name T582
Test name
Test status
Simulation time 55133673227 ps
CPU time 86.93 seconds
Started Jun 22 04:29:33 PM PDT 24
Finished Jun 22 04:31:01 PM PDT 24
Peak memory 200564 kb
Host smart-582ce312-81bd-424c-8485-9b2bb64f562d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732696241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.2732696241
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.3864042094
Short name T396
Test name
Test status
Simulation time 200241078354 ps
CPU time 96.02 seconds
Started Jun 22 04:29:45 PM PDT 24
Finished Jun 22 04:31:22 PM PDT 24
Peak memory 200444 kb
Host smart-1735b367-ec09-4c15-a49e-0347bdedd6f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3864042094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.3864042094
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.1993507393
Short name T1055
Test name
Test status
Simulation time 1282007432 ps
CPU time 2.39 seconds
Started Jun 22 04:29:35 PM PDT 24
Finished Jun 22 04:29:38 PM PDT 24
Peak memory 200832 kb
Host smart-587bb7a8-e3cf-45ae-ab8e-6286d8fbba6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993507393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.1993507393
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_perf.1876149592
Short name T423
Test name
Test status
Simulation time 14166757139 ps
CPU time 759.38 seconds
Started Jun 22 04:29:39 PM PDT 24
Finished Jun 22 04:42:20 PM PDT 24
Peak memory 200488 kb
Host smart-a3814ca3-29a3-4219-a8b5-8b3e8977a15e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1876149592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.1876149592
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.3558571437
Short name T944
Test name
Test status
Simulation time 6400995264 ps
CPU time 31.27 seconds
Started Jun 22 04:29:44 PM PDT 24
Finished Jun 22 04:30:16 PM PDT 24
Peak memory 199272 kb
Host smart-adcdddeb-b0bf-46ee-9ab8-075c5f23bc40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3558571437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.3558571437
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.1513260783
Short name T833
Test name
Test status
Simulation time 61532351517 ps
CPU time 85.65 seconds
Started Jun 22 04:29:32 PM PDT 24
Finished Jun 22 04:30:58 PM PDT 24
Peak memory 200876 kb
Host smart-86cd66f6-f32f-4f87-94c2-7b287b717e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513260783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.1513260783
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.3827897517
Short name T613
Test name
Test status
Simulation time 3667971634 ps
CPU time 4.15 seconds
Started Jun 22 04:29:41 PM PDT 24
Finished Jun 22 04:29:46 PM PDT 24
Peak memory 196804 kb
Host smart-9a2fd840-4782-4a4f-8c88-5081fd8ade99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827897517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.3827897517
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.2665755006
Short name T391
Test name
Test status
Simulation time 851434877 ps
CPU time 3.64 seconds
Started Jun 22 04:29:39 PM PDT 24
Finished Jun 22 04:29:43 PM PDT 24
Peak memory 200460 kb
Host smart-80a4c265-d643-4970-bab9-414a43640d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665755006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.2665755006
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.901786095
Short name T810
Test name
Test status
Simulation time 252822191409 ps
CPU time 335.16 seconds
Started Jun 22 04:29:33 PM PDT 24
Finished Jun 22 04:35:09 PM PDT 24
Peak memory 200464 kb
Host smart-7fa0d9c8-16fb-45f9-b638-4c5b635ffc66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901786095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.901786095
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.3054268746
Short name T892
Test name
Test status
Simulation time 1586872802 ps
CPU time 3.23 seconds
Started Jun 22 04:29:42 PM PDT 24
Finished Jun 22 04:29:46 PM PDT 24
Peak memory 199048 kb
Host smart-47047e8d-432f-4c29-a4d9-8dab0cdb8599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054268746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.3054268746
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.1342298257
Short name T875
Test name
Test status
Simulation time 86449298323 ps
CPU time 82.47 seconds
Started Jun 22 04:29:33 PM PDT 24
Finished Jun 22 04:30:57 PM PDT 24
Peak memory 200588 kb
Host smart-19f2b812-6c86-4bc4-b6bc-1d5ec1d56c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342298257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.1342298257
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.335582162
Short name T483
Test name
Test status
Simulation time 17633724 ps
CPU time 0.58 seconds
Started Jun 22 04:29:38 PM PDT 24
Finished Jun 22 04:29:40 PM PDT 24
Peak memory 195880 kb
Host smart-05797685-0b01-4d8d-aa67-f9e547fb0701
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335582162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.335582162
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.3299177802
Short name T50
Test name
Test status
Simulation time 65779620659 ps
CPU time 113.54 seconds
Started Jun 22 04:29:36 PM PDT 24
Finished Jun 22 04:31:31 PM PDT 24
Peak memory 200512 kb
Host smart-0b34809b-9c3a-480b-8637-b7fe8319dfd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299177802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.3299177802
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.2669709171
Short name T321
Test name
Test status
Simulation time 235147906631 ps
CPU time 92.6 seconds
Started Jun 22 04:29:43 PM PDT 24
Finished Jun 22 04:31:16 PM PDT 24
Peak memory 200540 kb
Host smart-93f23dcf-09cd-4575-974e-1f679c7e1b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669709171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.2669709171
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.236271348
Short name T239
Test name
Test status
Simulation time 97274819504 ps
CPU time 43.34 seconds
Started Jun 22 04:29:41 PM PDT 24
Finished Jun 22 04:30:25 PM PDT 24
Peak memory 200540 kb
Host smart-8a1318b2-82d0-413d-a6f3-4e25fd093dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236271348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.236271348
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.2956367430
Short name T964
Test name
Test status
Simulation time 190026438280 ps
CPU time 220.36 seconds
Started Jun 22 04:29:45 PM PDT 24
Finished Jun 22 04:33:26 PM PDT 24
Peak memory 200532 kb
Host smart-96269dc8-d5ea-4fe7-a105-2126ca7d1749
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956367430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.2956367430
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.3727247932
Short name T948
Test name
Test status
Simulation time 137773944967 ps
CPU time 1177.42 seconds
Started Jun 22 04:29:43 PM PDT 24
Finished Jun 22 04:49:21 PM PDT 24
Peak memory 200528 kb
Host smart-dc3fc641-8fda-4ec7-bb09-2bfb7b6dbded
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3727247932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.3727247932
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.3495345760
Short name T916
Test name
Test status
Simulation time 11615837514 ps
CPU time 5.86 seconds
Started Jun 22 04:29:36 PM PDT 24
Finished Jun 22 04:29:43 PM PDT 24
Peak memory 199744 kb
Host smart-9ddb495f-ba59-407e-8d93-c8c91995272b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495345760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.3495345760
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_perf.2699142857
Short name T1049
Test name
Test status
Simulation time 14931667707 ps
CPU time 223.91 seconds
Started Jun 22 04:29:37 PM PDT 24
Finished Jun 22 04:33:22 PM PDT 24
Peak memory 200944 kb
Host smart-4be951ef-bf23-49a7-a2e8-87f0c99c42e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2699142857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.2699142857
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.815888770
Short name T670
Test name
Test status
Simulation time 2548698619 ps
CPU time 3.01 seconds
Started Jun 22 04:29:41 PM PDT 24
Finished Jun 22 04:29:45 PM PDT 24
Peak memory 198752 kb
Host smart-2c18a5fb-270e-408c-b430-b89877fa0c46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=815888770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.815888770
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.3980659355
Short name T166
Test name
Test status
Simulation time 11697771941 ps
CPU time 17.14 seconds
Started Jun 22 04:29:37 PM PDT 24
Finished Jun 22 04:29:55 PM PDT 24
Peak memory 200480 kb
Host smart-96f10883-82be-4ee0-b686-f5e8a53ce2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980659355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.3980659355
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.3301377877
Short name T572
Test name
Test status
Simulation time 2649619944 ps
CPU time 1.19 seconds
Started Jun 22 04:29:40 PM PDT 24
Finished Jun 22 04:29:42 PM PDT 24
Peak memory 197056 kb
Host smart-fbd84157-0883-4338-8946-00a3b40da2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301377877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.3301377877
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.2289236010
Short name T343
Test name
Test status
Simulation time 883120358 ps
CPU time 0.87 seconds
Started Jun 22 04:29:31 PM PDT 24
Finished Jun 22 04:29:32 PM PDT 24
Peak memory 199184 kb
Host smart-3563e85b-4dcd-4511-b812-3b3d6502626c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289236010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.2289236010
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.2403036815
Short name T318
Test name
Test status
Simulation time 69297664037 ps
CPU time 1105.99 seconds
Started Jun 22 04:29:48 PM PDT 24
Finished Jun 22 04:48:14 PM PDT 24
Peak memory 215440 kb
Host smart-3d0e819e-5bca-4e30-b13a-69bbc63bdf31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403036815 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.2403036815
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.2913144083
Short name T995
Test name
Test status
Simulation time 3338201745 ps
CPU time 1.5 seconds
Started Jun 22 04:29:37 PM PDT 24
Finished Jun 22 04:29:40 PM PDT 24
Peak memory 199592 kb
Host smart-1d4ee6e5-0530-463e-8300-ad62c0645b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913144083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.2913144083
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.2490496179
Short name T448
Test name
Test status
Simulation time 11952805992 ps
CPU time 20.12 seconds
Started Jun 22 04:29:45 PM PDT 24
Finished Jun 22 04:30:06 PM PDT 24
Peak memory 200576 kb
Host smart-61904dc4-3728-4a87-b6ec-21935df89dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490496179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.2490496179
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.3355711976
Short name T568
Test name
Test status
Simulation time 19137904 ps
CPU time 0.61 seconds
Started Jun 22 04:29:37 PM PDT 24
Finished Jun 22 04:29:39 PM PDT 24
Peak memory 195832 kb
Host smart-d4ca7691-df2f-4658-b420-6440ab98a5ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355711976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.3355711976
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.3594054940
Short name T316
Test name
Test status
Simulation time 56512822336 ps
CPU time 84.31 seconds
Started Jun 22 04:29:38 PM PDT 24
Finished Jun 22 04:31:03 PM PDT 24
Peak memory 200100 kb
Host smart-e1cd0f1b-21e6-4a1b-a14e-1a28f08c9285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594054940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.3594054940
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.253756625
Short name T644
Test name
Test status
Simulation time 111377648970 ps
CPU time 94.27 seconds
Started Jun 22 04:29:41 PM PDT 24
Finished Jun 22 04:31:16 PM PDT 24
Peak memory 200424 kb
Host smart-77bade87-91e4-4963-99ca-942151f47394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253756625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.253756625
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.3480413223
Short name T690
Test name
Test status
Simulation time 10643381845 ps
CPU time 19.73 seconds
Started Jun 22 04:29:56 PM PDT 24
Finished Jun 22 04:30:17 PM PDT 24
Peak memory 200496 kb
Host smart-fd7f2fc0-17a0-4deb-9875-fc727ca62aad
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480413223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.3480413223
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.480561608
Short name T325
Test name
Test status
Simulation time 134507480082 ps
CPU time 1003.97 seconds
Started Jun 22 04:29:41 PM PDT 24
Finished Jun 22 04:46:26 PM PDT 24
Peak memory 200496 kb
Host smart-cf5c61c1-c819-4ddd-9f20-066dd69553a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=480561608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.480561608
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.3534792298
Short name T758
Test name
Test status
Simulation time 2014025705 ps
CPU time 2.6 seconds
Started Jun 22 04:29:44 PM PDT 24
Finished Jun 22 04:29:48 PM PDT 24
Peak memory 196820 kb
Host smart-783a6c52-fd6b-4e70-9ce1-1b29c19f0525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534792298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.3534792298
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_perf.3107710207
Short name T581
Test name
Test status
Simulation time 15892413742 ps
CPU time 815.63 seconds
Started Jun 22 04:29:49 PM PDT 24
Finished Jun 22 04:43:25 PM PDT 24
Peak memory 200560 kb
Host smart-5197e83a-828f-40f8-9289-8b4795500dd3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3107710207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.3107710207
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.10031679
Short name T379
Test name
Test status
Simulation time 7263628559 ps
CPU time 21.6 seconds
Started Jun 22 04:29:37 PM PDT 24
Finished Jun 22 04:29:59 PM PDT 24
Peak memory 199772 kb
Host smart-af9e2f81-aa62-483b-9877-675b64f85665
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=10031679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.10031679
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.1226773110
Short name T165
Test name
Test status
Simulation time 211281056641 ps
CPU time 103.18 seconds
Started Jun 22 04:29:47 PM PDT 24
Finished Jun 22 04:31:31 PM PDT 24
Peak memory 200540 kb
Host smart-e441e6ab-6095-4980-bb78-48e379b8d39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226773110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.1226773110
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.4199668612
Short name T393
Test name
Test status
Simulation time 2210442379 ps
CPU time 1.44 seconds
Started Jun 22 04:29:37 PM PDT 24
Finished Jun 22 04:29:40 PM PDT 24
Peak memory 196084 kb
Host smart-6371e13e-761e-4793-93e3-5003411efd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199668612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.4199668612
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.3716966403
Short name T1073
Test name
Test status
Simulation time 305729383 ps
CPU time 1.11 seconds
Started Jun 22 04:29:41 PM PDT 24
Finished Jun 22 04:29:43 PM PDT 24
Peak memory 199252 kb
Host smart-fd5b752a-5348-4196-a38b-8b157db0f6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716966403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.3716966403
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.1790568178
Short name T380
Test name
Test status
Simulation time 1607688661 ps
CPU time 1.65 seconds
Started Jun 22 04:29:39 PM PDT 24
Finished Jun 22 04:29:42 PM PDT 24
Peak memory 198604 kb
Host smart-404195df-48f5-4003-8c4e-3002ca673329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790568178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.1790568178
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.617049765
Short name T420
Test name
Test status
Simulation time 85891840378 ps
CPU time 31.3 seconds
Started Jun 22 04:29:39 PM PDT 24
Finished Jun 22 04:30:11 PM PDT 24
Peak memory 200452 kb
Host smart-2c064ece-5606-45e0-921a-5f92ea3b6ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617049765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.617049765
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.2108494871
Short name T440
Test name
Test status
Simulation time 12646286 ps
CPU time 0.56 seconds
Started Jun 22 04:29:40 PM PDT 24
Finished Jun 22 04:29:41 PM PDT 24
Peak memory 195884 kb
Host smart-fe8a8c9c-cbbc-4ada-bd6e-58fbc35229f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108494871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.2108494871
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.3071533128
Short name T607
Test name
Test status
Simulation time 27933409429 ps
CPU time 47.18 seconds
Started Jun 22 04:29:40 PM PDT 24
Finished Jun 22 04:30:28 PM PDT 24
Peak memory 200468 kb
Host smart-d5ff2608-295e-49f7-b63e-687b0410d111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071533128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.3071533128
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.2855578369
Short name T519
Test name
Test status
Simulation time 157877500959 ps
CPU time 220.17 seconds
Started Jun 22 04:29:56 PM PDT 24
Finished Jun 22 04:33:37 PM PDT 24
Peak memory 200496 kb
Host smart-919a69bb-96bd-4aee-88f4-ef427a5e4e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855578369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.2855578369
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.1653815832
Short name T839
Test name
Test status
Simulation time 46354057192 ps
CPU time 21.49 seconds
Started Jun 22 04:29:35 PM PDT 24
Finished Jun 22 04:29:57 PM PDT 24
Peak memory 200524 kb
Host smart-94182b80-b4a5-401c-b090-9b101a0670cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653815832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.1653815832
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.3186518876
Short name T492
Test name
Test status
Simulation time 6625516980 ps
CPU time 4.11 seconds
Started Jun 22 04:29:48 PM PDT 24
Finished Jun 22 04:29:53 PM PDT 24
Peak memory 200528 kb
Host smart-247afd76-a725-409c-8acb-6a1992b4fc4b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186518876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.3186518876
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.2776674627
Short name T850
Test name
Test status
Simulation time 103431448579 ps
CPU time 242.02 seconds
Started Jun 22 04:29:39 PM PDT 24
Finished Jun 22 04:33:42 PM PDT 24
Peak memory 200508 kb
Host smart-31725ffd-3e9a-43cb-8441-1fcfc8ba8cc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2776674627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.2776674627
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.1826088650
Short name T377
Test name
Test status
Simulation time 1048896963 ps
CPU time 1.19 seconds
Started Jun 22 04:29:43 PM PDT 24
Finished Jun 22 04:29:45 PM PDT 24
Peak memory 197444 kb
Host smart-76cd1ee4-b1df-40a7-a15c-03a8e775cc44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826088650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.1826088650
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_perf.583089409
Short name T826
Test name
Test status
Simulation time 12878408382 ps
CPU time 184.98 seconds
Started Jun 22 04:29:44 PM PDT 24
Finished Jun 22 04:32:50 PM PDT 24
Peak memory 200476 kb
Host smart-3935ce94-3125-4a2f-9bc2-9b7a12fc34da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=583089409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.583089409
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.500103417
Short name T610
Test name
Test status
Simulation time 4954429454 ps
CPU time 45.84 seconds
Started Jun 22 04:29:36 PM PDT 24
Finished Jun 22 04:30:23 PM PDT 24
Peak memory 199844 kb
Host smart-f1e32b1b-83a1-4cb7-bf08-d5c117b5f8f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=500103417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.500103417
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.336609622
Short name T186
Test name
Test status
Simulation time 22353944655 ps
CPU time 34.79 seconds
Started Jun 22 04:29:47 PM PDT 24
Finished Jun 22 04:30:22 PM PDT 24
Peak memory 200384 kb
Host smart-988de531-c5b0-4646-994b-a9d460440489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336609622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.336609622
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.421397545
Short name T462
Test name
Test status
Simulation time 6865520874 ps
CPU time 3.2 seconds
Started Jun 22 04:29:42 PM PDT 24
Finished Jun 22 04:29:46 PM PDT 24
Peak memory 196572 kb
Host smart-1eb328fd-17da-4f8e-a421-93c3fbbd54e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421397545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.421397545
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.1780451332
Short name T722
Test name
Test status
Simulation time 478381142 ps
CPU time 1.66 seconds
Started Jun 22 04:29:46 PM PDT 24
Finished Jun 22 04:29:49 PM PDT 24
Peak memory 198880 kb
Host smart-9ee68aef-5e53-4471-8182-e3cf93d94f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780451332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.1780451332
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.3994146508
Short name T883
Test name
Test status
Simulation time 154091973239 ps
CPU time 97.13 seconds
Started Jun 22 04:29:42 PM PDT 24
Finished Jun 22 04:31:20 PM PDT 24
Peak memory 200536 kb
Host smart-b70d96cf-413a-4b25-a585-6f591abaeece
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994146508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.3994146508
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.2942969560
Short name T331
Test name
Test status
Simulation time 128028184564 ps
CPU time 633.75 seconds
Started Jun 22 04:29:40 PM PDT 24
Finished Jun 22 04:40:14 PM PDT 24
Peak memory 216916 kb
Host smart-c0f06e67-bdf7-4551-ace8-a888d6324d42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942969560 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.2942969560
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.909420575
Short name T532
Test name
Test status
Simulation time 7543275187 ps
CPU time 8.46 seconds
Started Jun 22 04:29:54 PM PDT 24
Finished Jun 22 04:30:03 PM PDT 24
Peak memory 200524 kb
Host smart-0a03a694-ee45-4441-8750-a5d416d20427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909420575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.909420575
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.446999305
Short name T671
Test name
Test status
Simulation time 101183453479 ps
CPU time 115.02 seconds
Started Jun 22 04:29:48 PM PDT 24
Finished Jun 22 04:31:43 PM PDT 24
Peak memory 200924 kb
Host smart-38d5fa3e-18c6-4e89-b671-8781623ed19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446999305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.446999305
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.1941031724
Short name T378
Test name
Test status
Simulation time 39326710 ps
CPU time 0.55 seconds
Started Jun 22 04:29:54 PM PDT 24
Finished Jun 22 04:29:55 PM PDT 24
Peak memory 195276 kb
Host smart-8644de3f-5e62-4c86-872d-1aa66b8fa1ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941031724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.1941031724
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.3207171901
Short name T282
Test name
Test status
Simulation time 41140192928 ps
CPU time 19.19 seconds
Started Jun 22 04:29:37 PM PDT 24
Finished Jun 22 04:29:58 PM PDT 24
Peak memory 200548 kb
Host smart-8e88475b-e7c5-4ca4-84f7-0195001def8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207171901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.3207171901
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.3268615850
Short name T750
Test name
Test status
Simulation time 138803268853 ps
CPU time 65.9 seconds
Started Jun 22 04:29:51 PM PDT 24
Finished Jun 22 04:30:57 PM PDT 24
Peak memory 200468 kb
Host smart-e0a46f3b-0eb2-47cd-8a68-0353e3c5895c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268615850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.3268615850
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_intr.977608489
Short name T535
Test name
Test status
Simulation time 2749868735 ps
CPU time 4.14 seconds
Started Jun 22 04:29:48 PM PDT 24
Finished Jun 22 04:29:53 PM PDT 24
Peak memory 197200 kb
Host smart-396a787b-7e27-4bba-8792-934d39e46156
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977608489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.977608489
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.707976949
Short name T447
Test name
Test status
Simulation time 61264749707 ps
CPU time 410.18 seconds
Started Jun 22 04:29:56 PM PDT 24
Finished Jun 22 04:36:47 PM PDT 24
Peak memory 200524 kb
Host smart-dae9cb03-3ac3-4071-b02e-ef47cfaf080b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=707976949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.707976949
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.2656972777
Short name T569
Test name
Test status
Simulation time 4085777802 ps
CPU time 7.62 seconds
Started Jun 22 04:29:54 PM PDT 24
Finished Jun 22 04:30:03 PM PDT 24
Peak memory 199136 kb
Host smart-276f6b5e-c84c-4fce-8538-18340b636c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656972777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.2656972777
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_perf.1828603588
Short name T878
Test name
Test status
Simulation time 6417432241 ps
CPU time 160.76 seconds
Started Jun 22 04:29:54 PM PDT 24
Finished Jun 22 04:32:36 PM PDT 24
Peak memory 200500 kb
Host smart-e9c14502-8333-43b4-a03e-9a891f11c3e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1828603588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.1828603588
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.618579482
Short name T1015
Test name
Test status
Simulation time 6083186022 ps
CPU time 12.91 seconds
Started Jun 22 04:29:44 PM PDT 24
Finished Jun 22 04:29:58 PM PDT 24
Peak memory 199108 kb
Host smart-e71b062b-6cf8-4bdf-9007-19e7cb536b57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=618579482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.618579482
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.1578712582
Short name T146
Test name
Test status
Simulation time 13355135155 ps
CPU time 21.55 seconds
Started Jun 22 04:29:56 PM PDT 24
Finished Jun 22 04:30:18 PM PDT 24
Peak memory 200284 kb
Host smart-230a1e8c-87f0-4aef-b2f3-947ffd1ac088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578712582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.1578712582
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.3350415307
Short name T484
Test name
Test status
Simulation time 3316043073 ps
CPU time 1.57 seconds
Started Jun 22 04:29:52 PM PDT 24
Finished Jun 22 04:29:54 PM PDT 24
Peak memory 196784 kb
Host smart-c3435172-f224-46c8-b4a0-1a385607c9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350415307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.3350415307
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.1708022
Short name T47
Test name
Test status
Simulation time 676415112 ps
CPU time 1.84 seconds
Started Jun 22 04:29:48 PM PDT 24
Finished Jun 22 04:29:51 PM PDT 24
Peak memory 199176 kb
Host smart-62d8e7f3-86e6-41b4-b93e-5bd9fc679286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.1708022
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.2610305074
Short name T348
Test name
Test status
Simulation time 77164445654 ps
CPU time 973.2 seconds
Started Jun 22 04:29:45 PM PDT 24
Finished Jun 22 04:46:00 PM PDT 24
Peak memory 217072 kb
Host smart-cb10ef34-dd23-43b9-843e-bc10c29c85e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610305074 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.2610305074
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.2156277567
Short name T874
Test name
Test status
Simulation time 610919486 ps
CPU time 2.01 seconds
Started Jun 22 04:29:48 PM PDT 24
Finished Jun 22 04:29:50 PM PDT 24
Peak memory 198896 kb
Host smart-21974561-933e-4207-8156-c0584a4b8859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156277567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.2156277567
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.3982932493
Short name T1059
Test name
Test status
Simulation time 76219726408 ps
CPU time 27.49 seconds
Started Jun 22 04:29:44 PM PDT 24
Finished Jun 22 04:30:13 PM PDT 24
Peak memory 200456 kb
Host smart-7547c339-ad69-447a-9260-1a31f25ffac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982932493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.3982932493
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.2421793492
Short name T436
Test name
Test status
Simulation time 48946704 ps
CPU time 0.54 seconds
Started Jun 22 04:29:47 PM PDT 24
Finished Jun 22 04:29:49 PM PDT 24
Peak memory 195920 kb
Host smart-a359e924-e13c-4432-8b0e-0b6e3cbf36c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421793492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.2421793492
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.3490911038
Short name T199
Test name
Test status
Simulation time 262211436749 ps
CPU time 122.67 seconds
Started Jun 22 04:29:51 PM PDT 24
Finished Jun 22 04:31:54 PM PDT 24
Peak memory 200472 kb
Host smart-f96d3c83-5d12-46ee-b36d-bda710d12fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490911038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.3490911038
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.3350361255
Short name T125
Test name
Test status
Simulation time 29739551871 ps
CPU time 61.48 seconds
Started Jun 22 04:29:45 PM PDT 24
Finished Jun 22 04:30:48 PM PDT 24
Peak memory 200460 kb
Host smart-ca8fd044-f82d-4c4c-b8fb-6b1e4214f9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350361255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.3350361255
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.2333468997
Short name T578
Test name
Test status
Simulation time 61360313733 ps
CPU time 84.84 seconds
Started Jun 22 04:29:53 PM PDT 24
Finished Jun 22 04:31:18 PM PDT 24
Peak memory 200476 kb
Host smart-ed2d1b88-0c6c-4d94-a342-5fe4797c9180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333468997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.2333468997
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.3263888351
Short name T853
Test name
Test status
Simulation time 257727888104 ps
CPU time 41.49 seconds
Started Jun 22 04:30:06 PM PDT 24
Finished Jun 22 04:30:48 PM PDT 24
Peak memory 200560 kb
Host smart-50b2349a-db06-486b-895f-dca2b93bb574
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263888351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.3263888351
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.3202439811
Short name T402
Test name
Test status
Simulation time 42641041373 ps
CPU time 59.28 seconds
Started Jun 22 04:29:48 PM PDT 24
Finished Jun 22 04:30:48 PM PDT 24
Peak memory 200556 kb
Host smart-db9cd51d-eb5c-4f8c-843b-b526009ef00b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3202439811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.3202439811
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.2594543204
Short name T828
Test name
Test status
Simulation time 3575900504 ps
CPU time 7.22 seconds
Started Jun 22 04:29:47 PM PDT 24
Finished Jun 22 04:29:55 PM PDT 24
Peak memory 199368 kb
Host smart-c3fd3b5d-6142-42f4-b659-c89697b15fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594543204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.2594543204
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.1067768275
Short name T1051
Test name
Test status
Simulation time 25555946908 ps
CPU time 9.27 seconds
Started Jun 22 04:29:45 PM PDT 24
Finished Jun 22 04:29:56 PM PDT 24
Peak memory 197836 kb
Host smart-cd6e0d7d-1903-4e20-8b7f-06b5f9ae7a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067768275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.1067768275
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.964176969
Short name T1046
Test name
Test status
Simulation time 3086525719 ps
CPU time 43.49 seconds
Started Jun 22 04:29:46 PM PDT 24
Finished Jun 22 04:30:31 PM PDT 24
Peak memory 200444 kb
Host smart-4e840c6b-961b-4606-9911-47b53901b1c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=964176969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.964176969
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.1478288659
Short name T918
Test name
Test status
Simulation time 2345000036 ps
CPU time 2.9 seconds
Started Jun 22 04:29:47 PM PDT 24
Finished Jun 22 04:29:51 PM PDT 24
Peak memory 199748 kb
Host smart-b57003eb-c133-44c9-9ef0-2ea6b08b6cf3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1478288659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.1478288659
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.2504427359
Short name T1024
Test name
Test status
Simulation time 234921574926 ps
CPU time 127.54 seconds
Started Jun 22 04:30:01 PM PDT 24
Finished Jun 22 04:32:09 PM PDT 24
Peak memory 200536 kb
Host smart-684fc78a-1eaf-4e73-b8ea-a2fc77366374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504427359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.2504427359
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.2387353830
Short name T684
Test name
Test status
Simulation time 3623890206 ps
CPU time 6.78 seconds
Started Jun 22 04:29:55 PM PDT 24
Finished Jun 22 04:30:03 PM PDT 24
Peak memory 196616 kb
Host smart-d5bcdaf6-c492-4498-b401-9c711e8db0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387353830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.2387353830
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.3107236880
Short name T855
Test name
Test status
Simulation time 6225197189 ps
CPU time 27.44 seconds
Started Jun 22 04:29:54 PM PDT 24
Finished Jun 22 04:30:23 PM PDT 24
Peak memory 199968 kb
Host smart-fdda5284-c5b2-4d1f-a4ed-ab0e8df3ba41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107236880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.3107236880
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.3563253812
Short name T674
Test name
Test status
Simulation time 133230322936 ps
CPU time 93.54 seconds
Started Jun 22 04:29:44 PM PDT 24
Finished Jun 22 04:31:19 PM PDT 24
Peak memory 200516 kb
Host smart-43a93ebe-894c-48d8-8b3d-47e4628dbe60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563253812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.3563253812
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.3429633648
Short name T251
Test name
Test status
Simulation time 356713307221 ps
CPU time 1020.31 seconds
Started Jun 22 04:29:47 PM PDT 24
Finished Jun 22 04:46:48 PM PDT 24
Peak memory 225548 kb
Host smart-475a1774-6522-4b91-a6cc-8bcd62430112
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429633648 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.3429633648
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.3961599290
Short name T927
Test name
Test status
Simulation time 7719324392 ps
CPU time 8.76 seconds
Started Jun 22 04:29:56 PM PDT 24
Finished Jun 22 04:30:05 PM PDT 24
Peak memory 200344 kb
Host smart-249f2ef1-d9f0-4598-baf3-7cb645c75385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961599290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.3961599290
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.819206235
Short name T503
Test name
Test status
Simulation time 154843110475 ps
CPU time 78.54 seconds
Started Jun 22 04:29:45 PM PDT 24
Finished Jun 22 04:31:05 PM PDT 24
Peak memory 200632 kb
Host smart-6d63e9e3-8298-4c96-b78b-a9edc73a5f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819206235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.819206235
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.1238311566
Short name T31
Test name
Test status
Simulation time 12339843 ps
CPU time 0.56 seconds
Started Jun 22 04:30:10 PM PDT 24
Finished Jun 22 04:30:11 PM PDT 24
Peak memory 194868 kb
Host smart-f2326d08-20e1-4bab-be1a-2259d789a70a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238311566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.1238311566
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.3747651318
Short name T523
Test name
Test status
Simulation time 31029468697 ps
CPU time 12.47 seconds
Started Jun 22 04:29:55 PM PDT 24
Finished Jun 22 04:30:08 PM PDT 24
Peak memory 200412 kb
Host smart-b406ea19-7143-4130-9114-3e54156772ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747651318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.3747651318
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.147880898
Short name T259
Test name
Test status
Simulation time 28788635794 ps
CPU time 14.2 seconds
Started Jun 22 04:29:43 PM PDT 24
Finished Jun 22 04:29:58 PM PDT 24
Peak memory 200456 kb
Host smart-a5786a56-5884-4c6b-81bf-4982c3bce45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147880898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.147880898
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.2270460549
Short name T955
Test name
Test status
Simulation time 70407998880 ps
CPU time 27.97 seconds
Started Jun 22 04:31:56 PM PDT 24
Finished Jun 22 04:32:24 PM PDT 24
Peak memory 200472 kb
Host smart-5b9e1ae9-c9ab-423c-bbaa-ed30592cfa62
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270460549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.2270460549
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.3439838131
Short name T85
Test name
Test status
Simulation time 33006896902 ps
CPU time 83.41 seconds
Started Jun 22 04:29:51 PM PDT 24
Finished Jun 22 04:31:15 PM PDT 24
Peak memory 200604 kb
Host smart-0154ac8d-cf2c-407e-99ed-843323bb67fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3439838131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.3439838131
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.2469018792
Short name T430
Test name
Test status
Simulation time 12899839027 ps
CPU time 25.9 seconds
Started Jun 22 04:29:53 PM PDT 24
Finished Jun 22 04:30:19 PM PDT 24
Peak memory 198980 kb
Host smart-49ce0030-8659-4f3c-869b-745ad815c3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469018792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.2469018792
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_perf.1415528938
Short name T286
Test name
Test status
Simulation time 25447030173 ps
CPU time 95.18 seconds
Started Jun 22 04:29:50 PM PDT 24
Finished Jun 22 04:31:26 PM PDT 24
Peak memory 200452 kb
Host smart-3133bdb3-d0a3-4de4-aad9-f1f269660d5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1415528938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.1415528938
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.1993814221
Short name T685
Test name
Test status
Simulation time 3384714581 ps
CPU time 25.09 seconds
Started Jun 22 04:29:51 PM PDT 24
Finished Jun 22 04:30:16 PM PDT 24
Peak memory 199736 kb
Host smart-80f19a03-9848-4b0c-8318-ae4b5b222ca9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1993814221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.1993814221
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.3383339709
Short name T732
Test name
Test status
Simulation time 65390296866 ps
CPU time 107.72 seconds
Started Jun 22 04:29:55 PM PDT 24
Finished Jun 22 04:31:44 PM PDT 24
Peak memory 200484 kb
Host smart-2ad18356-c8d2-4b6b-8007-47930f8a2171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383339709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.3383339709
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.1831533940
Short name T518
Test name
Test status
Simulation time 666131146 ps
CPU time 1.64 seconds
Started Jun 22 04:29:47 PM PDT 24
Finished Jun 22 04:29:49 PM PDT 24
Peak memory 196584 kb
Host smart-2ee359ca-3d28-4cad-8ceb-010379fe7e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831533940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.1831533940
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.1354969006
Short name T426
Test name
Test status
Simulation time 6271681894 ps
CPU time 10.74 seconds
Started Jun 22 04:29:45 PM PDT 24
Finished Jun 22 04:30:02 PM PDT 24
Peak memory 199936 kb
Host smart-155f1c6b-b1f7-47e9-9248-51d52eff65e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354969006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.1354969006
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.2209320747
Short name T890
Test name
Test status
Simulation time 386832204936 ps
CPU time 675.47 seconds
Started Jun 22 04:29:51 PM PDT 24
Finished Jun 22 04:41:07 PM PDT 24
Peak memory 200576 kb
Host smart-565b7187-d1de-4cb3-9190-996ff986b84b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209320747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.2209320747
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.702860157
Short name T937
Test name
Test status
Simulation time 47893590457 ps
CPU time 196.26 seconds
Started Jun 22 04:29:51 PM PDT 24
Finished Jun 22 04:33:08 PM PDT 24
Peak memory 216948 kb
Host smart-e4cdc043-80dd-4826-90ab-1c1ac4bf33f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702860157 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.702860157
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.569110118
Short name T929
Test name
Test status
Simulation time 2463586948 ps
CPU time 2.99 seconds
Started Jun 22 04:29:52 PM PDT 24
Finished Jun 22 04:29:55 PM PDT 24
Peak memory 200272 kb
Host smart-443033c8-446c-48aa-8686-ff7fe9b8ed4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569110118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.569110118
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.2920754523
Short name T541
Test name
Test status
Simulation time 64769033385 ps
CPU time 6.24 seconds
Started Jun 22 04:29:45 PM PDT 24
Finished Jun 22 04:29:52 PM PDT 24
Peak memory 198412 kb
Host smart-df5a88e9-eebb-49fb-be9d-395fb0f4ab7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920754523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.2920754523
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.990223670
Short name T1009
Test name
Test status
Simulation time 27917975 ps
CPU time 0.56 seconds
Started Jun 22 04:29:53 PM PDT 24
Finished Jun 22 04:29:54 PM PDT 24
Peak memory 194844 kb
Host smart-14db093e-519a-4564-9b47-c46db50f7d90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990223670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.990223670
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.3826186957
Short name T458
Test name
Test status
Simulation time 75352530562 ps
CPU time 75.51 seconds
Started Jun 22 04:30:13 PM PDT 24
Finished Jun 22 04:31:29 PM PDT 24
Peak memory 200536 kb
Host smart-e35f4820-a8e2-47cb-b9ff-d0725e5e18a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826186957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.3826186957
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.2172419680
Short name T822
Test name
Test status
Simulation time 136689514625 ps
CPU time 293.14 seconds
Started Jun 22 04:29:54 PM PDT 24
Finished Jun 22 04:34:48 PM PDT 24
Peak memory 200508 kb
Host smart-524529fa-9d5d-4c49-9c9f-81767d12f2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172419680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.2172419680
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.3328895004
Short name T953
Test name
Test status
Simulation time 83130631404 ps
CPU time 35.15 seconds
Started Jun 22 04:29:56 PM PDT 24
Finished Jun 22 04:30:32 PM PDT 24
Peak memory 200516 kb
Host smart-83787bcb-5669-439c-9adb-7203e4bdd74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328895004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.3328895004
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.4267413600
Short name T21
Test name
Test status
Simulation time 35066229106 ps
CPU time 49.8 seconds
Started Jun 22 04:29:54 PM PDT 24
Finished Jun 22 04:30:45 PM PDT 24
Peak memory 200428 kb
Host smart-6b31082d-ef88-4a60-be84-869cbf4e438a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267413600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.4267413600
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.2675136317
Short name T753
Test name
Test status
Simulation time 127081240089 ps
CPU time 843.14 seconds
Started Jun 22 04:29:54 PM PDT 24
Finished Jun 22 04:43:58 PM PDT 24
Peak memory 200468 kb
Host smart-73e29fb8-e28b-47bc-9585-053f66ca053a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2675136317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.2675136317
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.2576124270
Short name T553
Test name
Test status
Simulation time 5997192718 ps
CPU time 3.88 seconds
Started Jun 22 04:29:57 PM PDT 24
Finished Jun 22 04:30:02 PM PDT 24
Peak memory 199424 kb
Host smart-05481e3d-0d2b-4d3b-a15a-4fe771d0f703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576124270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.2576124270
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.4067873580
Short name T509
Test name
Test status
Simulation time 82010547248 ps
CPU time 88.54 seconds
Started Jun 22 04:30:11 PM PDT 24
Finished Jun 22 04:31:40 PM PDT 24
Peak memory 200504 kb
Host smart-dd42ad14-fd18-4210-a468-3385c2a1c64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067873580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.4067873580
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.828310426
Short name T846
Test name
Test status
Simulation time 13627409101 ps
CPU time 203.63 seconds
Started Jun 22 04:29:56 PM PDT 24
Finished Jun 22 04:33:20 PM PDT 24
Peak memory 200464 kb
Host smart-0c6dd4f2-96bc-4b96-adbf-e35ac280c595
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=828310426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.828310426
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.1063088349
Short name T542
Test name
Test status
Simulation time 1906469118 ps
CPU time 12.87 seconds
Started Jun 22 04:29:52 PM PDT 24
Finished Jun 22 04:30:06 PM PDT 24
Peak memory 198640 kb
Host smart-85ebce68-7bdf-4e89-9a11-29b231b64f46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1063088349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.1063088349
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.2463562183
Short name T938
Test name
Test status
Simulation time 45798533230 ps
CPU time 61.52 seconds
Started Jun 22 04:29:54 PM PDT 24
Finished Jun 22 04:30:57 PM PDT 24
Peak memory 200520 kb
Host smart-3049b2c5-d7cc-4c21-842e-60fbdc3a34f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463562183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.2463562183
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.1060197609
Short name T424
Test name
Test status
Simulation time 2788362555 ps
CPU time 2.28 seconds
Started Jun 22 04:29:56 PM PDT 24
Finished Jun 22 04:29:59 PM PDT 24
Peak memory 197044 kb
Host smart-3b6afa5c-e1f0-46f4-8447-9a4def526a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060197609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.1060197609
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.2695148750
Short name T1048
Test name
Test status
Simulation time 947016778 ps
CPU time 3.2 seconds
Started Jun 22 04:29:51 PM PDT 24
Finished Jun 22 04:29:55 PM PDT 24
Peak memory 200500 kb
Host smart-f530697c-bd5a-4bee-b6e8-8497e3463774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695148750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.2695148750
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.1146504772
Short name T799
Test name
Test status
Simulation time 239455513585 ps
CPU time 501.46 seconds
Started Jun 22 04:29:51 PM PDT 24
Finished Jun 22 04:38:13 PM PDT 24
Peak memory 200460 kb
Host smart-ec6d8b42-c51e-4cfd-8660-52213b0477bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146504772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.1146504772
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.2375218064
Short name T75
Test name
Test status
Simulation time 50942742679 ps
CPU time 202.22 seconds
Started Jun 22 04:29:52 PM PDT 24
Finished Jun 22 04:33:15 PM PDT 24
Peak memory 217000 kb
Host smart-8c7d2a0d-1c6e-493a-aba5-17d88cab40c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375218064 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.2375218064
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.27982522
Short name T403
Test name
Test status
Simulation time 7506576684 ps
CPU time 13.61 seconds
Started Jun 22 04:29:53 PM PDT 24
Finished Jun 22 04:30:07 PM PDT 24
Peak memory 199892 kb
Host smart-192dc60c-accb-4d27-9853-fe57fd7fc474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27982522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.27982522
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.308789186
Short name T743
Test name
Test status
Simulation time 15610507622 ps
CPU time 10.58 seconds
Started Jun 22 04:30:15 PM PDT 24
Finished Jun 22 04:30:26 PM PDT 24
Peak memory 197640 kb
Host smart-9f2bc23a-eef1-4a51-96bf-2c6e40135516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308789186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.308789186
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.29887263
Short name T32
Test name
Test status
Simulation time 34135971 ps
CPU time 0.58 seconds
Started Jun 22 04:30:11 PM PDT 24
Finished Jun 22 04:30:12 PM PDT 24
Peak memory 195892 kb
Host smart-bbd03df5-2d33-4a17-a35c-f4ce7d534c85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29887263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.29887263
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.3849815393
Short name T999
Test name
Test status
Simulation time 114222473618 ps
CPU time 149.28 seconds
Started Jun 22 04:30:09 PM PDT 24
Finished Jun 22 04:32:39 PM PDT 24
Peak memory 200552 kb
Host smart-0a304678-3d89-4ae0-bc65-b1fdf30ca952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849815393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.3849815393
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.416477091
Short name T922
Test name
Test status
Simulation time 151696203411 ps
CPU time 82.05 seconds
Started Jun 22 04:29:51 PM PDT 24
Finished Jun 22 04:31:14 PM PDT 24
Peak memory 200500 kb
Host smart-57d21d6a-fec5-4c8f-9cb4-2fa013d843b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416477091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.416477091
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.1531850951
Short name T234
Test name
Test status
Simulation time 10937003452 ps
CPU time 18.26 seconds
Started Jun 22 04:29:55 PM PDT 24
Finished Jun 22 04:30:14 PM PDT 24
Peak memory 200524 kb
Host smart-2d93958b-f07e-4968-9cea-a4c77d519897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531850951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.1531850951
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.2189361706
Short name T823
Test name
Test status
Simulation time 9245113168 ps
CPU time 8.24 seconds
Started Jun 22 04:29:55 PM PDT 24
Finished Jun 22 04:30:04 PM PDT 24
Peak memory 200536 kb
Host smart-cb0e8cb1-0711-48bd-b751-9c6a03b5d0f1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189361706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.2189361706
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.715959811
Short name T1078
Test name
Test status
Simulation time 93295252517 ps
CPU time 1010.27 seconds
Started Jun 22 04:29:52 PM PDT 24
Finished Jun 22 04:46:43 PM PDT 24
Peak memory 200468 kb
Host smart-0eceed7d-5ff8-4d43-afa1-189219da83f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=715959811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.715959811
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.482081161
Short name T821
Test name
Test status
Simulation time 10863776112 ps
CPU time 14.47 seconds
Started Jun 22 04:30:07 PM PDT 24
Finished Jun 22 04:30:22 PM PDT 24
Peak memory 199616 kb
Host smart-10427525-728c-4bb7-9a8d-45271736b27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482081161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.482081161
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_perf.2745695772
Short name T987
Test name
Test status
Simulation time 39753672454 ps
CPU time 550.45 seconds
Started Jun 22 04:29:53 PM PDT 24
Finished Jun 22 04:39:04 PM PDT 24
Peak memory 200524 kb
Host smart-ee29b37d-d704-4240-ac3a-5bc0c5498167
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2745695772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.2745695772
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.282328820
Short name T811
Test name
Test status
Simulation time 1692226886 ps
CPU time 5.81 seconds
Started Jun 22 04:30:31 PM PDT 24
Finished Jun 22 04:30:37 PM PDT 24
Peak memory 199588 kb
Host smart-c98adfaa-d13d-4302-81e8-36214d29511f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=282328820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.282328820
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.2195279955
Short name T145
Test name
Test status
Simulation time 45307155320 ps
CPU time 35.93 seconds
Started Jun 22 04:29:52 PM PDT 24
Finished Jun 22 04:30:29 PM PDT 24
Peak memory 200460 kb
Host smart-e6d8879e-d591-460c-9650-2d1356af8652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195279955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.2195279955
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.458966036
Short name T438
Test name
Test status
Simulation time 1868874623 ps
CPU time 1.31 seconds
Started Jun 22 04:29:53 PM PDT 24
Finished Jun 22 04:29:55 PM PDT 24
Peak memory 195948 kb
Host smart-ea204d47-2d01-4f8c-8411-2ed5326489f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458966036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.458966036
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.2525956172
Short name T1017
Test name
Test status
Simulation time 451560796 ps
CPU time 2.29 seconds
Started Jun 22 04:29:56 PM PDT 24
Finished Jun 22 04:29:58 PM PDT 24
Peak memory 200268 kb
Host smart-bdc74653-4c59-46c9-9f17-0bebf53e7c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525956172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.2525956172
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.156738739
Short name T195
Test name
Test status
Simulation time 121524001428 ps
CPU time 189.22 seconds
Started Jun 22 04:29:54 PM PDT 24
Finished Jun 22 04:33:05 PM PDT 24
Peak memory 200464 kb
Host smart-fefeb5cc-ec5f-43ac-90f0-2aa17560fb4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156738739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.156738739
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.1407221811
Short name T718
Test name
Test status
Simulation time 986767671 ps
CPU time 1.82 seconds
Started Jun 22 04:30:13 PM PDT 24
Finished Jun 22 04:30:16 PM PDT 24
Peak memory 199016 kb
Host smart-dee12a01-16b3-46d1-9b21-a841662c79ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407221811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.1407221811
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.2427277705
Short name T439
Test name
Test status
Simulation time 33173558742 ps
CPU time 29.16 seconds
Started Jun 22 04:29:50 PM PDT 24
Finished Jun 22 04:30:20 PM PDT 24
Peak memory 200624 kb
Host smart-7da1c64b-cd05-4a3a-a5b2-40b8c1423861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427277705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.2427277705
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.2354656059
Short name T452
Test name
Test status
Simulation time 48259235 ps
CPU time 0.55 seconds
Started Jun 22 04:30:02 PM PDT 24
Finished Jun 22 04:30:03 PM PDT 24
Peak memory 195848 kb
Host smart-232f8634-cd81-4184-8d1c-85c86c6b17a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354656059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.2354656059
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.2884446864
Short name T988
Test name
Test status
Simulation time 26925466108 ps
CPU time 38.13 seconds
Started Jun 22 04:30:13 PM PDT 24
Finished Jun 22 04:30:52 PM PDT 24
Peak memory 200556 kb
Host smart-abd64892-5731-4839-b562-c887c2d1eb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884446864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.2884446864
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.4250671620
Short name T520
Test name
Test status
Simulation time 321528631345 ps
CPU time 162.06 seconds
Started Jun 22 04:29:58 PM PDT 24
Finished Jun 22 04:32:40 PM PDT 24
Peak memory 200488 kb
Host smart-cc35078b-1763-4be5-99a7-b730e151a4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250671620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.4250671620
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.580241356
Short name T435
Test name
Test status
Simulation time 224399278262 ps
CPU time 98.14 seconds
Started Jun 22 04:29:58 PM PDT 24
Finished Jun 22 04:31:36 PM PDT 24
Peak memory 200500 kb
Host smart-0cbb77ed-562d-44ad-acc5-16e0421268be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580241356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.580241356
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.3527532237
Short name T154
Test name
Test status
Simulation time 81288158633 ps
CPU time 44.92 seconds
Started Jun 22 04:29:59 PM PDT 24
Finished Jun 22 04:30:45 PM PDT 24
Peak memory 200400 kb
Host smart-b5588945-beca-4477-beda-97a5fca7a986
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527532237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.3527532237
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.1477613851
Short name T1010
Test name
Test status
Simulation time 69666301498 ps
CPU time 170.56 seconds
Started Jun 22 04:30:06 PM PDT 24
Finished Jun 22 04:32:58 PM PDT 24
Peak memory 200464 kb
Host smart-1389b497-22d4-43a3-816d-4e9c3a4a25a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1477613851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.1477613851
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.1810605222
Short name T408
Test name
Test status
Simulation time 4152722466 ps
CPU time 3.35 seconds
Started Jun 22 04:29:58 PM PDT 24
Finished Jun 22 04:30:02 PM PDT 24
Peak memory 199972 kb
Host smart-dd6c1b9b-5b6a-42ae-89d4-c96f72f20fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810605222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.1810605222
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_perf.3146626148
Short name T289
Test name
Test status
Simulation time 8715977071 ps
CPU time 163.58 seconds
Started Jun 22 04:30:02 PM PDT 24
Finished Jun 22 04:32:46 PM PDT 24
Peak memory 200480 kb
Host smart-3212ae22-cc48-4ed0-9eeb-b12ac1650e35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3146626148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.3146626148
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.4013562712
Short name T772
Test name
Test status
Simulation time 4866629515 ps
CPU time 12.35 seconds
Started Jun 22 04:30:05 PM PDT 24
Finished Jun 22 04:30:18 PM PDT 24
Peak memory 199632 kb
Host smart-800c6e79-42e4-4e43-954d-db1f0343bcc9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4013562712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.4013562712
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.1252784152
Short name T2
Test name
Test status
Simulation time 68449766032 ps
CPU time 111.21 seconds
Started Jun 22 04:30:06 PM PDT 24
Finished Jun 22 04:31:58 PM PDT 24
Peak memory 200464 kb
Host smart-63cc50d0-1718-43b5-9348-e0691a985647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252784152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.1252784152
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.1251248235
Short name T1036
Test name
Test status
Simulation time 456225085 ps
CPU time 1.35 seconds
Started Jun 22 04:29:57 PM PDT 24
Finished Jun 22 04:29:59 PM PDT 24
Peak memory 195976 kb
Host smart-f77cffe3-b2ae-435f-894d-a7e7ca27d60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251248235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.1251248235
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.563550728
Short name T1039
Test name
Test status
Simulation time 501023784 ps
CPU time 1.84 seconds
Started Jun 22 04:30:05 PM PDT 24
Finished Jun 22 04:30:07 PM PDT 24
Peak memory 199996 kb
Host smart-e7cc1bfa-2e3f-43ee-8754-f89e29af0a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563550728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.563550728
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.2269109695
Short name T656
Test name
Test status
Simulation time 377250442934 ps
CPU time 799.76 seconds
Started Jun 22 04:30:00 PM PDT 24
Finished Jun 22 04:43:20 PM PDT 24
Peak memory 200440 kb
Host smart-08d8b50c-2c31-416a-b40b-b44fa034a2f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269109695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.2269109695
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.1105070143
Short name T985
Test name
Test status
Simulation time 97646947093 ps
CPU time 1013.61 seconds
Started Jun 22 04:30:05 PM PDT 24
Finished Jun 22 04:47:00 PM PDT 24
Peak memory 216988 kb
Host smart-5d11556d-1bfd-4f05-84bb-3c7ea6ad0b3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105070143 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.1105070143
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.3186340268
Short name T973
Test name
Test status
Simulation time 908988490 ps
CPU time 3.36 seconds
Started Jun 22 04:30:00 PM PDT 24
Finished Jun 22 04:30:04 PM PDT 24
Peak memory 199264 kb
Host smart-2a233069-5d4f-4ee8-979d-a576a536a454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186340268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.3186340268
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.2601339287
Short name T301
Test name
Test status
Simulation time 44268549178 ps
CPU time 22.26 seconds
Started Jun 22 04:29:51 PM PDT 24
Finished Jun 22 04:30:14 PM PDT 24
Peak memory 200540 kb
Host smart-40aae2b2-7efa-4730-bc45-91b269512ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601339287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.2601339287
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.2515062621
Short name T469
Test name
Test status
Simulation time 42888081 ps
CPU time 0.55 seconds
Started Jun 22 04:27:59 PM PDT 24
Finished Jun 22 04:28:01 PM PDT 24
Peak memory 195860 kb
Host smart-55288f3d-f818-45b2-95cc-1d738dc7143e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515062621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.2515062621
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.2899884410
Short name T837
Test name
Test status
Simulation time 140445148706 ps
CPU time 218.12 seconds
Started Jun 22 04:28:02 PM PDT 24
Finished Jun 22 04:31:42 PM PDT 24
Peak memory 200564 kb
Host smart-7b2338c3-99c5-49ac-9fe4-319c43851e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899884410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.2899884410
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.1820405264
Short name T401
Test name
Test status
Simulation time 31923113443 ps
CPU time 54.66 seconds
Started Jun 22 04:28:01 PM PDT 24
Finished Jun 22 04:28:57 PM PDT 24
Peak memory 200104 kb
Host smart-07340db6-9eae-4180-8120-7b31a1c97f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820405264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.1820405264
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.3590711607
Short name T213
Test name
Test status
Simulation time 200753283819 ps
CPU time 85.26 seconds
Started Jun 22 04:28:02 PM PDT 24
Finished Jun 22 04:29:29 PM PDT 24
Peak memory 200464 kb
Host smart-3ca58254-78dc-45a1-8f12-4a7889a42a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590711607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.3590711607
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.1257579211
Short name T788
Test name
Test status
Simulation time 187972590366 ps
CPU time 138.97 seconds
Started Jun 22 04:28:00 PM PDT 24
Finished Jun 22 04:30:20 PM PDT 24
Peak memory 197972 kb
Host smart-f6c991ec-a748-42a1-81df-b56fa8953534
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257579211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.1257579211
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.3985331821
Short name T412
Test name
Test status
Simulation time 274036146616 ps
CPU time 346.91 seconds
Started Jun 22 04:27:59 PM PDT 24
Finished Jun 22 04:33:48 PM PDT 24
Peak memory 200508 kb
Host smart-3384a05f-e34b-4e98-8a08-a98306331c56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3985331821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.3985331821
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.990132739
Short name T1061
Test name
Test status
Simulation time 4470628457 ps
CPU time 7.29 seconds
Started Jun 22 04:27:58 PM PDT 24
Finished Jun 22 04:28:06 PM PDT 24
Peak memory 199428 kb
Host smart-a974da3e-99d1-4b51-9f9f-4ed9f72ce436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990132739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.990132739
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_perf.1694222299
Short name T445
Test name
Test status
Simulation time 25587041094 ps
CPU time 788.49 seconds
Started Jun 22 04:28:11 PM PDT 24
Finished Jun 22 04:41:21 PM PDT 24
Peak memory 200816 kb
Host smart-5f4bbbeb-1c4f-43d2-949d-cda10e607a5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1694222299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.1694222299
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.3078197922
Short name T3
Test name
Test status
Simulation time 6777370278 ps
CPU time 16.4 seconds
Started Jun 22 04:28:09 PM PDT 24
Finished Jun 22 04:28:26 PM PDT 24
Peak memory 200512 kb
Host smart-5a4da064-8aa0-4f5b-9a01-ba763f9ad004
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3078197922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.3078197922
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.3374738834
Short name T1026
Test name
Test status
Simulation time 73527699193 ps
CPU time 124.99 seconds
Started Jun 22 04:28:06 PM PDT 24
Finished Jun 22 04:30:12 PM PDT 24
Peak memory 200476 kb
Host smart-f7a7dd80-62d8-4228-aa46-9809b67c150f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374738834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.3374738834
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.2034878453
Short name T744
Test name
Test status
Simulation time 37777127751 ps
CPU time 14.01 seconds
Started Jun 22 04:28:28 PM PDT 24
Finished Jun 22 04:28:42 PM PDT 24
Peak memory 196308 kb
Host smart-58c79206-b59b-415a-bf40-4379985495df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034878453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.2034878453
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.4026785637
Short name T308
Test name
Test status
Simulation time 10569984924 ps
CPU time 38.11 seconds
Started Jun 22 04:27:59 PM PDT 24
Finished Jun 22 04:28:39 PM PDT 24
Peak memory 200464 kb
Host smart-aa196fc4-0074-472f-a779-837eb982c7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026785637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.4026785637
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.3903586112
Short name T580
Test name
Test status
Simulation time 204932874841 ps
CPU time 65.13 seconds
Started Jun 22 04:28:01 PM PDT 24
Finished Jun 22 04:29:08 PM PDT 24
Peak memory 200564 kb
Host smart-76013559-d054-4ccf-8d4b-6b9c4a75960e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903586112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.3903586112
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.506210409
Short name T675
Test name
Test status
Simulation time 39830201634 ps
CPU time 269.27 seconds
Started Jun 22 04:28:03 PM PDT 24
Finished Jun 22 04:32:34 PM PDT 24
Peak memory 208776 kb
Host smart-3ac5fee5-99bd-4349-9817-0ee3b87e5073
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506210409 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.506210409
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.162666843
Short name T740
Test name
Test status
Simulation time 761982981 ps
CPU time 1.56 seconds
Started Jun 22 04:28:04 PM PDT 24
Finished Jun 22 04:28:07 PM PDT 24
Peak memory 198624 kb
Host smart-271f2297-decb-4824-9c6e-4097135fbcb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162666843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.162666843
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.2262365134
Short name T294
Test name
Test status
Simulation time 120388936838 ps
CPU time 78.75 seconds
Started Jun 22 04:28:04 PM PDT 24
Finished Jun 22 04:29:24 PM PDT 24
Peak memory 200432 kb
Host smart-4d196759-5a27-4a40-8842-9ce345d9bf8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262365134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.2262365134
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.1036636438
Short name T643
Test name
Test status
Simulation time 13150797399 ps
CPU time 25.46 seconds
Started Jun 22 04:30:00 PM PDT 24
Finished Jun 22 04:30:26 PM PDT 24
Peak memory 200544 kb
Host smart-be520ebd-5029-4de8-80ae-2c8b1aca7c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036636438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.1036636438
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.920621321
Short name T604
Test name
Test status
Simulation time 40757170505 ps
CPU time 15.94 seconds
Started Jun 22 04:30:00 PM PDT 24
Finished Jun 22 04:30:17 PM PDT 24
Peak memory 199472 kb
Host smart-c1a5c240-62ee-49c4-8364-6dd8a20f01d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920621321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.920621321
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.1931730641
Short name T1002
Test name
Test status
Simulation time 248840270625 ps
CPU time 867 seconds
Started Jun 22 04:30:07 PM PDT 24
Finished Jun 22 04:44:35 PM PDT 24
Peak memory 215144 kb
Host smart-d3c40393-7325-4150-9303-6bf45d0a1d7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931730641 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.1931730641
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.98662464
Short name T224
Test name
Test status
Simulation time 42058720755 ps
CPU time 20.6 seconds
Started Jun 22 04:30:02 PM PDT 24
Finished Jun 22 04:30:23 PM PDT 24
Peak memory 200544 kb
Host smart-d7dbe954-6bf3-457c-b86b-eeb9fbb93263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98662464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.98662464
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.4047309874
Short name T223
Test name
Test status
Simulation time 37855836607 ps
CPU time 62.68 seconds
Started Jun 22 04:30:06 PM PDT 24
Finished Jun 22 04:31:10 PM PDT 24
Peak memory 200452 kb
Host smart-ed255e0b-3665-4e84-83a3-afe288b58ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047309874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.4047309874
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.2314450424
Short name T1006
Test name
Test status
Simulation time 51397056082 ps
CPU time 303.83 seconds
Started Jun 22 04:30:10 PM PDT 24
Finished Jun 22 04:35:14 PM PDT 24
Peak memory 216908 kb
Host smart-45915cd9-e52f-4593-bb58-512825f9db59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314450424 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.2314450424
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.3195064194
Short name T952
Test name
Test status
Simulation time 116424422601 ps
CPU time 49.92 seconds
Started Jun 22 04:30:00 PM PDT 24
Finished Jun 22 04:30:50 PM PDT 24
Peak memory 200464 kb
Host smart-1380e8de-373b-4d8f-9ae7-692a6259dbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195064194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.3195064194
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.897260563
Short name T87
Test name
Test status
Simulation time 43102772375 ps
CPU time 482.32 seconds
Started Jun 22 04:29:59 PM PDT 24
Finished Jun 22 04:38:02 PM PDT 24
Peak memory 216980 kb
Host smart-5b65ecdc-179a-42c0-ac46-e189181206db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897260563 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.897260563
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.3842787700
Short name T193
Test name
Test status
Simulation time 8723375303 ps
CPU time 14.33 seconds
Started Jun 22 04:30:09 PM PDT 24
Finished Jun 22 04:30:24 PM PDT 24
Peak memory 200556 kb
Host smart-e4e00ad8-c89a-4d3b-910e-b1c4618fd364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842787700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.3842787700
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.1057250636
Short name T219
Test name
Test status
Simulation time 39682411950 ps
CPU time 15.33 seconds
Started Jun 22 04:29:59 PM PDT 24
Finished Jun 22 04:30:15 PM PDT 24
Peak memory 200572 kb
Host smart-c23e3332-fe7f-44a1-88fb-5cb838ce805b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057250636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.1057250636
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.2544281702
Short name T191
Test name
Test status
Simulation time 49419728049 ps
CPU time 21.01 seconds
Started Jun 22 04:30:01 PM PDT 24
Finished Jun 22 04:30:22 PM PDT 24
Peak memory 200292 kb
Host smart-449c5d71-958f-4313-8a24-c21fcff4d5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544281702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.2544281702
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.541499033
Short name T891
Test name
Test status
Simulation time 57675238293 ps
CPU time 64.76 seconds
Started Jun 22 04:30:00 PM PDT 24
Finished Jun 22 04:31:05 PM PDT 24
Peak memory 200464 kb
Host smart-f202b6e0-d938-434e-b950-e1433faa388b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541499033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.541499033
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.418014072
Short name T898
Test name
Test status
Simulation time 34928129505 ps
CPU time 353.94 seconds
Started Jun 22 04:29:58 PM PDT 24
Finished Jun 22 04:35:52 PM PDT 24
Peak memory 216732 kb
Host smart-729b708b-8f9d-4381-828f-3cb3e35c7961
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418014072 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.418014072
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.1955912364
Short name T764
Test name
Test status
Simulation time 17944363463 ps
CPU time 18.97 seconds
Started Jun 22 04:30:03 PM PDT 24
Finished Jun 22 04:30:23 PM PDT 24
Peak memory 200524 kb
Host smart-7ce7d1bc-3b2d-4152-bea6-5c2481d91693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955912364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.1955912364
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.3644948005
Short name T449
Test name
Test status
Simulation time 97496437 ps
CPU time 0.54 seconds
Started Jun 22 04:28:15 PM PDT 24
Finished Jun 22 04:28:16 PM PDT 24
Peak memory 195904 kb
Host smart-289a0caa-73d8-4eee-81fc-71b48a50719f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644948005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.3644948005
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.2211457687
Short name T838
Test name
Test status
Simulation time 74375129623 ps
CPU time 104.91 seconds
Started Jun 22 04:27:58 PM PDT 24
Finished Jun 22 04:29:45 PM PDT 24
Peak memory 200524 kb
Host smart-d47cd193-3215-455c-884c-84ad4ef53277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211457687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.2211457687
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.2983192582
Short name T284
Test name
Test status
Simulation time 88271518209 ps
CPU time 51.89 seconds
Started Jun 22 04:28:05 PM PDT 24
Finished Jun 22 04:28:58 PM PDT 24
Peak memory 200448 kb
Host smart-404f43c8-fa81-45aa-bb55-085a694a37a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983192582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.2983192582
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.2452065727
Short name T235
Test name
Test status
Simulation time 23396790397 ps
CPU time 65.02 seconds
Started Jun 22 04:28:08 PM PDT 24
Finished Jun 22 04:29:14 PM PDT 24
Peak memory 200460 kb
Host smart-b457d5c9-d8fd-4be1-81fc-88c46b331937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452065727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.2452065727
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.2752375381
Short name T104
Test name
Test status
Simulation time 54371789776 ps
CPU time 26.72 seconds
Started Jun 22 04:27:59 PM PDT 24
Finished Jun 22 04:28:28 PM PDT 24
Peak memory 200484 kb
Host smart-edaf2b45-1520-495d-abf6-c0275d320116
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752375381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.2752375381
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.344462512
Short name T664
Test name
Test status
Simulation time 242754938661 ps
CPU time 225.51 seconds
Started Jun 22 04:28:13 PM PDT 24
Finished Jun 22 04:31:59 PM PDT 24
Peak memory 200472 kb
Host smart-5e31c407-35a1-4a7e-b534-c2ae1f65c906
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=344462512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.344462512
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.2816705057
Short name T23
Test name
Test status
Simulation time 5628041873 ps
CPU time 6.19 seconds
Started Jun 22 04:28:14 PM PDT 24
Finished Jun 22 04:28:21 PM PDT 24
Peak memory 198996 kb
Host smart-bd82ff52-2918-4adb-bc9c-b254a3bda6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816705057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.2816705057
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_perf.1799346343
Short name T910
Test name
Test status
Simulation time 12280503729 ps
CPU time 218.64 seconds
Started Jun 22 04:27:58 PM PDT 24
Finished Jun 22 04:31:38 PM PDT 24
Peak memory 200488 kb
Host smart-5aecb843-d63e-4dd2-a297-e95b84124f57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1799346343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.1799346343
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.3640126012
Short name T43
Test name
Test status
Simulation time 6274256146 ps
CPU time 54.64 seconds
Started Jun 22 04:28:04 PM PDT 24
Finished Jun 22 04:29:00 PM PDT 24
Peak memory 198652 kb
Host smart-aeb76315-c9d6-4bfa-915b-fe98fd321a0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3640126012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.3640126012
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.1127542593
Short name T814
Test name
Test status
Simulation time 26960363256 ps
CPU time 16.46 seconds
Started Jun 22 04:27:57 PM PDT 24
Finished Jun 22 04:28:15 PM PDT 24
Peak memory 200444 kb
Host smart-00b2332e-2569-4857-a7c7-4871b5d48d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127542593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.1127542593
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.969083754
Short name T866
Test name
Test status
Simulation time 1788929981 ps
CPU time 3.14 seconds
Started Jun 22 04:28:13 PM PDT 24
Finished Jun 22 04:28:17 PM PDT 24
Peak memory 195948 kb
Host smart-2fd60f9b-633a-4aa0-bc70-296d1367b186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969083754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.969083754
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.2462939863
Short name T639
Test name
Test status
Simulation time 464291129 ps
CPU time 1.37 seconds
Started Jun 22 04:28:13 PM PDT 24
Finished Jun 22 04:28:15 PM PDT 24
Peak memory 199196 kb
Host smart-6f7e4efc-0ac1-4fd5-9da3-5c83da73da10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462939863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.2462939863
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.1723492897
Short name T142
Test name
Test status
Simulation time 5608790534 ps
CPU time 11.31 seconds
Started Jun 22 04:28:02 PM PDT 24
Finished Jun 22 04:28:15 PM PDT 24
Peak memory 200492 kb
Host smart-36e68c21-f7b4-4fba-95f5-7ede2885b6ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723492897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.1723492897
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.2514190281
Short name T88
Test name
Test status
Simulation time 1104149289 ps
CPU time 2.6 seconds
Started Jun 22 04:28:05 PM PDT 24
Finished Jun 22 04:28:09 PM PDT 24
Peak memory 198852 kb
Host smart-ac4778f5-3185-4f5c-b01f-7902cefb6678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514190281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.2514190281
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.1699693077
Short name T335
Test name
Test status
Simulation time 59549426957 ps
CPU time 46.9 seconds
Started Jun 22 04:28:04 PM PDT 24
Finished Jun 22 04:28:53 PM PDT 24
Peak memory 200520 kb
Host smart-45bfb782-0f63-4e05-bf2a-781e7a807bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699693077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.1699693077
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.4096150429
Short name T835
Test name
Test status
Simulation time 64694658718 ps
CPU time 94.29 seconds
Started Jun 22 04:30:05 PM PDT 24
Finished Jun 22 04:31:40 PM PDT 24
Peak memory 200580 kb
Host smart-43548a61-8ba4-45c9-9b5a-412bec9dfa26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096150429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.4096150429
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.220848445
Short name T1030
Test name
Test status
Simulation time 386661322732 ps
CPU time 1203.86 seconds
Started Jun 22 04:30:08 PM PDT 24
Finished Jun 22 04:50:13 PM PDT 24
Peak memory 225252 kb
Host smart-849b0e45-6346-4735-943f-ea8f18e80730
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220848445 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.220848445
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.2303447651
Short name T667
Test name
Test status
Simulation time 54273381162 ps
CPU time 44.81 seconds
Started Jun 22 04:30:11 PM PDT 24
Finished Jun 22 04:30:56 PM PDT 24
Peak memory 200500 kb
Host smart-67af07e5-d5b4-4faf-b036-97a9996271a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303447651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.2303447651
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.2213174533
Short name T129
Test name
Test status
Simulation time 311993973438 ps
CPU time 733.62 seconds
Started Jun 22 04:30:10 PM PDT 24
Finished Jun 22 04:42:24 PM PDT 24
Peak memory 216996 kb
Host smart-18464db6-e73a-4ef7-ba94-d1ac1b97dc75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213174533 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.2213174533
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.2563883639
Short name T1022
Test name
Test status
Simulation time 87398357215 ps
CPU time 137.81 seconds
Started Jun 22 04:30:08 PM PDT 24
Finished Jun 22 04:32:27 PM PDT 24
Peak memory 200512 kb
Host smart-c359c83d-837d-4bcd-bff0-46b414367008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563883639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.2563883639
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.3657844141
Short name T785
Test name
Test status
Simulation time 14528608454 ps
CPU time 14.22 seconds
Started Jun 22 04:30:05 PM PDT 24
Finished Jun 22 04:30:20 PM PDT 24
Peak memory 200608 kb
Host smart-421df78a-b06c-4b07-93e3-c3e401123ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657844141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.3657844141
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.3494603021
Short name T132
Test name
Test status
Simulation time 211259878299 ps
CPU time 573.36 seconds
Started Jun 22 04:30:07 PM PDT 24
Finished Jun 22 04:39:41 PM PDT 24
Peak memory 217036 kb
Host smart-ec75f671-528b-42dc-8cd8-02a0d17445fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494603021 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.3494603021
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.2522216994
Short name T946
Test name
Test status
Simulation time 17554300464 ps
CPU time 26.17 seconds
Started Jun 22 04:30:18 PM PDT 24
Finished Jun 22 04:30:44 PM PDT 24
Peak memory 199324 kb
Host smart-329e061b-f201-42e9-b274-2e9066f6be93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522216994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.2522216994
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.2647386591
Short name T291
Test name
Test status
Simulation time 83274510755 ps
CPU time 98.65 seconds
Started Jun 22 04:30:09 PM PDT 24
Finished Jun 22 04:31:48 PM PDT 24
Peak memory 200540 kb
Host smart-a19fd395-c82e-4bbe-8fc7-10e7fe9a68fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647386591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.2647386591
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.195024056
Short name T677
Test name
Test status
Simulation time 37281448570 ps
CPU time 13.64 seconds
Started Jun 22 04:30:06 PM PDT 24
Finished Jun 22 04:30:20 PM PDT 24
Peak memory 200464 kb
Host smart-083741b1-6831-4b3e-98b7-5bac95a18eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195024056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.195024056
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.3262833569
Short name T352
Test name
Test status
Simulation time 211126412992 ps
CPU time 249.09 seconds
Started Jun 22 04:30:12 PM PDT 24
Finished Jun 22 04:34:22 PM PDT 24
Peak memory 216944 kb
Host smart-7a76270e-ff33-427a-8865-48f2f4355041
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262833569 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.3262833569
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.1686218887
Short name T233
Test name
Test status
Simulation time 246575350984 ps
CPU time 79.76 seconds
Started Jun 22 04:30:09 PM PDT 24
Finished Jun 22 04:31:30 PM PDT 24
Peak memory 200512 kb
Host smart-60e39a54-8944-47b4-bd5c-5ea2f2c0aa41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686218887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.1686218887
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.2207057631
Short name T854
Test name
Test status
Simulation time 30167052414 ps
CPU time 12.99 seconds
Started Jun 22 04:30:09 PM PDT 24
Finished Jun 22 04:30:23 PM PDT 24
Peak memory 200500 kb
Host smart-c43e5d85-a7ea-4f58-94ff-68c81b37161c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207057631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.2207057631
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.4225604891
Short name T298
Test name
Test status
Simulation time 84676419810 ps
CPU time 1595.07 seconds
Started Jun 22 04:30:08 PM PDT 24
Finished Jun 22 04:56:44 PM PDT 24
Peak memory 216948 kb
Host smart-863ef078-a69f-4776-94e0-5bdc57c8f5a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225604891 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.4225604891
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.845010289
Short name T247
Test name
Test status
Simulation time 82777309108 ps
CPU time 77.91 seconds
Started Jun 22 04:30:12 PM PDT 24
Finished Jun 22 04:31:30 PM PDT 24
Peak memory 200520 kb
Host smart-45057b2f-f88c-4cfe-abf7-24001ac8d29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845010289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.845010289
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.2764350476
Short name T28
Test name
Test status
Simulation time 50046770252 ps
CPU time 559.51 seconds
Started Jun 22 04:30:10 PM PDT 24
Finished Jun 22 04:39:30 PM PDT 24
Peak memory 216948 kb
Host smart-06604684-176f-47c9-aff4-4329e23129d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764350476 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.2764350476
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.2710088105
Short name T68
Test name
Test status
Simulation time 64230059 ps
CPU time 0.53 seconds
Started Jun 22 04:28:16 PM PDT 24
Finished Jun 22 04:28:18 PM PDT 24
Peak memory 195860 kb
Host smart-a47cac0d-a40a-4729-b76b-0a6c0530a7db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710088105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.2710088105
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.2619964470
Short name T857
Test name
Test status
Simulation time 5676681664 ps
CPU time 8.97 seconds
Started Jun 22 04:28:11 PM PDT 24
Finished Jun 22 04:28:20 PM PDT 24
Peak memory 200436 kb
Host smart-e2be49b3-7404-4f81-beb1-b451aecae242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619964470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.2619964470
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.1396418671
Short name T387
Test name
Test status
Simulation time 5980925833 ps
CPU time 12.79 seconds
Started Jun 22 04:28:04 PM PDT 24
Finished Jun 22 04:28:19 PM PDT 24
Peak memory 200384 kb
Host smart-1a5161a4-3458-45e3-afd3-5051556d247a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396418671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.1396418671
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.4202907942
Short name T841
Test name
Test status
Simulation time 85246749004 ps
CPU time 139.77 seconds
Started Jun 22 04:28:16 PM PDT 24
Finished Jun 22 04:30:37 PM PDT 24
Peak memory 200288 kb
Host smart-39da5c50-cc6c-4779-a448-9b048e22a437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202907942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.4202907942
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.3774561273
Short name T1040
Test name
Test status
Simulation time 17662727685 ps
CPU time 7.17 seconds
Started Jun 22 04:28:02 PM PDT 24
Finished Jun 22 04:28:11 PM PDT 24
Peak memory 200484 kb
Host smart-684b7558-0126-4040-ba66-6610f4065c39
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774561273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.3774561273
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.1855067842
Short name T287
Test name
Test status
Simulation time 122070037676 ps
CPU time 143.34 seconds
Started Jun 22 04:28:08 PM PDT 24
Finished Jun 22 04:30:32 PM PDT 24
Peak memory 200536 kb
Host smart-eb9b68f3-82ba-4e1e-b2ee-325ef914d37f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1855067842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.1855067842
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.1127814589
Short name T818
Test name
Test status
Simulation time 5710793590 ps
CPU time 10.16 seconds
Started Jun 22 04:28:00 PM PDT 24
Finished Jun 22 04:28:12 PM PDT 24
Peak memory 199040 kb
Host smart-75b89d2d-1799-4b6e-88fd-7c053a708ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127814589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.1127814589
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_perf.1724575873
Short name T747
Test name
Test status
Simulation time 34589816991 ps
CPU time 1004.43 seconds
Started Jun 22 04:27:59 PM PDT 24
Finished Jun 22 04:44:46 PM PDT 24
Peak memory 200584 kb
Host smart-621f1704-6b6a-410f-9ab2-c10beebf32d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1724575873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.1724575873
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.916546310
Short name T813
Test name
Test status
Simulation time 5781013099 ps
CPU time 45.69 seconds
Started Jun 22 04:28:01 PM PDT 24
Finished Jun 22 04:28:49 PM PDT 24
Peak memory 198812 kb
Host smart-e0a5c7ec-4a63-42dc-b742-563212e98fb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=916546310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.916546310
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.1925377540
Short name T158
Test name
Test status
Simulation time 35619775642 ps
CPU time 29.89 seconds
Started Jun 22 04:28:02 PM PDT 24
Finished Jun 22 04:28:34 PM PDT 24
Peak memory 200344 kb
Host smart-46f42f23-1458-447f-b63b-406384337e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925377540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.1925377540
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.3907229627
Short name T637
Test name
Test status
Simulation time 3449738977 ps
CPU time 5.51 seconds
Started Jun 22 04:28:07 PM PDT 24
Finished Jun 22 04:28:18 PM PDT 24
Peak memory 196436 kb
Host smart-8f1344d9-313b-470b-9c8d-1947d3c1f169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907229627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.3907229627
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.1972525730
Short name T410
Test name
Test status
Simulation time 6320372745 ps
CPU time 8.23 seconds
Started Jun 22 04:28:02 PM PDT 24
Finished Jun 22 04:28:12 PM PDT 24
Peak memory 199824 kb
Host smart-3edfdefd-52a5-4c1c-b2cf-1f9afb3d7152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972525730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.1972525730
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.3627292622
Short name T465
Test name
Test status
Simulation time 93866096740 ps
CPU time 1867.31 seconds
Started Jun 22 04:28:24 PM PDT 24
Finished Jun 22 04:59:32 PM PDT 24
Peak memory 200504 kb
Host smart-43bbcf9e-56d8-460a-bf0d-3462c8413c12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627292622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.3627292622
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.3456601503
Short name T981
Test name
Test status
Simulation time 93405271040 ps
CPU time 1330.2 seconds
Started Jun 22 04:28:02 PM PDT 24
Finished Jun 22 04:50:15 PM PDT 24
Peak memory 216896 kb
Host smart-598a6aa0-fcdc-4c0c-a492-6f2eecebb69e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456601503 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.3456601503
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.868500436
Short name T310
Test name
Test status
Simulation time 2061404884 ps
CPU time 2.51 seconds
Started Jun 22 04:28:05 PM PDT 24
Finished Jun 22 04:28:09 PM PDT 24
Peak memory 199516 kb
Host smart-571d39ea-d096-40e0-8066-f4e89b33b5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868500436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.868500436
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.318882455
Short name T468
Test name
Test status
Simulation time 20908851878 ps
CPU time 18.78 seconds
Started Jun 22 04:27:59 PM PDT 24
Finished Jun 22 04:28:20 PM PDT 24
Peak memory 200344 kb
Host smart-8072a304-3ca8-4b40-a4f9-fda89b4479d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318882455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.318882455
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.1494672129
Short name T901
Test name
Test status
Simulation time 26813815467 ps
CPU time 30.39 seconds
Started Jun 22 04:30:12 PM PDT 24
Finished Jun 22 04:30:43 PM PDT 24
Peak memory 200480 kb
Host smart-210162d7-d477-4fb7-9254-119f7278bbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494672129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.1494672129
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.2833619554
Short name T1067
Test name
Test status
Simulation time 17332417970 ps
CPU time 29.51 seconds
Started Jun 22 04:30:09 PM PDT 24
Finished Jun 22 04:30:40 PM PDT 24
Peak memory 200464 kb
Host smart-84dfd229-8d50-4bc0-8f18-63fdcf5abdd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833619554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.2833619554
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.1150458953
Short name T1038
Test name
Test status
Simulation time 36693399560 ps
CPU time 125.94 seconds
Started Jun 22 04:30:06 PM PDT 24
Finished Jun 22 04:32:12 PM PDT 24
Peak memory 216760 kb
Host smart-3878d272-af70-4ccd-bff3-0db026532ac8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150458953 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.1150458953
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.3437981409
Short name T563
Test name
Test status
Simulation time 97296538031 ps
CPU time 40.15 seconds
Started Jun 22 04:30:11 PM PDT 24
Finished Jun 22 04:30:52 PM PDT 24
Peak memory 200476 kb
Host smart-d3719fa8-9832-4507-a9f9-b98622933708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437981409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.3437981409
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.1986447581
Short name T481
Test name
Test status
Simulation time 52618051719 ps
CPU time 104.47 seconds
Started Jun 22 04:30:08 PM PDT 24
Finished Jun 22 04:31:54 PM PDT 24
Peak memory 200532 kb
Host smart-e86e8016-41d3-4bae-abdd-cfed534c0cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986447581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.1986447581
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.3920405129
Short name T25
Test name
Test status
Simulation time 22631649572 ps
CPU time 109.52 seconds
Started Jun 22 04:30:08 PM PDT 24
Finished Jun 22 04:31:58 PM PDT 24
Peak memory 208784 kb
Host smart-72741279-16fb-49ee-ab0b-dc840a1dafa6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920405129 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.3920405129
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.3822200842
Short name T900
Test name
Test status
Simulation time 120578822866 ps
CPU time 154.77 seconds
Started Jun 22 04:30:08 PM PDT 24
Finished Jun 22 04:32:44 PM PDT 24
Peak memory 200508 kb
Host smart-0e847276-c45a-4a57-be4d-d2cf23de608a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822200842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.3822200842
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.3621007819
Short name T71
Test name
Test status
Simulation time 199513013651 ps
CPU time 1047.26 seconds
Started Jun 22 04:30:08 PM PDT 24
Finished Jun 22 04:47:36 PM PDT 24
Peak memory 216920 kb
Host smart-d0c6f882-fbc9-4512-8235-07b5c0531bbb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621007819 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.3621007819
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.32899339
Short name T528
Test name
Test status
Simulation time 15862319129 ps
CPU time 23.54 seconds
Started Jun 22 04:30:07 PM PDT 24
Finished Jun 22 04:30:32 PM PDT 24
Peak memory 200528 kb
Host smart-083be013-6b7b-4dc9-b578-1e3c898bfa26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32899339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.32899339
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.3337496681
Short name T39
Test name
Test status
Simulation time 54488450535 ps
CPU time 168.36 seconds
Started Jun 22 04:30:09 PM PDT 24
Finished Jun 22 04:32:58 PM PDT 24
Peak memory 216996 kb
Host smart-d545d176-e4b7-4062-b438-923f4bc3c89b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337496681 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.3337496681
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.1813184449
Short name T330
Test name
Test status
Simulation time 182523402194 ps
CPU time 247.65 seconds
Started Jun 22 04:30:07 PM PDT 24
Finished Jun 22 04:34:15 PM PDT 24
Peak memory 200636 kb
Host smart-91fe59cb-817f-4c9c-bf35-66ead8a3c1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813184449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.1813184449
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.1755299614
Short name T693
Test name
Test status
Simulation time 62408108203 ps
CPU time 651.18 seconds
Started Jun 22 04:30:09 PM PDT 24
Finished Jun 22 04:41:01 PM PDT 24
Peak memory 216972 kb
Host smart-0b746b7f-835d-48f4-8d3c-a42cbc261305
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755299614 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.1755299614
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.815047666
Short name T296
Test name
Test status
Simulation time 14676106514 ps
CPU time 36.22 seconds
Started Jun 22 04:30:11 PM PDT 24
Finished Jun 22 04:30:48 PM PDT 24
Peak memory 200512 kb
Host smart-cdf587f6-c47f-4d3c-9483-4ac725883d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815047666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.815047666
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.99846255
Short name T131
Test name
Test status
Simulation time 370246315959 ps
CPU time 490.97 seconds
Started Jun 22 04:30:07 PM PDT 24
Finished Jun 22 04:38:18 PM PDT 24
Peak memory 216980 kb
Host smart-3bede25c-6d34-4fee-bada-cce85c93fc21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99846255 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.99846255
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.4170369763
Short name T267
Test name
Test status
Simulation time 234444395427 ps
CPU time 377.79 seconds
Started Jun 22 04:30:07 PM PDT 24
Finished Jun 22 04:36:26 PM PDT 24
Peak memory 200484 kb
Host smart-45287959-1c30-435b-9465-e2bc1bf7c317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170369763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.4170369763
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.1992375277
Short name T70
Test name
Test status
Simulation time 83175708322 ps
CPU time 902.68 seconds
Started Jun 22 04:30:06 PM PDT 24
Finished Jun 22 04:45:09 PM PDT 24
Peak memory 225192 kb
Host smart-8e4be109-7042-43c7-bb3b-08c55a893957
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992375277 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.1992375277
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.299765332
Short name T564
Test name
Test status
Simulation time 28826418345 ps
CPU time 20.87 seconds
Started Jun 22 04:30:10 PM PDT 24
Finished Jun 22 04:30:32 PM PDT 24
Peak memory 200432 kb
Host smart-a43fd5f4-88a1-4d46-95a9-7617525a70aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299765332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.299765332
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.3395983434
Short name T73
Test name
Test status
Simulation time 108411518565 ps
CPU time 1445.93 seconds
Started Jun 22 04:30:11 PM PDT 24
Finished Jun 22 04:54:18 PM PDT 24
Peak memory 224908 kb
Host smart-2548c6bc-5ad7-41f2-934f-5bf20cf31219
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395983434 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.3395983434
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.2745695273
Short name T92
Test name
Test status
Simulation time 14938912 ps
CPU time 0.61 seconds
Started Jun 22 04:28:05 PM PDT 24
Finished Jun 22 04:28:07 PM PDT 24
Peak memory 196272 kb
Host smart-1beaecdc-5049-454a-844a-3e7517fcb1c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745695273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.2745695273
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.3235903991
Short name T971
Test name
Test status
Simulation time 98709642372 ps
CPU time 157.87 seconds
Started Jun 22 04:28:22 PM PDT 24
Finished Jun 22 04:31:00 PM PDT 24
Peak memory 200428 kb
Host smart-2ad26141-4fdd-49b6-94ce-58ceff642a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235903991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.3235903991
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.2312452275
Short name T547
Test name
Test status
Simulation time 215557284213 ps
CPU time 328.54 seconds
Started Jun 22 04:28:28 PM PDT 24
Finished Jun 22 04:33:57 PM PDT 24
Peak memory 200584 kb
Host smart-89c91dbf-8771-4885-beb7-ba57618205c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312452275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.2312452275
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.2132448617
Short name T169
Test name
Test status
Simulation time 45460407693 ps
CPU time 33.63 seconds
Started Jun 22 04:28:02 PM PDT 24
Finished Jun 22 04:28:37 PM PDT 24
Peak memory 200464 kb
Host smart-61869c7d-1060-4bf7-b694-1b8552e730a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132448617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.2132448617
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.2657977147
Short name T658
Test name
Test status
Simulation time 58248480002 ps
CPU time 118.78 seconds
Started Jun 22 04:28:17 PM PDT 24
Finished Jun 22 04:30:17 PM PDT 24
Peak memory 200500 kb
Host smart-9b1c8182-2c5a-4e54-accf-49dd911f9166
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657977147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.2657977147
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.817830194
Short name T135
Test name
Test status
Simulation time 68821537509 ps
CPU time 714.51 seconds
Started Jun 22 04:28:18 PM PDT 24
Finished Jun 22 04:40:13 PM PDT 24
Peak memory 200556 kb
Host smart-38c1760d-db04-4208-8f31-a8c843509ad0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=817830194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.817830194
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.4287422418
Short name T419
Test name
Test status
Simulation time 7109943859 ps
CPU time 4.45 seconds
Started Jun 22 04:28:04 PM PDT 24
Finished Jun 22 04:28:10 PM PDT 24
Peak memory 199252 kb
Host smart-8dc59f2b-37f4-4bd8-b92a-61de229b0062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287422418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.4287422418
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_perf.3597055230
Short name T124
Test name
Test status
Simulation time 16187643917 ps
CPU time 258.89 seconds
Started Jun 22 04:28:05 PM PDT 24
Finished Jun 22 04:32:26 PM PDT 24
Peak memory 200504 kb
Host smart-59268b77-6f09-4373-a1cc-ba540f0e01f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3597055230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.3597055230
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.2856904596
Short name T692
Test name
Test status
Simulation time 5449215866 ps
CPU time 23.18 seconds
Started Jun 22 04:28:27 PM PDT 24
Finished Jun 22 04:28:50 PM PDT 24
Peak memory 198688 kb
Host smart-6896f55e-1a2a-4f08-83f7-64d4991279ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2856904596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.2856904596
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.3499163086
Short name T792
Test name
Test status
Simulation time 60944742877 ps
CPU time 24.57 seconds
Started Jun 22 04:28:04 PM PDT 24
Finished Jun 22 04:28:31 PM PDT 24
Peak memory 200492 kb
Host smart-5fbfbeab-d41a-4c68-b0b2-1e9db23b5d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499163086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.3499163086
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.1188962767
Short name T526
Test name
Test status
Simulation time 4240621086 ps
CPU time 1.5 seconds
Started Jun 22 04:28:05 PM PDT 24
Finished Jun 22 04:28:08 PM PDT 24
Peak memory 196604 kb
Host smart-304e6821-dfa0-4632-b7c0-31752535adf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188962767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.1188962767
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.2688481405
Short name T647
Test name
Test status
Simulation time 141176317 ps
CPU time 0.78 seconds
Started Jun 22 04:28:04 PM PDT 24
Finished Jun 22 04:28:10 PM PDT 24
Peak memory 197520 kb
Host smart-90839955-2231-497e-a554-b066e718cf7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688481405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.2688481405
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.549881548
Short name T143
Test name
Test status
Simulation time 105307709412 ps
CPU time 71.91 seconds
Started Jun 22 04:28:03 PM PDT 24
Finished Jun 22 04:29:16 PM PDT 24
Peak memory 200480 kb
Host smart-2b6ec37d-692b-420b-ba18-6db993b9575f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549881548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.549881548
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.1536774452
Short name T1042
Test name
Test status
Simulation time 49283449808 ps
CPU time 555.55 seconds
Started Jun 22 04:28:11 PM PDT 24
Finished Jun 22 04:37:27 PM PDT 24
Peak memory 216236 kb
Host smart-da02e049-e731-4454-9d2b-85692343849b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536774452 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.1536774452
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.3886810424
Short name T666
Test name
Test status
Simulation time 1715174777 ps
CPU time 2.21 seconds
Started Jun 22 04:28:21 PM PDT 24
Finished Jun 22 04:28:24 PM PDT 24
Peak memory 199524 kb
Host smart-7fc75427-7c73-4b0d-847e-dc2f9866a040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886810424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.3886810424
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.2487546527
Short name T724
Test name
Test status
Simulation time 37296414701 ps
CPU time 32.11 seconds
Started Jun 22 04:28:00 PM PDT 24
Finished Jun 22 04:28:33 PM PDT 24
Peak memory 200500 kb
Host smart-78681270-1b24-4def-93e1-a420bd0dade0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487546527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.2487546527
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.2255325265
Short name T204
Test name
Test status
Simulation time 39493525000 ps
CPU time 59.94 seconds
Started Jun 22 04:30:13 PM PDT 24
Finished Jun 22 04:31:13 PM PDT 24
Peak memory 200484 kb
Host smart-dfac3076-4575-4238-b208-599931ccdf79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255325265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.2255325265
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.2837946318
Short name T306
Test name
Test status
Simulation time 107857518998 ps
CPU time 85.31 seconds
Started Jun 22 04:30:14 PM PDT 24
Finished Jun 22 04:31:40 PM PDT 24
Peak memory 200572 kb
Host smart-15d0f9de-420a-4410-b0bf-350b51cc24f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837946318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.2837946318
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.3086321100
Short name T237
Test name
Test status
Simulation time 115955807524 ps
CPU time 959.86 seconds
Started Jun 22 04:30:13 PM PDT 24
Finished Jun 22 04:46:14 PM PDT 24
Peak memory 227968 kb
Host smart-7d2649f5-b10f-45ee-8b21-6dd49fb5cdf5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086321100 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.3086321100
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.1107636783
Short name T1035
Test name
Test status
Simulation time 32225208367 ps
CPU time 55.72 seconds
Started Jun 22 04:30:14 PM PDT 24
Finished Jun 22 04:31:10 PM PDT 24
Peak memory 200864 kb
Host smart-853dc8a9-cf44-4409-9311-9ba78ef3463e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107636783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.1107636783
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.2189593261
Short name T347
Test name
Test status
Simulation time 35606593451 ps
CPU time 1163.37 seconds
Started Jun 22 04:30:17 PM PDT 24
Finished Jun 22 04:49:41 PM PDT 24
Peak memory 216932 kb
Host smart-be399018-abf2-49d0-8b63-decd0cab08a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189593261 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.2189593261
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.3791406510
Short name T636
Test name
Test status
Simulation time 71026082769 ps
CPU time 26.44 seconds
Started Jun 22 04:30:12 PM PDT 24
Finished Jun 22 04:30:39 PM PDT 24
Peak memory 200216 kb
Host smart-cc788ed7-69a2-4c2f-9d23-1128b249b167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791406510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.3791406510
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.441115207
Short name T817
Test name
Test status
Simulation time 112481618533 ps
CPU time 1323.05 seconds
Started Jun 22 04:30:12 PM PDT 24
Finished Jun 22 04:52:16 PM PDT 24
Peak memory 216952 kb
Host smart-13025479-97b7-4d42-9607-2a60352974d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441115207 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.441115207
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.841380812
Short name T217
Test name
Test status
Simulation time 111264703728 ps
CPU time 77.02 seconds
Started Jun 22 04:30:31 PM PDT 24
Finished Jun 22 04:31:49 PM PDT 24
Peak memory 200504 kb
Host smart-74cdbe7e-e688-4708-9840-df179d75859e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841380812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.841380812
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.4083314924
Short name T593
Test name
Test status
Simulation time 33487499825 ps
CPU time 510.3 seconds
Started Jun 22 04:30:33 PM PDT 24
Finished Jun 22 04:39:04 PM PDT 24
Peak memory 217060 kb
Host smart-346bbc7f-ad84-4da0-bd9b-a0d1b1c63a2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083314924 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.4083314924
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.1320621232
Short name T653
Test name
Test status
Simulation time 161277607745 ps
CPU time 106.63 seconds
Started Jun 22 04:30:13 PM PDT 24
Finished Jun 22 04:32:00 PM PDT 24
Peak memory 200528 kb
Host smart-15748e4d-7cd7-49dd-a1b4-7b9d05e91b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320621232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.1320621232
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.948714938
Short name T346
Test name
Test status
Simulation time 64560482105 ps
CPU time 596.81 seconds
Started Jun 22 04:30:13 PM PDT 24
Finished Jun 22 04:40:10 PM PDT 24
Peak memory 216916 kb
Host smart-dca2cd1d-1bb9-436c-b3f6-6c1b90cf18cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948714938 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.948714938
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.808574344
Short name T336
Test name
Test status
Simulation time 199108557553 ps
CPU time 89.83 seconds
Started Jun 22 04:30:13 PM PDT 24
Finished Jun 22 04:31:44 PM PDT 24
Peak memory 200544 kb
Host smart-61db4a70-30c3-41cc-8766-cfe0794ec1d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808574344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.808574344
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.1294449380
Short name T230
Test name
Test status
Simulation time 48135937281 ps
CPU time 37.59 seconds
Started Jun 22 04:30:15 PM PDT 24
Finished Jun 22 04:30:53 PM PDT 24
Peak memory 200528 kb
Host smart-c7a717f9-5b93-4b30-9e77-96e68cc6e676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294449380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.1294449380
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.912125039
Short name T650
Test name
Test status
Simulation time 13393800 ps
CPU time 0.57 seconds
Started Jun 22 04:28:09 PM PDT 24
Finished Jun 22 04:28:10 PM PDT 24
Peak memory 195864 kb
Host smart-a5f8a266-aecb-43ef-bb6d-92797898d300
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912125039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.912125039
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.1412151353
Short name T972
Test name
Test status
Simulation time 154478644296 ps
CPU time 39.74 seconds
Started Jun 22 04:28:05 PM PDT 24
Finished Jun 22 04:28:46 PM PDT 24
Peak memory 200528 kb
Host smart-5d121d9c-9843-4529-ba3a-c3b087fd7af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412151353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.1412151353
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.2965392219
Short name T800
Test name
Test status
Simulation time 31503247022 ps
CPU time 26.66 seconds
Started Jun 22 04:28:04 PM PDT 24
Finished Jun 22 04:28:33 PM PDT 24
Peak memory 200408 kb
Host smart-3ce96838-983e-418e-b643-5a7b1b7cfad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965392219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.2965392219
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.4294338060
Short name T364
Test name
Test status
Simulation time 50960154453 ps
CPU time 13.31 seconds
Started Jun 22 04:28:06 PM PDT 24
Finished Jun 22 04:28:20 PM PDT 24
Peak memory 200520 kb
Host smart-6599c760-fc82-4c1c-99a9-efe85bf403cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294338060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.4294338060
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.1907929541
Short name T596
Test name
Test status
Simulation time 180276124741 ps
CPU time 30.52 seconds
Started Jun 22 04:28:08 PM PDT 24
Finished Jun 22 04:28:38 PM PDT 24
Peak memory 200468 kb
Host smart-5af12db0-c2ef-4e9b-8b50-090a8d66ec9d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907929541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.1907929541
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_loopback.500908437
Short name T65
Test name
Test status
Simulation time 3299298046 ps
CPU time 7.53 seconds
Started Jun 22 04:28:06 PM PDT 24
Finished Jun 22 04:28:15 PM PDT 24
Peak memory 199320 kb
Host smart-4db52faa-7945-4d05-9cc1-e54f9aadcdc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500908437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.500908437
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.1007039168
Short name T786
Test name
Test status
Simulation time 22080542453 ps
CPU time 33.57 seconds
Started Jun 22 04:28:01 PM PDT 24
Finished Jun 22 04:28:36 PM PDT 24
Peak memory 200100 kb
Host smart-99460031-96f8-4433-959e-6a2e3f55f89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007039168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.1007039168
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.1760156389
Short name T752
Test name
Test status
Simulation time 15032711255 ps
CPU time 141.75 seconds
Started Jun 22 04:28:14 PM PDT 24
Finished Jun 22 04:30:37 PM PDT 24
Peak memory 200504 kb
Host smart-141e2a3b-41fc-4398-bb1b-fc226cf7f22b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1760156389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.1760156389
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.477114028
Short name T414
Test name
Test status
Simulation time 1489591046 ps
CPU time 3.07 seconds
Started Jun 22 04:28:15 PM PDT 24
Finished Jun 22 04:28:24 PM PDT 24
Peak memory 198488 kb
Host smart-6f7885c4-b3e0-4dbd-a09f-0f668923e122
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=477114028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.477114028
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.1075584766
Short name T843
Test name
Test status
Simulation time 105288028429 ps
CPU time 42.87 seconds
Started Jun 22 04:29:12 PM PDT 24
Finished Jun 22 04:29:57 PM PDT 24
Peak memory 200516 kb
Host smart-9d8bd9da-d650-4a40-9cd6-08af03822541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075584766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.1075584766
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.3129835006
Short name T895
Test name
Test status
Simulation time 4821117860 ps
CPU time 8.25 seconds
Started Jun 22 04:28:04 PM PDT 24
Finished Jun 22 04:28:14 PM PDT 24
Peak memory 197428 kb
Host smart-915340d9-5543-47dd-92ea-b6dddfa8e064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129835006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.3129835006
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.4045551256
Short name T538
Test name
Test status
Simulation time 5381448525 ps
CPU time 10.39 seconds
Started Jun 22 04:28:00 PM PDT 24
Finished Jun 22 04:28:12 PM PDT 24
Peak memory 200408 kb
Host smart-cb9bdd9f-31b9-46d9-b406-e55ee2780c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045551256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.4045551256
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.3434096726
Short name T994
Test name
Test status
Simulation time 112125111875 ps
CPU time 86.12 seconds
Started Jun 22 04:28:03 PM PDT 24
Finished Jun 22 04:29:31 PM PDT 24
Peak memory 200452 kb
Host smart-dcfba800-03ef-4cbe-af0e-d718bbdb4e6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434096726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.3434096726
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.2594240410
Short name T351
Test name
Test status
Simulation time 122207320000 ps
CPU time 364.42 seconds
Started Jun 22 04:28:06 PM PDT 24
Finished Jun 22 04:34:11 PM PDT 24
Peak memory 216956 kb
Host smart-a5d40b03-70a1-49a7-a6ec-229303fb3eec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594240410 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.2594240410
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.2999824919
Short name T574
Test name
Test status
Simulation time 7220078423 ps
CPU time 15.36 seconds
Started Jun 22 04:28:24 PM PDT 24
Finished Jun 22 04:28:40 PM PDT 24
Peak memory 200392 kb
Host smart-7e7b10e7-39e6-4f62-9dcc-d066d2161e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999824919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.2999824919
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.3012637576
Short name T398
Test name
Test status
Simulation time 66638919789 ps
CPU time 15.51 seconds
Started Jun 22 04:28:13 PM PDT 24
Finished Jun 22 04:28:29 PM PDT 24
Peak memory 200240 kb
Host smart-c6616d3f-6222-4901-8f8a-b2dfa1079cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012637576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.3012637576
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.1207637584
Short name T599
Test name
Test status
Simulation time 193049744177 ps
CPU time 305.51 seconds
Started Jun 22 04:30:13 PM PDT 24
Finished Jun 22 04:35:20 PM PDT 24
Peak memory 200468 kb
Host smart-7eedf03a-c03b-448b-a9d7-6bcd4c5e8d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207637584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.1207637584
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.1768313648
Short name T38
Test name
Test status
Simulation time 40678871488 ps
CPU time 551.17 seconds
Started Jun 22 04:30:16 PM PDT 24
Finished Jun 22 04:39:27 PM PDT 24
Peak memory 216976 kb
Host smart-042255df-77c4-4999-bd9c-10f52548fe31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768313648 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.1768313648
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.3683919230
Short name T288
Test name
Test status
Simulation time 97135011165 ps
CPU time 183.28 seconds
Started Jun 22 04:30:12 PM PDT 24
Finished Jun 22 04:33:16 PM PDT 24
Peak memory 200508 kb
Host smart-9fdd6207-48b4-4443-92b8-7ab991bebdf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683919230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.3683919230
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.1652336657
Short name T991
Test name
Test status
Simulation time 46539929385 ps
CPU time 779.74 seconds
Started Jun 22 04:30:15 PM PDT 24
Finished Jun 22 04:43:15 PM PDT 24
Peak memory 217048 kb
Host smart-9c858ea6-031f-4498-8549-2a0cddbb9a80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652336657 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.1652336657
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.3378539501
Short name T460
Test name
Test status
Simulation time 20745529411 ps
CPU time 35.48 seconds
Started Jun 22 04:30:20 PM PDT 24
Finished Jun 22 04:30:56 PM PDT 24
Peak memory 200484 kb
Host smart-adeb95a1-506f-4a27-bbe6-3d0ec439e3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378539501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.3378539501
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.3963696337
Short name T293
Test name
Test status
Simulation time 105821572482 ps
CPU time 149.17 seconds
Started Jun 22 04:30:32 PM PDT 24
Finished Jun 22 04:33:02 PM PDT 24
Peak memory 200548 kb
Host smart-a1675064-3e82-4de8-8df9-7b7aa9419332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963696337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.3963696337
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.3876363826
Short name T561
Test name
Test status
Simulation time 15900892975 ps
CPU time 14.04 seconds
Started Jun 22 04:30:13 PM PDT 24
Finished Jun 22 04:30:28 PM PDT 24
Peak memory 200484 kb
Host smart-1cd2a1a4-c18b-404e-aad9-5760b20a2cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876363826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.3876363826
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.4031470190
Short name T1027
Test name
Test status
Simulation time 110022104909 ps
CPU time 510.13 seconds
Started Jun 22 04:30:19 PM PDT 24
Finished Jun 22 04:38:49 PM PDT 24
Peak memory 216972 kb
Host smart-1cb25274-fcdf-4992-b125-6193637ac5f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031470190 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.4031470190
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.365769408
Short name T161
Test name
Test status
Simulation time 29142429019 ps
CPU time 10.75 seconds
Started Jun 22 04:30:21 PM PDT 24
Finished Jun 22 04:30:32 PM PDT 24
Peak memory 200092 kb
Host smart-ed6d7596-8a94-4234-a6f6-79cfa6d13096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365769408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.365769408
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.482122967
Short name T69
Test name
Test status
Simulation time 109676149504 ps
CPU time 754.63 seconds
Started Jun 22 04:30:14 PM PDT 24
Finished Jun 22 04:42:50 PM PDT 24
Peak memory 210352 kb
Host smart-d215bc78-3725-4630-922b-f21669c76e91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482122967 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.482122967
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.3614200997
Short name T1063
Test name
Test status
Simulation time 33234081188 ps
CPU time 64.28 seconds
Started Jun 22 04:30:14 PM PDT 24
Finished Jun 22 04:31:19 PM PDT 24
Peak memory 200524 kb
Host smart-74df0f9f-39a9-4217-9d11-1aad0ddac64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614200997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.3614200997
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.3137384289
Short name T36
Test name
Test status
Simulation time 51457534028 ps
CPU time 871.96 seconds
Started Jun 22 04:30:12 PM PDT 24
Finished Jun 22 04:44:44 PM PDT 24
Peak memory 216916 kb
Host smart-22dba654-7e9a-429e-a994-b94795e1c07a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137384289 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.3137384289
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.2507168465
Short name T611
Test name
Test status
Simulation time 29643105481 ps
CPU time 52.81 seconds
Started Jun 22 04:30:14 PM PDT 24
Finished Jun 22 04:31:08 PM PDT 24
Peak memory 200432 kb
Host smart-b78745bd-1297-4ecb-8a90-a86019761434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507168465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.2507168465
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.50978093
Short name T554
Test name
Test status
Simulation time 374176737184 ps
CPU time 1060.01 seconds
Started Jun 22 04:30:20 PM PDT 24
Finished Jun 22 04:48:01 PM PDT 24
Peak memory 213664 kb
Host smart-ea2c83bf-f15e-4a68-b977-e746d6001dcc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50978093 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.50978093
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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