Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	101049	1			T1	529		T2	2		T3	47
all_values[1]	101049	1			T1	529		T2	2		T3	47
all_values[2]	101049	1			T1	529		T2	2		T3	47
all_values[3]	101049	1			T1	529		T2	2		T3	47
all_values[4]	101049	1			T1	529		T2	2		T3	47
all_values[5]	101049	1			T1	529		T2	2		T3	47
all_values[6]	101049	1			T1	529		T2	2		T3	47
all_values[7]	101049	1			T1	529		T2	2		T3	47
all_values[8]	101049	1			T1	529		T2	2		T3	47

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

454937

1

T1

1675

T2

18

T3

283

auto[1]

454504

1

T1

3086

T3

140

T4

238

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

823762

1

T1

4439

T2

13

T3

368

auto[1]

85679

1

T1

322

T2

5

T3

55

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	29766	1			T3	11		T4	16		T6	14
all_values[0]	auto[0]	auto[1]	21274	1			T1	64		T2	2		T3	34
all_values[0]	auto[1]	auto[0]	28099	1			T1	369		T4	28		T7	4
all_values[0]	auto[1]	auto[1]	21910	1			T1	96		T3	2		T4	3
all_values[1]	auto[0]	auto[0]	52141	1			T1	84		T2	2		T3	1
all_values[1]	auto[0]	auto[1]	1312	1			T6	2		T9	11		T12	4
all_values[1]	auto[1]	auto[0]	46245	1			T1	445		T3	46		T4	2
all_values[1]	auto[1]	auto[1]	1351	1			T6	7		T9	16		T12	5
all_values[2]	auto[0]	auto[0]	42503	1			T1	65		T2	1		T3	45
all_values[2]	auto[0]	auto[1]	2158	1			T2	1		T3	2		T4	1
all_values[2]	auto[1]	auto[0]	54197	1			T1	462		T4	31		T6	64
all_values[2]	auto[1]	auto[1]	2191	1			T1	2		T7	8		T9	4
all_values[3]	auto[0]	auto[0]	52478	1			T1	237		T2	2		T3	3
all_values[3]	auto[0]	auto[1]	268	1			T6	2		T9	2		T13	2
all_values[3]	auto[1]	auto[0]	48023	1			T1	292		T3	44		T4	45
all_values[3]	auto[1]	auto[1]	280	1			T9	5		T14	4		T15	3
all_values[4]	auto[0]	auto[0]	48385	1			T1	386		T2	2		T3	47
all_values[4]	auto[0]	auto[1]	386	1			T6	1		T9	1		T14	2
all_values[4]	auto[1]	auto[0]	51870	1			T1	143		T4	18		T6	64
all_values[4]	auto[1]	auto[1]	408	1			T9	5		T14	1		T29	6
all_values[5]	auto[0]	auto[0]	52057	1			T1	292		T2	2		T3	1
all_values[5]	auto[0]	auto[1]	138	1			T9	2		T43	1		T80	2
all_values[5]	auto[1]	auto[0]	48715	1			T1	237		T3	46		T4	31
all_values[5]	auto[1]	auto[1]	139	1			T9	2		T15	1		T29	3
all_values[6]	auto[0]	auto[0]	53462	1			T1	292		T2	2		T3	47
all_values[6]	auto[0]	auto[1]	140	1			T9	2		T15	1		T29	1
all_values[6]	auto[1]	auto[0]	47313	1			T1	237		T4	31		T6	106
all_values[6]	auto[1]	auto[1]	134	1			T29	2		T92	1		T43	5
all_values[7]	auto[0]	auto[0]	49004	1			T1	174		T2	2		T3	45
all_values[7]	auto[0]	auto[1]	311	1			T6	1		T12	2		T18	1
all_values[7]	auto[1]	auto[0]	51429	1			T1	355		T3	2		T4	18
all_values[7]	auto[1]	auto[1]	305	1			T6	1		T9	5		T14	2
all_values[8]	auto[0]	auto[0]	32439	1			T1	80		T3	30		T4	16
all_values[8]	auto[0]	auto[1]	16715	1			T1	1		T2	2		T3	17
all_values[8]	auto[1]	auto[0]	35636	1			T1	289		T4	31		T6	22
all_values[8]	auto[1]	auto[1]	16259	1			T1	159		T6	78		T7	10