Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2242

1

T1

1

T2

1

T3

1

auto[UartRx]

2242

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4082	1			T1	2		T2	2		T3	2
values[1]	23	1			T32	1		T43	1		T101	1
values[2]	44	1			T4	2		T15	1		T28	1
values[3]	35	1			T15	1		T30	1		T31	1
values[4]	34	1			T29	1		T30	1		T32	1
values[5]	40	1			T4	1		T28	1		T43	3
values[6]	38	1			T4	1		T28	2		T34	1
values[7]	52	1			T4	2		T18	1		T28	3
values[8]	33	1			T28	1		T32	1		T245	2
values[9]	45	1			T4	1		T18	1		T30	1
values[10]	35	1			T32	4		T34	1		T245	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2117	1			T1	1		T2	1		T3	1
auto[UartTx]	values[1]	6	1			T101	1		T45	1		T46	1
auto[UartTx]	values[2]	12	1			T4	1		T15	1		T28	1
auto[UartTx]	values[3]	10	1			T15	1		T43	1		T82	1
auto[UartTx]	values[4]	11	1			T30	1		T32	1		T34	1
auto[UartTx]	values[5]	11	1			T43	1		T83	1		T159	1
auto[UartTx]	values[6]	15	1			T34	1		T43	1		T249	1
auto[UartTx]	values[7]	14	1			T4	1		T18	1		T28	1
auto[UartTx]	values[8]	12	1			T28	1		T245	2		T145	1
auto[UartTx]	values[9]	15	1			T4	1		T245	1		T43	1
auto[UartTx]	values[10]	12	1			T32	3		T81	1		T303	1
auto[UartRx]	values[0]	1965	1			T1	1		T2	1		T3	1
auto[UartRx]	values[1]	17	1			T32	1		T43	1		T82	1
auto[UartRx]	values[2]	32	1			T4	1		T32	1		T245	1
auto[UartRx]	values[3]	25	1			T30	1		T31	1		T80	1
auto[UartRx]	values[4]	23	1			T29	1		T33	1		T34	1
auto[UartRx]	values[5]	29	1			T4	1		T28	1		T43	2
auto[UartRx]	values[6]	23	1			T4	1		T28	2		T43	1
auto[UartRx]	values[7]	38	1			T4	1		T28	2		T245	2
auto[UartRx]	values[8]	21	1			T32	1		T185	1		T81	1
auto[UartRx]	values[9]	30	1			T18	1		T30	1		T33	1
auto[UartRx]	values[10]	23	1			T32	1		T34	1		T245	1