Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1888	1			T3	1		T4	5		T7	2
auto[BaudRate115200]	1590	1			T1	2		T2	1		T7	1
auto[BaudRate230400]	1634	1			T1	1		T4	1		T5	1
auto[BaudRate128Kbps]	1604	1			T1	2		T6	3		T7	2
auto[BaudRate256Kbps]	1737	1			T1	2		T3	1		T5	1
auto[BaudRate1Mbps]	1606	1			T3	2		T4	2		T9	1
auto[BaudRate1p5Mbps]	1089	1			T1	1		T2	1		T3	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	863	1			T10	6		T35	4		T39	7
freqs[25]	1037	1			T12	34		T36	10		T78	7
freqs[48]	383	1			T109	8		T235	6		T278	2
freqs[50]	574	1			T6	4		T42	6		T113	10
freqs[100]	1010	1			T4	9		T20	36		T77	15

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	161	1			T10	3		T35	1		T29	2
auto[BaudRate9600]	freqs[25]	160	1			T12	3		T36	1		T154	1
auto[BaudRate9600]	freqs[48]	110	1			T235	2		T304	16		T305	2
auto[BaudRate9600]	freqs[50]	68	1			T113	1		T306	6		T302	1
auto[BaudRate9600]	freqs[100]	158	1			T4	5		T20	6		T77	2
auto[BaudRate115200]	freqs[24]	110	1			T39	1		T29	4		T307	15
auto[BaudRate115200]	freqs[25]	145	1			T12	2		T36	3		T78	3
auto[BaudRate115200]	freqs[48]	31	1			T123	3		T99	2		T199	1
auto[BaudRate115200]	freqs[50]	83	1			T113	4		T308	15		T81	17
auto[BaudRate115200]	freqs[100]	137	1			T20	6		T77	1		T93	1
auto[BaudRate230400]	freqs[24]	136	1			T10	1		T39	3		T29	5
auto[BaudRate230400]	freqs[25]	162	1			T12	7		T36	2		T154	2
auto[BaudRate230400]	freqs[48]	30	1			T99	1		T199	1		T309	2
auto[BaudRate230400]	freqs[50]	73	1			T6	1		T42	1		T306	6
auto[BaudRate230400]	freqs[100]	122	1			T4	1		T77	4		T93	2
auto[BaudRate128Kbps]	freqs[24]	135	1			T10	1		T35	2		T39	1
auto[BaudRate128Kbps]	freqs[25]	152	1			T12	14		T36	1		T78	1
auto[BaudRate128Kbps]	freqs[48]	54	1			T109	3		T235	2		T278	1
auto[BaudRate128Kbps]	freqs[50]	72	1			T6	3		T42	1		T302	1
auto[BaudRate128Kbps]	freqs[100]	161	1			T20	9		T77	2		T310	12
auto[BaudRate256Kbps]	freqs[24]	119	1			T39	1		T29	6		T91	2
auto[BaudRate256Kbps]	freqs[25]	148	1			T12	5		T36	2		T78	1
auto[BaudRate256Kbps]	freqs[48]	51	1			T109	3		T123	2		T199	3
auto[BaudRate256Kbps]	freqs[50]	87	1			T42	1		T113	1		T306	3
auto[BaudRate256Kbps]	freqs[100]	135	1			T20	6		T77	2		T93	2
auto[BaudRate1Mbps]	freqs[24]	140	1			T35	1		T29	7		T91	3
auto[BaudRate1Mbps]	freqs[25]	179	1			T12	1		T36	1		T78	1
auto[BaudRate1Mbps]	freqs[48]	48	1			T109	2		T309	1		T294	2
auto[BaudRate1Mbps]	freqs[50]	108	1			T42	2		T113	3		T306	9
auto[BaudRate1Mbps]	freqs[100]	157	1			T4	2		T20	6		T77	3
auto[BaudRate1p5Mbps]	freqs[25]	91	1			T12	2		T78	1		T265	6
auto[BaudRate1p5Mbps]	freqs[48]	59	1			T235	2		T278	1		T123	2
auto[BaudRate1p5Mbps]	freqs[50]	83	1			T42	1		T113	1		T306	6
auto[BaudRate1p5Mbps]	freqs[100]	140	1			T4	1		T20	3		T77	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded