Group : uart_env_pkg::uart_env_cov::rx_break_err_cg
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Group : uart_env_pkg::uart_env_cov::rx_break_err_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv



Summary for Group uart_env_pkg::uart_env_cov::rx_break_err_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group uart_env_pkg::uart_env_cov::rx_break_err_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_break_level 4 0 4 100.00 100 1 1 0


Summary for Variable cp_break_level

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_break_level

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_levels[0] 288 1 T9 1 T15 1 T29 3
all_levels[1] 38 1 T9 4 T16 1 T19 1
all_levels[2] 18 1 T311 1 T312 3 T313 2
all_levels[3] 26 1 T180 1 T314 1 T126 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%