Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.42	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	11	119	91.54

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	11	119	91.54	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	28816343	1			T1	169538		T3	112		T4	41
all_levels[1]	173325	1			T1	100		T4	7		T7	13
all_levels[2]	2014	1			T7	9		T10	3		T12	6
all_levels[3]	901	1			T7	5		T10	3		T12	8
all_levels[4]	594	1			T7	4		T10	4		T12	1
all_levels[5]	408	1			T3	1		T7	2		T10	1
all_levels[6]	373	1			T3	1		T7	8		T12	2
all_levels[7]	299	1			T3	1		T7	2		T41	1
all_levels[8]	264	1			T7	3		T76	2		T77	1
all_levels[9]	236	1			T12	1		T36	1		T76	2
all_levels[10]	175	1			T12	2		T76	1		T77	2
all_levels[11]	160	1			T7	1		T41	2		T39	1
all_levels[12]	138	1			T41	1		T76	1		T78	1
all_levels[13]	109	1			T10	1		T42	2		T76	3
all_levels[14]	112	1			T10	1		T42	1		T76	1
all_levels[15]	122	1			T12	2		T66	1		T76	2
all_levels[16]	93	1			T76	2		T94	1		T90	1
all_levels[17]	98	1			T18	2		T42	1		T76	1
all_levels[18]	89	1			T12	1		T36	1		T42	1
all_levels[19]	67	1			T18	1		T28	1		T31	2
all_levels[20]	65	1			T41	1		T76	1		T77	1
all_levels[21]	81	1			T18	1		T94	1		T108	1
all_levels[22]	47	1			T12	1		T18	1		T41	1
all_levels[23]	56	1			T12	1		T109	2		T110	1
all_levels[24]	60	1			T12	1		T18	1		T42	1
all_levels[25]	40	1			T41	1		T80	1		T111	1
all_levels[26]	50	1			T7	2		T36	2		T88	3
all_levels[27]	30	1			T66	2		T112	1		T110	1
all_levels[28]	37	1			T12	1		T39	2		T113	1
all_levels[29]	35	1			T12	1		T41	1		T39	1
all_levels[30]	36	1			T114	1		T115	1		T116	3
all_levels[31]	29	1			T76	1		T117	3		T118	1
all_levels[32]	43	1			T12	2		T76	1		T94	1
all_levels[33]	25	1			T113	1		T119	1		T120	1
all_levels[34]	25	1			T119	1		T121	1		T122	1
all_levels[35]	19	1			T12	1		T94	1		T123	1
all_levels[36]	14	1			T124	1		T125	1		T126	1
all_levels[37]	20	1			T127	1		T128	1		T129	1
all_levels[38]	22	1			T12	2		T32	1		T115	1
all_levels[39]	23	1			T66	3		T113	1		T32	1
all_levels[40]	21	1			T97	2		T130	1		T131	1
all_levels[41]	8	1			T132	1		T133	1		T134	1
all_levels[42]	17	1			T66	1		T132	1		T96	2
all_levels[43]	8	1			T12	1		T96	1		T135	1
all_levels[44]	16	1			T12	1		T113	2		T136	3
all_levels[45]	17	1			T123	1		T97	1		T98	1
all_levels[46]	19	1			T109	1		T123	1		T126	1
all_levels[47]	10	1			T137	1		T138	1		T139	2
all_levels[48]	10	1			T95	1		T124	1		T130	1
all_levels[49]	15	1			T140	2		T141	1		T142	2
all_levels[50]	4	1			T12	1		T143	1		T144	1
all_levels[51]	8	1			T145	1		T146	1		T147	1
all_levels[52]	15	1			T148	1		T126	1		T149	2
all_levels[53]	9	1			T97	1		T150	2		T151	1
all_levels[54]	4	1			T148	1		T152	1		T153	1
all_levels[55]	12	1			T39	2		T154	4		T138	1
all_levels[56]	5	1			T155	1		T118	1		T156	1
all_levels[57]	6	1			T157	1		T158	1		T44	1
all_levels[58]	3	1			T159	1		T160	1		T161	1
all_levels[59]	17	1			T162	2		T163	1		T164	3
all_levels[60]	5	1			T165	1		T166	1		T167	1
all_levels[61]	5	1			T168	2		T143	1		T169	1
all_levels[62]	6	1			T170	1		T164	1		T149	1
all_levels[63]	5	1			T115	1		T164	1		T171	1
all_levels[64]	85	1			T12	2		T13	2		T112	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28992771

1

T1

169638

T3

115

T4

48

auto[1]

4236

1

T6

40

T7

6

T9

74

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	11	119	91.54	11

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[33]]	[auto[1]]	0	1	1
[all_levels[38]]	[auto[1]]	0	1	1
[all_levels[41]]	[auto[1]]	0	1	1
[all_levels[43]]	[auto[1]]	0	1	1
[all_levels[50]]	[auto[1]]	0	1	1
[all_levels[54]]	[auto[1]]	0	1	1
[all_levels[56] , all_levels[57] , all_levels[58]]	[auto[1]]	--	--	3
[all_levels[62] , all_levels[63]]	[auto[1]]	--	--	2

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	28812591	1			T1	169538		T3	112		T4	41
all_levels[0]	auto[1]	3752	1			T6	40		T7	5		T9	74
all_levels[1]	auto[0]	173248	1			T1	100		T4	7		T7	13
all_levels[1]	auto[1]	77	1			T66	1		T13	2		T93	1
all_levels[2]	auto[0]	1982	1			T7	9		T10	3		T12	6
all_levels[2]	auto[1]	32	1			T157	1		T120	1		T133	1
all_levels[3]	auto[0]	885	1			T7	5		T10	3		T12	8
all_levels[3]	auto[1]	16	1			T42	1		T96	1		T172	4
all_levels[4]	auto[0]	566	1			T7	4		T10	4		T12	1
all_levels[4]	auto[1]	28	1			T96	1		T98	1		T173	3
all_levels[5]	auto[0]	388	1			T3	1		T7	2		T10	1
all_levels[5]	auto[1]	20	1			T113	2		T32	2		T174	1
all_levels[6]	auto[0]	353	1			T3	1		T7	7		T12	2
all_levels[6]	auto[1]	20	1			T7	1		T88	1		T137	2
all_levels[7]	auto[0]	281	1			T3	1		T7	2		T41	1
all_levels[7]	auto[1]	18	1			T76	1		T94	2		T109	2
all_levels[8]	auto[0]	235	1			T7	3		T76	2		T77	1
all_levels[8]	auto[1]	29	1			T174	1		T175	1		T101	5
all_levels[9]	auto[0]	227	1			T12	1		T36	1		T76	2
all_levels[9]	auto[1]	9	1			T113	2		T176	1		T177	2
all_levels[10]	auto[0]	172	1			T12	2		T76	1		T77	2
all_levels[10]	auto[1]	3	1			T178	1		T148	1		T179	1
all_levels[11]	auto[0]	142	1			T7	1		T41	2		T39	1
all_levels[11]	auto[1]	18	1			T76	1		T78	1		T180	1
all_levels[12]	auto[0]	130	1			T41	1		T76	1		T78	1
all_levels[12]	auto[1]	8	1			T96	1		T181	2		T182	1
all_levels[13]	auto[0]	105	1			T10	1		T42	2		T76	3
all_levels[13]	auto[1]	4	1			T121	1		T183	2		T171	1
all_levels[14]	auto[0]	101	1			T10	1		T42	1		T76	1
all_levels[14]	auto[1]	11	1			T165	1		T122	1		T184	2
all_levels[15]	auto[0]	113	1			T12	2		T66	1		T76	2
all_levels[15]	auto[1]	9	1			T185	1		T186	1		T187	1
all_levels[16]	auto[0]	85	1			T76	2		T94	1		T90	1
all_levels[16]	auto[1]	8	1			T130	2		T188	2		T189	2
all_levels[17]	auto[0]	90	1			T18	2		T42	1		T76	1
all_levels[17]	auto[1]	8	1			T114	2		T117	1		T190	1
all_levels[18]	auto[0]	79	1			T12	1		T36	1		T42	1
all_levels[18]	auto[1]	10	1			T180	1		T191	3		T192	2
all_levels[19]	auto[0]	63	1			T18	1		T28	1		T31	2
all_levels[19]	auto[1]	4	1			T193	1		T194	1		T177	1
all_levels[20]	auto[0]	60	1			T41	1		T76	1		T77	1
all_levels[20]	auto[1]	5	1			T114	2		T193	1		T195	2
all_levels[21]	auto[0]	70	1			T18	1		T94	1		T108	1
all_levels[21]	auto[1]	11	1			T149	2		T196	3		T183	5
all_levels[22]	auto[0]	45	1			T12	1		T18	1		T41	1
all_levels[22]	auto[1]	2	1			T120	2		-	-		-	-
all_levels[23]	auto[0]	48	1			T12	1		T109	1		T110	1
all_levels[23]	auto[1]	8	1			T109	1		T154	2		T178	2
all_levels[24]	auto[0]	49	1			T12	1		T18	1		T42	1
all_levels[24]	auto[1]	11	1			T76	3		T178	2		T186	1
all_levels[25]	auto[0]	32	1			T41	1		T80	1		T111	1
all_levels[25]	auto[1]	8	1			T138	3		T197	1		T198	2
all_levels[26]	auto[0]	39	1			T7	2		T36	2		T88	1
all_levels[26]	auto[1]	11	1			T88	2		T199	3		T200	1
all_levels[27]	auto[0]	27	1			T66	1		T112	1		T110	1
all_levels[27]	auto[1]	3	1			T66	1		T201	2		-	-
all_levels[28]	auto[0]	30	1			T12	1		T39	1		T113	1
all_levels[28]	auto[1]	7	1			T39	1		T165	1		T147	3
all_levels[29]	auto[0]	33	1			T12	1		T41	1		T39	1
all_levels[29]	auto[1]	2	1			T183	1		T202	1		-	-
all_levels[30]	auto[0]	33	1			T114	1		T115	1		T116	2
all_levels[30]	auto[1]	3	1			T116	1		T203	2		-	-
all_levels[31]	auto[0]	23	1			T76	1		T117	1		T118	1
all_levels[31]	auto[1]	6	1			T117	2		T190	1		T204	2
all_levels[32]	auto[0]	34	1			T12	2		T76	1		T94	1
all_levels[32]	auto[1]	9	1			T205	3		T96	1		T206	1
all_levels[33]	auto[0]	25	1			T113	1		T119	1		T120	1
all_levels[34]	auto[0]	24	1			T119	1		T121	1		T122	1
all_levels[34]	auto[1]	1	1			T149	1		-	-		-	-
all_levels[35]	auto[0]	17	1			T12	1		T94	1		T123	1
all_levels[35]	auto[1]	2	1			T207	2		-	-		-	-
all_levels[36]	auto[0]	13	1			T124	1		T125	1		T126	1
all_levels[36]	auto[1]	1	1			T208	1		-	-		-	-
all_levels[37]	auto[0]	17	1			T127	1		T128	1		T129	1
all_levels[37]	auto[1]	3	1			T194	1		T209	1		T210	1
all_levels[38]	auto[0]	22	1			T12	2		T32	1		T115	1
all_levels[39]	auto[0]	18	1			T66	1		T113	1		T32	1
all_levels[39]	auto[1]	5	1			T66	2		T211	3		-	-
all_levels[40]	auto[0]	20	1			T97	2		T130	1		T131	1
all_levels[40]	auto[1]	1	1			T166	1		-	-		-	-
all_levels[41]	auto[0]	8	1			T132	1		T133	1		T134	1
all_levels[42]	auto[0]	14	1			T66	1		T132	1		T96	1
all_levels[42]	auto[1]	3	1			T96	1		T182	1		T212	1
all_levels[43]	auto[0]	8	1			T12	1		T96	1		T135	1
all_levels[44]	auto[0]	11	1			T12	1		T113	1		T136	1
all_levels[44]	auto[1]	5	1			T113	1		T136	2		T213	2
all_levels[45]	auto[0]	15	1			T123	1		T97	1		T98	1
all_levels[45]	auto[1]	2	1			T214	2		-	-		-	-
all_levels[46]	auto[0]	14	1			T109	1		T123	1		T126	1
all_levels[46]	auto[1]	5	1			T215	2		T216	1		T207	2
all_levels[47]	auto[0]	8	1			T137	1		T138	1		T139	1
all_levels[47]	auto[1]	2	1			T139	1		T217	1		-	-
all_levels[48]	auto[0]	9	1			T95	1		T124	1		T130	1
all_levels[48]	auto[1]	1	1			T218	1		-	-		-	-
all_levels[49]	auto[0]	10	1			T140	1		T141	1		T142	1
all_levels[49]	auto[1]	5	1			T140	1		T142	1		T187	2
all_levels[50]	auto[0]	4	1			T12	1		T143	1		T144	1
all_levels[51]	auto[0]	6	1			T145	1		T146	1		T147	1
all_levels[51]	auto[1]	2	1			T219	2		-	-		-	-
all_levels[52]	auto[0]	12	1			T148	1		T126	1		T149	1
all_levels[52]	auto[1]	3	1			T149	1		T220	1		T221	1
all_levels[53]	auto[0]	7	1			T97	1		T150	1		T151	1
all_levels[53]	auto[1]	2	1			T150	1		T222	1		-	-
all_levels[54]	auto[0]	4	1			T148	1		T152	1		T153	1
all_levels[55]	auto[0]	5	1			T39	1		T154	1		T138	1
all_levels[55]	auto[1]	7	1			T39	1		T154	3		T223	1
all_levels[56]	auto[0]	5	1			T155	1		T118	1		T156	1
all_levels[57]	auto[0]	6	1			T157	1		T158	1		T44	1
all_levels[58]	auto[0]	3	1			T159	1		T160	1		T161	1
all_levels[59]	auto[0]	14	1			T162	1		T163	1		T164	1
all_levels[59]	auto[1]	3	1			T162	1		T164	2		-	-
all_levels[60]	auto[0]	4	1			T165	1		T166	1		T167	1
all_levels[60]	auto[1]	1	1			T224	1		-	-		-	-
all_levels[61]	auto[0]	4	1			T168	1		T143	1		T169	1
all_levels[61]	auto[1]	1	1			T168	1		-	-		-	-
all_levels[62]	auto[0]	6	1			T170	1		T164	1		T149	1
all_levels[63]	auto[0]	5	1			T115	1		T164	1		T171	1
all_levels[64]	auto[0]	74	1			T12	2		T13	2		T112	1
all_levels[64]	auto[1]	11	1			T186	1		T138	1		T225	1