Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	101049	1			T1	529		T2	2		T3	47
all_pins[1]	101049	1			T1	529		T2	2		T3	47
all_pins[2]	101049	1			T1	529		T2	2		T3	47
all_pins[3]	101049	1			T1	529		T2	2		T3	47
all_pins[4]	101049	1			T1	529		T2	2		T3	47
all_pins[5]	101049	1			T1	529		T2	2		T3	47
all_pins[6]	101049	1			T1	529		T2	2		T3	47
all_pins[7]	101049	1			T1	529		T2	2		T3	47
all_pins[8]	101049	1			T1	529		T2	2		T3	47

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	865635	1			T1	4504		T2	18		T3	421
values[0x1]	43806	1			T1	257		T3	2		T4	3
transitions[0x0=>0x1]	34972	1			T1	161		T3	2		T4	3
transitions[0x1=>0x0]	34787	1			T1	161		T3	1		T4	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	79056	1			T1	433		T2	2		T3	45
all_pins[0]	values[0x1]	21993	1			T1	96		T3	2		T4	3
all_pins[0]	transitions[0x0=>0x1]	21570	1			T1	96		T3	2		T4	3
all_pins[0]	transitions[0x1=>0x0]	923	1			T6	7		T9	15		T12	5
all_pins[1]	values[0x0]	99703	1			T1	529		T2	2		T3	47
all_pins[1]	values[0x1]	1346	1			T6	7		T9	16		T12	5
all_pins[1]	transitions[0x0=>0x1]	1274	1			T6	7		T9	16		T12	5
all_pins[1]	transitions[0x1=>0x0]	2181	1			T1	2		T6	1		T7	8
all_pins[2]	values[0x0]	98796	1			T1	527		T2	2		T3	47
all_pins[2]	values[0x1]	2253	1			T1	2		T6	1		T7	8
all_pins[2]	transitions[0x0=>0x1]	2204	1			T1	2		T6	1		T7	8
all_pins[2]	transitions[0x1=>0x0]	231	1			T9	5		T14	4		T15	3
all_pins[3]	values[0x0]	100769	1			T1	529		T2	2		T3	47
all_pins[3]	values[0x1]	280	1			T9	5		T14	4		T15	3
all_pins[3]	transitions[0x0=>0x1]	250	1			T9	5		T14	4		T15	3
all_pins[3]	transitions[0x1=>0x0]	378	1			T9	5		T14	1		T29	4
all_pins[4]	values[0x0]	100641	1			T1	529		T2	2		T3	47
all_pins[4]	values[0x1]	408	1			T9	5		T14	1		T29	6
all_pins[4]	transitions[0x0=>0x1]	346	1			T9	4		T14	1		T29	4
all_pins[4]	transitions[0x1=>0x0]	130	1			T9	2		T15	1		T29	1
all_pins[5]	values[0x0]	100857	1			T1	529		T2	2		T3	47
all_pins[5]	values[0x1]	192	1			T9	3		T15	1		T29	3
all_pins[5]	transitions[0x0=>0x1]	155	1			T9	3		T15	1		T29	3
all_pins[5]	transitions[0x1=>0x0]	683	1			T9	6		T12	6		T35	2
all_pins[6]	values[0x0]	100329	1			T1	529		T2	2		T3	47
all_pins[6]	values[0x1]	720	1			T9	6		T12	6		T35	2
all_pins[6]	transitions[0x0=>0x1]	680	1			T9	6		T12	6		T35	2
all_pins[6]	transitions[0x1=>0x0]	265	1			T6	1		T9	5		T14	2
all_pins[7]	values[0x0]	100744	1			T1	529		T2	2		T3	47
all_pins[7]	values[0x1]	305	1			T6	1		T9	5		T14	2
all_pins[7]	transitions[0x0=>0x1]	167	1			T9	3		T14	2		T29	3
all_pins[7]	transitions[0x1=>0x0]	16171	1			T1	159		T6	82		T7	10
all_pins[8]	values[0x0]	84740	1			T1	370		T2	2		T3	47
all_pins[8]	values[0x1]	16309	1			T1	159		T6	83		T7	10
all_pins[8]	transitions[0x0=>0x1]	8326	1			T1	63		T6	82		T7	9
all_pins[8]	transitions[0x1=>0x0]	13825	1			T3	1		T4	3		T9	59