Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	7782492	1			T1	104027		T3	98		T4	5
all_levels[1]	1686016	1			T1	529		T3	6		T4	2
all_levels[2]	283060	1			T1	528		T3	2		T4	2
all_levels[3]	290131	1			T1	529		T3	4		T7	1
all_levels[4]	345703	1			T1	515		T3	1		T7	2
all_levels[5]	208649	1			T1	529		T7	2		T9	5511
all_levels[6]	449206	1			T1	528		T3	1		T7	2
all_levels[7]	318132	1			T1	528		T3	3		T7	1
all_levels[8]	232609	1			T1	524		T9	5510		T11	42
all_levels[9]	316631	1			T1	529		T9	5512		T11	39
all_levels[10]	226633	1			T1	528		T7	1		T9	5508
all_levels[11]	281828	1			T1	526		T7	1		T9	5516
all_levels[12]	200115	1			T1	527		T9	5492		T11	36
all_levels[13]	226562	1			T1	521		T7	5		T9	5401
all_levels[14]	512140	1			T1	520		T9	3535		T11	31
all_levels[15]	183841	1			T1	528		T6	5		T9	3557
all_levels[16]	296484	1			T1	520		T6	413		T9	7748
all_levels[17]	167195	1			T1	516		T7	1		T9	3553
all_levels[18]	163171	1			T1	528		T9	3545		T11	35
all_levels[19]	350213	1			T1	529		T9	3532		T11	43
all_levels[20]	203520	1			T1	528		T9	3546		T11	31
all_levels[21]	323592	1			T1	528		T9	3546		T11	43
all_levels[22]	433758	1			T1	523		T9	3547		T11	46
all_levels[23]	345511	1			T1	528		T9	102400		T11	33
all_levels[24]	187171	1			T1	528		T9	21031		T11	43
all_levels[25]	247032	1			T1	528		T4	1		T9	3018
all_levels[26]	547572	1			T1	509		T4	3		T9	3025
all_levels[27]	431434	1			T1	528		T4	4		T9	3016
all_levels[28]	660186	1			T1	529		T4	2		T9	3016
all_levels[29]	189935	1			T1	36502		T4	5		T9	3023
all_levels[30]	494333	1			T1	527		T4	5		T9	3013
all_levels[31]	458132	1			T1	1205		T4	6		T9	5176
all_levels[32]	9953763	1			T1	12667		T4	13		T7	6

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28992771

1

T1

169638

T3

115

T4

48

auto[1]

3979

1

T1

1

T6

36

T7

7

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	7780311	1			T1	104027		T3	98		T4	5
all_levels[0]	auto[1]	2181	1			T6	32		T7	4		T9	23
all_levels[1]	auto[0]	1685726	1			T1	529		T3	6		T4	2
all_levels[1]	auto[1]	290	1			T9	12		T36	1		T229	1
all_levels[2]	auto[0]	283024	1			T1	528		T3	2		T4	2
all_levels[2]	auto[1]	36	1			T7	1		T39	1		T77	4
all_levels[3]	auto[0]	290003	1			T1	529		T3	4		T7	1
all_levels[3]	auto[1]	128	1			T9	31		T37	1		T39	2
all_levels[4]	auto[0]	345679	1			T1	515		T3	1		T7	2
all_levels[4]	auto[1]	24	1			T255	2		T315	1		T316	1
all_levels[5]	auto[0]	208619	1			T1	529		T7	2		T9	5511
all_levels[5]	auto[1]	30	1			T13	2		T39	1		T81	1
all_levels[6]	auto[0]	449172	1			T1	528		T3	1		T7	2
all_levels[6]	auto[1]	34	1			T36	3		T254	1		T98	3
all_levels[7]	auto[0]	318019	1			T1	528		T3	3		T7	1
all_levels[7]	auto[1]	113	1			T93	1		T94	1		T108	2
all_levels[8]	auto[0]	232587	1			T1	524		T9	5510		T11	42
all_levels[8]	auto[1]	22	1			T93	2		T94	1		T199	1
all_levels[9]	auto[0]	316593	1			T1	529		T9	5512		T11	39
all_levels[9]	auto[1]	38	1			T241	1		T137	2		T180	1
all_levels[10]	auto[0]	226608	1			T1	528		T7	1		T9	5508
all_levels[10]	auto[1]	25	1			T76	1		T30	1		T173	4
all_levels[11]	auto[0]	281803	1			T1	526		T7	1		T9	5516
all_levels[11]	auto[1]	25	1			T114	2		T127	2		T180	1
all_levels[12]	auto[0]	200085	1			T1	527		T9	5492		T11	36
all_levels[12]	auto[1]	30	1			T113	1		T235	1		T239	1
all_levels[13]	auto[0]	226536	1			T1	521		T7	5		T9	5401
all_levels[13]	auto[1]	26	1			T108	1		T279	1		T317	1
all_levels[14]	auto[0]	512114	1			T1	520		T9	3535		T11	31
all_levels[14]	auto[1]	26	1			T88	1		T174	1		T101	4
all_levels[15]	auto[0]	183690	1			T1	528		T6	1		T9	3551
all_levels[15]	auto[1]	151	1			T6	4		T9	6		T14	4
all_levels[16]	auto[0]	296462	1			T1	520		T6	413		T9	7748
all_levels[16]	auto[1]	22	1			T98	1		T318	1		T319	1
all_levels[17]	auto[0]	167166	1			T1	516		T7	1		T9	3553
all_levels[17]	auto[1]	29	1			T268	2		T127	2		T154	2
all_levels[18]	auto[0]	163150	1			T1	528		T9	3545		T11	35
all_levels[18]	auto[1]	21	1			T77	1		T178	2		T148	2
all_levels[19]	auto[0]	350188	1			T1	529		T9	3532		T11	43
all_levels[19]	auto[1]	25	1			T36	1		T205	1		T179	2
all_levels[20]	auto[0]	203512	1			T1	528		T9	3546		T11	31
all_levels[20]	auto[1]	8	1			T94	1		T320	1		T166	2
all_levels[21]	auto[0]	323573	1			T1	528		T9	3546		T11	43
all_levels[21]	auto[1]	19	1			T114	2		T164	1		T146	2
all_levels[22]	auto[0]	433744	1			T1	523		T9	3547		T11	46
all_levels[22]	auto[1]	14	1			T13	1		T109	1		T120	2
all_levels[23]	auto[0]	345489	1			T1	528		T9	102400		T11	33
all_levels[23]	auto[1]	22	1			T66	1		T150	2		T185	1
all_levels[24]	auto[0]	187163	1			T1	528		T9	21031		T11	43
all_levels[24]	auto[1]	8	1			T279	1		T83	3		T190	1
all_levels[25]	auto[0]	247022	1			T1	528		T4	1		T9	3018
all_levels[25]	auto[1]	10	1			T92	1		T121	1		T321	1
all_levels[26]	auto[0]	547554	1			T1	509		T4	3		T9	3025
all_levels[26]	auto[1]	18	1			T256	1		T184	2		T322	4
all_levels[27]	auto[0]	431414	1			T1	528		T4	4		T9	3016
all_levels[27]	auto[1]	20	1			T76	1		T268	2		T134	1
all_levels[28]	auto[0]	660175	1			T1	529		T4	2		T9	3016
all_levels[28]	auto[1]	11	1			T157	1		T114	2		T235	1
all_levels[29]	auto[0]	189919	1			T1	36501		T4	5		T9	3023
all_levels[29]	auto[1]	16	1			T1	1		T109	3		T125	4
all_levels[30]	auto[0]	494316	1			T1	527		T4	5		T9	3013
all_levels[30]	auto[1]	17	1			T205	1		T315	2		T323	3
all_levels[31]	auto[0]	458117	1			T1	1205		T4	6		T9	5176
all_levels[31]	auto[1]	15	1			T174	2		T324	1		T260	1
all_levels[32]	auto[0]	9953238	1			T1	12667		T4	13		T7	4
all_levels[32]	auto[1]	525	1			T7	2		T10	1		T36	2