Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	618	1			T9	4		T15	4		T29	11
all_values[1]	618	1			T9	4		T15	4		T29	11
all_values[2]	618	1			T9	4		T15	4		T29	11
all_values[3]	618	1			T9	4		T15	4		T29	11
all_values[4]	618	1			T9	4		T15	4		T29	11
all_values[5]	618	1			T9	4		T15	4		T29	11
all_values[6]	618	1			T9	4		T15	4		T29	11
all_values[7]	618	1			T9	4		T15	4		T29	11
all_values[8]	618	1			T9	4		T15	4		T29	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2927

1

T9

20

T15

18

T29

37

auto[1]

2635

1

T9

16

T15

18

T29

62

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1803

1

T9

12

T15

15

T29

35

auto[1]

3759

1

T9

24

T15

21

T29

64

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3250

1

T9

21

T15

25

T29

60

auto[1]

2312

1

T9

15

T15

11

T29

39

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	173	1			T9	2		T15	1		T29	4
all_values[0]	auto[0]	auto[1]	auto[1]	183	1			T9	1		T15	2		T29	4
all_values[0]	auto[1]	auto[0]	auto[1]	157	1			T9	1		T29	2		T92	1
all_values[0]	auto[1]	auto[1]	auto[1]	105	1			T15	1		T29	1		T80	1
all_values[1]	auto[0]	auto[0]	auto[0]	201	1			T9	2		T29	3		T92	4
all_values[1]	auto[0]	auto[1]	auto[0]	174	1			T15	2		T29	5		T92	1
all_values[1]	auto[1]	auto[0]	auto[1]	126	1			T9	1		T15	2		T92	1
all_values[1]	auto[1]	auto[1]	auto[1]	117	1			T9	1		T29	3		T92	1
all_values[2]	auto[0]	auto[0]	auto[0]	117	1			T9	1		T15	3		T29	2
all_values[2]	auto[0]	auto[0]	auto[1]	55	1			T92	1		T43	3		T81	2
all_values[2]	auto[0]	auto[1]	auto[0]	118	1			T29	1		T43	1		T80	3
all_values[2]	auto[0]	auto[1]	auto[1]	64	1			T9	1		T29	2		T92	1
all_values[2]	auto[1]	auto[0]	auto[1]	141	1			T29	1		T92	3		T43	3
all_values[2]	auto[1]	auto[1]	auto[1]	123	1			T9	2		T15	1		T29	5
all_values[3]	auto[0]	auto[0]	auto[0]	133	1			T9	2		T29	4		T92	1
all_values[3]	auto[0]	auto[0]	auto[1]	55	1			T9	1		T29	1		T80	1
all_values[3]	auto[0]	auto[1]	auto[0]	109	1			T92	2		T43	2		T101	1
all_values[3]	auto[0]	auto[1]	auto[1]	70	1			T15	2		T29	1		T92	1
all_values[3]	auto[1]	auto[0]	auto[1]	141	1			T9	1		T15	1		T29	2
all_values[3]	auto[1]	auto[1]	auto[1]	110	1			T15	1		T29	3		T92	1
all_values[4]	auto[0]	auto[0]	auto[0]	118	1			T15	1		T92	1		T43	1
all_values[4]	auto[0]	auto[0]	auto[1]	55	1			T92	1		T43	1		T101	1
all_values[4]	auto[0]	auto[1]	auto[0]	108	1			T9	3		T15	2		T29	1
all_values[4]	auto[0]	auto[1]	auto[1]	66	1			T29	4		T92	1		T43	1
all_values[4]	auto[1]	auto[0]	auto[1]	152	1			T9	1		T29	3		T92	3
all_values[4]	auto[1]	auto[1]	auto[1]	119	1			T15	1		T29	3		T43	1
all_values[5]	auto[0]	auto[0]	auto[0]	134	1			T15	3		T43	6		T80	3
all_values[5]	auto[0]	auto[0]	auto[1]	60	1			T9	2		T29	1		T102	1
all_values[5]	auto[0]	auto[1]	auto[0]	110	1			T29	7		T92	2		T43	3
all_values[5]	auto[0]	auto[1]	auto[1]	58	1			T29	1		T92	2		T80	1
all_values[5]	auto[1]	auto[0]	auto[1]	142	1			T29	1		T92	2		T43	2
all_values[5]	auto[1]	auto[1]	auto[1]	114	1			T9	2		T15	1		T29	1
all_values[6]	auto[0]	auto[0]	auto[0]	115	1			T9	1		T29	3		T43	3
all_values[6]	auto[0]	auto[0]	auto[1]	62	1			T9	1		T29	1		T92	1
all_values[6]	auto[0]	auto[1]	auto[0]	124	1			T9	1		T15	2		T29	4
all_values[6]	auto[0]	auto[1]	auto[1]	65	1			T29	1		T43	2		T80	2
all_values[6]	auto[1]	auto[0]	auto[1]	138	1			T9	1		T15	2		T92	3
all_values[6]	auto[1]	auto[1]	auto[1]	114	1			T29	2		T92	3		T43	3
all_values[7]	auto[0]	auto[0]	auto[0]	132	1			T15	2		T43	5		T80	3
all_values[7]	auto[0]	auto[0]	auto[1]	56	1			T15	1		T92	1		T83	1
all_values[7]	auto[0]	auto[1]	auto[0]	110	1			T9	2		T29	5		T43	1
all_values[7]	auto[0]	auto[1]	auto[1]	66	1			T29	1		T92	1		T43	3
all_values[7]	auto[1]	auto[0]	auto[1]	125	1			T15	1		T29	3		T92	2
all_values[7]	auto[1]	auto[1]	auto[1]	129	1			T9	2		T29	2		T92	3
all_values[8]	auto[0]	auto[0]	auto[1]	195	1			T9	1		T15	1		T29	2
all_values[8]	auto[0]	auto[1]	auto[1]	164	1			T15	3		T29	2		T92	1
all_values[8]	auto[1]	auto[0]	auto[1]	144	1			T9	2		T29	4		T92	2
all_values[8]	auto[1]	auto[1]	auto[1]	115	1			T9	1		T29	3		T92	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal