Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.11 99.10 97.65 100.00 98.38 100.00 99.53


Total test records in report: 1236
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T203 /workspace/coverage/default/91.uart_fifo_reset.3390131301 Jun 23 05:44:16 PM PDT 24 Jun 23 05:44:36 PM PDT 24 168283401552 ps
T1033 /workspace/coverage/default/133.uart_fifo_reset.2065975974 Jun 23 05:44:31 PM PDT 24 Jun 23 05:45:17 PM PDT 24 29654207165 ps
T1034 /workspace/coverage/default/10.uart_smoke.142159715 Jun 23 05:40:17 PM PDT 24 Jun 23 05:40:18 PM PDT 24 103208322 ps
T1035 /workspace/coverage/default/3.uart_alert_test.225117512 Jun 23 05:40:03 PM PDT 24 Jun 23 05:40:04 PM PDT 24 11219469 ps
T1036 /workspace/coverage/default/44.uart_fifo_full.390305101 Jun 23 05:43:28 PM PDT 24 Jun 23 05:43:47 PM PDT 24 22713895165 ps
T1037 /workspace/coverage/default/12.uart_stress_all_with_rand_reset.1694811827 Jun 23 05:40:29 PM PDT 24 Jun 23 05:47:46 PM PDT 24 64319581990 ps
T1038 /workspace/coverage/default/7.uart_perf.3002168385 Jun 23 05:40:13 PM PDT 24 Jun 23 05:44:02 PM PDT 24 15825532807 ps
T1039 /workspace/coverage/default/268.uart_fifo_reset.2380336023 Jun 23 05:45:22 PM PDT 24 Jun 23 05:45:39 PM PDT 24 105238012144 ps
T1040 /workspace/coverage/default/21.uart_fifo_reset.440853367 Jun 23 05:41:21 PM PDT 24 Jun 23 05:41:43 PM PDT 24 41002494206 ps
T1041 /workspace/coverage/default/5.uart_long_xfer_wo_dly.2195972043 Jun 23 05:40:01 PM PDT 24 Jun 23 05:52:03 PM PDT 24 94739333061 ps
T1042 /workspace/coverage/default/123.uart_fifo_reset.1865650313 Jun 23 05:44:25 PM PDT 24 Jun 23 05:44:36 PM PDT 24 6211824571 ps
T1043 /workspace/coverage/default/34.uart_rx_start_bit_filter.1020311247 Jun 23 05:42:25 PM PDT 24 Jun 23 05:42:30 PM PDT 24 4346193565 ps
T1044 /workspace/coverage/default/10.uart_rx_parity_err.2503738521 Jun 23 05:40:18 PM PDT 24 Jun 23 05:41:12 PM PDT 24 31219365573 ps
T1045 /workspace/coverage/default/42.uart_rx_start_bit_filter.3091050386 Jun 23 05:43:17 PM PDT 24 Jun 23 05:43:18 PM PDT 24 701449179 ps
T1046 /workspace/coverage/default/15.uart_smoke.2806062762 Jun 23 05:40:44 PM PDT 24 Jun 23 05:40:47 PM PDT 24 272957461 ps
T1047 /workspace/coverage/default/177.uart_fifo_reset.3801739954 Jun 23 05:44:50 PM PDT 24 Jun 23 05:45:49 PM PDT 24 22139122008 ps
T1048 /workspace/coverage/default/41.uart_long_xfer_wo_dly.2303983073 Jun 23 05:43:19 PM PDT 24 Jun 23 05:45:07 PM PDT 24 67043959311 ps
T1049 /workspace/coverage/default/266.uart_fifo_reset.2017956386 Jun 23 05:45:24 PM PDT 24 Jun 23 05:46:02 PM PDT 24 20508802908 ps
T1050 /workspace/coverage/default/14.uart_fifo_overflow.2209708012 Jun 23 05:40:40 PM PDT 24 Jun 23 05:41:02 PM PDT 24 262552224570 ps
T1051 /workspace/coverage/default/44.uart_fifo_reset.2584733208 Jun 23 05:43:27 PM PDT 24 Jun 23 05:43:49 PM PDT 24 14390467507 ps
T1052 /workspace/coverage/default/34.uart_stress_all_with_rand_reset.2622337122 Jun 23 05:42:24 PM PDT 24 Jun 23 06:01:45 PM PDT 24 81891312506 ps
T1053 /workspace/coverage/default/278.uart_fifo_reset.3561950782 Jun 23 05:45:28 PM PDT 24 Jun 23 05:47:47 PM PDT 24 107335067585 ps
T1054 /workspace/coverage/default/38.uart_rx_parity_err.2858734518 Jun 23 05:42:45 PM PDT 24 Jun 23 05:43:25 PM PDT 24 147342833459 ps
T1055 /workspace/coverage/default/55.uart_stress_all_with_rand_reset.1302817526 Jun 23 05:44:02 PM PDT 24 Jun 23 05:45:50 PM PDT 24 10294430164 ps
T1056 /workspace/coverage/default/210.uart_fifo_reset.3266733837 Jun 23 05:45:03 PM PDT 24 Jun 23 05:45:36 PM PDT 24 95654155929 ps
T1057 /workspace/coverage/default/5.uart_stress_all.2690258284 Jun 23 05:40:03 PM PDT 24 Jun 23 05:45:12 PM PDT 24 155068421464 ps
T1058 /workspace/coverage/default/0.uart_stress_all.3500423202 Jun 23 05:39:44 PM PDT 24 Jun 23 05:41:38 PM PDT 24 243297375547 ps
T1059 /workspace/coverage/default/42.uart_tx_rx.2193894401 Jun 23 05:43:20 PM PDT 24 Jun 23 05:46:36 PM PDT 24 96914419171 ps
T1060 /workspace/coverage/default/132.uart_fifo_reset.2006318594 Jun 23 05:44:29 PM PDT 24 Jun 23 05:45:14 PM PDT 24 96406411940 ps
T1061 /workspace/coverage/default/37.uart_tx_ovrd.1425279626 Jun 23 05:42:42 PM PDT 24 Jun 23 05:42:44 PM PDT 24 2412040590 ps
T201 /workspace/coverage/default/149.uart_fifo_reset.1038674250 Jun 23 05:44:34 PM PDT 24 Jun 23 05:45:20 PM PDT 24 164994235844 ps
T1062 /workspace/coverage/default/8.uart_rx_parity_err.757717694 Jun 23 05:40:13 PM PDT 24 Jun 23 05:40:18 PM PDT 24 41236965557 ps
T1063 /workspace/coverage/default/15.uart_long_xfer_wo_dly.1690761497 Jun 23 05:40:46 PM PDT 24 Jun 23 05:44:17 PM PDT 24 65712656238 ps
T1064 /workspace/coverage/default/20.uart_rx_start_bit_filter.4180566461 Jun 23 05:41:16 PM PDT 24 Jun 23 05:41:18 PM PDT 24 4866309468 ps
T1065 /workspace/coverage/default/228.uart_fifo_reset.1659547636 Jun 23 05:45:11 PM PDT 24 Jun 23 05:45:53 PM PDT 24 25484282149 ps
T1066 /workspace/coverage/default/6.uart_stress_all.4246723886 Jun 23 05:40:06 PM PDT 24 Jun 23 05:42:10 PM PDT 24 309480447982 ps
T1067 /workspace/coverage/default/35.uart_fifo_full.292476723 Jun 23 05:42:29 PM PDT 24 Jun 23 05:43:26 PM PDT 24 59619134188 ps
T1068 /workspace/coverage/default/39.uart_rx_oversample.1190577886 Jun 23 05:42:57 PM PDT 24 Jun 23 05:43:44 PM PDT 24 5496841898 ps
T1069 /workspace/coverage/default/6.uart_fifo_overflow.261059522 Jun 23 05:40:07 PM PDT 24 Jun 23 05:41:49 PM PDT 24 64737917738 ps
T1070 /workspace/coverage/default/45.uart_smoke.3627323120 Jun 23 05:43:29 PM PDT 24 Jun 23 05:43:30 PM PDT 24 115672113 ps
T167 /workspace/coverage/default/12.uart_fifo_reset.2604636226 Jun 23 05:40:25 PM PDT 24 Jun 23 05:41:11 PM PDT 24 118622869618 ps
T1071 /workspace/coverage/default/271.uart_fifo_reset.399096599 Jun 23 05:45:26 PM PDT 24 Jun 23 05:49:00 PM PDT 24 312539296583 ps
T1072 /workspace/coverage/default/5.uart_perf.4104430150 Jun 23 05:40:02 PM PDT 24 Jun 23 05:46:18 PM PDT 24 13871859880 ps
T1073 /workspace/coverage/default/24.uart_alert_test.4024047329 Jun 23 05:41:38 PM PDT 24 Jun 23 05:41:39 PM PDT 24 25264756 ps
T1074 /workspace/coverage/default/15.uart_rx_start_bit_filter.2609995101 Jun 23 05:40:46 PM PDT 24 Jun 23 05:41:24 PM PDT 24 52317080236 ps
T1075 /workspace/coverage/default/43.uart_perf.435775392 Jun 23 05:43:27 PM PDT 24 Jun 23 05:48:34 PM PDT 24 24495660344 ps
T1076 /workspace/coverage/default/3.uart_fifo_full.544735453 Jun 23 05:39:54 PM PDT 24 Jun 23 05:40:26 PM PDT 24 32293262019 ps
T1077 /workspace/coverage/default/30.uart_stress_all.2863288569 Jun 23 05:42:06 PM PDT 24 Jun 23 05:46:04 PM PDT 24 238266545573 ps
T1078 /workspace/coverage/default/33.uart_tx_ovrd.3311635001 Jun 23 05:42:16 PM PDT 24 Jun 23 05:42:19 PM PDT 24 3769146133 ps
T1079 /workspace/coverage/default/7.uart_rx_parity_err.4289885630 Jun 23 05:40:19 PM PDT 24 Jun 23 05:40:42 PM PDT 24 30736160909 ps
T224 /workspace/coverage/default/42.uart_fifo_reset.488131163 Jun 23 05:43:19 PM PDT 24 Jun 23 05:43:39 PM PDT 24 50489926919 ps
T1080 /workspace/coverage/default/18.uart_fifo_full.3225501657 Jun 23 05:40:58 PM PDT 24 Jun 23 05:43:53 PM PDT 24 108827149274 ps
T1081 /workspace/coverage/default/126.uart_fifo_reset.1601934212 Jun 23 05:44:30 PM PDT 24 Jun 23 05:44:48 PM PDT 24 39221926876 ps
T1082 /workspace/coverage/default/16.uart_fifo_reset.3213162092 Jun 23 05:40:49 PM PDT 24 Jun 23 05:41:39 PM PDT 24 34742359378 ps
T1083 /workspace/coverage/default/151.uart_fifo_reset.3709692211 Jun 23 05:44:34 PM PDT 24 Jun 23 05:46:41 PM PDT 24 84602659780 ps
T1084 /workspace/coverage/default/19.uart_tx_rx.1262813277 Jun 23 05:41:04 PM PDT 24 Jun 23 05:41:21 PM PDT 24 19696402848 ps
T1085 /workspace/coverage/default/4.uart_rx_parity_err.2156801646 Jun 23 05:40:00 PM PDT 24 Jun 23 05:41:18 PM PDT 24 45806841699 ps
T1086 /workspace/coverage/default/0.uart_tx_ovrd.2993502536 Jun 23 05:39:46 PM PDT 24 Jun 23 05:39:48 PM PDT 24 414608064 ps
T1087 /workspace/coverage/default/236.uart_fifo_reset.242880608 Jun 23 05:45:12 PM PDT 24 Jun 23 05:45:47 PM PDT 24 20369699272 ps
T1088 /workspace/coverage/default/46.uart_rx_start_bit_filter.69427677 Jun 23 05:43:40 PM PDT 24 Jun 23 05:43:49 PM PDT 24 5180413855 ps
T1089 /workspace/coverage/default/6.uart_loopback.1515898719 Jun 23 05:40:06 PM PDT 24 Jun 23 05:40:09 PM PDT 24 4152454298 ps
T1090 /workspace/coverage/default/45.uart_stress_all_with_rand_reset.3003706816 Jun 23 05:43:41 PM PDT 24 Jun 23 05:47:08 PM PDT 24 75218495595 ps
T1091 /workspace/coverage/default/27.uart_rx_parity_err.2348459118 Jun 23 05:41:51 PM PDT 24 Jun 23 05:42:14 PM PDT 24 16682316547 ps
T1092 /workspace/coverage/default/6.uart_rx_parity_err.1594719469 Jun 23 05:40:07 PM PDT 24 Jun 23 05:40:57 PM PDT 24 114514853532 ps
T1093 /workspace/coverage/default/43.uart_stress_all.1081155566 Jun 23 05:43:28 PM PDT 24 Jun 23 05:46:19 PM PDT 24 180174414513 ps
T1094 /workspace/coverage/default/32.uart_fifo_reset.12179351 Jun 23 05:42:12 PM PDT 24 Jun 23 05:42:35 PM PDT 24 62423333010 ps
T1095 /workspace/coverage/default/13.uart_tx_ovrd.3396856001 Jun 23 05:40:37 PM PDT 24 Jun 23 05:40:40 PM PDT 24 745398025 ps
T1096 /workspace/coverage/default/84.uart_fifo_reset.416062612 Jun 23 05:44:13 PM PDT 24 Jun 23 05:45:13 PM PDT 24 117249155539 ps
T1097 /workspace/coverage/default/40.uart_rx_start_bit_filter.779330292 Jun 23 05:43:10 PM PDT 24 Jun 23 05:43:14 PM PDT 24 6909659965 ps
T1098 /workspace/coverage/default/0.uart_fifo_reset.3712768658 Jun 23 05:39:47 PM PDT 24 Jun 23 05:40:13 PM PDT 24 158306605354 ps
T1099 /workspace/coverage/default/9.uart_fifo_reset.2791362056 Jun 23 05:40:19 PM PDT 24 Jun 23 05:40:47 PM PDT 24 17618215554 ps
T59 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.3592550367 Jun 23 05:33:25 PM PDT 24 Jun 23 05:33:26 PM PDT 24 31360357 ps
T1100 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1091076 Jun 23 05:33:11 PM PDT 24 Jun 23 05:33:12 PM PDT 24 16348595 ps
T1101 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.578291083 Jun 23 05:33:05 PM PDT 24 Jun 23 05:33:06 PM PDT 24 84533729 ps
T1102 /workspace/coverage/cover_reg_top/12.uart_tl_errors.1181536775 Jun 23 05:33:17 PM PDT 24 Jun 23 05:33:19 PM PDT 24 209836125 ps
T1103 /workspace/coverage/cover_reg_top/15.uart_intr_test.2289987632 Jun 23 05:33:22 PM PDT 24 Jun 23 05:33:23 PM PDT 24 34347021 ps
T50 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1145574378 Jun 23 05:32:30 PM PDT 24 Jun 23 05:32:31 PM PDT 24 23316744 ps
T1104 /workspace/coverage/cover_reg_top/8.uart_tl_errors.1654176770 Jun 23 05:33:06 PM PDT 24 Jun 23 05:33:09 PM PDT 24 42055057 ps
T60 /workspace/coverage/cover_reg_top/16.uart_csr_rw.4276766946 Jun 23 05:33:23 PM PDT 24 Jun 23 05:33:24 PM PDT 24 79992147 ps
T1105 /workspace/coverage/cover_reg_top/30.uart_intr_test.2133560975 Jun 23 05:33:29 PM PDT 24 Jun 23 05:33:30 PM PDT 24 56626808 ps
T1106 /workspace/coverage/cover_reg_top/0.uart_tl_errors.1096838805 Jun 23 05:32:26 PM PDT 24 Jun 23 05:32:28 PM PDT 24 71814880 ps
T1107 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3733417103 Jun 23 05:33:17 PM PDT 24 Jun 23 05:33:19 PM PDT 24 194942180 ps
T61 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3297652416 Jun 23 05:33:31 PM PDT 24 Jun 23 05:33:32 PM PDT 24 14378639 ps
T1108 /workspace/coverage/cover_reg_top/13.uart_intr_test.1137014396 Jun 23 05:33:17 PM PDT 24 Jun 23 05:33:18 PM PDT 24 16638830 ps
T1109 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3085518632 Jun 23 05:33:27 PM PDT 24 Jun 23 05:33:29 PM PDT 24 83281842 ps
T1110 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2932877969 Jun 23 05:32:39 PM PDT 24 Jun 23 05:32:41 PM PDT 24 91409913 ps
T62 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.3287207453 Jun 23 05:33:22 PM PDT 24 Jun 23 05:33:23 PM PDT 24 53139907 ps
T1111 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.4051839237 Jun 23 05:33:17 PM PDT 24 Jun 23 05:33:18 PM PDT 24 49360802 ps
T1112 /workspace/coverage/cover_reg_top/31.uart_intr_test.2770321517 Jun 23 05:33:32 PM PDT 24 Jun 23 05:33:34 PM PDT 24 24834012 ps
T1113 /workspace/coverage/cover_reg_top/19.uart_intr_test.3179476401 Jun 23 05:33:28 PM PDT 24 Jun 23 05:33:29 PM PDT 24 70825729 ps
T1114 /workspace/coverage/cover_reg_top/8.uart_intr_test.1364018589 Jun 23 05:33:09 PM PDT 24 Jun 23 05:33:10 PM PDT 24 41832419 ps
T63 /workspace/coverage/cover_reg_top/0.uart_csr_rw.4276749486 Jun 23 05:32:30 PM PDT 24 Jun 23 05:32:31 PM PDT 24 15193821 ps
T67 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.315303786 Jun 23 05:33:03 PM PDT 24 Jun 23 05:33:04 PM PDT 24 82680779 ps
T1115 /workspace/coverage/cover_reg_top/10.uart_intr_test.3098073555 Jun 23 05:33:13 PM PDT 24 Jun 23 05:33:14 PM PDT 24 24503448 ps
T1116 /workspace/coverage/cover_reg_top/6.uart_intr_test.2712475423 Jun 23 05:33:03 PM PDT 24 Jun 23 05:33:04 PM PDT 24 26513269 ps
T1117 /workspace/coverage/cover_reg_top/26.uart_intr_test.1276618026 Jun 23 05:33:29 PM PDT 24 Jun 23 05:33:30 PM PDT 24 21200709 ps
T1118 /workspace/coverage/cover_reg_top/4.uart_intr_test.3342591662 Jun 23 05:32:58 PM PDT 24 Jun 23 05:32:59 PM PDT 24 22079454 ps
T68 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.689461547 Jun 23 05:32:52 PM PDT 24 Jun 23 05:32:53 PM PDT 24 107580024 ps
T51 /workspace/coverage/cover_reg_top/8.uart_csr_rw.1987744499 Jun 23 05:33:11 PM PDT 24 Jun 23 05:33:12 PM PDT 24 13668434 ps
T1119 /workspace/coverage/cover_reg_top/17.uart_tl_errors.3189130699 Jun 23 05:33:30 PM PDT 24 Jun 23 05:33:32 PM PDT 24 173821213 ps
T52 /workspace/coverage/cover_reg_top/14.uart_csr_rw.2535233872 Jun 23 05:33:18 PM PDT 24 Jun 23 05:33:20 PM PDT 24 12300587 ps
T69 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3608430316 Jun 23 05:33:12 PM PDT 24 Jun 23 05:33:14 PM PDT 24 90832855 ps
T1120 /workspace/coverage/cover_reg_top/7.uart_tl_errors.470768072 Jun 23 05:33:03 PM PDT 24 Jun 23 05:33:04 PM PDT 24 20254674 ps
T53 /workspace/coverage/cover_reg_top/5.uart_csr_rw.1993047447 Jun 23 05:32:57 PM PDT 24 Jun 23 05:32:58 PM PDT 24 76356832 ps
T1121 /workspace/coverage/cover_reg_top/28.uart_intr_test.2087477865 Jun 23 05:33:32 PM PDT 24 Jun 23 05:33:34 PM PDT 24 16485833 ps
T1122 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3877819149 Jun 23 05:32:51 PM PDT 24 Jun 23 05:32:52 PM PDT 24 35214908 ps
T73 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.1850308216 Jun 23 05:33:19 PM PDT 24 Jun 23 05:33:21 PM PDT 24 50456028 ps
T64 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2080520777 Jun 23 05:33:18 PM PDT 24 Jun 23 05:33:19 PM PDT 24 41706232 ps
T65 /workspace/coverage/cover_reg_top/12.uart_csr_rw.364395206 Jun 23 05:33:17 PM PDT 24 Jun 23 05:33:18 PM PDT 24 21591680 ps
T1123 /workspace/coverage/cover_reg_top/49.uart_intr_test.3054651819 Jun 23 05:33:43 PM PDT 24 Jun 23 05:33:44 PM PDT 24 23498253 ps
T1124 /workspace/coverage/cover_reg_top/12.uart_intr_test.72788994 Jun 23 05:33:19 PM PDT 24 Jun 23 05:33:20 PM PDT 24 13202097 ps
T1125 /workspace/coverage/cover_reg_top/38.uart_intr_test.967042550 Jun 23 05:33:36 PM PDT 24 Jun 23 05:33:37 PM PDT 24 111564240 ps
T1126 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.4165978273 Jun 23 05:33:04 PM PDT 24 Jun 23 05:33:06 PM PDT 24 140505962 ps
T1127 /workspace/coverage/cover_reg_top/11.uart_tl_errors.2952273391 Jun 23 05:33:12 PM PDT 24 Jun 23 05:33:13 PM PDT 24 57878670 ps
T103 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2220702161 Jun 23 05:32:31 PM PDT 24 Jun 23 05:32:32 PM PDT 24 116181320 ps
T104 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3529043091 Jun 23 05:33:18 PM PDT 24 Jun 23 05:33:19 PM PDT 24 46177778 ps
T54 /workspace/coverage/cover_reg_top/3.uart_csr_rw.2246097028 Jun 23 05:32:45 PM PDT 24 Jun 23 05:32:46 PM PDT 24 46369968 ps
T1128 /workspace/coverage/cover_reg_top/11.uart_intr_test.2998815054 Jun 23 05:33:13 PM PDT 24 Jun 23 05:33:14 PM PDT 24 24744013 ps
T1129 /workspace/coverage/cover_reg_top/11.uart_csr_rw.2028771172 Jun 23 05:33:13 PM PDT 24 Jun 23 05:33:14 PM PDT 24 14919309 ps
T1130 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.678499771 Jun 23 05:33:29 PM PDT 24 Jun 23 05:33:30 PM PDT 24 21299039 ps
T1131 /workspace/coverage/cover_reg_top/23.uart_intr_test.915385797 Jun 23 05:33:32 PM PDT 24 Jun 23 05:33:33 PM PDT 24 25977714 ps
T1132 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2061203667 Jun 23 05:32:51 PM PDT 24 Jun 23 05:32:52 PM PDT 24 16811324 ps
T1133 /workspace/coverage/cover_reg_top/33.uart_intr_test.1278469965 Jun 23 05:33:32 PM PDT 24 Jun 23 05:33:33 PM PDT 24 64763975 ps
T1134 /workspace/coverage/cover_reg_top/7.uart_csr_rw.2112401930 Jun 23 05:33:07 PM PDT 24 Jun 23 05:33:08 PM PDT 24 13362769 ps
T1135 /workspace/coverage/cover_reg_top/15.uart_csr_rw.2231295495 Jun 23 05:33:21 PM PDT 24 Jun 23 05:33:22 PM PDT 24 46211025 ps
T105 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1730291781 Jun 23 05:32:56 PM PDT 24 Jun 23 05:32:57 PM PDT 24 333179779 ps
T1136 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.88802016 Jun 23 05:32:58 PM PDT 24 Jun 23 05:32:59 PM PDT 24 172808914 ps
T1137 /workspace/coverage/cover_reg_top/45.uart_intr_test.3390730244 Jun 23 05:33:44 PM PDT 24 Jun 23 05:33:45 PM PDT 24 14397492 ps
T1138 /workspace/coverage/cover_reg_top/42.uart_intr_test.1704892186 Jun 23 05:33:37 PM PDT 24 Jun 23 05:33:38 PM PDT 24 29444799 ps
T1139 /workspace/coverage/cover_reg_top/7.uart_intr_test.200786556 Jun 23 05:33:01 PM PDT 24 Jun 23 05:33:02 PM PDT 24 15478450 ps
T1140 /workspace/coverage/cover_reg_top/29.uart_intr_test.1787925069 Jun 23 05:33:31 PM PDT 24 Jun 23 05:33:32 PM PDT 24 39038243 ps
T1141 /workspace/coverage/cover_reg_top/1.uart_tl_errors.1409100994 Jun 23 05:32:31 PM PDT 24 Jun 23 05:32:33 PM PDT 24 121759942 ps
T1142 /workspace/coverage/cover_reg_top/10.uart_tl_errors.1451360624 Jun 23 05:33:12 PM PDT 24 Jun 23 05:33:13 PM PDT 24 355606783 ps
T1143 /workspace/coverage/cover_reg_top/39.uart_intr_test.2540616221 Jun 23 05:33:36 PM PDT 24 Jun 23 05:33:36 PM PDT 24 29002389 ps
T1144 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1165174900 Jun 23 05:33:23 PM PDT 24 Jun 23 05:33:25 PM PDT 24 30851077 ps
T1145 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.105221516 Jun 23 05:32:36 PM PDT 24 Jun 23 05:32:38 PM PDT 24 34742704 ps
T1146 /workspace/coverage/cover_reg_top/16.uart_intr_test.2385004221 Jun 23 05:33:21 PM PDT 24 Jun 23 05:33:22 PM PDT 24 41020683 ps
T1147 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1207050582 Jun 23 05:32:36 PM PDT 24 Jun 23 05:32:37 PM PDT 24 34036543 ps
T1148 /workspace/coverage/cover_reg_top/19.uart_tl_errors.2989475215 Jun 23 05:33:25 PM PDT 24 Jun 23 05:33:28 PM PDT 24 676249336 ps
T1149 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2267724404 Jun 23 05:32:43 PM PDT 24 Jun 23 05:32:44 PM PDT 24 37144391 ps
T1150 /workspace/coverage/cover_reg_top/13.uart_tl_errors.2832627558 Jun 23 05:33:16 PM PDT 24 Jun 23 05:33:17 PM PDT 24 22379520 ps
T1151 /workspace/coverage/cover_reg_top/17.uart_csr_rw.2894957673 Jun 23 05:33:27 PM PDT 24 Jun 23 05:33:28 PM PDT 24 63093485 ps
T1152 /workspace/coverage/cover_reg_top/16.uart_tl_errors.2489239972 Jun 23 05:33:23 PM PDT 24 Jun 23 05:33:26 PM PDT 24 186209945 ps
T70 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.1741266754 Jun 23 05:33:12 PM PDT 24 Jun 23 05:33:13 PM PDT 24 442740512 ps
T55 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3108081192 Jun 23 05:33:04 PM PDT 24 Jun 23 05:33:06 PM PDT 24 646915052 ps
T1153 /workspace/coverage/cover_reg_top/1.uart_intr_test.2442288631 Jun 23 05:32:32 PM PDT 24 Jun 23 05:32:32 PM PDT 24 12667353 ps
T1154 /workspace/coverage/cover_reg_top/2.uart_intr_test.640048620 Jun 23 05:32:42 PM PDT 24 Jun 23 05:32:43 PM PDT 24 22325090 ps
T1155 /workspace/coverage/cover_reg_top/24.uart_intr_test.3704823333 Jun 23 05:33:29 PM PDT 24 Jun 23 05:33:30 PM PDT 24 10566983 ps
T1156 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1426810931 Jun 23 05:33:04 PM PDT 24 Jun 23 05:33:05 PM PDT 24 28006243 ps
T1157 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.4238910009 Jun 23 05:33:27 PM PDT 24 Jun 23 05:33:28 PM PDT 24 58705373 ps
T71 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.2638416836 Jun 23 05:32:46 PM PDT 24 Jun 23 05:32:48 PM PDT 24 144678205 ps
T1158 /workspace/coverage/cover_reg_top/17.uart_intr_test.2722485235 Jun 23 05:33:28 PM PDT 24 Jun 23 05:33:29 PM PDT 24 54172219 ps
T72 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.754972898 Jun 23 05:33:26 PM PDT 24 Jun 23 05:33:28 PM PDT 24 315163737 ps
T1159 /workspace/coverage/cover_reg_top/14.uart_tl_errors.1274215517 Jun 23 05:33:18 PM PDT 24 Jun 23 05:33:20 PM PDT 24 368321574 ps
T1160 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1600553955 Jun 23 05:33:08 PM PDT 24 Jun 23 05:33:09 PM PDT 24 70014659 ps
T1161 /workspace/coverage/cover_reg_top/27.uart_intr_test.587482990 Jun 23 05:33:32 PM PDT 24 Jun 23 05:33:33 PM PDT 24 17883244 ps
T1162 /workspace/coverage/cover_reg_top/34.uart_intr_test.4145566679 Jun 23 05:33:32 PM PDT 24 Jun 23 05:33:33 PM PDT 24 20561443 ps
T1163 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1931759328 Jun 23 05:33:27 PM PDT 24 Jun 23 05:33:29 PM PDT 24 100659243 ps
T1164 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.2822191783 Jun 23 05:32:31 PM PDT 24 Jun 23 05:32:33 PM PDT 24 38536920 ps
T1165 /workspace/coverage/cover_reg_top/19.uart_csr_rw.1129970763 Jun 23 05:33:27 PM PDT 24 Jun 23 05:33:28 PM PDT 24 13043641 ps
T1166 /workspace/coverage/cover_reg_top/44.uart_intr_test.4207737155 Jun 23 05:33:38 PM PDT 24 Jun 23 05:33:39 PM PDT 24 39728392 ps
T106 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.2604265699 Jun 23 05:33:30 PM PDT 24 Jun 23 05:33:31 PM PDT 24 93829184 ps
T1167 /workspace/coverage/cover_reg_top/2.uart_tl_errors.2799791036 Jun 23 05:32:36 PM PDT 24 Jun 23 05:32:38 PM PDT 24 131005459 ps
T1168 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.922339678 Jun 23 05:32:40 PM PDT 24 Jun 23 05:32:42 PM PDT 24 31789115 ps
T1169 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.833635651 Jun 23 05:33:16 PM PDT 24 Jun 23 05:33:17 PM PDT 24 59515493 ps
T1170 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3991968908 Jun 23 05:33:14 PM PDT 24 Jun 23 05:33:15 PM PDT 24 48761479 ps
T1171 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2073542537 Jun 23 05:33:26 PM PDT 24 Jun 23 05:33:28 PM PDT 24 24458078 ps
T1172 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3329289883 Jun 23 05:32:57 PM PDT 24 Jun 23 05:32:58 PM PDT 24 17851318 ps
T1173 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.3901124512 Jun 23 05:32:41 PM PDT 24 Jun 23 05:32:42 PM PDT 24 41494345 ps
T1174 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.37690567 Jun 23 05:32:39 PM PDT 24 Jun 23 05:32:40 PM PDT 24 17090976 ps
T1175 /workspace/coverage/cover_reg_top/32.uart_intr_test.4050541921 Jun 23 05:33:32 PM PDT 24 Jun 23 05:33:33 PM PDT 24 28004603 ps
T1176 /workspace/coverage/cover_reg_top/22.uart_intr_test.163095460 Jun 23 05:33:32 PM PDT 24 Jun 23 05:33:34 PM PDT 24 13085494 ps
T1177 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2113677955 Jun 23 05:32:48 PM PDT 24 Jun 23 05:32:49 PM PDT 24 14189296 ps
T1178 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2662371981 Jun 23 05:32:38 PM PDT 24 Jun 23 05:32:39 PM PDT 24 32929766 ps
T1179 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2037406771 Jun 23 05:33:08 PM PDT 24 Jun 23 05:33:09 PM PDT 24 82522490 ps
T1180 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2326665050 Jun 23 05:33:13 PM PDT 24 Jun 23 05:33:14 PM PDT 24 17878682 ps
T1181 /workspace/coverage/cover_reg_top/46.uart_intr_test.1480378083 Jun 23 05:33:42 PM PDT 24 Jun 23 05:33:43 PM PDT 24 21074221 ps
T1182 /workspace/coverage/cover_reg_top/5.uart_intr_test.2575116020 Jun 23 05:33:04 PM PDT 24 Jun 23 05:33:05 PM PDT 24 50561639 ps
T1183 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.2610201133 Jun 23 05:33:17 PM PDT 24 Jun 23 05:33:18 PM PDT 24 59833206 ps
T1184 /workspace/coverage/cover_reg_top/10.uart_csr_rw.206166731 Jun 23 05:33:11 PM PDT 24 Jun 23 05:33:12 PM PDT 24 13928886 ps
T58 /workspace/coverage/cover_reg_top/9.uart_csr_rw.1786645056 Jun 23 05:33:07 PM PDT 24 Jun 23 05:33:08 PM PDT 24 101769107 ps
T1185 /workspace/coverage/cover_reg_top/3.uart_intr_test.1557304772 Jun 23 05:32:46 PM PDT 24 Jun 23 05:32:47 PM PDT 24 12267827 ps
T1186 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2780594723 Jun 23 05:32:53 PM PDT 24 Jun 23 05:32:55 PM PDT 24 27840195 ps
T1187 /workspace/coverage/cover_reg_top/5.uart_tl_errors.727670068 Jun 23 05:32:56 PM PDT 24 Jun 23 05:32:59 PM PDT 24 283630768 ps
T1188 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2820129022 Jun 23 05:32:56 PM PDT 24 Jun 23 05:32:57 PM PDT 24 73515652 ps
T56 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.2690259516 Jun 23 05:32:32 PM PDT 24 Jun 23 05:32:33 PM PDT 24 16203685 ps
T107 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1704148067 Jun 23 05:33:19 PM PDT 24 Jun 23 05:33:20 PM PDT 24 299964939 ps
T1189 /workspace/coverage/cover_reg_top/20.uart_intr_test.3334423405 Jun 23 05:33:26 PM PDT 24 Jun 23 05:33:27 PM PDT 24 52380899 ps
T1190 /workspace/coverage/cover_reg_top/9.uart_tl_errors.1650310813 Jun 23 05:33:04 PM PDT 24 Jun 23 05:33:07 PM PDT 24 174259277 ps
T1191 /workspace/coverage/cover_reg_top/13.uart_csr_rw.3036737385 Jun 23 05:33:17 PM PDT 24 Jun 23 05:33:18 PM PDT 24 12406462 ps
T1192 /workspace/coverage/cover_reg_top/18.uart_tl_errors.950211018 Jun 23 05:33:26 PM PDT 24 Jun 23 05:33:28 PM PDT 24 384802129 ps
T1193 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.2813418754 Jun 23 05:33:07 PM PDT 24 Jun 23 05:33:07 PM PDT 24 58557938 ps
T1194 /workspace/coverage/cover_reg_top/0.uart_intr_test.1660145475 Jun 23 05:32:30 PM PDT 24 Jun 23 05:32:31 PM PDT 24 31872426 ps
T1195 /workspace/coverage/cover_reg_top/18.uart_csr_rw.687951997 Jun 23 05:33:26 PM PDT 24 Jun 23 05:33:27 PM PDT 24 15225230 ps
T1196 /workspace/coverage/cover_reg_top/41.uart_intr_test.909974948 Jun 23 05:33:37 PM PDT 24 Jun 23 05:33:38 PM PDT 24 41141646 ps
T1197 /workspace/coverage/cover_reg_top/47.uart_intr_test.3890642407 Jun 23 05:33:39 PM PDT 24 Jun 23 05:33:40 PM PDT 24 16258758 ps
T1198 /workspace/coverage/cover_reg_top/9.uart_intr_test.1299390480 Jun 23 05:33:06 PM PDT 24 Jun 23 05:33:07 PM PDT 24 15371801 ps
T1199 /workspace/coverage/cover_reg_top/1.uart_csr_rw.3405441541 Jun 23 05:32:36 PM PDT 24 Jun 23 05:32:37 PM PDT 24 58868888 ps
T1200 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.984143040 Jun 23 05:32:42 PM PDT 24 Jun 23 05:32:43 PM PDT 24 94816496 ps
T1201 /workspace/coverage/cover_reg_top/15.uart_tl_errors.1383012169 Jun 23 05:33:23 PM PDT 24 Jun 23 05:33:26 PM PDT 24 94852202 ps
T1202 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1844295599 Jun 23 05:32:40 PM PDT 24 Jun 23 05:32:42 PM PDT 24 174649463 ps
T1203 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2478957004 Jun 23 05:33:23 PM PDT 24 Jun 23 05:33:25 PM PDT 24 106174135 ps
T1204 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1108725400 Jun 23 05:33:22 PM PDT 24 Jun 23 05:33:23 PM PDT 24 21134547 ps
T1205 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.3002907274 Jun 23 05:32:52 PM PDT 24 Jun 23 05:32:53 PM PDT 24 54729878 ps
T1206 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.304707493 Jun 23 05:32:46 PM PDT 24 Jun 23 05:32:49 PM PDT 24 528583129 ps
T1207 /workspace/coverage/cover_reg_top/43.uart_intr_test.2434776891 Jun 23 05:33:41 PM PDT 24 Jun 23 05:33:42 PM PDT 24 15280164 ps
T1208 /workspace/coverage/cover_reg_top/14.uart_intr_test.117502430 Jun 23 05:33:16 PM PDT 24 Jun 23 05:33:17 PM PDT 24 17632945 ps
T1209 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1295012319 Jun 23 05:32:33 PM PDT 24 Jun 23 05:32:34 PM PDT 24 227110563 ps
T1210 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1998901890 Jun 23 05:33:02 PM PDT 24 Jun 23 05:33:04 PM PDT 24 772051316 ps
T1211 /workspace/coverage/cover_reg_top/6.uart_csr_rw.149594032 Jun 23 05:33:01 PM PDT 24 Jun 23 05:33:02 PM PDT 24 17647514 ps
T1212 /workspace/coverage/cover_reg_top/37.uart_intr_test.4273992112 Jun 23 05:33:35 PM PDT 24 Jun 23 05:33:36 PM PDT 24 12105119 ps
T1213 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.748999345 Jun 23 05:32:42 PM PDT 24 Jun 23 05:32:43 PM PDT 24 28522990 ps
T1214 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.814869530 Jun 23 05:33:13 PM PDT 24 Jun 23 05:33:14 PM PDT 24 31169239 ps
T57 /workspace/coverage/cover_reg_top/2.uart_csr_rw.3562502233 Jun 23 05:32:41 PM PDT 24 Jun 23 05:32:42 PM PDT 24 34094237 ps
T1215 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.616227935 Jun 23 05:33:07 PM PDT 24 Jun 23 05:33:08 PM PDT 24 253588644 ps
T1216 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.1027423181 Jun 23 05:33:17 PM PDT 24 Jun 23 05:33:19 PM PDT 24 48953876 ps
T1217 /workspace/coverage/cover_reg_top/48.uart_intr_test.4157617096 Jun 23 05:33:42 PM PDT 24 Jun 23 05:33:43 PM PDT 24 12651358 ps
T1218 /workspace/coverage/cover_reg_top/4.uart_tl_errors.3940702960 Jun 23 05:32:51 PM PDT 24 Jun 23 05:32:54 PM PDT 24 468304905 ps
T1219 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3520832317 Jun 23 05:33:13 PM PDT 24 Jun 23 05:33:14 PM PDT 24 38209506 ps
T1220 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.1817673592 Jun 23 05:33:10 PM PDT 24 Jun 23 05:33:11 PM PDT 24 88801456 ps
T1221 /workspace/coverage/cover_reg_top/18.uart_intr_test.1231037142 Jun 23 05:33:28 PM PDT 24 Jun 23 05:33:29 PM PDT 24 47156669 ps
T1222 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.472023735 Jun 23 05:32:32 PM PDT 24 Jun 23 05:32:33 PM PDT 24 66279009 ps
T1223 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3175820053 Jun 23 05:33:28 PM PDT 24 Jun 23 05:33:29 PM PDT 24 23693020 ps
T1224 /workspace/coverage/cover_reg_top/35.uart_intr_test.492466869 Jun 23 05:33:37 PM PDT 24 Jun 23 05:33:38 PM PDT 24 15492953 ps
T1225 /workspace/coverage/cover_reg_top/36.uart_intr_test.1845657048 Jun 23 05:33:36 PM PDT 24 Jun 23 05:33:37 PM PDT 24 16633066 ps
T1226 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.2242269982 Jun 23 05:33:30 PM PDT 24 Jun 23 05:33:32 PM PDT 24 145047225 ps
T1227 /workspace/coverage/cover_reg_top/3.uart_tl_errors.2296024247 Jun 23 05:32:52 PM PDT 24 Jun 23 05:32:54 PM PDT 24 77120284 ps
T1228 /workspace/coverage/cover_reg_top/21.uart_intr_test.1200210145 Jun 23 05:33:28 PM PDT 24 Jun 23 05:33:29 PM PDT 24 23478777 ps
T1229 /workspace/coverage/cover_reg_top/25.uart_intr_test.2299133229 Jun 23 05:33:30 PM PDT 24 Jun 23 05:33:31 PM PDT 24 21083971 ps
T1230 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.4126067517 Jun 23 05:32:31 PM PDT 24 Jun 23 05:32:32 PM PDT 24 183023143 ps
T1231 /workspace/coverage/cover_reg_top/40.uart_intr_test.1043719885 Jun 23 05:33:36 PM PDT 24 Jun 23 05:33:37 PM PDT 24 44063411 ps
T1232 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.3854758615 Jun 23 05:32:56 PM PDT 24 Jun 23 05:32:57 PM PDT 24 237810493 ps
T1233 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.1388490216 Jun 23 05:33:18 PM PDT 24 Jun 23 05:33:19 PM PDT 24 26984789 ps
T1234 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.1572451405 Jun 23 05:33:23 PM PDT 24 Jun 23 05:33:24 PM PDT 24 43024693 ps
T1235 /workspace/coverage/cover_reg_top/4.uart_csr_rw.2370944487 Jun 23 05:32:56 PM PDT 24 Jun 23 05:32:57 PM PDT 24 11757881 ps
T1236 /workspace/coverage/cover_reg_top/6.uart_tl_errors.1358792347 Jun 23 05:33:04 PM PDT 24 Jun 23 05:33:05 PM PDT 24 57775234 ps

Test location /workspace/coverage/default/26.uart_stress_all.2945999280
Short name T9
Test name
Test status
Simulation time 163318020822 ps
CPU time 709.71 seconds
Started Jun 23 05:41:49 PM PDT 24
Finished Jun 23 05:53:39 PM PDT 24
Peak memory 200712 kb
Host smart-cf107459-4c73-4182-b1c0-6a9c50546b60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945999280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.2945999280
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.2378061928
Short name T31
Test name
Test status
Simulation time 212028826606 ps
CPU time 311.96 seconds
Started Jun 23 05:43:52 PM PDT 24
Finished Jun 23 05:49:04 PM PDT 24
Peak memory 217320 kb
Host smart-04251518-4d6a-4d1e-88c7-6394f61c1779
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378061928 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.2378061928
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_stress_all.1503017083
Short name T241
Test name
Test status
Simulation time 357410993221 ps
CPU time 1311.36 seconds
Started Jun 23 05:41:29 PM PDT 24
Finished Jun 23 06:03:20 PM PDT 24
Peak memory 200676 kb
Host smart-3d517eef-abae-4f97-8f5b-1b738fbc1ffc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503017083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.1503017083
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.1217010009
Short name T230
Test name
Test status
Simulation time 64520431869 ps
CPU time 257.59 seconds
Started Jun 23 05:41:53 PM PDT 24
Finished Jun 23 05:46:10 PM PDT 24
Peak memory 200740 kb
Host smart-298518fe-c904-4967-bc9c-b3bb94ed09ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1217010009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.1217010009
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_stress_all.758994872
Short name T12
Test name
Test status
Simulation time 234768301710 ps
CPU time 132.32 seconds
Started Jun 23 05:42:36 PM PDT 24
Finished Jun 23 05:44:49 PM PDT 24
Peak memory 200668 kb
Host smart-ddb89e6e-611d-4b13-9a37-8abe88d80b0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758994872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.758994872
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all.2697284923
Short name T180
Test name
Test status
Simulation time 222903039620 ps
CPU time 497.49 seconds
Started Jun 23 05:43:51 PM PDT 24
Finished Jun 23 05:52:09 PM PDT 24
Peak memory 200676 kb
Host smart-920e1b63-22f0-4cdd-95ff-ddea6175b1d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697284923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.2697284923
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.1673271139
Short name T43
Test name
Test status
Simulation time 56828595838 ps
CPU time 1095.17 seconds
Started Jun 23 05:42:40 PM PDT 24
Finished Jun 23 06:00:56 PM PDT 24
Peak memory 217184 kb
Host smart-493086b0-31a0-4b89-a127-6cd3e0f8963e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673271139 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.1673271139
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_sec_cm.2783900063
Short name T27
Test name
Test status
Simulation time 126396021 ps
CPU time 0.77 seconds
Started Jun 23 05:39:42 PM PDT 24
Finished Jun 23 05:39:44 PM PDT 24
Peak memory 219236 kb
Host smart-f4685b65-fc13-461d-b93c-3271ed045101
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783900063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.2783900063
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.11332742
Short name T33
Test name
Test status
Simulation time 57136840935 ps
CPU time 1249.92 seconds
Started Jun 23 05:43:43 PM PDT 24
Finished Jun 23 06:04:33 PM PDT 24
Peak memory 217176 kb
Host smart-956b5297-4eb6-4eb3-93ff-47aa860e5dec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11332742 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.11332742
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.2305594741
Short name T32
Test name
Test status
Simulation time 70555454044 ps
CPU time 885.7 seconds
Started Jun 23 05:44:28 PM PDT 24
Finished Jun 23 05:59:14 PM PDT 24
Peak memory 217196 kb
Host smart-e4e7047d-d702-44cd-b1a8-da934b9b81ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305594741 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.2305594741
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_stress_all.2105032759
Short name T92
Test name
Test status
Simulation time 210652103865 ps
CPU time 667.93 seconds
Started Jun 23 05:40:36 PM PDT 24
Finished Jun 23 05:51:44 PM PDT 24
Peak memory 200732 kb
Host smart-f7cae3d7-0fe2-414f-97eb-bb585ab29be4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105032759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.2105032759
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all.2167040096
Short name T126
Test name
Test status
Simulation time 275475212172 ps
CPU time 120.78 seconds
Started Jun 23 05:43:28 PM PDT 24
Finished Jun 23 05:45:29 PM PDT 24
Peak memory 200676 kb
Host smart-440ce7ec-d4cb-48ff-b5a9-a4a34e8ff45d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167040096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.2167040096
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.2838659046
Short name T185
Test name
Test status
Simulation time 84402795222 ps
CPU time 1204.49 seconds
Started Jun 23 05:43:59 PM PDT 24
Finished Jun 23 06:04:04 PM PDT 24
Peak memory 217212 kb
Host smart-5c684f79-1d6d-405c-ae4b-9d691708a60b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838659046 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.2838659046
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.351754873
Short name T260
Test name
Test status
Simulation time 189187212898 ps
CPU time 111.35 seconds
Started Jun 23 05:43:26 PM PDT 24
Finished Jun 23 05:45:18 PM PDT 24
Peak memory 200692 kb
Host smart-6db15e04-da6c-4f8c-90f3-0273b12eaf13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351754873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.351754873
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_fifo_full.3744209324
Short name T95
Test name
Test status
Simulation time 147422300582 ps
CPU time 300.44 seconds
Started Jun 23 05:42:11 PM PDT 24
Finished Jun 23 05:47:12 PM PDT 24
Peak memory 200760 kb
Host smart-d28e3064-1b7e-432e-8975-bc6bfab5ef05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744209324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.3744209324
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.2246097028
Short name T54
Test name
Test status
Simulation time 46369968 ps
CPU time 0.61 seconds
Started Jun 23 05:32:45 PM PDT 24
Finished Jun 23 05:32:46 PM PDT 24
Peak memory 195620 kb
Host smart-dde0878a-b3a6-4cd4-8cbb-3f9651b6fd13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246097028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.2246097028
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3608430316
Short name T69
Test name
Test status
Simulation time 90832855 ps
CPU time 1.35 seconds
Started Jun 23 05:33:12 PM PDT 24
Finished Jun 23 05:33:14 PM PDT 24
Peak memory 199396 kb
Host smart-0c0eb060-1793-4429-befa-0a3df2f14ae8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608430316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.3608430316
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/default/9.uart_alert_test.3301676693
Short name T8
Test name
Test status
Simulation time 251262128 ps
CPU time 0.55 seconds
Started Jun 23 05:40:16 PM PDT 24
Finished Jun 23 05:40:17 PM PDT 24
Peak memory 196036 kb
Host smart-86587c66-36d1-4f5f-8cb4-28e95f54a374
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301676693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.3301676693
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.3545218689
Short name T113
Test name
Test status
Simulation time 128530376143 ps
CPU time 134.74 seconds
Started Jun 23 05:45:08 PM PDT 24
Finished Jun 23 05:47:23 PM PDT 24
Peak memory 200720 kb
Host smart-369e5652-e7a0-4b56-8422-ef39175868e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545218689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.3545218689
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.1182811647
Short name T154
Test name
Test status
Simulation time 116004337966 ps
CPU time 49.39 seconds
Started Jun 23 05:45:32 PM PDT 24
Finished Jun 23 05:46:22 PM PDT 24
Peak memory 200668 kb
Host smart-64e4c8a5-c88b-41fb-8a8f-d4edcad551ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182811647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.1182811647
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.1382644933
Short name T245
Test name
Test status
Simulation time 47745529216 ps
CPU time 686.87 seconds
Started Jun 23 05:44:09 PM PDT 24
Finished Jun 23 05:55:36 PM PDT 24
Peak memory 217108 kb
Host smart-81809102-1b89-40bf-81bc-796348026d2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382644933 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.1382644933
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.2674941045
Short name T157
Test name
Test status
Simulation time 174378772574 ps
CPU time 118.4 seconds
Started Jun 23 05:44:22 PM PDT 24
Finished Jun 23 05:46:21 PM PDT 24
Peak memory 200684 kb
Host smart-3b0a0c71-94f6-44ed-a15e-219688b0d73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674941045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.2674941045
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.4259501277
Short name T81
Test name
Test status
Simulation time 180606259400 ps
CPU time 872.49 seconds
Started Jun 23 05:39:59 PM PDT 24
Finished Jun 23 05:54:32 PM PDT 24
Peak memory 217024 kb
Host smart-d08dcb2b-ac84-4590-a286-e29cc8df605c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259501277 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.4259501277
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.121934326
Short name T291
Test name
Test status
Simulation time 251024198517 ps
CPU time 234.93 seconds
Started Jun 23 05:41:36 PM PDT 24
Finished Jun 23 05:45:31 PM PDT 24
Peak memory 200764 kb
Host smart-27be5c3d-cc87-4afa-ba10-68bd52a90d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121934326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.121934326
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.4153950351
Short name T94
Test name
Test status
Simulation time 58260266188 ps
CPU time 31.64 seconds
Started Jun 23 05:44:18 PM PDT 24
Finished Jun 23 05:44:50 PM PDT 24
Peak memory 200640 kb
Host smart-b2846a30-5307-4d05-8f32-15a85c778b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153950351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.4153950351
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.2690259516
Short name T56
Test name
Test status
Simulation time 16203685 ps
CPU time 0.6 seconds
Started Jun 23 05:32:32 PM PDT 24
Finished Jun 23 05:32:33 PM PDT 24
Peak memory 195440 kb
Host smart-10e1460a-a5a1-4255-bd36-bbfecdc21ee1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690259516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.2690259516
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.1743197928
Short name T83
Test name
Test status
Simulation time 92973130466 ps
CPU time 496.95 seconds
Started Jun 23 05:44:15 PM PDT 24
Finished Jun 23 05:52:32 PM PDT 24
Peak memory 215284 kb
Host smart-cf2815c2-2244-4f2d-b0c5-107c6853ee49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743197928 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.1743197928
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.2369657935
Short name T146
Test name
Test status
Simulation time 152931246164 ps
CPU time 138.89 seconds
Started Jun 23 05:45:38 PM PDT 24
Finished Jun 23 05:47:57 PM PDT 24
Peak memory 200664 kb
Host smart-6cd5fe30-e16d-40fd-9567-8b030dc3b6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369657935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.2369657935
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.2912243358
Short name T137
Test name
Test status
Simulation time 12851798561 ps
CPU time 30.31 seconds
Started Jun 23 05:44:57 PM PDT 24
Finished Jun 23 05:45:28 PM PDT 24
Peak memory 200692 kb
Host smart-8b890b32-3eb5-404a-8e49-b17aaf1f18bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912243358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.2912243358
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.1578084653
Short name T194
Test name
Test status
Simulation time 33878000121 ps
CPU time 26.77 seconds
Started Jun 23 05:45:22 PM PDT 24
Finished Jun 23 05:45:49 PM PDT 24
Peak memory 200688 kb
Host smart-2b37b7de-bcad-4286-a29d-4c6ce6b18333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578084653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.1578084653
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.867222716
Short name T15
Test name
Test status
Simulation time 45523654446 ps
CPU time 487.69 seconds
Started Jun 23 05:42:14 PM PDT 24
Finished Jun 23 05:50:23 PM PDT 24
Peak memory 210564 kb
Host smart-2e6a04b3-7287-496f-b4ea-1359f7e2ed27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867222716 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.867222716
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.989009789
Short name T36
Test name
Test status
Simulation time 136979482107 ps
CPU time 168.38 seconds
Started Jun 23 05:45:41 PM PDT 24
Finished Jun 23 05:48:29 PM PDT 24
Peak memory 200700 kb
Host smart-dd0a24e0-027d-468e-97e8-cab8df870595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989009789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.989009789
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.754972898
Short name T72
Test name
Test status
Simulation time 315163737 ps
CPU time 1.32 seconds
Started Jun 23 05:33:26 PM PDT 24
Finished Jun 23 05:33:28 PM PDT 24
Peak memory 199376 kb
Host smart-1231760c-5c9a-42d5-a975-711698b11f0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754972898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.754972898
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.3258134302
Short name T149
Test name
Test status
Simulation time 13143365013 ps
CPU time 19.28 seconds
Started Jun 23 05:44:30 PM PDT 24
Finished Jun 23 05:44:50 PM PDT 24
Peak memory 200668 kb
Host smart-053f77f7-0cbb-447e-a641-6db8d880a8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258134302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.3258134302
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.4061173811
Short name T199
Test name
Test status
Simulation time 106006435564 ps
CPU time 109.31 seconds
Started Jun 23 05:44:37 PM PDT 24
Finished Jun 23 05:46:27 PM PDT 24
Peak memory 200660 kb
Host smart-f087c4f4-d581-49bb-b51c-45768fdb58ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061173811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.4061173811
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_stress_all.1102686008
Short name T153
Test name
Test status
Simulation time 817410063798 ps
CPU time 282.54 seconds
Started Jun 23 05:42:25 PM PDT 24
Finished Jun 23 05:47:08 PM PDT 24
Peak memory 200700 kb
Host smart-d81f86f4-74e2-412d-9112-3e48703d227b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102686008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.1102686008
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.45797879
Short name T96
Test name
Test status
Simulation time 20420741436 ps
CPU time 30.9 seconds
Started Jun 23 05:44:21 PM PDT 24
Finished Jun 23 05:44:53 PM PDT 24
Peak memory 200760 kb
Host smart-96cefb53-23b6-400c-9650-e32efa4c12f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45797879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.45797879
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.1581356684
Short name T39
Test name
Test status
Simulation time 21392268755 ps
CPU time 13.66 seconds
Started Jun 23 05:44:30 PM PDT 24
Finished Jun 23 05:44:44 PM PDT 24
Peak memory 200664 kb
Host smart-04e5172e-e3a6-4399-aa7d-336d5ef7424b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581356684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.1581356684
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.201006363
Short name T164
Test name
Test status
Simulation time 27803317246 ps
CPU time 13.64 seconds
Started Jun 23 05:45:11 PM PDT 24
Finished Jun 23 05:45:25 PM PDT 24
Peak memory 200752 kb
Host smart-a1db5a3f-8461-4bdb-86ce-f6c8fbe0fd60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201006363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.201006363
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.3434568399
Short name T175
Test name
Test status
Simulation time 262092924181 ps
CPU time 73.04 seconds
Started Jun 23 05:45:27 PM PDT 24
Finished Jun 23 05:46:40 PM PDT 24
Peak memory 200740 kb
Host smart-2c596fba-a0af-4e56-a82b-678d8f33c543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434568399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.3434568399
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.429511594
Short name T140
Test name
Test status
Simulation time 17058821576 ps
CPU time 17.84 seconds
Started Jun 23 05:45:26 PM PDT 24
Finished Jun 23 05:45:44 PM PDT 24
Peak memory 200788 kb
Host smart-e0ae7361-bd94-4909-af33-d1ca3c1b9fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429511594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.429511594
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.2544558780
Short name T183
Test name
Test status
Simulation time 252810954686 ps
CPU time 1141.35 seconds
Started Jun 23 05:44:02 PM PDT 24
Finished Jun 23 06:03:04 PM PDT 24
Peak memory 225356 kb
Host smart-91e25f60-79cb-474c-9c2b-8e9140040540
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544558780 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.2544558780
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.2933822438
Short name T168
Test name
Test status
Simulation time 180427605309 ps
CPU time 78.89 seconds
Started Jun 23 05:44:10 PM PDT 24
Finished Jun 23 05:45:30 PM PDT 24
Peak memory 200688 kb
Host smart-42cd3b4a-6529-44fe-b00c-cc2c1e2e664d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933822438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.2933822438
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.2340009121
Short name T161
Test name
Test status
Simulation time 46484490994 ps
CPU time 29.98 seconds
Started Jun 23 05:40:57 PM PDT 24
Finished Jun 23 05:41:27 PM PDT 24
Peak memory 200736 kb
Host smart-c451d39c-e042-4017-a3a8-9521088b02fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340009121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.2340009121
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_tx_rx.1635720273
Short name T401
Test name
Test status
Simulation time 84314925810 ps
CPU time 71.38 seconds
Started Jun 23 05:41:25 PM PDT 24
Finished Jun 23 05:42:37 PM PDT 24
Peak memory 200728 kb
Host smart-f11845ac-3aab-4fb3-82da-1559ea022fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635720273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.1635720273
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.1193177489
Short name T322
Test name
Test status
Simulation time 127641260588 ps
CPU time 15 seconds
Started Jun 23 05:45:23 PM PDT 24
Finished Jun 23 05:45:39 PM PDT 24
Peak memory 200672 kb
Host smart-15dffd0f-24fa-4542-a463-23666143c768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193177489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.1193177489
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.3952192995
Short name T148
Test name
Test status
Simulation time 70074603721 ps
CPU time 62.75 seconds
Started Jun 23 05:44:23 PM PDT 24
Finished Jun 23 05:45:26 PM PDT 24
Peak memory 200624 kb
Host smart-1b4bbd0f-3c94-4972-9e58-8ab6595038a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952192995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.3952192995
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.2604636226
Short name T167
Test name
Test status
Simulation time 118622869618 ps
CPU time 45.92 seconds
Started Jun 23 05:40:25 PM PDT 24
Finished Jun 23 05:41:11 PM PDT 24
Peak memory 200504 kb
Host smart-cb92032c-ad93-4dc2-a74a-09f10985785e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604636226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.2604636226
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.2775669009
Short name T109
Test name
Test status
Simulation time 23533044904 ps
CPU time 32.73 seconds
Started Jun 23 05:44:57 PM PDT 24
Finished Jun 23 05:45:30 PM PDT 24
Peak memory 200700 kb
Host smart-4b2d4e0f-a37e-4bdf-bc08-0d246f16fb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775669009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.2775669009
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.4043929899
Short name T128
Test name
Test status
Simulation time 170551746059 ps
CPU time 206.94 seconds
Started Jun 23 05:40:28 PM PDT 24
Finished Jun 23 05:43:55 PM PDT 24
Peak memory 200732 kb
Host smart-253123c1-8059-47b6-92d1-cb44a643135b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043929899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.4043929899
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.2595216227
Short name T222
Test name
Test status
Simulation time 128116788244 ps
CPU time 29.38 seconds
Started Jun 23 05:44:26 PM PDT 24
Finished Jun 23 05:44:56 PM PDT 24
Peak memory 200636 kb
Host smart-a7204847-dba8-4234-b7a5-908d8fdb7c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595216227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.2595216227
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.2087825244
Short name T66
Test name
Test status
Simulation time 107280023234 ps
CPU time 165.4 seconds
Started Jun 23 05:44:42 PM PDT 24
Finished Jun 23 05:47:28 PM PDT 24
Peak memory 200716 kb
Host smart-4a8b6fc7-e4ed-4856-ac99-9518c4d25740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087825244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.2087825244
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.3854470503
Short name T120
Test name
Test status
Simulation time 26382836254 ps
CPU time 43.77 seconds
Started Jun 23 05:45:12 PM PDT 24
Finished Jun 23 05:45:56 PM PDT 24
Peak memory 200700 kb
Host smart-1b3c7e56-0171-41df-969c-a5f96174c352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854470503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.3854470503
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.3892400818
Short name T188
Test name
Test status
Simulation time 140579585504 ps
CPU time 204.04 seconds
Started Jun 23 05:41:32 PM PDT 24
Finished Jun 23 05:44:56 PM PDT 24
Peak memory 200696 kb
Host smart-c4f48131-f2df-479d-b31b-cc427db6bce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892400818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.3892400818
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.2626567248
Short name T114
Test name
Test status
Simulation time 121112576095 ps
CPU time 48.25 seconds
Started Jun 23 05:45:15 PM PDT 24
Finished Jun 23 05:46:04 PM PDT 24
Peak memory 200756 kb
Host smart-9951dc50-429c-49a3-a741-88f5e1dfedc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626567248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.2626567248
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_fifo_full.2096001790
Short name T156
Test name
Test status
Simulation time 17040179799 ps
CPU time 23.17 seconds
Started Jun 23 05:42:00 PM PDT 24
Finished Jun 23 05:42:24 PM PDT 24
Peak memory 200668 kb
Host smart-06576bef-1a5a-4367-b1c0-6e9b4d94f759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096001790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.2096001790
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.1219662434
Short name T138
Test name
Test status
Simulation time 66068074951 ps
CPU time 61.01 seconds
Started Jun 23 05:42:31 PM PDT 24
Finished Jun 23 05:43:32 PM PDT 24
Peak memory 200712 kb
Host smart-e66c47f8-0ddf-4087-a4f3-6472ac6da336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219662434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.1219662434
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.1005958597
Short name T207
Test name
Test status
Simulation time 42915416911 ps
CPU time 16.83 seconds
Started Jun 23 05:40:18 PM PDT 24
Finished Jun 23 05:40:36 PM PDT 24
Peak memory 200620 kb
Host smart-4e806ed7-3742-4955-9c4d-9f22070e2c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005958597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.1005958597
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.2958067745
Short name T737
Test name
Test status
Simulation time 45782257773 ps
CPU time 60.87 seconds
Started Jun 23 05:39:46 PM PDT 24
Finished Jun 23 05:40:47 PM PDT 24
Peak memory 200020 kb
Host smart-676a10e7-1c4b-4a2f-ac73-3b13ea867e47
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958067745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.2958067745
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.410079119
Short name T219
Test name
Test status
Simulation time 112891159418 ps
CPU time 24.17 seconds
Started Jun 23 05:39:44 PM PDT 24
Finished Jun 23 05:40:09 PM PDT 24
Peak memory 200708 kb
Host smart-d96e1e46-3892-479e-b00a-b11ef77deb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410079119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.410079119
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.3554268940
Short name T139
Test name
Test status
Simulation time 15845364950 ps
CPU time 25.11 seconds
Started Jun 23 05:44:22 PM PDT 24
Finished Jun 23 05:44:48 PM PDT 24
Peak memory 200748 kb
Host smart-858ad18b-434e-4e8c-ad23-21d39b228752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554268940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.3554268940
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.4243160003
Short name T166
Test name
Test status
Simulation time 115837904712 ps
CPU time 161.32 seconds
Started Jun 23 05:44:36 PM PDT 24
Finished Jun 23 05:47:18 PM PDT 24
Peak memory 200700 kb
Host smart-8e57d1c0-efd7-41e8-88e8-dcea2d60200a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243160003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.4243160003
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.2087906161
Short name T841
Test name
Test status
Simulation time 252127351842 ps
CPU time 45.76 seconds
Started Jun 23 05:44:37 PM PDT 24
Finished Jun 23 05:45:23 PM PDT 24
Peak memory 200700 kb
Host smart-0ece28be-6f5d-4c69-877a-d07fb8eb46bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087906161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.2087906161
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.1905610877
Short name T218
Test name
Test status
Simulation time 20225302078 ps
CPU time 14.77 seconds
Started Jun 23 05:45:06 PM PDT 24
Finished Jun 23 05:45:21 PM PDT 24
Peak memory 200748 kb
Host smart-1313620b-9676-401e-844b-1dfee584036a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905610877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.1905610877
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.1381520179
Short name T116
Test name
Test status
Simulation time 16985369509 ps
CPU time 30.04 seconds
Started Jun 23 05:45:17 PM PDT 24
Finished Jun 23 05:45:47 PM PDT 24
Peak memory 200660 kb
Host smart-01f2ec62-baab-4544-9012-1ff296718149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381520179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.1381520179
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.3813272775
Short name T208
Test name
Test status
Simulation time 21261957415 ps
CPU time 20.38 seconds
Started Jun 23 05:45:19 PM PDT 24
Finished Jun 23 05:45:40 PM PDT 24
Peak memory 200612 kb
Host smart-abf048c6-9e65-4b02-9864-acc2ccb24c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813272775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.3813272775
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.3935417998
Short name T214
Test name
Test status
Simulation time 204909573122 ps
CPU time 88.78 seconds
Started Jun 23 05:41:43 PM PDT 24
Finished Jun 23 05:43:13 PM PDT 24
Peak memory 200688 kb
Host smart-7ca06ee4-938c-49e7-92ec-a1b399583dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935417998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.3935417998
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.488131163
Short name T224
Test name
Test status
Simulation time 50489926919 ps
CPU time 19.96 seconds
Started Jun 23 05:43:19 PM PDT 24
Finished Jun 23 05:43:39 PM PDT 24
Peak memory 200312 kb
Host smart-0b6ca72a-6051-4f32-95ba-cc00b4af75cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488131163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.488131163
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1145574378
Short name T50
Test name
Test status
Simulation time 23316744 ps
CPU time 0.66 seconds
Started Jun 23 05:32:30 PM PDT 24
Finished Jun 23 05:32:31 PM PDT 24
Peak memory 194812 kb
Host smart-3dcedf5a-5675-4200-8e73-c0fdedfbd985
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145574378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.1145574378
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.2822191783
Short name T1164
Test name
Test status
Simulation time 38536920 ps
CPU time 1.36 seconds
Started Jun 23 05:32:31 PM PDT 24
Finished Jun 23 05:32:33 PM PDT 24
Peak memory 197876 kb
Host smart-3f78b288-0a6f-44af-b8b0-9d5c03c02e22
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822191783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.2822191783
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1295012319
Short name T1209
Test name
Test status
Simulation time 227110563 ps
CPU time 0.72 seconds
Started Jun 23 05:32:33 PM PDT 24
Finished Jun 23 05:32:34 PM PDT 24
Peak memory 198532 kb
Host smart-a4270736-6268-4d2b-baef-4cc5cef728bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295012319 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.1295012319
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.4276749486
Short name T63
Test name
Test status
Simulation time 15193821 ps
CPU time 0.62 seconds
Started Jun 23 05:32:30 PM PDT 24
Finished Jun 23 05:32:31 PM PDT 24
Peak memory 195436 kb
Host smart-1cf2e2c2-3fd2-4f03-aaef-6ed09c020333
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276749486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.4276749486
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.1660145475
Short name T1194
Test name
Test status
Simulation time 31872426 ps
CPU time 0.56 seconds
Started Jun 23 05:32:30 PM PDT 24
Finished Jun 23 05:32:31 PM PDT 24
Peak memory 194404 kb
Host smart-9f5732bb-2ef4-48bd-9bbd-b402c960eceb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660145475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.1660145475
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.472023735
Short name T1222
Test name
Test status
Simulation time 66279009 ps
CPU time 0.6 seconds
Started Jun 23 05:32:32 PM PDT 24
Finished Jun 23 05:32:33 PM PDT 24
Peak memory 195552 kb
Host smart-af470dcc-35a0-437d-b917-5d4afeeb77ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472023735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr_
outstanding.472023735
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.1096838805
Short name T1106
Test name
Test status
Simulation time 71814880 ps
CPU time 1.5 seconds
Started Jun 23 05:32:26 PM PDT 24
Finished Jun 23 05:32:28 PM PDT 24
Peak memory 200028 kb
Host smart-1661fc7e-5d71-4b89-b572-fc258c332ef4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096838805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.1096838805
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.4126067517
Short name T1230
Test name
Test status
Simulation time 183023143 ps
CPU time 0.95 seconds
Started Jun 23 05:32:31 PM PDT 24
Finished Jun 23 05:32:32 PM PDT 24
Peak memory 199012 kb
Host smart-aac43c18-96c2-4282-ba92-7dffd86bf96b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126067517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.4126067517
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2662371981
Short name T1178
Test name
Test status
Simulation time 32929766 ps
CPU time 0.66 seconds
Started Jun 23 05:32:38 PM PDT 24
Finished Jun 23 05:32:39 PM PDT 24
Peak memory 195388 kb
Host smart-93ca77f4-cc30-4435-be77-1ff64c457d6c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662371981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.2662371981
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.105221516
Short name T1145
Test name
Test status
Simulation time 34742704 ps
CPU time 1.45 seconds
Started Jun 23 05:32:36 PM PDT 24
Finished Jun 23 05:32:38 PM PDT 24
Peak memory 197932 kb
Host smart-85500a62-1d9c-49d9-abd5-a6ca8aa50ed2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105221516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.105221516
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.37690567
Short name T1174
Test name
Test status
Simulation time 17090976 ps
CPU time 0.62 seconds
Started Jun 23 05:32:39 PM PDT 24
Finished Jun 23 05:32:40 PM PDT 24
Peak memory 195436 kb
Host smart-5ea6aaf8-5a7d-4752-a45e-ada4042ed137
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37690567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.37690567
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2932877969
Short name T1110
Test name
Test status
Simulation time 91409913 ps
CPU time 0.63 seconds
Started Jun 23 05:32:39 PM PDT 24
Finished Jun 23 05:32:41 PM PDT 24
Peak memory 197052 kb
Host smart-8fd5064f-c1d2-4bb3-9dfa-08803fd94657
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932877969 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.2932877969
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.3405441541
Short name T1199
Test name
Test status
Simulation time 58868888 ps
CPU time 0.62 seconds
Started Jun 23 05:32:36 PM PDT 24
Finished Jun 23 05:32:37 PM PDT 24
Peak memory 195588 kb
Host smart-40d3dd92-7a25-4622-b0f6-6d890c95b98c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405441541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.3405441541
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.2442288631
Short name T1153
Test name
Test status
Simulation time 12667353 ps
CPU time 0.55 seconds
Started Jun 23 05:32:32 PM PDT 24
Finished Jun 23 05:32:32 PM PDT 24
Peak memory 194480 kb
Host smart-b04401d6-23d2-48bf-8938-4c939b02fac9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442288631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.2442288631
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1207050582
Short name T1147
Test name
Test status
Simulation time 34036543 ps
CPU time 0.62 seconds
Started Jun 23 05:32:36 PM PDT 24
Finished Jun 23 05:32:37 PM PDT 24
Peak memory 195744 kb
Host smart-46e488c5-5383-47ab-a618-09c5454cd51d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207050582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.1207050582
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.1409100994
Short name T1141
Test name
Test status
Simulation time 121759942 ps
CPU time 1.26 seconds
Started Jun 23 05:32:31 PM PDT 24
Finished Jun 23 05:32:33 PM PDT 24
Peak memory 199988 kb
Host smart-0a8dffe3-b753-46a8-96c4-cf0f04a43312
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409100994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.1409100994
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2220702161
Short name T103
Test name
Test status
Simulation time 116181320 ps
CPU time 1.03 seconds
Started Jun 23 05:32:31 PM PDT 24
Finished Jun 23 05:32:32 PM PDT 24
Peak memory 199068 kb
Host smart-c2eb2cbd-78ad-42a4-b49a-e9fde77eed8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220702161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.2220702161
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3991968908
Short name T1170
Test name
Test status
Simulation time 48761479 ps
CPU time 0.73 seconds
Started Jun 23 05:33:14 PM PDT 24
Finished Jun 23 05:33:15 PM PDT 24
Peak memory 198432 kb
Host smart-1d316923-93ed-4331-b48e-8591654509fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991968908 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.3991968908
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.206166731
Short name T1184
Test name
Test status
Simulation time 13928886 ps
CPU time 0.6 seconds
Started Jun 23 05:33:11 PM PDT 24
Finished Jun 23 05:33:12 PM PDT 24
Peak memory 195412 kb
Host smart-9baabee1-22fa-4c12-b796-03a271c8dac7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206166731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.206166731
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.3098073555
Short name T1115
Test name
Test status
Simulation time 24503448 ps
CPU time 0.55 seconds
Started Jun 23 05:33:13 PM PDT 24
Finished Jun 23 05:33:14 PM PDT 24
Peak memory 194412 kb
Host smart-a15469aa-ed87-4601-a146-f4c16e902a65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098073555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.3098073555
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.814869530
Short name T1214
Test name
Test status
Simulation time 31169239 ps
CPU time 0.67 seconds
Started Jun 23 05:33:13 PM PDT 24
Finished Jun 23 05:33:14 PM PDT 24
Peak memory 194720 kb
Host smart-4c7fff38-52f3-4c5b-bf0a-07525022c524
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814869530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_csr
_outstanding.814869530
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.1451360624
Short name T1142
Test name
Test status
Simulation time 355606783 ps
CPU time 0.97 seconds
Started Jun 23 05:33:12 PM PDT 24
Finished Jun 23 05:33:13 PM PDT 24
Peak memory 199864 kb
Host smart-be898793-8fe6-4fbb-91f7-5a7fc1db00e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451360624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.1451360624
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.4051839237
Short name T1111
Test name
Test status
Simulation time 49360802 ps
CPU time 0.81 seconds
Started Jun 23 05:33:17 PM PDT 24
Finished Jun 23 05:33:18 PM PDT 24
Peak memory 199904 kb
Host smart-22129565-c4f3-413f-8df8-213ea9896ea4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051839237 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.4051839237
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.2028771172
Short name T1129
Test name
Test status
Simulation time 14919309 ps
CPU time 0.57 seconds
Started Jun 23 05:33:13 PM PDT 24
Finished Jun 23 05:33:14 PM PDT 24
Peak memory 195560 kb
Host smart-e0906170-40a3-4122-a1d4-ab3913a9ad43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028771172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.2028771172
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.2998815054
Short name T1128
Test name
Test status
Simulation time 24744013 ps
CPU time 0.58 seconds
Started Jun 23 05:33:13 PM PDT 24
Finished Jun 23 05:33:14 PM PDT 24
Peak memory 194444 kb
Host smart-1e5e3fc7-6040-4361-9583-0545d858c13a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998815054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.2998815054
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.833635651
Short name T1169
Test name
Test status
Simulation time 59515493 ps
CPU time 0.77 seconds
Started Jun 23 05:33:16 PM PDT 24
Finished Jun 23 05:33:17 PM PDT 24
Peak memory 197084 kb
Host smart-30833f49-d021-4c22-a303-c856eb9f8606
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833635651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_csr
_outstanding.833635651
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.2952273391
Short name T1127
Test name
Test status
Simulation time 57878670 ps
CPU time 1.36 seconds
Started Jun 23 05:33:12 PM PDT 24
Finished Jun 23 05:33:13 PM PDT 24
Peak memory 200036 kb
Host smart-b1d9d313-9eaa-44b5-9e03-973c98d552ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952273391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.2952273391
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.1741266754
Short name T70
Test name
Test status
Simulation time 442740512 ps
CPU time 1.35 seconds
Started Jun 23 05:33:12 PM PDT 24
Finished Jun 23 05:33:13 PM PDT 24
Peak memory 199176 kb
Host smart-d4cd702e-cb61-476e-a17d-dcaadf6092b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741266754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.1741266754
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.2610201133
Short name T1183
Test name
Test status
Simulation time 59833206 ps
CPU time 0.65 seconds
Started Jun 23 05:33:17 PM PDT 24
Finished Jun 23 05:33:18 PM PDT 24
Peak memory 197748 kb
Host smart-a0d3ce73-d814-4ee2-aeb1-89262188046e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610201133 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.2610201133
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.364395206
Short name T65
Test name
Test status
Simulation time 21591680 ps
CPU time 0.6 seconds
Started Jun 23 05:33:17 PM PDT 24
Finished Jun 23 05:33:18 PM PDT 24
Peak memory 195680 kb
Host smart-d19a1a84-8ab4-4235-9ddd-2e0e0d1449be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364395206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.364395206
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.72788994
Short name T1124
Test name
Test status
Simulation time 13202097 ps
CPU time 0.58 seconds
Started Jun 23 05:33:19 PM PDT 24
Finished Jun 23 05:33:20 PM PDT 24
Peak memory 194420 kb
Host smart-5993f08f-689e-4eec-97b8-5da100e70212
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72788994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.72788994
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2080520777
Short name T64
Test name
Test status
Simulation time 41706232 ps
CPU time 0.62 seconds
Started Jun 23 05:33:18 PM PDT 24
Finished Jun 23 05:33:19 PM PDT 24
Peak memory 195632 kb
Host smart-df0ecd93-aa2a-4249-92ce-295d49261009
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080520777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.2080520777
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.1181536775
Short name T1102
Test name
Test status
Simulation time 209836125 ps
CPU time 1 seconds
Started Jun 23 05:33:17 PM PDT 24
Finished Jun 23 05:33:19 PM PDT 24
Peak memory 199872 kb
Host smart-54f4f252-9bc1-4bca-8392-1403c6537acd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181536775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.1181536775
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.1850308216
Short name T73
Test name
Test status
Simulation time 50456028 ps
CPU time 0.98 seconds
Started Jun 23 05:33:19 PM PDT 24
Finished Jun 23 05:33:21 PM PDT 24
Peak memory 199120 kb
Host smart-5cc3c9cf-103c-4178-b7f1-57aa5b9d49f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850308216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.1850308216
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3733417103
Short name T1107
Test name
Test status
Simulation time 194942180 ps
CPU time 1.21 seconds
Started Jun 23 05:33:17 PM PDT 24
Finished Jun 23 05:33:19 PM PDT 24
Peak memory 200004 kb
Host smart-147c24c5-d48d-416d-8263-993d9b308b68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733417103 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.3733417103
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.3036737385
Short name T1191
Test name
Test status
Simulation time 12406462 ps
CPU time 0.59 seconds
Started Jun 23 05:33:17 PM PDT 24
Finished Jun 23 05:33:18 PM PDT 24
Peak memory 195440 kb
Host smart-fce41413-72a8-49a3-86cd-e46abef71cec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036737385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.3036737385
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.1137014396
Short name T1108
Test name
Test status
Simulation time 16638830 ps
CPU time 0.58 seconds
Started Jun 23 05:33:17 PM PDT 24
Finished Jun 23 05:33:18 PM PDT 24
Peak memory 194484 kb
Host smart-257756fa-df60-4304-9fb3-d86a5bde0e73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137014396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.1137014396
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.1388490216
Short name T1233
Test name
Test status
Simulation time 26984789 ps
CPU time 0.74 seconds
Started Jun 23 05:33:18 PM PDT 24
Finished Jun 23 05:33:19 PM PDT 24
Peak memory 197012 kb
Host smart-8353927a-0bf8-4565-a4eb-0b2aef081316
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388490216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.1388490216
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.2832627558
Short name T1150
Test name
Test status
Simulation time 22379520 ps
CPU time 1.05 seconds
Started Jun 23 05:33:16 PM PDT 24
Finished Jun 23 05:33:17 PM PDT 24
Peak memory 199896 kb
Host smart-b533cb0b-aac1-4027-a0ca-d1c89aec6203
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832627558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.2832627558
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.1027423181
Short name T1216
Test name
Test status
Simulation time 48953876 ps
CPU time 0.93 seconds
Started Jun 23 05:33:17 PM PDT 24
Finished Jun 23 05:33:19 PM PDT 24
Peak memory 199076 kb
Host smart-d0d948c9-84d4-4828-a96f-031dad3ffcc5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027423181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.1027423181
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2478957004
Short name T1203
Test name
Test status
Simulation time 106174135 ps
CPU time 1.57 seconds
Started Jun 23 05:33:23 PM PDT 24
Finished Jun 23 05:33:25 PM PDT 24
Peak memory 200064 kb
Host smart-b0806e7d-d33f-4558-bbf6-4270fe9717c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478957004 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.2478957004
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.2535233872
Short name T52
Test name
Test status
Simulation time 12300587 ps
CPU time 0.62 seconds
Started Jun 23 05:33:18 PM PDT 24
Finished Jun 23 05:33:20 PM PDT 24
Peak memory 195520 kb
Host smart-6eb87864-4fd2-4fce-b103-3044ec580a91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535233872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.2535233872
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.117502430
Short name T1208
Test name
Test status
Simulation time 17632945 ps
CPU time 0.61 seconds
Started Jun 23 05:33:16 PM PDT 24
Finished Jun 23 05:33:17 PM PDT 24
Peak memory 194476 kb
Host smart-0a100a48-915d-48dd-9bd5-bf9b925be0c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117502430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.117502430
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.1572451405
Short name T1234
Test name
Test status
Simulation time 43024693 ps
CPU time 0.66 seconds
Started Jun 23 05:33:23 PM PDT 24
Finished Jun 23 05:33:24 PM PDT 24
Peak memory 194840 kb
Host smart-78c7ed38-e232-47bb-9702-5a5346bc5d4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572451405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.1572451405
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.1274215517
Short name T1159
Test name
Test status
Simulation time 368321574 ps
CPU time 2.01 seconds
Started Jun 23 05:33:18 PM PDT 24
Finished Jun 23 05:33:20 PM PDT 24
Peak memory 200060 kb
Host smart-d560817e-610e-4bca-96d0-71324afb5996
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274215517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.1274215517
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3529043091
Short name T104
Test name
Test status
Simulation time 46177778 ps
CPU time 1.02 seconds
Started Jun 23 05:33:18 PM PDT 24
Finished Jun 23 05:33:19 PM PDT 24
Peak memory 199120 kb
Host smart-7a7a940a-d8e2-4107-bd2d-d582298cd6d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529043091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.3529043091
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1165174900
Short name T1144
Test name
Test status
Simulation time 30851077 ps
CPU time 0.88 seconds
Started Jun 23 05:33:23 PM PDT 24
Finished Jun 23 05:33:25 PM PDT 24
Peak memory 199908 kb
Host smart-21e5c242-a67e-438e-9b38-8f2a690de597
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165174900 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.1165174900
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.2231295495
Short name T1135
Test name
Test status
Simulation time 46211025 ps
CPU time 0.58 seconds
Started Jun 23 05:33:21 PM PDT 24
Finished Jun 23 05:33:22 PM PDT 24
Peak memory 195440 kb
Host smart-20f906a9-2a98-4f0f-9442-60b742400795
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231295495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.2231295495
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.2289987632
Short name T1103
Test name
Test status
Simulation time 34347021 ps
CPU time 0.57 seconds
Started Jun 23 05:33:22 PM PDT 24
Finished Jun 23 05:33:23 PM PDT 24
Peak memory 194488 kb
Host smart-71b93751-3f7d-46ae-8b96-65468c6b011f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289987632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.2289987632
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1108725400
Short name T1204
Test name
Test status
Simulation time 21134547 ps
CPU time 0.62 seconds
Started Jun 23 05:33:22 PM PDT 24
Finished Jun 23 05:33:23 PM PDT 24
Peak memory 195532 kb
Host smart-27074be9-4faa-4c48-92fb-e3efd7c698e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108725400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.1108725400
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.1383012169
Short name T1201
Test name
Test status
Simulation time 94852202 ps
CPU time 2.03 seconds
Started Jun 23 05:33:23 PM PDT 24
Finished Jun 23 05:33:26 PM PDT 24
Peak memory 200064 kb
Host smart-e52cc340-8ac3-49f3-a993-3c72e2cd9465
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383012169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.1383012169
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1704148067
Short name T107
Test name
Test status
Simulation time 299964939 ps
CPU time 0.91 seconds
Started Jun 23 05:33:19 PM PDT 24
Finished Jun 23 05:33:20 PM PDT 24
Peak memory 199088 kb
Host smart-274c0b35-c222-49ae-99b9-361fe2489675
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704148067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.1704148067
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3085518632
Short name T1109
Test name
Test status
Simulation time 83281842 ps
CPU time 1.07 seconds
Started Jun 23 05:33:27 PM PDT 24
Finished Jun 23 05:33:29 PM PDT 24
Peak memory 199912 kb
Host smart-c959cccd-ddcb-4a67-b998-8770128db571
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085518632 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.3085518632
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.4276766946
Short name T60
Test name
Test status
Simulation time 79992147 ps
CPU time 0.61 seconds
Started Jun 23 05:33:23 PM PDT 24
Finished Jun 23 05:33:24 PM PDT 24
Peak memory 195620 kb
Host smart-b7a2dda7-6d1b-4c34-b814-218f0662a7ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276766946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.4276766946
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.2385004221
Short name T1146
Test name
Test status
Simulation time 41020683 ps
CPU time 0.58 seconds
Started Jun 23 05:33:21 PM PDT 24
Finished Jun 23 05:33:22 PM PDT 24
Peak memory 194456 kb
Host smart-6f5b192b-874e-465d-a83b-1e0c304c583f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385004221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.2385004221
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.3287207453
Short name T62
Test name
Test status
Simulation time 53139907 ps
CPU time 0.72 seconds
Started Jun 23 05:33:22 PM PDT 24
Finished Jun 23 05:33:23 PM PDT 24
Peak memory 197820 kb
Host smart-e9b8b327-a220-4999-b0f7-79b2059e9d7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287207453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.3287207453
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.2489239972
Short name T1152
Test name
Test status
Simulation time 186209945 ps
CPU time 2.3 seconds
Started Jun 23 05:33:23 PM PDT 24
Finished Jun 23 05:33:26 PM PDT 24
Peak memory 200036 kb
Host smart-857fd3b0-9d2a-40cb-9c75-a4154b0d9c89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489239972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.2489239972
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2073542537
Short name T1171
Test name
Test status
Simulation time 24458078 ps
CPU time 0.77 seconds
Started Jun 23 05:33:26 PM PDT 24
Finished Jun 23 05:33:28 PM PDT 24
Peak memory 199472 kb
Host smart-40d3fd9f-9c83-4273-af5e-d3e939fe065b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073542537 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.2073542537
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.2894957673
Short name T1151
Test name
Test status
Simulation time 63093485 ps
CPU time 0.63 seconds
Started Jun 23 05:33:27 PM PDT 24
Finished Jun 23 05:33:28 PM PDT 24
Peak memory 195524 kb
Host smart-9933d632-8d97-4577-b186-ffee4e010e6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894957673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.2894957673
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.2722485235
Short name T1158
Test name
Test status
Simulation time 54172219 ps
CPU time 0.57 seconds
Started Jun 23 05:33:28 PM PDT 24
Finished Jun 23 05:33:29 PM PDT 24
Peak memory 194420 kb
Host smart-03c33ff7-1c33-495b-a3dd-a2358b658932
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722485235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.2722485235
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.4238910009
Short name T1157
Test name
Test status
Simulation time 58705373 ps
CPU time 0.73 seconds
Started Jun 23 05:33:27 PM PDT 24
Finished Jun 23 05:33:28 PM PDT 24
Peak memory 197488 kb
Host smart-f1c9ed73-4a44-4341-a3f3-7482d3b99335
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238910009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.4238910009
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.3189130699
Short name T1119
Test name
Test status
Simulation time 173821213 ps
CPU time 2.39 seconds
Started Jun 23 05:33:30 PM PDT 24
Finished Jun 23 05:33:32 PM PDT 24
Peak memory 200036 kb
Host smart-2b7a5dbe-8aed-495d-b3dd-d6474344e819
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189130699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.3189130699
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.2242269982
Short name T1226
Test name
Test status
Simulation time 145047225 ps
CPU time 1.27 seconds
Started Jun 23 05:33:30 PM PDT 24
Finished Jun 23 05:33:32 PM PDT 24
Peak memory 199388 kb
Host smart-0c72ab31-3b02-4bbd-a3c8-3d333a6462c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242269982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.2242269982
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3175820053
Short name T1223
Test name
Test status
Simulation time 23693020 ps
CPU time 0.7 seconds
Started Jun 23 05:33:28 PM PDT 24
Finished Jun 23 05:33:29 PM PDT 24
Peak memory 198140 kb
Host smart-607b08a3-d33a-4042-bce4-f65cf60076cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175820053 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.3175820053
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.687951997
Short name T1195
Test name
Test status
Simulation time 15225230 ps
CPU time 0.63 seconds
Started Jun 23 05:33:26 PM PDT 24
Finished Jun 23 05:33:27 PM PDT 24
Peak memory 195492 kb
Host smart-5846bf70-bb3c-45e4-b6e5-c63fb9ac789e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687951997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.687951997
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.1231037142
Short name T1221
Test name
Test status
Simulation time 47156669 ps
CPU time 0.59 seconds
Started Jun 23 05:33:28 PM PDT 24
Finished Jun 23 05:33:29 PM PDT 24
Peak memory 194484 kb
Host smart-ec163489-b9ef-4af0-8b47-16c0a9eed5f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231037142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.1231037142
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3297652416
Short name T61
Test name
Test status
Simulation time 14378639 ps
CPU time 0.64 seconds
Started Jun 23 05:33:31 PM PDT 24
Finished Jun 23 05:33:32 PM PDT 24
Peak memory 196828 kb
Host smart-e2130e2a-7a94-43d3-99b1-a9132b4af86c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297652416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.3297652416
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.950211018
Short name T1192
Test name
Test status
Simulation time 384802129 ps
CPU time 1.75 seconds
Started Jun 23 05:33:26 PM PDT 24
Finished Jun 23 05:33:28 PM PDT 24
Peak memory 200092 kb
Host smart-2f61b5ea-ee1d-4962-9344-5b28cf13b43c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950211018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.950211018
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.2604265699
Short name T106
Test name
Test status
Simulation time 93829184 ps
CPU time 1.29 seconds
Started Jun 23 05:33:30 PM PDT 24
Finished Jun 23 05:33:31 PM PDT 24
Peak memory 199388 kb
Host smart-56684ccf-8f20-4a61-b71b-ac1ec7a10bd8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604265699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.2604265699
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.678499771
Short name T1130
Test name
Test status
Simulation time 21299039 ps
CPU time 0.73 seconds
Started Jun 23 05:33:29 PM PDT 24
Finished Jun 23 05:33:30 PM PDT 24
Peak memory 198312 kb
Host smart-5b7f7502-b971-47dc-8194-97b75edfe545
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678499771 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.678499771
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.1129970763
Short name T1165
Test name
Test status
Simulation time 13043641 ps
CPU time 0.59 seconds
Started Jun 23 05:33:27 PM PDT 24
Finished Jun 23 05:33:28 PM PDT 24
Peak memory 195440 kb
Host smart-c9a32cae-b664-47f5-b8f4-d23f6735bbe2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129970763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.1129970763
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.3179476401
Short name T1113
Test name
Test status
Simulation time 70825729 ps
CPU time 0.57 seconds
Started Jun 23 05:33:28 PM PDT 24
Finished Jun 23 05:33:29 PM PDT 24
Peak memory 194420 kb
Host smart-eda6876c-e999-4c97-86c1-60fb6a145d87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179476401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.3179476401
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.3592550367
Short name T59
Test name
Test status
Simulation time 31360357 ps
CPU time 0.76 seconds
Started Jun 23 05:33:25 PM PDT 24
Finished Jun 23 05:33:26 PM PDT 24
Peak memory 197248 kb
Host smart-3f77fdc6-2d42-4cf0-9c30-ea2333f49ed4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592550367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.3592550367
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.2989475215
Short name T1148
Test name
Test status
Simulation time 676249336 ps
CPU time 2.49 seconds
Started Jun 23 05:33:25 PM PDT 24
Finished Jun 23 05:33:28 PM PDT 24
Peak memory 199920 kb
Host smart-6b265a3c-f8fe-40f1-8f8c-88d3470d2a58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989475215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.2989475215
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1931759328
Short name T1163
Test name
Test status
Simulation time 100659243 ps
CPU time 1.41 seconds
Started Jun 23 05:33:27 PM PDT 24
Finished Jun 23 05:33:29 PM PDT 24
Peak memory 199592 kb
Host smart-7f7445bd-1f86-4d2a-bc7d-acd2b6a68f41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931759328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.1931759328
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.984143040
Short name T1200
Test name
Test status
Simulation time 94816496 ps
CPU time 0.8 seconds
Started Jun 23 05:32:42 PM PDT 24
Finished Jun 23 05:32:43 PM PDT 24
Peak memory 196188 kb
Host smart-b580c836-070a-4d57-8c04-2d23e55de0ac
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984143040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.984143040
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1844295599
Short name T1202
Test name
Test status
Simulation time 174649463 ps
CPU time 1.51 seconds
Started Jun 23 05:32:40 PM PDT 24
Finished Jun 23 05:32:42 PM PDT 24
Peak memory 197576 kb
Host smart-9ee46589-5d63-4b2c-8d84-eb29f65ae2f9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844295599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.1844295599
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.2267724404
Short name T1149
Test name
Test status
Simulation time 37144391 ps
CPU time 0.59 seconds
Started Jun 23 05:32:43 PM PDT 24
Finished Jun 23 05:32:44 PM PDT 24
Peak memory 195440 kb
Host smart-41d4bec8-b387-4eb9-b60d-4a579e9b7f58
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267724404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.2267724404
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.922339678
Short name T1168
Test name
Test status
Simulation time 31789115 ps
CPU time 0.81 seconds
Started Jun 23 05:32:40 PM PDT 24
Finished Jun 23 05:32:42 PM PDT 24
Peak memory 199768 kb
Host smart-27779ad8-a656-4137-8403-f4ea92be0cf0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922339678 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.922339678
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.3562502233
Short name T57
Test name
Test status
Simulation time 34094237 ps
CPU time 0.61 seconds
Started Jun 23 05:32:41 PM PDT 24
Finished Jun 23 05:32:42 PM PDT 24
Peak memory 195516 kb
Host smart-b0e34d7c-5f99-4b07-a460-f018f00d8802
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562502233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.3562502233
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.640048620
Short name T1154
Test name
Test status
Simulation time 22325090 ps
CPU time 0.56 seconds
Started Jun 23 05:32:42 PM PDT 24
Finished Jun 23 05:32:43 PM PDT 24
Peak memory 194412 kb
Host smart-083113a4-4869-4bd2-b2f4-6a319675b9e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640048620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.640048620
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.748999345
Short name T1213
Test name
Test status
Simulation time 28522990 ps
CPU time 0.75 seconds
Started Jun 23 05:32:42 PM PDT 24
Finished Jun 23 05:32:43 PM PDT 24
Peak memory 197016 kb
Host smart-5d16b29b-8b1a-481a-b175-b7285a2f0978
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748999345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr_
outstanding.748999345
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.2799791036
Short name T1167
Test name
Test status
Simulation time 131005459 ps
CPU time 1.89 seconds
Started Jun 23 05:32:36 PM PDT 24
Finished Jun 23 05:32:38 PM PDT 24
Peak memory 200056 kb
Host smart-eb2b5e63-e75c-48c3-9d4e-a794f0f5fc69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799791036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.2799791036
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.3901124512
Short name T1173
Test name
Test status
Simulation time 41494345 ps
CPU time 0.9 seconds
Started Jun 23 05:32:41 PM PDT 24
Finished Jun 23 05:32:42 PM PDT 24
Peak memory 198860 kb
Host smart-d08446c9-1094-430e-8390-66aed1d1ecde
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901124512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.3901124512
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.3334423405
Short name T1189
Test name
Test status
Simulation time 52380899 ps
CPU time 0.59 seconds
Started Jun 23 05:33:26 PM PDT 24
Finished Jun 23 05:33:27 PM PDT 24
Peak memory 194420 kb
Host smart-80a24f1d-bcdc-4e1f-9f75-75f0d3e96753
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334423405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.3334423405
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.1200210145
Short name T1228
Test name
Test status
Simulation time 23478777 ps
CPU time 0.58 seconds
Started Jun 23 05:33:28 PM PDT 24
Finished Jun 23 05:33:29 PM PDT 24
Peak memory 194424 kb
Host smart-89a8471b-544f-455d-87e6-06522ff5cf10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200210145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.1200210145
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.163095460
Short name T1176
Test name
Test status
Simulation time 13085494 ps
CPU time 0.59 seconds
Started Jun 23 05:33:32 PM PDT 24
Finished Jun 23 05:33:34 PM PDT 24
Peak memory 194460 kb
Host smart-0a193fc0-e314-4c3e-97b5-d3698b8ee47a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163095460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.163095460
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.915385797
Short name T1131
Test name
Test status
Simulation time 25977714 ps
CPU time 0.55 seconds
Started Jun 23 05:33:32 PM PDT 24
Finished Jun 23 05:33:33 PM PDT 24
Peak memory 194456 kb
Host smart-fb68ec54-80d8-44cf-8253-4aab951e6bc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915385797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.915385797
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.3704823333
Short name T1155
Test name
Test status
Simulation time 10566983 ps
CPU time 0.55 seconds
Started Jun 23 05:33:29 PM PDT 24
Finished Jun 23 05:33:30 PM PDT 24
Peak memory 194416 kb
Host smart-a8d3ec5f-5dba-4fa4-b90e-2614856894b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704823333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.3704823333
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.2299133229
Short name T1229
Test name
Test status
Simulation time 21083971 ps
CPU time 0.62 seconds
Started Jun 23 05:33:30 PM PDT 24
Finished Jun 23 05:33:31 PM PDT 24
Peak memory 194472 kb
Host smart-5467edc3-b5f6-49ea-9eac-420df787b42e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299133229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.2299133229
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.1276618026
Short name T1117
Test name
Test status
Simulation time 21200709 ps
CPU time 0.56 seconds
Started Jun 23 05:33:29 PM PDT 24
Finished Jun 23 05:33:30 PM PDT 24
Peak memory 194368 kb
Host smart-5aab8453-cd52-4451-996a-1ee417ea9856
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276618026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.1276618026
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.587482990
Short name T1161
Test name
Test status
Simulation time 17883244 ps
CPU time 0.57 seconds
Started Jun 23 05:33:32 PM PDT 24
Finished Jun 23 05:33:33 PM PDT 24
Peak memory 194364 kb
Host smart-29f5c53e-8906-42e2-9b9a-a645d748cc41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587482990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.587482990
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.2087477865
Short name T1121
Test name
Test status
Simulation time 16485833 ps
CPU time 0.6 seconds
Started Jun 23 05:33:32 PM PDT 24
Finished Jun 23 05:33:34 PM PDT 24
Peak memory 194436 kb
Host smart-15034d04-3f42-4e9a-8e77-91dcf2bb1bb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087477865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.2087477865
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.1787925069
Short name T1140
Test name
Test status
Simulation time 39038243 ps
CPU time 0.56 seconds
Started Jun 23 05:33:31 PM PDT 24
Finished Jun 23 05:33:32 PM PDT 24
Peak memory 194392 kb
Host smart-5257a783-376e-434e-ade6-c931c6106303
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787925069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.1787925069
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2780594723
Short name T1186
Test name
Test status
Simulation time 27840195 ps
CPU time 0.82 seconds
Started Jun 23 05:32:53 PM PDT 24
Finished Jun 23 05:32:55 PM PDT 24
Peak memory 196352 kb
Host smart-676c5315-dc7b-4cd0-912c-004c2982abbe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780594723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.2780594723
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.304707493
Short name T1206
Test name
Test status
Simulation time 528583129 ps
CPU time 2.51 seconds
Started Jun 23 05:32:46 PM PDT 24
Finished Jun 23 05:32:49 PM PDT 24
Peak memory 197808 kb
Host smart-745b74c8-2862-4076-84e2-474d3a943999
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304707493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.304707493
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.3002907274
Short name T1205
Test name
Test status
Simulation time 54729878 ps
CPU time 0.58 seconds
Started Jun 23 05:32:52 PM PDT 24
Finished Jun 23 05:32:53 PM PDT 24
Peak memory 195416 kb
Host smart-6a31ef0a-baff-401c-ae41-c1e16040ed96
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002907274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.3002907274
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3877819149
Short name T1122
Test name
Test status
Simulation time 35214908 ps
CPU time 0.73 seconds
Started Jun 23 05:32:51 PM PDT 24
Finished Jun 23 05:32:52 PM PDT 24
Peak memory 198436 kb
Host smart-04b6d469-d97b-43eb-acbe-b25a7ccb7cbe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877819149 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.3877819149
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.1557304772
Short name T1185
Test name
Test status
Simulation time 12267827 ps
CPU time 0.56 seconds
Started Jun 23 05:32:46 PM PDT 24
Finished Jun 23 05:32:47 PM PDT 24
Peak memory 194412 kb
Host smart-127a50d3-d202-4e86-ab2c-b3f8c211a862
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557304772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.1557304772
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2113677955
Short name T1177
Test name
Test status
Simulation time 14189296 ps
CPU time 0.69 seconds
Started Jun 23 05:32:48 PM PDT 24
Finished Jun 23 05:32:49 PM PDT 24
Peak memory 197004 kb
Host smart-aaa9ad8e-66c9-43f9-82f9-fd6fa66c9cb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113677955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.2113677955
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.2296024247
Short name T1227
Test name
Test status
Simulation time 77120284 ps
CPU time 1.09 seconds
Started Jun 23 05:32:52 PM PDT 24
Finished Jun 23 05:32:54 PM PDT 24
Peak memory 199748 kb
Host smart-2104c9e7-aff4-4a32-a7b3-a82fb0d59989
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296024247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.2296024247
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.2638416836
Short name T71
Test name
Test status
Simulation time 144678205 ps
CPU time 1.27 seconds
Started Jun 23 05:32:46 PM PDT 24
Finished Jun 23 05:32:48 PM PDT 24
Peak memory 199352 kb
Host smart-8358c4e0-af66-4cdb-898b-1b5ac8f463ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638416836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.2638416836
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.2133560975
Short name T1105
Test name
Test status
Simulation time 56626808 ps
CPU time 0.57 seconds
Started Jun 23 05:33:29 PM PDT 24
Finished Jun 23 05:33:30 PM PDT 24
Peak memory 194264 kb
Host smart-b6c67785-5c45-4634-b91e-e43092e7bb3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133560975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.2133560975
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.2770321517
Short name T1112
Test name
Test status
Simulation time 24834012 ps
CPU time 0.6 seconds
Started Jun 23 05:33:32 PM PDT 24
Finished Jun 23 05:33:34 PM PDT 24
Peak memory 194380 kb
Host smart-24a962e8-e0c0-4c05-8614-fc2af60cf555
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770321517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.2770321517
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.4050541921
Short name T1175
Test name
Test status
Simulation time 28004603 ps
CPU time 0.57 seconds
Started Jun 23 05:33:32 PM PDT 24
Finished Jun 23 05:33:33 PM PDT 24
Peak memory 194416 kb
Host smart-0edfe97a-4ab6-4198-9e58-4704308acd95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050541921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.4050541921
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.1278469965
Short name T1133
Test name
Test status
Simulation time 64763975 ps
CPU time 0.57 seconds
Started Jun 23 05:33:32 PM PDT 24
Finished Jun 23 05:33:33 PM PDT 24
Peak memory 194480 kb
Host smart-651cf3f6-7e35-4e30-afeb-216b32f36783
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278469965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.1278469965
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.4145566679
Short name T1162
Test name
Test status
Simulation time 20561443 ps
CPU time 0.6 seconds
Started Jun 23 05:33:32 PM PDT 24
Finished Jun 23 05:33:33 PM PDT 24
Peak memory 194480 kb
Host smart-5c00a9b4-ced4-4e03-b6c1-a5aeb77c8347
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145566679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.4145566679
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.492466869
Short name T1224
Test name
Test status
Simulation time 15492953 ps
CPU time 0.6 seconds
Started Jun 23 05:33:37 PM PDT 24
Finished Jun 23 05:33:38 PM PDT 24
Peak memory 194356 kb
Host smart-14068a71-0b15-4190-b03a-59fcc8361aa0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492466869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.492466869
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.1845657048
Short name T1225
Test name
Test status
Simulation time 16633066 ps
CPU time 0.6 seconds
Started Jun 23 05:33:36 PM PDT 24
Finished Jun 23 05:33:37 PM PDT 24
Peak memory 194420 kb
Host smart-99895867-97b4-4175-bebe-4df7c7c87533
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845657048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.1845657048
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.4273992112
Short name T1212
Test name
Test status
Simulation time 12105119 ps
CPU time 0.55 seconds
Started Jun 23 05:33:35 PM PDT 24
Finished Jun 23 05:33:36 PM PDT 24
Peak memory 194412 kb
Host smart-727114dc-c424-4152-8552-646092b2f0ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273992112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.4273992112
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.967042550
Short name T1125
Test name
Test status
Simulation time 111564240 ps
CPU time 0.58 seconds
Started Jun 23 05:33:36 PM PDT 24
Finished Jun 23 05:33:37 PM PDT 24
Peak memory 194424 kb
Host smart-c8fa5863-67ce-43cd-850a-c65855c5bb1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967042550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.967042550
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.2540616221
Short name T1143
Test name
Test status
Simulation time 29002389 ps
CPU time 0.57 seconds
Started Jun 23 05:33:36 PM PDT 24
Finished Jun 23 05:33:36 PM PDT 24
Peak memory 194432 kb
Host smart-745602b5-4fe6-4436-9000-daeddc633a62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540616221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.2540616221
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.3854758615
Short name T1232
Test name
Test status
Simulation time 237810493 ps
CPU time 0.63 seconds
Started Jun 23 05:32:56 PM PDT 24
Finished Jun 23 05:32:57 PM PDT 24
Peak memory 194804 kb
Host smart-4d65bffc-09e0-4cf0-9408-8d4ced4e1998
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854758615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.3854758615
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3108081192
Short name T55
Test name
Test status
Simulation time 646915052 ps
CPU time 1.6 seconds
Started Jun 23 05:33:04 PM PDT 24
Finished Jun 23 05:33:06 PM PDT 24
Peak memory 197576 kb
Host smart-cbb434c9-6d9e-4aca-8967-40f37ad44be6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108081192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.3108081192
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2061203667
Short name T1132
Test name
Test status
Simulation time 16811324 ps
CPU time 0.63 seconds
Started Jun 23 05:32:51 PM PDT 24
Finished Jun 23 05:32:52 PM PDT 24
Peak memory 195452 kb
Host smart-6e45253e-98cf-446c-9f9e-88b2c273f2e7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061203667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.2061203667
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.4165978273
Short name T1126
Test name
Test status
Simulation time 140505962 ps
CPU time 0.91 seconds
Started Jun 23 05:33:04 PM PDT 24
Finished Jun 23 05:33:06 PM PDT 24
Peak memory 199912 kb
Host smart-fc73ccee-555a-478b-8b01-15863074d7e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165978273 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.4165978273
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.2370944487
Short name T1235
Test name
Test status
Simulation time 11757881 ps
CPU time 0.59 seconds
Started Jun 23 05:32:56 PM PDT 24
Finished Jun 23 05:32:57 PM PDT 24
Peak memory 195408 kb
Host smart-cb985752-539e-4a6a-b7ce-19d0a05d5584
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370944487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.2370944487
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.3342591662
Short name T1118
Test name
Test status
Simulation time 22079454 ps
CPU time 0.58 seconds
Started Jun 23 05:32:58 PM PDT 24
Finished Jun 23 05:32:59 PM PDT 24
Peak memory 194620 kb
Host smart-3cb8dc20-ece6-4d59-a1a7-8f85d2816c28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342591662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.3342591662
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.88802016
Short name T1136
Test name
Test status
Simulation time 172808914 ps
CPU time 0.73 seconds
Started Jun 23 05:32:58 PM PDT 24
Finished Jun 23 05:32:59 PM PDT 24
Peak memory 197560 kb
Host smart-49f4751e-6b3e-43ba-b556-e5d19d26fb61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88802016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_o
utstanding.88802016
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.3940702960
Short name T1218
Test name
Test status
Simulation time 468304905 ps
CPU time 2.19 seconds
Started Jun 23 05:32:51 PM PDT 24
Finished Jun 23 05:32:54 PM PDT 24
Peak memory 200028 kb
Host smart-b3fe7e4c-8cb6-43a0-84ba-8027d35f1eb4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940702960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.3940702960
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.689461547
Short name T68
Test name
Test status
Simulation time 107580024 ps
CPU time 0.94 seconds
Started Jun 23 05:32:52 PM PDT 24
Finished Jun 23 05:32:53 PM PDT 24
Peak memory 198708 kb
Host smart-cd3d11e6-6a8f-4e45-bc44-c500b16db9b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689461547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.689461547
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.1043719885
Short name T1231
Test name
Test status
Simulation time 44063411 ps
CPU time 0.57 seconds
Started Jun 23 05:33:36 PM PDT 24
Finished Jun 23 05:33:37 PM PDT 24
Peak memory 194416 kb
Host smart-719ea3ae-e2c0-4143-81da-fb44f5bb3f92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043719885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.1043719885
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.909974948
Short name T1196
Test name
Test status
Simulation time 41141646 ps
CPU time 0.58 seconds
Started Jun 23 05:33:37 PM PDT 24
Finished Jun 23 05:33:38 PM PDT 24
Peak memory 194388 kb
Host smart-3c33cd95-ae2e-4949-a2aa-ea7b8e58df16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909974948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.909974948
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.1704892186
Short name T1138
Test name
Test status
Simulation time 29444799 ps
CPU time 0.58 seconds
Started Jun 23 05:33:37 PM PDT 24
Finished Jun 23 05:33:38 PM PDT 24
Peak memory 194420 kb
Host smart-49652424-393f-466a-b5a6-51540edc5965
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704892186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.1704892186
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.2434776891
Short name T1207
Test name
Test status
Simulation time 15280164 ps
CPU time 0.59 seconds
Started Jun 23 05:33:41 PM PDT 24
Finished Jun 23 05:33:42 PM PDT 24
Peak memory 194484 kb
Host smart-066e1ee4-a750-4870-b37d-5910ae9f7015
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434776891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.2434776891
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.4207737155
Short name T1166
Test name
Test status
Simulation time 39728392 ps
CPU time 0.58 seconds
Started Jun 23 05:33:38 PM PDT 24
Finished Jun 23 05:33:39 PM PDT 24
Peak memory 194460 kb
Host smart-a35862db-bc2b-4bc6-81f5-28533f956894
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207737155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.4207737155
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.3390730244
Short name T1137
Test name
Test status
Simulation time 14397492 ps
CPU time 0.57 seconds
Started Jun 23 05:33:44 PM PDT 24
Finished Jun 23 05:33:45 PM PDT 24
Peak memory 194368 kb
Host smart-956980fa-3857-485c-a27e-1543f1a9bea6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390730244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.3390730244
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.1480378083
Short name T1181
Test name
Test status
Simulation time 21074221 ps
CPU time 0.6 seconds
Started Jun 23 05:33:42 PM PDT 24
Finished Jun 23 05:33:43 PM PDT 24
Peak memory 194608 kb
Host smart-2710985f-9196-4b16-85b5-d4eeb0f08e96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480378083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.1480378083
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.3890642407
Short name T1197
Test name
Test status
Simulation time 16258758 ps
CPU time 0.58 seconds
Started Jun 23 05:33:39 PM PDT 24
Finished Jun 23 05:33:40 PM PDT 24
Peak memory 194420 kb
Host smart-10f850c1-053e-4eb9-bf8b-d286e99a9e35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890642407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.3890642407
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.4157617096
Short name T1217
Test name
Test status
Simulation time 12651358 ps
CPU time 0.59 seconds
Started Jun 23 05:33:42 PM PDT 24
Finished Jun 23 05:33:43 PM PDT 24
Peak memory 194420 kb
Host smart-5b26ef8d-48a9-4f46-9497-9dacee654ff0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157617096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.4157617096
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.3054651819
Short name T1123
Test name
Test status
Simulation time 23498253 ps
CPU time 0.57 seconds
Started Jun 23 05:33:43 PM PDT 24
Finished Jun 23 05:33:44 PM PDT 24
Peak memory 194432 kb
Host smart-6ea78bb0-85af-4210-a20a-aa5c90dc0b4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054651819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.3054651819
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3329289883
Short name T1172
Test name
Test status
Simulation time 17851318 ps
CPU time 0.64 seconds
Started Jun 23 05:32:57 PM PDT 24
Finished Jun 23 05:32:58 PM PDT 24
Peak memory 197300 kb
Host smart-f4e81390-0bae-4869-bbdb-3fd243c530d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329289883 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.3329289883
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.1993047447
Short name T53
Test name
Test status
Simulation time 76356832 ps
CPU time 0.61 seconds
Started Jun 23 05:32:57 PM PDT 24
Finished Jun 23 05:32:58 PM PDT 24
Peak memory 195520 kb
Host smart-aa4a1dc8-ff45-497f-bcad-bc30bd180866
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993047447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.1993047447
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.2575116020
Short name T1182
Test name
Test status
Simulation time 50561639 ps
CPU time 0.59 seconds
Started Jun 23 05:33:04 PM PDT 24
Finished Jun 23 05:33:05 PM PDT 24
Peak memory 194476 kb
Host smart-7001b8fc-0134-4b7f-8696-579a0ae7711b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575116020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.2575116020
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2820129022
Short name T1188
Test name
Test status
Simulation time 73515652 ps
CPU time 0.66 seconds
Started Jun 23 05:32:56 PM PDT 24
Finished Jun 23 05:32:57 PM PDT 24
Peak memory 196556 kb
Host smart-2e628d81-87a8-41ab-843b-428a563a38bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820129022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.2820129022
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.727670068
Short name T1187
Test name
Test status
Simulation time 283630768 ps
CPU time 2.24 seconds
Started Jun 23 05:32:56 PM PDT 24
Finished Jun 23 05:32:59 PM PDT 24
Peak memory 200028 kb
Host smart-d284625a-52ad-4f82-9842-da50ee4aa501
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727670068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.727670068
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1730291781
Short name T105
Test name
Test status
Simulation time 333179779 ps
CPU time 1.25 seconds
Started Jun 23 05:32:56 PM PDT 24
Finished Jun 23 05:32:57 PM PDT 24
Peak memory 199252 kb
Host smart-8c005b4d-8c8d-4d6a-953b-8bad265e26e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730291781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.1730291781
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.578291083
Short name T1101
Test name
Test status
Simulation time 84533729 ps
CPU time 0.78 seconds
Started Jun 23 05:33:05 PM PDT 24
Finished Jun 23 05:33:06 PM PDT 24
Peak memory 198916 kb
Host smart-5a4fcdd9-bd82-40e9-9dce-6c84c02753d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578291083 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.578291083
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.149594032
Short name T1211
Test name
Test status
Simulation time 17647514 ps
CPU time 0.64 seconds
Started Jun 23 05:33:01 PM PDT 24
Finished Jun 23 05:33:02 PM PDT 24
Peak memory 195680 kb
Host smart-4d763db3-d4e0-488b-ad32-933866ad22bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149594032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.149594032
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.2712475423
Short name T1116
Test name
Test status
Simulation time 26513269 ps
CPU time 0.61 seconds
Started Jun 23 05:33:03 PM PDT 24
Finished Jun 23 05:33:04 PM PDT 24
Peak memory 194448 kb
Host smart-a0ee2ee3-e7bf-488d-b70c-f752d1a9dc47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712475423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.2712475423
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1426810931
Short name T1156
Test name
Test status
Simulation time 28006243 ps
CPU time 0.77 seconds
Started Jun 23 05:33:04 PM PDT 24
Finished Jun 23 05:33:05 PM PDT 24
Peak memory 196892 kb
Host smart-26a1b4b2-8c68-4f07-80f0-407679473fc6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426810931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.1426810931
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.1358792347
Short name T1236
Test name
Test status
Simulation time 57775234 ps
CPU time 0.93 seconds
Started Jun 23 05:33:04 PM PDT 24
Finished Jun 23 05:33:05 PM PDT 24
Peak memory 199900 kb
Host smart-7e3ee0ce-b966-475c-bedf-8b71407b85bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358792347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.1358792347
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.315303786
Short name T67
Test name
Test status
Simulation time 82680779 ps
CPU time 1.26 seconds
Started Jun 23 05:33:03 PM PDT 24
Finished Jun 23 05:33:04 PM PDT 24
Peak memory 199344 kb
Host smart-0af9065e-2645-4b72-b4f5-93db97ea32b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315303786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.315303786
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1091076
Short name T1100
Test name
Test status
Simulation time 16348595 ps
CPU time 0.68 seconds
Started Jun 23 05:33:11 PM PDT 24
Finished Jun 23 05:33:12 PM PDT 24
Peak memory 197888 kb
Host smart-16219c07-f6b0-4b4b-8a32-559955b20ad4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091076 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.1091076
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.2112401930
Short name T1134
Test name
Test status
Simulation time 13362769 ps
CPU time 0.6 seconds
Started Jun 23 05:33:07 PM PDT 24
Finished Jun 23 05:33:08 PM PDT 24
Peak memory 195436 kb
Host smart-424f20ad-e38d-4570-bfe8-bf7fab017dd8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112401930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.2112401930
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.200786556
Short name T1139
Test name
Test status
Simulation time 15478450 ps
CPU time 0.61 seconds
Started Jun 23 05:33:01 PM PDT 24
Finished Jun 23 05:33:02 PM PDT 24
Peak memory 194368 kb
Host smart-574a4202-8332-4d6f-a0dd-8b27e87182c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200786556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.200786556
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1600553955
Short name T1160
Test name
Test status
Simulation time 70014659 ps
CPU time 0.63 seconds
Started Jun 23 05:33:08 PM PDT 24
Finished Jun 23 05:33:09 PM PDT 24
Peak memory 194580 kb
Host smart-941f299f-a6ad-42d8-ac68-98fbe638c7aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600553955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.1600553955
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.470768072
Short name T1120
Test name
Test status
Simulation time 20254674 ps
CPU time 1.13 seconds
Started Jun 23 05:33:03 PM PDT 24
Finished Jun 23 05:33:04 PM PDT 24
Peak memory 199912 kb
Host smart-f36ceb99-ab80-4b43-9bfa-0111a532f7af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470768072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.470768072
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1998901890
Short name T1210
Test name
Test status
Simulation time 772051316 ps
CPU time 1.3 seconds
Started Jun 23 05:33:02 PM PDT 24
Finished Jun 23 05:33:04 PM PDT 24
Peak memory 199364 kb
Host smart-a72bfb0f-0e86-48db-995d-fa7ef8fddb55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998901890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.1998901890
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2037406771
Short name T1179
Test name
Test status
Simulation time 82522490 ps
CPU time 1.11 seconds
Started Jun 23 05:33:08 PM PDT 24
Finished Jun 23 05:33:09 PM PDT 24
Peak memory 199916 kb
Host smart-a64547d0-e6fb-4ff5-b7e3-5a6b3e3ca348
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037406771 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.2037406771
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.1987744499
Short name T51
Test name
Test status
Simulation time 13668434 ps
CPU time 0.59 seconds
Started Jun 23 05:33:11 PM PDT 24
Finished Jun 23 05:33:12 PM PDT 24
Peak memory 195436 kb
Host smart-d208201c-9b01-45d2-bd7b-0d828d3ef231
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987744499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.1987744499
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.1364018589
Short name T1114
Test name
Test status
Simulation time 41832419 ps
CPU time 0.57 seconds
Started Jun 23 05:33:09 PM PDT 24
Finished Jun 23 05:33:10 PM PDT 24
Peak memory 194408 kb
Host smart-58e0df39-7375-4ff6-a85c-d570558118b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364018589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.1364018589
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.2813418754
Short name T1193
Test name
Test status
Simulation time 58557938 ps
CPU time 0.64 seconds
Started Jun 23 05:33:07 PM PDT 24
Finished Jun 23 05:33:07 PM PDT 24
Peak memory 196552 kb
Host smart-c50b9d0f-5ddd-421c-b806-6693841616ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813418754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.2813418754
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.1654176770
Short name T1104
Test name
Test status
Simulation time 42055057 ps
CPU time 2.19 seconds
Started Jun 23 05:33:06 PM PDT 24
Finished Jun 23 05:33:09 PM PDT 24
Peak memory 200024 kb
Host smart-d3eff6fc-70c3-4afc-a202-9b2e7efad011
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654176770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.1654176770
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.1817673592
Short name T1220
Test name
Test status
Simulation time 88801456 ps
CPU time 1.32 seconds
Started Jun 23 05:33:10 PM PDT 24
Finished Jun 23 05:33:11 PM PDT 24
Peak memory 199392 kb
Host smart-7d91d82a-d76a-4e5e-be2f-21c535da6fa1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817673592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.1817673592
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3520832317
Short name T1219
Test name
Test status
Simulation time 38209506 ps
CPU time 0.68 seconds
Started Jun 23 05:33:13 PM PDT 24
Finished Jun 23 05:33:14 PM PDT 24
Peak memory 198676 kb
Host smart-f484c442-ed35-4099-b39b-660fe694deca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520832317 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.3520832317
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.1786645056
Short name T58
Test name
Test status
Simulation time 101769107 ps
CPU time 0.6 seconds
Started Jun 23 05:33:07 PM PDT 24
Finished Jun 23 05:33:08 PM PDT 24
Peak memory 195436 kb
Host smart-ec8952a9-c199-4d0f-8604-714e4acfa0f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786645056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.1786645056
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.1299390480
Short name T1198
Test name
Test status
Simulation time 15371801 ps
CPU time 0.57 seconds
Started Jun 23 05:33:06 PM PDT 24
Finished Jun 23 05:33:07 PM PDT 24
Peak memory 194396 kb
Host smart-f15951b4-42f2-49cf-a666-87d3ee917a13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299390480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.1299390480
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2326665050
Short name T1180
Test name
Test status
Simulation time 17878682 ps
CPU time 0.66 seconds
Started Jun 23 05:33:13 PM PDT 24
Finished Jun 23 05:33:14 PM PDT 24
Peak memory 195852 kb
Host smart-fc9c0d20-a7df-4014-a5d4-5cd2c56b497c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326665050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.2326665050
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.1650310813
Short name T1190
Test name
Test status
Simulation time 174259277 ps
CPU time 1.93 seconds
Started Jun 23 05:33:04 PM PDT 24
Finished Jun 23 05:33:07 PM PDT 24
Peak memory 200052 kb
Host smart-eeecf991-4d72-47b8-9af8-b35e50940cc3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650310813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.1650310813
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.616227935
Short name T1215
Test name
Test status
Simulation time 253588644 ps
CPU time 1.34 seconds
Started Jun 23 05:33:07 PM PDT 24
Finished Jun 23 05:33:08 PM PDT 24
Peak memory 199276 kb
Host smart-63365736-5ecc-4870-9163-3b7000c201f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616227935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.616227935
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.107345626
Short name T439
Test name
Test status
Simulation time 33486862 ps
CPU time 0.56 seconds
Started Jun 23 05:39:45 PM PDT 24
Finished Jun 23 05:39:46 PM PDT 24
Peak memory 195984 kb
Host smart-648571a4-7515-4279-8b4c-3e9e72b93f14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107345626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.107345626
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.2639977218
Short name T901
Test name
Test status
Simulation time 258940310526 ps
CPU time 394.63 seconds
Started Jun 23 05:39:43 PM PDT 24
Finished Jun 23 05:46:18 PM PDT 24
Peak memory 200716 kb
Host smart-a64f93fa-df6b-4a1c-b2c1-91a88c29bbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639977218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.2639977218
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.1166916218
Short name T751
Test name
Test status
Simulation time 51095281733 ps
CPU time 36.1 seconds
Started Jun 23 05:39:43 PM PDT 24
Finished Jun 23 05:40:19 PM PDT 24
Peak memory 200400 kb
Host smart-e2b09f45-faa2-4d0b-a2d8-515bc5568244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166916218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.1166916218
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.3712768658
Short name T1098
Test name
Test status
Simulation time 158306605354 ps
CPU time 25.48 seconds
Started Jun 23 05:39:47 PM PDT 24
Finished Jun 23 05:40:13 PM PDT 24
Peak memory 200748 kb
Host smart-0918fc01-b81e-40b8-a303-392880780eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712768658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.3712768658
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.4214189936
Short name T91
Test name
Test status
Simulation time 112673926632 ps
CPU time 161.93 seconds
Started Jun 23 05:39:44 PM PDT 24
Finished Jun 23 05:42:26 PM PDT 24
Peak memory 200656 kb
Host smart-2eb0a7d0-8775-4eca-84e5-be86a6d31fa0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4214189936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.4214189936
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.1798888062
Short name T792
Test name
Test status
Simulation time 1731134091 ps
CPU time 2.2 seconds
Started Jun 23 05:39:43 PM PDT 24
Finished Jun 23 05:39:45 PM PDT 24
Peak memory 196144 kb
Host smart-d2800eea-e67f-465f-bb8d-d4b9b78de714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798888062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.1798888062
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_perf.4250604776
Short name T546
Test name
Test status
Simulation time 33738985494 ps
CPU time 410.19 seconds
Started Jun 23 05:39:51 PM PDT 24
Finished Jun 23 05:46:42 PM PDT 24
Peak memory 200640 kb
Host smart-ade353cc-696b-4ec5-97ab-9709e86dbf50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4250604776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.4250604776
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.1796159678
Short name T951
Test name
Test status
Simulation time 5061696836 ps
CPU time 22.24 seconds
Started Jun 23 05:39:46 PM PDT 24
Finished Jun 23 05:40:09 PM PDT 24
Peak memory 200104 kb
Host smart-d8546f3e-56e9-499b-a4db-b5daf571b8dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1796159678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.1796159678
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.3386126889
Short name T864
Test name
Test status
Simulation time 126329308635 ps
CPU time 156.24 seconds
Started Jun 23 05:39:51 PM PDT 24
Finished Jun 23 05:42:28 PM PDT 24
Peak memory 200640 kb
Host smart-064c1b13-5aa7-4b36-8ea3-802da90c453d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386126889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.3386126889
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.2424948345
Short name T725
Test name
Test status
Simulation time 3463701429 ps
CPU time 1.57 seconds
Started Jun 23 05:39:51 PM PDT 24
Finished Jun 23 05:39:53 PM PDT 24
Peak memory 196980 kb
Host smart-ffe41eff-cd90-4bc3-9d46-4b087d6bc3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424948345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.2424948345
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.3036177376
Short name T1016
Test name
Test status
Simulation time 928632716 ps
CPU time 4.68 seconds
Started Jun 23 05:39:45 PM PDT 24
Finished Jun 23 05:39:50 PM PDT 24
Peak memory 200584 kb
Host smart-09779059-e87d-4799-bcbf-9a1d030cc710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036177376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.3036177376
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.3500423202
Short name T1058
Test name
Test status
Simulation time 243297375547 ps
CPU time 113.62 seconds
Started Jun 23 05:39:44 PM PDT 24
Finished Jun 23 05:41:38 PM PDT 24
Peak memory 200680 kb
Host smart-a7d2e489-7111-49f3-b802-65cc6a86ee32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500423202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.3500423202
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.49965981
Short name T159
Test name
Test status
Simulation time 84266262262 ps
CPU time 347.79 seconds
Started Jun 23 05:39:44 PM PDT 24
Finished Jun 23 05:45:32 PM PDT 24
Peak memory 217132 kb
Host smart-8a552747-6eca-4833-bca0-329a23df86eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49965981 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.49965981
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.2993502536
Short name T1086
Test name
Test status
Simulation time 414608064 ps
CPU time 1.11 seconds
Started Jun 23 05:39:46 PM PDT 24
Finished Jun 23 05:39:48 PM PDT 24
Peak memory 198596 kb
Host smart-358e7a88-a0b4-4b6d-9fdb-c1f43d993f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993502536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.2993502536
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.2519886647
Short name T693
Test name
Test status
Simulation time 72679794070 ps
CPU time 93.79 seconds
Started Jun 23 05:39:51 PM PDT 24
Finished Jun 23 05:41:25 PM PDT 24
Peak memory 200604 kb
Host smart-de6a2ba3-708f-4e06-8286-96b7782ed57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519886647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.2519886647
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.3820481642
Short name T667
Test name
Test status
Simulation time 24259058 ps
CPU time 0.57 seconds
Started Jun 23 05:39:51 PM PDT 24
Finished Jun 23 05:39:53 PM PDT 24
Peak memory 196084 kb
Host smart-bf8e4276-4d9f-43ea-84a6-5a88e9979b8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820481642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.3820481642
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.267248215
Short name T799
Test name
Test status
Simulation time 52214532484 ps
CPU time 87.02 seconds
Started Jun 23 05:39:44 PM PDT 24
Finished Jun 23 05:41:11 PM PDT 24
Peak memory 200660 kb
Host smart-d85004c5-09fe-46cb-b1e1-c83abccc011f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267248215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.267248215
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.1664577460
Short name T256
Test name
Test status
Simulation time 66740646894 ps
CPU time 78.62 seconds
Started Jun 23 05:39:45 PM PDT 24
Finished Jun 23 05:41:04 PM PDT 24
Peak memory 200636 kb
Host smart-31733af5-c0a1-4837-850c-d5363f8e230c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664577460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.1664577460
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_intr.697278823
Short name T625
Test name
Test status
Simulation time 1150312368 ps
CPU time 2.21 seconds
Started Jun 23 05:39:51 PM PDT 24
Finished Jun 23 05:39:54 PM PDT 24
Peak memory 196340 kb
Host smart-282eabd3-5315-44cb-b97f-ae5423925250
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697278823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.697278823
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.3710523232
Short name T371
Test name
Test status
Simulation time 148885183573 ps
CPU time 331.06 seconds
Started Jun 23 05:39:51 PM PDT 24
Finished Jun 23 05:45:23 PM PDT 24
Peak memory 200728 kb
Host smart-c51d77d6-dd94-4315-8f41-7b880a55e2ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3710523232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.3710523232
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.1583312712
Short name T919
Test name
Test status
Simulation time 3850346865 ps
CPU time 8.89 seconds
Started Jun 23 05:39:47 PM PDT 24
Finished Jun 23 05:39:56 PM PDT 24
Peak memory 200420 kb
Host smart-e94ea87a-3421-41bb-8ae8-1fe51dfb3d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583312712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.1583312712
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_perf.551770743
Short name T461
Test name
Test status
Simulation time 6830791085 ps
CPU time 416.52 seconds
Started Jun 23 05:39:49 PM PDT 24
Finished Jun 23 05:46:46 PM PDT 24
Peak memory 200772 kb
Host smart-16570e6d-0689-4e2e-81d1-0dc5fbd5fde3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=551770743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.551770743
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.2624256652
Short name T1008
Test name
Test status
Simulation time 5384199491 ps
CPU time 43.11 seconds
Started Jun 23 05:39:50 PM PDT 24
Finished Jun 23 05:40:34 PM PDT 24
Peak memory 199636 kb
Host smart-90640864-81cc-4537-9001-ad7926e24bfa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2624256652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.2624256652
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.3808531783
Short name T40
Test name
Test status
Simulation time 40687995279 ps
CPU time 29.62 seconds
Started Jun 23 05:39:52 PM PDT 24
Finished Jun 23 05:40:22 PM PDT 24
Peak memory 200388 kb
Host smart-8b58ba94-d67f-43c7-bfa5-70f8f5026ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808531783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.3808531783
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.1109585038
Short name T910
Test name
Test status
Simulation time 5863004057 ps
CPU time 4.28 seconds
Started Jun 23 05:39:49 PM PDT 24
Finished Jun 23 05:39:53 PM PDT 24
Peak memory 196820 kb
Host smart-b181b0de-373b-4ef3-bd67-5d94dec0e098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109585038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.1109585038
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.1934809104
Short name T74
Test name
Test status
Simulation time 129104064 ps
CPU time 0.76 seconds
Started Jun 23 05:39:50 PM PDT 24
Finished Jun 23 05:39:52 PM PDT 24
Peak memory 219144 kb
Host smart-24bcad1a-198e-4318-abeb-1a8b3010e06c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934809104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.1934809104
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.2279572684
Short name T602
Test name
Test status
Simulation time 5977337539 ps
CPU time 8.98 seconds
Started Jun 23 05:39:42 PM PDT 24
Finished Jun 23 05:39:51 PM PDT 24
Peak memory 200436 kb
Host smart-7ea699e8-a4b1-4cb1-91ef-d05148a5dd47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279572684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.2279572684
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.2591984403
Short name T655
Test name
Test status
Simulation time 109750842125 ps
CPU time 161 seconds
Started Jun 23 05:39:48 PM PDT 24
Finished Jun 23 05:42:29 PM PDT 24
Peak memory 200680 kb
Host smart-1b7b874d-42b1-4066-8960-e76768b24193
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591984403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.2591984403
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.1225194693
Short name T4
Test name
Test status
Simulation time 18182055535 ps
CPU time 235.02 seconds
Started Jun 23 05:39:51 PM PDT 24
Finished Jun 23 05:43:47 PM PDT 24
Peak memory 200604 kb
Host smart-46b887b0-1bda-49d2-998d-491a7182b335
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225194693 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.1225194693
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.537792202
Short name T778
Test name
Test status
Simulation time 2174626411 ps
CPU time 1.54 seconds
Started Jun 23 05:39:49 PM PDT 24
Finished Jun 23 05:39:50 PM PDT 24
Peak memory 199948 kb
Host smart-a5a962bc-a27c-4160-abf7-b384afebdcf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537792202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.537792202
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.2828648944
Short name T320
Test name
Test status
Simulation time 132490032518 ps
CPU time 106.96 seconds
Started Jun 23 05:39:45 PM PDT 24
Finished Jun 23 05:41:33 PM PDT 24
Peak memory 200620 kb
Host smart-459cca2a-9261-4f91-8231-8aaa57ca82fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828648944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.2828648944
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.107112148
Short name T595
Test name
Test status
Simulation time 20552954 ps
CPU time 0.54 seconds
Started Jun 23 05:40:20 PM PDT 24
Finished Jun 23 05:40:21 PM PDT 24
Peak memory 195436 kb
Host smart-f77e33f3-1293-4b58-9962-0a616d68895d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107112148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.107112148
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.1776477451
Short name T654
Test name
Test status
Simulation time 21598876782 ps
CPU time 15.68 seconds
Started Jun 23 05:40:18 PM PDT 24
Finished Jun 23 05:40:35 PM PDT 24
Peak memory 200692 kb
Host smart-58ea3cbc-549c-41c7-bbf5-8c02c592c715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776477451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.1776477451
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.4279958498
Short name T259
Test name
Test status
Simulation time 96593192984 ps
CPU time 173.81 seconds
Started Jun 23 05:40:17 PM PDT 24
Finished Jun 23 05:43:11 PM PDT 24
Peak memory 200720 kb
Host smart-45355e9d-3fed-46e9-b101-27fff460d3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279958498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.4279958498
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.1877559270
Short name T525
Test name
Test status
Simulation time 36284850819 ps
CPU time 57.44 seconds
Started Jun 23 05:40:16 PM PDT 24
Finished Jun 23 05:41:14 PM PDT 24
Peak memory 200772 kb
Host smart-549e44e9-adb5-4730-a062-9783d12cc26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877559270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.1877559270
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.1564721993
Short name T906
Test name
Test status
Simulation time 14272658903 ps
CPU time 7.86 seconds
Started Jun 23 05:40:18 PM PDT 24
Finished Jun 23 05:40:26 PM PDT 24
Peak memory 200216 kb
Host smart-af7a6a31-3a8c-4060-84e6-5ad74d90daba
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564721993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.1564721993
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.3373886385
Short name T702
Test name
Test status
Simulation time 78792271560 ps
CPU time 230.01 seconds
Started Jun 23 05:40:18 PM PDT 24
Finished Jun 23 05:44:09 PM PDT 24
Peak memory 200708 kb
Host smart-dd3dd254-4e99-4297-a736-5f6c1ac5429a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3373886385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.3373886385
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.3111881664
Short name T307
Test name
Test status
Simulation time 11666736170 ps
CPU time 7.58 seconds
Started Jun 23 05:40:20 PM PDT 24
Finished Jun 23 05:40:28 PM PDT 24
Peak memory 200412 kb
Host smart-6b0861e5-c19c-431f-bf34-e845c6bbe4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111881664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.3111881664
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.1524382268
Short name T744
Test name
Test status
Simulation time 47329972399 ps
CPU time 94.45 seconds
Started Jun 23 05:40:18 PM PDT 24
Finished Jun 23 05:41:53 PM PDT 24
Peak memory 200708 kb
Host smart-cb1703ff-6fb0-472f-a636-3c553a559fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524382268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.1524382268
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.2213753079
Short name T681
Test name
Test status
Simulation time 32341182986 ps
CPU time 1774.02 seconds
Started Jun 23 05:40:17 PM PDT 24
Finished Jun 23 06:09:52 PM PDT 24
Peak memory 200724 kb
Host smart-e4309a08-924b-4b30-8ac0-44b173986aca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2213753079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.2213753079
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.1012056140
Short name T731
Test name
Test status
Simulation time 2745153901 ps
CPU time 9.34 seconds
Started Jun 23 05:40:19 PM PDT 24
Finished Jun 23 05:40:29 PM PDT 24
Peak memory 199072 kb
Host smart-c2e01575-93b9-480f-af84-6e6d98272fef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1012056140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.1012056140
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.2503738521
Short name T1044
Test name
Test status
Simulation time 31219365573 ps
CPU time 52.69 seconds
Started Jun 23 05:40:18 PM PDT 24
Finished Jun 23 05:41:12 PM PDT 24
Peak memory 200696 kb
Host smart-833c4312-f1c7-4897-b8bc-94c071772a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503738521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.2503738521
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.4127088937
Short name T532
Test name
Test status
Simulation time 3265379066 ps
CPU time 5.86 seconds
Started Jun 23 05:40:19 PM PDT 24
Finished Jun 23 05:40:26 PM PDT 24
Peak memory 196936 kb
Host smart-7ca95c7c-e9e6-45e9-833a-30eabe63b707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127088937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.4127088937
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.142159715
Short name T1034
Test name
Test status
Simulation time 103208322 ps
CPU time 0.93 seconds
Started Jun 23 05:40:17 PM PDT 24
Finished Jun 23 05:40:18 PM PDT 24
Peak memory 197884 kb
Host smart-c407af3a-9a48-4e41-ac7d-d414d719baf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142159715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.142159715
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.3400808580
Short name T819
Test name
Test status
Simulation time 485188680870 ps
CPU time 832.82 seconds
Started Jun 23 05:40:19 PM PDT 24
Finished Jun 23 05:54:13 PM PDT 24
Peak memory 225244 kb
Host smart-898635be-825c-4426-9cc1-7b3889090d46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400808580 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.3400808580
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.3699837090
Short name T605
Test name
Test status
Simulation time 6072699127 ps
CPU time 18.79 seconds
Started Jun 23 05:40:16 PM PDT 24
Finished Jun 23 05:40:36 PM PDT 24
Peak memory 200744 kb
Host smart-c3496554-3c1d-4608-be21-190411d7f175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699837090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.3699837090
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.1602789903
Short name T386
Test name
Test status
Simulation time 9376815721 ps
CPU time 15.85 seconds
Started Jun 23 05:40:19 PM PDT 24
Finished Jun 23 05:40:36 PM PDT 24
Peak memory 200628 kb
Host smart-ece4521a-ef87-4ae1-8737-164ec8641e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602789903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.1602789903
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.2522364195
Short name T818
Test name
Test status
Simulation time 36749214610 ps
CPU time 55.01 seconds
Started Jun 23 05:44:21 PM PDT 24
Finished Jun 23 05:45:17 PM PDT 24
Peak memory 200692 kb
Host smart-03e95c5a-40bc-4690-aa2e-57bdee194504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522364195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.2522364195
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.2524429932
Short name T1027
Test name
Test status
Simulation time 151009499885 ps
CPU time 56.35 seconds
Started Jun 23 05:44:23 PM PDT 24
Finished Jun 23 05:45:20 PM PDT 24
Peak memory 200652 kb
Host smart-28b0946d-e078-4347-96ad-04605728ac3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524429932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.2524429932
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.102038705
Short name T399
Test name
Test status
Simulation time 38646062945 ps
CPU time 60.17 seconds
Started Jun 23 05:44:23 PM PDT 24
Finished Jun 23 05:45:23 PM PDT 24
Peak memory 200700 kb
Host smart-378fc86c-3284-44c3-96a6-8e7f54ae8091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102038705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.102038705
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.2438425664
Short name T457
Test name
Test status
Simulation time 33880363879 ps
CPU time 20.59 seconds
Started Jun 23 05:44:22 PM PDT 24
Finished Jun 23 05:44:43 PM PDT 24
Peak memory 200688 kb
Host smart-86bc717b-dd83-4830-9a66-6409fc361073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438425664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.2438425664
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.3595936213
Short name T318
Test name
Test status
Simulation time 147814004440 ps
CPU time 174.64 seconds
Started Jun 23 05:44:20 PM PDT 24
Finished Jun 23 05:47:15 PM PDT 24
Peak memory 200612 kb
Host smart-5b087210-27e9-4931-82d7-eb6c0968ae64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595936213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.3595936213
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.3123138780
Short name T88
Test name
Test status
Simulation time 12184043986 ps
CPU time 21.74 seconds
Started Jun 23 05:44:22 PM PDT 24
Finished Jun 23 05:44:45 PM PDT 24
Peak memory 200716 kb
Host smart-201e84a9-15c4-4639-ae10-c82322449194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123138780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.3123138780
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.4251685670
Short name T512
Test name
Test status
Simulation time 85481791564 ps
CPU time 253.26 seconds
Started Jun 23 05:44:23 PM PDT 24
Finished Jun 23 05:48:37 PM PDT 24
Peak memory 200728 kb
Host smart-406e6760-b6f8-4f50-a048-b6ea9acfd339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251685670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.4251685670
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.1676729709
Short name T746
Test name
Test status
Simulation time 19075637563 ps
CPU time 17.51 seconds
Started Jun 23 05:44:22 PM PDT 24
Finished Jun 23 05:44:40 PM PDT 24
Peak memory 200632 kb
Host smart-b5457abd-8fa1-43d7-8df4-751a1489f5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676729709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.1676729709
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.3272911803
Short name T281
Test name
Test status
Simulation time 200876073356 ps
CPU time 37.5 seconds
Started Jun 23 05:44:22 PM PDT 24
Finished Jun 23 05:45:00 PM PDT 24
Peak memory 200700 kb
Host smart-7c8d7f8a-c3cd-439d-81b2-1d9953d6ec48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272911803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.3272911803
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.129532407
Short name T438
Test name
Test status
Simulation time 13259468 ps
CPU time 0.57 seconds
Started Jun 23 05:40:25 PM PDT 24
Finished Jun 23 05:40:26 PM PDT 24
Peak memory 196100 kb
Host smart-5aaaa08f-3686-41e9-abab-ff9c76a9dbcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129532407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.129532407
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.1973966566
Short name T3
Test name
Test status
Simulation time 120756855925 ps
CPU time 46.4 seconds
Started Jun 23 05:40:19 PM PDT 24
Finished Jun 23 05:41:07 PM PDT 24
Peak memory 200624 kb
Host smart-c914a7a7-d8a5-48dd-b20a-b3ccd34aaa2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973966566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.1973966566
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.1795715715
Short name T578
Test name
Test status
Simulation time 23631983524 ps
CPU time 29.65 seconds
Started Jun 23 05:40:21 PM PDT 24
Finished Jun 23 05:40:51 PM PDT 24
Peak memory 200704 kb
Host smart-db25bfd5-813d-4027-9e89-d244eb883f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795715715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.1795715715
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.188096775
Short name T279
Test name
Test status
Simulation time 8853211771 ps
CPU time 15.42 seconds
Started Jun 23 05:40:24 PM PDT 24
Finished Jun 23 05:40:40 PM PDT 24
Peak memory 200720 kb
Host smart-1a953f9d-3a0e-40f3-874c-0c0a8a76fc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188096775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.188096775
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.2678329902
Short name T16
Test name
Test status
Simulation time 19439467992 ps
CPU time 11.57 seconds
Started Jun 23 05:40:24 PM PDT 24
Finished Jun 23 05:40:36 PM PDT 24
Peak memory 199616 kb
Host smart-154d3059-b52d-4fcb-9b82-d6549732ad15
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678329902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.2678329902
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.3056121442
Short name T419
Test name
Test status
Simulation time 47910702641 ps
CPU time 285.65 seconds
Started Jun 23 05:40:30 PM PDT 24
Finished Jun 23 05:45:16 PM PDT 24
Peak memory 200672 kb
Host smart-a76aad92-430f-49b0-b80c-511a20b033e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3056121442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.3056121442
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.1727166742
Short name T627
Test name
Test status
Simulation time 6558517408 ps
CPU time 13.6 seconds
Started Jun 23 05:40:22 PM PDT 24
Finished Jun 23 05:40:36 PM PDT 24
Peak memory 200340 kb
Host smart-5ef3bf76-cc89-495b-8959-d33a58f98e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727166742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.1727166742
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_perf.2605052673
Short name T524
Test name
Test status
Simulation time 14521800999 ps
CPU time 210.33 seconds
Started Jun 23 05:40:26 PM PDT 24
Finished Jun 23 05:43:57 PM PDT 24
Peak memory 200676 kb
Host smart-8b3095c6-ecc2-4da2-8241-08c01812d1b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2605052673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.2605052673
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.1709739938
Short name T390
Test name
Test status
Simulation time 7663952615 ps
CPU time 63.5 seconds
Started Jun 23 05:40:23 PM PDT 24
Finished Jun 23 05:41:27 PM PDT 24
Peak memory 200128 kb
Host smart-aff8f4f3-8188-4a5c-9cbd-6ccef8496174
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1709739938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.1709739938
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.1289934038
Short name T124
Test name
Test status
Simulation time 20938246229 ps
CPU time 28.79 seconds
Started Jun 23 05:40:20 PM PDT 24
Finished Jun 23 05:40:50 PM PDT 24
Peak memory 200312 kb
Host smart-8d99f15b-85c9-4021-b0f0-0eb3d80bfd6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289934038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.1289934038
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.1072561926
Short name T614
Test name
Test status
Simulation time 30538504536 ps
CPU time 6.05 seconds
Started Jun 23 05:40:20 PM PDT 24
Finished Jun 23 05:40:27 PM PDT 24
Peak memory 196808 kb
Host smart-5fdfeae4-6801-4937-b64d-07cd63e4fb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072561926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.1072561926
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.2338496322
Short name T531
Test name
Test status
Simulation time 5367121751 ps
CPU time 12.39 seconds
Started Jun 23 05:40:22 PM PDT 24
Finished Jun 23 05:40:35 PM PDT 24
Peak memory 200024 kb
Host smart-3a8425fa-507e-4d41-808d-53d1279db605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338496322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.2338496322
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.657513637
Short name T451
Test name
Test status
Simulation time 228987924159 ps
CPU time 105.66 seconds
Started Jun 23 05:40:25 PM PDT 24
Finished Jun 23 05:42:11 PM PDT 24
Peak memory 200644 kb
Host smart-57230980-6e89-4818-aa4b-9e8f14a250a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657513637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.657513637
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.3821401826
Short name T272
Test name
Test status
Simulation time 15239663340 ps
CPU time 20.71 seconds
Started Jun 23 05:40:24 PM PDT 24
Finished Jun 23 05:40:45 PM PDT 24
Peak memory 200716 kb
Host smart-578bf75b-3df9-4da8-bcbb-4219b3f53ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821401826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.3821401826
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.3960271889
Short name T239
Test name
Test status
Simulation time 38403827344 ps
CPU time 11.69 seconds
Started Jun 23 05:40:23 PM PDT 24
Finished Jun 23 05:40:35 PM PDT 24
Peak memory 200648 kb
Host smart-23afc7e2-5401-4d20-85b3-03eb61885cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960271889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.3960271889
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.1426204882
Short name T769
Test name
Test status
Simulation time 111374713398 ps
CPU time 46.25 seconds
Started Jun 23 05:44:22 PM PDT 24
Finished Jun 23 05:45:09 PM PDT 24
Peak memory 200720 kb
Host smart-befcfd83-afb2-4fe8-8f28-e65cecec6919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426204882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.1426204882
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.2558261341
Short name T436
Test name
Test status
Simulation time 92934679972 ps
CPU time 77.3 seconds
Started Jun 23 05:44:21 PM PDT 24
Finished Jun 23 05:45:38 PM PDT 24
Peak memory 200692 kb
Host smart-78bca42f-4d34-4e9f-8cb4-d5d2fc2bea8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558261341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.2558261341
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.2941523785
Short name T837
Test name
Test status
Simulation time 159816146772 ps
CPU time 65.52 seconds
Started Jun 23 05:44:24 PM PDT 24
Finished Jun 23 05:45:30 PM PDT 24
Peak memory 200588 kb
Host smart-82256ce3-8620-4568-a13d-a661b540d445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941523785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.2941523785
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.14678984
Short name T883
Test name
Test status
Simulation time 38682987267 ps
CPU time 64.77 seconds
Started Jun 23 05:44:20 PM PDT 24
Finished Jun 23 05:45:25 PM PDT 24
Peak memory 200648 kb
Host smart-c82cb1d1-7b4b-4f4c-b480-4ca88b7674a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14678984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.14678984
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.3870416850
Short name T93
Test name
Test status
Simulation time 18312760405 ps
CPU time 36.74 seconds
Started Jun 23 05:44:18 PM PDT 24
Finished Jun 23 05:44:55 PM PDT 24
Peak memory 200740 kb
Host smart-5d92ff06-0803-4209-a582-2fa5a5f4ae8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870416850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.3870416850
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.476130602
Short name T821
Test name
Test status
Simulation time 42408369497 ps
CPU time 38.41 seconds
Started Jun 23 05:44:25 PM PDT 24
Finished Jun 23 05:45:04 PM PDT 24
Peak memory 200760 kb
Host smart-ff99b471-0a2d-4c6f-a0d7-03f57a1b0647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476130602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.476130602
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.1105386310
Short name T130
Test name
Test status
Simulation time 58906489388 ps
CPU time 93.17 seconds
Started Jun 23 05:44:27 PM PDT 24
Finished Jun 23 05:46:01 PM PDT 24
Peak memory 200620 kb
Host smart-9ec2e02e-b3c4-40e7-a268-2229ede25eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105386310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.1105386310
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.1702150620
Short name T506
Test name
Test status
Simulation time 12695564 ps
CPU time 0.57 seconds
Started Jun 23 05:40:32 PM PDT 24
Finished Jun 23 05:40:33 PM PDT 24
Peak memory 195072 kb
Host smart-f1c50b86-eeb4-497a-9126-fac923e49f6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702150620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.1702150620
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.3341677605
Short name T403
Test name
Test status
Simulation time 35998177061 ps
CPU time 30.49 seconds
Started Jun 23 05:40:24 PM PDT 24
Finished Jun 23 05:40:55 PM PDT 24
Peak memory 200924 kb
Host smart-2b4638dc-de2a-41d5-bbdb-ad84be5809ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341677605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.3341677605
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_intr.3303912352
Short name T276
Test name
Test status
Simulation time 18296375535 ps
CPU time 30.08 seconds
Started Jun 23 05:40:26 PM PDT 24
Finished Jun 23 05:40:57 PM PDT 24
Peak memory 200212 kb
Host smart-b474cb3e-d88b-4fae-b7e5-edce93ee0241
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303912352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.3303912352
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.2153792714
Short name T993
Test name
Test status
Simulation time 153739973903 ps
CPU time 158.09 seconds
Started Jun 23 05:40:32 PM PDT 24
Finished Jun 23 05:43:10 PM PDT 24
Peak memory 200708 kb
Host smart-48bd3fee-5e91-4564-af43-2134930e6e63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2153792714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.2153792714
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.731269826
Short name T947
Test name
Test status
Simulation time 11663155991 ps
CPU time 26.4 seconds
Started Jun 23 05:40:32 PM PDT 24
Finished Jun 23 05:40:59 PM PDT 24
Peak memory 199908 kb
Host smart-ae0c455f-8358-4cf3-953c-886e7c629c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731269826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.731269826
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_perf.937800147
Short name T228
Test name
Test status
Simulation time 21812916236 ps
CPU time 1077.37 seconds
Started Jun 23 05:40:30 PM PDT 24
Finished Jun 23 05:58:28 PM PDT 24
Peak memory 200564 kb
Host smart-d4e964c9-ce0d-423e-a0e7-b1c1a0a84a76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=937800147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.937800147
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.2444327494
Short name T708
Test name
Test status
Simulation time 6093149695 ps
CPU time 29.93 seconds
Started Jun 23 05:40:25 PM PDT 24
Finished Jun 23 05:40:55 PM PDT 24
Peak memory 199836 kb
Host smart-e3c52b1a-2725-4d5d-ae43-8ae05f55af08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2444327494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.2444327494
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.1246171880
Short name T646
Test name
Test status
Simulation time 93055256431 ps
CPU time 41.63 seconds
Started Jun 23 05:40:26 PM PDT 24
Finished Jun 23 05:41:08 PM PDT 24
Peak memory 200700 kb
Host smart-694dd543-6abc-4e14-aa82-d2c52f8e4f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246171880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.1246171880
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.1076267609
Short name T851
Test name
Test status
Simulation time 45168678158 ps
CPU time 37.78 seconds
Started Jun 23 05:40:25 PM PDT 24
Finished Jun 23 05:41:03 PM PDT 24
Peak memory 196724 kb
Host smart-226250d3-adea-4f30-a202-03a5b9af578f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076267609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.1076267609
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.870513806
Short name T5
Test name
Test status
Simulation time 430992725 ps
CPU time 1.86 seconds
Started Jun 23 05:40:29 PM PDT 24
Finished Jun 23 05:40:31 PM PDT 24
Peak memory 199072 kb
Host smart-4c66d27b-6274-40a8-8a43-e498f21b7434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870513806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.870513806
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.1694811827
Short name T1037
Test name
Test status
Simulation time 64319581990 ps
CPU time 436.23 seconds
Started Jun 23 05:40:29 PM PDT 24
Finished Jun 23 05:47:46 PM PDT 24
Peak memory 216976 kb
Host smart-6df20a1a-c42f-44a2-bef4-5154a58370e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694811827 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.1694811827
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.1466532632
Short name T669
Test name
Test status
Simulation time 2729852542 ps
CPU time 2.08 seconds
Started Jun 23 05:40:32 PM PDT 24
Finished Jun 23 05:40:35 PM PDT 24
Peak memory 199508 kb
Host smart-4f5a06d3-0bc3-489d-bae3-1c96b99e0baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466532632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.1466532632
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.268026860
Short name T711
Test name
Test status
Simulation time 90992883321 ps
CPU time 41.79 seconds
Started Jun 23 05:40:26 PM PDT 24
Finished Jun 23 05:41:08 PM PDT 24
Peak memory 200680 kb
Host smart-20611578-b2c4-4d1a-896e-0b91c4dd70a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268026860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.268026860
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.831597662
Short name T445
Test name
Test status
Simulation time 289617757315 ps
CPU time 47.26 seconds
Started Jun 23 05:44:28 PM PDT 24
Finished Jun 23 05:45:16 PM PDT 24
Peak memory 200704 kb
Host smart-4a684152-3e21-45c2-b9eb-44d79a25012a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831597662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.831597662
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.3845639138
Short name T916
Test name
Test status
Simulation time 21543900170 ps
CPU time 4.84 seconds
Started Jun 23 05:44:28 PM PDT 24
Finished Jun 23 05:44:34 PM PDT 24
Peak memory 200664 kb
Host smart-329b3ba9-2c40-4e00-a70e-1a9ecd672436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845639138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.3845639138
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.1865650313
Short name T1042
Test name
Test status
Simulation time 6211824571 ps
CPU time 10.81 seconds
Started Jun 23 05:44:25 PM PDT 24
Finished Jun 23 05:44:36 PM PDT 24
Peak memory 200652 kb
Host smart-d7167233-d81c-488a-be4c-5029bf6fe7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865650313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.1865650313
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.4001457533
Short name T978
Test name
Test status
Simulation time 21706865673 ps
CPU time 16.73 seconds
Started Jun 23 05:44:29 PM PDT 24
Finished Jun 23 05:44:46 PM PDT 24
Peak memory 200592 kb
Host smart-cd0406e4-d57e-4534-871a-b619c7b42931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001457533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.4001457533
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.3364753075
Short name T845
Test name
Test status
Simulation time 86412819048 ps
CPU time 43.98 seconds
Started Jun 23 05:44:28 PM PDT 24
Finished Jun 23 05:45:13 PM PDT 24
Peak memory 200644 kb
Host smart-8bd693f6-56b8-45db-9ed9-b162cc463501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364753075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.3364753075
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.1601934212
Short name T1081
Test name
Test status
Simulation time 39221926876 ps
CPU time 16.75 seconds
Started Jun 23 05:44:30 PM PDT 24
Finished Jun 23 05:44:48 PM PDT 24
Peak memory 200692 kb
Host smart-ced00346-77f8-403c-a810-053f55182cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601934212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.1601934212
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.1667280070
Short name T413
Test name
Test status
Simulation time 25401571046 ps
CPU time 22.31 seconds
Started Jun 23 05:44:30 PM PDT 24
Finished Jun 23 05:44:52 PM PDT 24
Peak memory 200664 kb
Host smart-19bc5ab7-a539-4811-9d21-c4ce31499853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667280070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.1667280070
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.583438075
Short name T202
Test name
Test status
Simulation time 135591437380 ps
CPU time 186.38 seconds
Started Jun 23 05:44:24 PM PDT 24
Finished Jun 23 05:47:32 PM PDT 24
Peak memory 200632 kb
Host smart-24f12856-2243-483d-b814-6d0302880687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583438075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.583438075
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.3074881074
Short name T7
Test name
Test status
Simulation time 106375331249 ps
CPU time 84.71 seconds
Started Jun 23 05:44:29 PM PDT 24
Finished Jun 23 05:45:54 PM PDT 24
Peak memory 200764 kb
Host smart-f72cd9bb-85ed-418a-b25f-5baa812fcb58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074881074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.3074881074
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.1201536468
Short name T804
Test name
Test status
Simulation time 13309223 ps
CPU time 0.55 seconds
Started Jun 23 05:40:41 PM PDT 24
Finished Jun 23 05:40:42 PM PDT 24
Peak memory 196096 kb
Host smart-3a248e0c-8c37-4874-8e34-237906bc1f15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201536468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.1201536468
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.1548920310
Short name T424
Test name
Test status
Simulation time 62899452846 ps
CPU time 67.13 seconds
Started Jun 23 05:40:31 PM PDT 24
Finished Jun 23 05:41:38 PM PDT 24
Peak memory 200708 kb
Host smart-d0a956bc-8c88-4045-89af-cc6117f5599d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548920310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.1548920310
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.3994327667
Short name T284
Test name
Test status
Simulation time 88227266985 ps
CPU time 342.21 seconds
Started Jun 23 05:40:36 PM PDT 24
Finished Jun 23 05:46:19 PM PDT 24
Peak memory 200540 kb
Host smart-a5218c0f-d91c-4cee-afa5-0088be106e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994327667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.3994327667
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.4157819178
Short name T554
Test name
Test status
Simulation time 14673606894 ps
CPU time 25.73 seconds
Started Jun 23 05:40:35 PM PDT 24
Finished Jun 23 05:41:01 PM PDT 24
Peak memory 200720 kb
Host smart-1e4cd80c-75e8-4c8d-bfb2-e7d7b6f4042f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157819178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.4157819178
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.2279833932
Short name T747
Test name
Test status
Simulation time 87389142897 ps
CPU time 42.77 seconds
Started Jun 23 05:40:36 PM PDT 24
Finished Jun 23 05:41:20 PM PDT 24
Peak memory 200716 kb
Host smart-64822b0f-533b-445a-a8c1-cb4c9f7b41ef
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279833932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.2279833932
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.3699346230
Short name T833
Test name
Test status
Simulation time 38801138741 ps
CPU time 106.45 seconds
Started Jun 23 05:40:34 PM PDT 24
Finished Jun 23 05:42:21 PM PDT 24
Peak memory 200660 kb
Host smart-97128db1-22e0-4042-8b91-62d290d69834
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3699346230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.3699346230
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.1896261769
Short name T308
Test name
Test status
Simulation time 5988357015 ps
CPU time 6.41 seconds
Started Jun 23 05:40:34 PM PDT 24
Finished Jun 23 05:40:41 PM PDT 24
Peak memory 199768 kb
Host smart-45d9fba8-bde6-4e3a-82ce-b1ccd06e1ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896261769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.1896261769
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_perf.693660769
Short name T380
Test name
Test status
Simulation time 25496119844 ps
CPU time 1449.96 seconds
Started Jun 23 05:40:37 PM PDT 24
Finished Jun 23 06:04:48 PM PDT 24
Peak memory 200668 kb
Host smart-bcac7598-00c8-414f-b9ba-31ea13231329
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=693660769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.693660769
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.3124925490
Short name T785
Test name
Test status
Simulation time 2023375424 ps
CPU time 6.53 seconds
Started Jun 23 05:40:35 PM PDT 24
Finished Jun 23 05:40:43 PM PDT 24
Peak memory 198704 kb
Host smart-0c9fdacd-b69b-4e9d-966d-d172eb4b8d51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3124925490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.3124925490
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.873704405
Short name T533
Test name
Test status
Simulation time 58329023954 ps
CPU time 10.86 seconds
Started Jun 23 05:40:35 PM PDT 24
Finished Jun 23 05:40:47 PM PDT 24
Peak memory 200712 kb
Host smart-f7f9a653-8002-4019-9cc7-c5d95c78ca63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873704405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.873704405
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.699567001
Short name T823
Test name
Test status
Simulation time 3367959965 ps
CPU time 2.1 seconds
Started Jun 23 05:40:38 PM PDT 24
Finished Jun 23 05:40:41 PM PDT 24
Peak memory 196824 kb
Host smart-34db82bc-adfd-41d8-b155-23c0c952b18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699567001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.699567001
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.4031644266
Short name T869
Test name
Test status
Simulation time 976764817 ps
CPU time 5.65 seconds
Started Jun 23 05:40:30 PM PDT 24
Finished Jun 23 05:40:36 PM PDT 24
Peak memory 199676 kb
Host smart-8abf884e-e12b-4623-aa84-2689a969b937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031644266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.4031644266
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.3396856001
Short name T1095
Test name
Test status
Simulation time 745398025 ps
CPU time 2.48 seconds
Started Jun 23 05:40:37 PM PDT 24
Finished Jun 23 05:40:40 PM PDT 24
Peak memory 200296 kb
Host smart-548c2be7-05a6-4d9e-9512-422a5ce0ae0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396856001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.3396856001
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.3883300280
Short name T634
Test name
Test status
Simulation time 81412203065 ps
CPU time 32.89 seconds
Started Jun 23 05:40:32 PM PDT 24
Finished Jun 23 05:41:05 PM PDT 24
Peak memory 200712 kb
Host smart-6117c8f4-cc81-4c0b-a612-ff9faa3d5888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883300280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.3883300280
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.3088259480
Short name T695
Test name
Test status
Simulation time 107199002098 ps
CPU time 90.73 seconds
Started Jun 23 05:44:31 PM PDT 24
Finished Jun 23 05:46:02 PM PDT 24
Peak memory 200688 kb
Host smart-8ce5d339-3d85-47c1-9ac2-3027fa619b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088259480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.3088259480
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.3975480508
Short name T549
Test name
Test status
Simulation time 48952315633 ps
CPU time 31.89 seconds
Started Jun 23 05:44:33 PM PDT 24
Finished Jun 23 05:45:05 PM PDT 24
Peak memory 200664 kb
Host smart-6c99e87c-6ba7-4d43-8012-8555625bc7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975480508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.3975480508
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.2006318594
Short name T1060
Test name
Test status
Simulation time 96406411940 ps
CPU time 44.2 seconds
Started Jun 23 05:44:29 PM PDT 24
Finished Jun 23 05:45:14 PM PDT 24
Peak memory 200812 kb
Host smart-3b88e644-0a2a-40ef-974c-668a3555a451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006318594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.2006318594
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.2065975974
Short name T1033
Test name
Test status
Simulation time 29654207165 ps
CPU time 45.74 seconds
Started Jun 23 05:44:31 PM PDT 24
Finished Jun 23 05:45:17 PM PDT 24
Peak memory 200584 kb
Host smart-0f577f90-fcf0-4522-bf38-f52bedc58e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065975974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.2065975974
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.2720587591
Short name T739
Test name
Test status
Simulation time 113380307291 ps
CPU time 168.95 seconds
Started Jun 23 05:44:31 PM PDT 24
Finished Jun 23 05:47:20 PM PDT 24
Peak memory 200692 kb
Host smart-f11f848f-203e-4349-89ae-e9391dbd6a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720587591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.2720587591
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.134828909
Short name T598
Test name
Test status
Simulation time 157397353708 ps
CPU time 64.76 seconds
Started Jun 23 05:44:32 PM PDT 24
Finished Jun 23 05:45:37 PM PDT 24
Peak memory 200568 kb
Host smart-db561751-eca2-4244-9d3f-7a433014df37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134828909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.134828909
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.1326263378
Short name T764
Test name
Test status
Simulation time 34372756424 ps
CPU time 52.68 seconds
Started Jun 23 05:44:31 PM PDT 24
Finished Jun 23 05:45:24 PM PDT 24
Peak memory 200728 kb
Host smart-0d8ac024-0b4f-431e-a130-2e418da2ddfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326263378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.1326263378
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.330371273
Short name T1010
Test name
Test status
Simulation time 231373020657 ps
CPU time 44.1 seconds
Started Jun 23 05:44:29 PM PDT 24
Finished Jun 23 05:45:13 PM PDT 24
Peak memory 200700 kb
Host smart-ae958d24-819a-4a55-8790-368a3c77ffc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330371273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.330371273
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.599447669
Short name T727
Test name
Test status
Simulation time 23339114 ps
CPU time 0.55 seconds
Started Jun 23 05:40:44 PM PDT 24
Finished Jun 23 05:40:45 PM PDT 24
Peak memory 196096 kb
Host smart-7b0a86f2-a204-42a6-b962-73f1008478a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599447669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.599447669
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.2876044287
Short name T427
Test name
Test status
Simulation time 95482770406 ps
CPU time 81.38 seconds
Started Jun 23 05:40:42 PM PDT 24
Finished Jun 23 05:42:04 PM PDT 24
Peak memory 200744 kb
Host smart-d33b9f92-cde1-4213-a1e1-401657c0253d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876044287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.2876044287
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.2209708012
Short name T1050
Test name
Test status
Simulation time 262552224570 ps
CPU time 22.22 seconds
Started Jun 23 05:40:40 PM PDT 24
Finished Jun 23 05:41:02 PM PDT 24
Peak memory 200468 kb
Host smart-a8d45f68-2b9b-4e9e-928d-199b55abffb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209708012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.2209708012
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.4003893127
Short name T704
Test name
Test status
Simulation time 49934788072 ps
CPU time 36.51 seconds
Started Jun 23 05:40:42 PM PDT 24
Finished Jun 23 05:41:19 PM PDT 24
Peak memory 200696 kb
Host smart-b61cfa79-2b56-4c5d-bad3-0187be3e8c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003893127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.4003893127
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.2523785725
Short name T651
Test name
Test status
Simulation time 25149125076 ps
CPU time 10.79 seconds
Started Jun 23 05:40:41 PM PDT 24
Finished Jun 23 05:40:52 PM PDT 24
Peak memory 200740 kb
Host smart-3e8043da-e3d2-437e-a3eb-92ce7b2b3289
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523785725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.2523785725
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.4112784725
Short name T615
Test name
Test status
Simulation time 132826335818 ps
CPU time 855.45 seconds
Started Jun 23 05:40:45 PM PDT 24
Finished Jun 23 05:55:01 PM PDT 24
Peak memory 200680 kb
Host smart-78dea527-ed96-4856-88d4-d6af9b04a859
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4112784725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.4112784725
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.1685767874
Short name T85
Test name
Test status
Simulation time 9592391622 ps
CPU time 6.48 seconds
Started Jun 23 05:40:42 PM PDT 24
Finished Jun 23 05:40:49 PM PDT 24
Peak memory 200688 kb
Host smart-985c4dac-fe47-4295-86b9-9bffbe29d990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685767874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.1685767874
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_perf.2316576123
Short name T969
Test name
Test status
Simulation time 14084077627 ps
CPU time 430.74 seconds
Started Jun 23 05:40:47 PM PDT 24
Finished Jun 23 05:47:59 PM PDT 24
Peak memory 200700 kb
Host smart-82d6dc35-179f-4cb1-b0be-02766b75bc45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2316576123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.2316576123
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.3982118456
Short name T734
Test name
Test status
Simulation time 1827363362 ps
CPU time 2.58 seconds
Started Jun 23 05:40:41 PM PDT 24
Finished Jun 23 05:40:45 PM PDT 24
Peak memory 198924 kb
Host smart-5ef62674-fa2c-4ade-8a28-e0c57bdac80a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3982118456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.3982118456
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.401381547
Short name T900
Test name
Test status
Simulation time 25432186957 ps
CPU time 41.14 seconds
Started Jun 23 05:40:40 PM PDT 24
Finished Jun 23 05:41:21 PM PDT 24
Peak memory 200756 kb
Host smart-137adf28-8f0c-42ae-b02b-54e775b178c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401381547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.401381547
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.1680063588
Short name T274
Test name
Test status
Simulation time 3723798944 ps
CPU time 2.14 seconds
Started Jun 23 05:40:42 PM PDT 24
Finished Jun 23 05:40:45 PM PDT 24
Peak memory 196836 kb
Host smart-8440716f-2b7f-4c68-a469-7c86a2411288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680063588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.1680063588
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.1282597114
Short name T770
Test name
Test status
Simulation time 11620202047 ps
CPU time 50.22 seconds
Started Jun 23 05:40:41 PM PDT 24
Finished Jun 23 05:41:32 PM PDT 24
Peak memory 200536 kb
Host smart-7953f1bb-803d-450a-b79a-e3d5ec1f15ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282597114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.1282597114
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.1599184452
Short name T570
Test name
Test status
Simulation time 70211045740 ps
CPU time 660.22 seconds
Started Jun 23 05:40:45 PM PDT 24
Finished Jun 23 05:51:45 PM PDT 24
Peak memory 200688 kb
Host smart-58585a42-552a-4f1c-8575-3111f38f6591
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599184452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.1599184452
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.4213412561
Short name T48
Test name
Test status
Simulation time 211136295332 ps
CPU time 732 seconds
Started Jun 23 05:40:46 PM PDT 24
Finished Jun 23 05:52:59 PM PDT 24
Peak memory 217128 kb
Host smart-599cb9bf-9854-45fd-931e-2095c5c3f965
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213412561 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.4213412561
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.969650317
Short name T741
Test name
Test status
Simulation time 8845326311 ps
CPU time 14.82 seconds
Started Jun 23 05:40:40 PM PDT 24
Finished Jun 23 05:40:55 PM PDT 24
Peak memory 200612 kb
Host smart-c3b0e666-3cc6-460b-af7d-6d8a89e9557c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969650317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.969650317
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.3213863225
Short name T396
Test name
Test status
Simulation time 75971486362 ps
CPU time 31.59 seconds
Started Jun 23 05:40:43 PM PDT 24
Finished Jun 23 05:41:15 PM PDT 24
Peak memory 200704 kb
Host smart-198165a5-0692-4cc1-b569-f5304483a638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213863225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.3213863225
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.3435007634
Short name T191
Test name
Test status
Simulation time 31685678409 ps
CPU time 15.67 seconds
Started Jun 23 05:44:31 PM PDT 24
Finished Jun 23 05:44:47 PM PDT 24
Peak memory 200696 kb
Host smart-1b82c942-c53b-40b0-bfa0-c146b3b7c0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435007634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.3435007634
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.4173465852
Short name T42
Test name
Test status
Simulation time 17716314459 ps
CPU time 15.08 seconds
Started Jun 23 05:44:29 PM PDT 24
Finished Jun 23 05:44:44 PM PDT 24
Peak memory 200684 kb
Host smart-be628a34-0e55-4f91-a5cc-20223df2f060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173465852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.4173465852
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.3322086786
Short name T190
Test name
Test status
Simulation time 89929639707 ps
CPU time 22.37 seconds
Started Jun 23 05:44:29 PM PDT 24
Finished Jun 23 05:44:52 PM PDT 24
Peak memory 200648 kb
Host smart-9f634bff-c410-47e5-a67a-e750c40d4495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322086786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.3322086786
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.2767177128
Short name T881
Test name
Test status
Simulation time 8677103013 ps
CPU time 14.4 seconds
Started Jun 23 05:44:36 PM PDT 24
Finished Jun 23 05:44:51 PM PDT 24
Peak memory 200692 kb
Host smart-63dc99b0-1280-414c-890c-cda20a79f1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767177128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.2767177128
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.2170289254
Short name T131
Test name
Test status
Simulation time 38947524308 ps
CPU time 81.3 seconds
Started Jun 23 05:44:34 PM PDT 24
Finished Jun 23 05:45:55 PM PDT 24
Peak memory 200700 kb
Host smart-f771aead-af21-451d-958c-246f4cf29755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170289254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.2170289254
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.2130960340
Short name T638
Test name
Test status
Simulation time 153130756422 ps
CPU time 101.49 seconds
Started Jun 23 05:44:35 PM PDT 24
Finished Jun 23 05:46:17 PM PDT 24
Peak memory 200692 kb
Host smart-a6d0c95e-8c84-45c1-88f8-444f9ff6d264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130960340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.2130960340
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.3369230685
Short name T123
Test name
Test status
Simulation time 71422335255 ps
CPU time 52.61 seconds
Started Jun 23 05:44:36 PM PDT 24
Finished Jun 23 05:45:29 PM PDT 24
Peak memory 200664 kb
Host smart-142d9e6c-7cf9-435f-85a7-f819136f3bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369230685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.3369230685
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.1038674250
Short name T201
Test name
Test status
Simulation time 164994235844 ps
CPU time 46.28 seconds
Started Jun 23 05:44:34 PM PDT 24
Finished Jun 23 05:45:20 PM PDT 24
Peak memory 200620 kb
Host smart-b55eae47-adfe-4b4d-a818-426adfd259bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038674250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.1038674250
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.1858433491
Short name T777
Test name
Test status
Simulation time 13464412 ps
CPU time 0.55 seconds
Started Jun 23 05:40:51 PM PDT 24
Finished Jun 23 05:40:52 PM PDT 24
Peak memory 195488 kb
Host smart-f879f25a-f5d7-4d77-939f-1ef4ddecc73c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858433491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.1858433491
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.417118904
Short name T409
Test name
Test status
Simulation time 230556190092 ps
CPU time 222.7 seconds
Started Jun 23 05:40:48 PM PDT 24
Finished Jun 23 05:44:31 PM PDT 24
Peak memory 200748 kb
Host smart-a9b3737b-8185-40b4-80c6-89af7b7bd9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417118904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.417118904
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.209708149
Short name T574
Test name
Test status
Simulation time 164974400918 ps
CPU time 237.99 seconds
Started Jun 23 05:40:45 PM PDT 24
Finished Jun 23 05:44:44 PM PDT 24
Peak memory 200756 kb
Host smart-bc247caf-0846-4a22-8513-91f1740b6a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209708149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.209708149
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.3897241174
Short name T192
Test name
Test status
Simulation time 26959401319 ps
CPU time 35.44 seconds
Started Jun 23 05:40:48 PM PDT 24
Finished Jun 23 05:41:24 PM PDT 24
Peak memory 200304 kb
Host smart-0d2d651f-a972-4fe8-aaf5-c95fb76739d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897241174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.3897241174
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.2394162336
Short name T552
Test name
Test status
Simulation time 45738102173 ps
CPU time 50.41 seconds
Started Jun 23 05:40:47 PM PDT 24
Finished Jun 23 05:41:38 PM PDT 24
Peak memory 200624 kb
Host smart-ceea5386-f69f-449b-821a-5d2bd4a51f2f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394162336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.2394162336
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.1690761497
Short name T1063
Test name
Test status
Simulation time 65712656238 ps
CPU time 209.58 seconds
Started Jun 23 05:40:46 PM PDT 24
Finished Jun 23 05:44:17 PM PDT 24
Peak memory 200672 kb
Host smart-77e44568-10a0-42ba-9340-13b4ddf07b4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1690761497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.1690761497
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.643471657
Short name T374
Test name
Test status
Simulation time 8949953698 ps
CPU time 17.82 seconds
Started Jun 23 05:40:46 PM PDT 24
Finished Jun 23 05:41:05 PM PDT 24
Peak memory 200748 kb
Host smart-7a781305-84ef-4bac-8cbe-9a79b54e154f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643471657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.643471657
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_perf.3474115855
Short name T309
Test name
Test status
Simulation time 10306675348 ps
CPU time 311.8 seconds
Started Jun 23 05:40:44 PM PDT 24
Finished Jun 23 05:45:56 PM PDT 24
Peak memory 200732 kb
Host smart-1db6112b-b901-4e95-8bca-848758202953
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3474115855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.3474115855
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.2889535367
Short name T325
Test name
Test status
Simulation time 4838434413 ps
CPU time 43.78 seconds
Started Jun 23 05:40:47 PM PDT 24
Finished Jun 23 05:41:32 PM PDT 24
Peak memory 200052 kb
Host smart-548d05c5-0961-480f-b889-d1e9a6602cef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2889535367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.2889535367
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.2294256189
Short name T618
Test name
Test status
Simulation time 134838987515 ps
CPU time 212.69 seconds
Started Jun 23 05:40:46 PM PDT 24
Finished Jun 23 05:44:20 PM PDT 24
Peak memory 200640 kb
Host smart-c1c400d9-2faf-40ea-93d9-dd428e8a57f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294256189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.2294256189
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.2609995101
Short name T1074
Test name
Test status
Simulation time 52317080236 ps
CPU time 37.52 seconds
Started Jun 23 05:40:46 PM PDT 24
Finished Jun 23 05:41:24 PM PDT 24
Peak memory 196564 kb
Host smart-0bd65047-a644-4e07-a365-e9705185e10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609995101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.2609995101
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.2806062762
Short name T1046
Test name
Test status
Simulation time 272957461 ps
CPU time 1.99 seconds
Started Jun 23 05:40:44 PM PDT 24
Finished Jun 23 05:40:47 PM PDT 24
Peak memory 199688 kb
Host smart-7f56f100-e155-49b5-bb4d-fbb1ece9bbe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806062762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.2806062762
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.489625551
Short name T563
Test name
Test status
Simulation time 84655915775 ps
CPU time 179.96 seconds
Started Jun 23 05:40:47 PM PDT 24
Finished Jun 23 05:43:48 PM PDT 24
Peak memory 200740 kb
Host smart-cdb00159-2e3a-45fc-87d4-e8811577293a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489625551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.489625551
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.1633163232
Short name T82
Test name
Test status
Simulation time 45547713024 ps
CPU time 373.13 seconds
Started Jun 23 05:40:46 PM PDT 24
Finished Jun 23 05:47:00 PM PDT 24
Peak memory 217124 kb
Host smart-c84214b4-e123-4410-af1e-9b47c2993dd6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633163232 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.1633163232
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.1575292192
Short name T548
Test name
Test status
Simulation time 1515946589 ps
CPU time 4.67 seconds
Started Jun 23 05:40:47 PM PDT 24
Finished Jun 23 05:40:52 PM PDT 24
Peak memory 200104 kb
Host smart-ace0f18d-f95c-4524-aa3b-9534338d825d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575292192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.1575292192
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.3218105169
Short name T408
Test name
Test status
Simulation time 10247551382 ps
CPU time 15.61 seconds
Started Jun 23 05:40:46 PM PDT 24
Finished Jun 23 05:41:02 PM PDT 24
Peak memory 200668 kb
Host smart-f1720cd4-124a-4f37-9cca-01fb1e7c9238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218105169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.3218105169
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.4047194325
Short name T491
Test name
Test status
Simulation time 135561264041 ps
CPU time 137.1 seconds
Started Jun 23 05:44:37 PM PDT 24
Finished Jun 23 05:46:54 PM PDT 24
Peak memory 200764 kb
Host smart-dcabe411-0fe1-4b33-8ac9-cbd895d9bcd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047194325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.4047194325
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.3709692211
Short name T1083
Test name
Test status
Simulation time 84602659780 ps
CPU time 126.63 seconds
Started Jun 23 05:44:34 PM PDT 24
Finished Jun 23 05:46:41 PM PDT 24
Peak memory 200724 kb
Host smart-fa8834b7-6b93-46c1-aec9-6b268296b646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709692211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.3709692211
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.2986149900
Short name T899
Test name
Test status
Simulation time 81167039834 ps
CPU time 99.55 seconds
Started Jun 23 05:44:35 PM PDT 24
Finished Jun 23 05:46:15 PM PDT 24
Peak memory 200772 kb
Host smart-e36bd1a9-9526-4ca4-87ae-c9f6ebbbbff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986149900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.2986149900
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.213588424
Short name T882
Test name
Test status
Simulation time 31352749201 ps
CPU time 16.93 seconds
Started Jun 23 05:44:36 PM PDT 24
Finished Jun 23 05:44:54 PM PDT 24
Peak memory 200664 kb
Host smart-5be87e5c-3b3a-45a2-8533-3936f16f3452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213588424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.213588424
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.1955889213
Short name T447
Test name
Test status
Simulation time 46325161994 ps
CPU time 29.77 seconds
Started Jun 23 05:44:38 PM PDT 24
Finished Jun 23 05:45:08 PM PDT 24
Peak memory 200704 kb
Host smart-f6c55b19-8ba2-48e5-ba29-e5f6c63c75d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955889213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.1955889213
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.1791803556
Short name T397
Test name
Test status
Simulation time 89464773631 ps
CPU time 66.56 seconds
Started Jun 23 05:44:41 PM PDT 24
Finished Jun 23 05:45:48 PM PDT 24
Peak memory 200728 kb
Host smart-8a653fdb-9f0a-4621-9b87-d1b86f9c3949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791803556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.1791803556
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.1600042572
Short name T205
Test name
Test status
Simulation time 31807865588 ps
CPU time 64.62 seconds
Started Jun 23 05:44:41 PM PDT 24
Finished Jun 23 05:45:46 PM PDT 24
Peak memory 200788 kb
Host smart-46b38b0a-cbc0-4cbe-a4c0-183f1ce6d2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600042572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.1600042572
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.170148004
Short name T78
Test name
Test status
Simulation time 38835287686 ps
CPU time 14.18 seconds
Started Jun 23 05:44:41 PM PDT 24
Finished Jun 23 05:44:55 PM PDT 24
Peak memory 200740 kb
Host smart-1aae8d5b-5d3e-433b-b529-1153145a525d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170148004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.170148004
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.2459175863
Short name T253
Test name
Test status
Simulation time 32633778626 ps
CPU time 50.95 seconds
Started Jun 23 05:44:40 PM PDT 24
Finished Jun 23 05:45:32 PM PDT 24
Peak memory 200320 kb
Host smart-03a0db60-fc40-4c74-8dab-1fe0d615e0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459175863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.2459175863
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.1743566122
Short name T523
Test name
Test status
Simulation time 54294611 ps
CPU time 0.54 seconds
Started Jun 23 05:40:57 PM PDT 24
Finished Jun 23 05:40:58 PM PDT 24
Peak memory 196036 kb
Host smart-12cf5104-8428-4dc0-8acf-a375ad36364c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743566122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.1743566122
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.1239356317
Short name T158
Test name
Test status
Simulation time 58471464648 ps
CPU time 44.12 seconds
Started Jun 23 05:40:48 PM PDT 24
Finished Jun 23 05:41:33 PM PDT 24
Peak memory 200696 kb
Host smart-ad1689f3-abb3-4c7e-b813-635cc9567815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239356317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.1239356317
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.1554028681
Short name T706
Test name
Test status
Simulation time 252957505257 ps
CPU time 105.68 seconds
Started Jun 23 05:40:51 PM PDT 24
Finished Jun 23 05:42:37 PM PDT 24
Peak memory 200768 kb
Host smart-638d8a5e-daa5-4c62-a52b-7caf90b69b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554028681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.1554028681
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.3213162092
Short name T1082
Test name
Test status
Simulation time 34742359378 ps
CPU time 49.4 seconds
Started Jun 23 05:40:49 PM PDT 24
Finished Jun 23 05:41:39 PM PDT 24
Peak memory 200696 kb
Host smart-71acd6d6-be7b-4bc9-b1a8-c1615b1a52ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213162092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.3213162092
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.3287670075
Short name T6
Test name
Test status
Simulation time 77461972047 ps
CPU time 70.08 seconds
Started Jun 23 05:41:00 PM PDT 24
Finished Jun 23 05:42:10 PM PDT 24
Peak memory 200664 kb
Host smart-e4f25c60-34ae-4719-8392-ae5bb6351810
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287670075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.3287670075
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.1108871291
Short name T961
Test name
Test status
Simulation time 207876453359 ps
CPU time 380.9 seconds
Started Jun 23 05:40:49 PM PDT 24
Finished Jun 23 05:47:10 PM PDT 24
Peak memory 200692 kb
Host smart-ef122cf7-e2d1-4515-b8fd-3c88a3d56847
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1108871291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.1108871291
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.647822112
Short name T977
Test name
Test status
Simulation time 2202442309 ps
CPU time 1.56 seconds
Started Jun 23 05:41:02 PM PDT 24
Finished Jun 23 05:41:04 PM PDT 24
Peak memory 196868 kb
Host smart-4416b547-deab-495e-8cbe-701d6c75a09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647822112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.647822112
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_perf.3381235142
Short name T398
Test name
Test status
Simulation time 19822969025 ps
CPU time 243.85 seconds
Started Jun 23 05:40:49 PM PDT 24
Finished Jun 23 05:44:53 PM PDT 24
Peak memory 200632 kb
Host smart-0ef82fa8-21cc-4b71-899b-af21e2b876de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3381235142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.3381235142
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.4172840423
Short name T908
Test name
Test status
Simulation time 6722329557 ps
CPU time 17.69 seconds
Started Jun 23 05:41:00 PM PDT 24
Finished Jun 23 05:41:18 PM PDT 24
Peak memory 200012 kb
Host smart-a95a88b8-f896-4d69-8f55-4000b496796d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4172840423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.4172840423
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.1233045825
Short name T354
Test name
Test status
Simulation time 13740135357 ps
CPU time 20.45 seconds
Started Jun 23 05:40:50 PM PDT 24
Finished Jun 23 05:41:11 PM PDT 24
Peak memory 200116 kb
Host smart-e763cc2b-d2a0-4bef-855c-1cd4279de99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233045825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.1233045825
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.1180367871
Short name T800
Test name
Test status
Simulation time 34852467318 ps
CPU time 56.97 seconds
Started Jun 23 05:41:00 PM PDT 24
Finished Jun 23 05:41:57 PM PDT 24
Peak memory 196492 kb
Host smart-0f0bdb1a-9aa5-4a27-ba2e-35c7e67591f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180367871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.1180367871
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.1420133591
Short name T583
Test name
Test status
Simulation time 111608224 ps
CPU time 0.98 seconds
Started Jun 23 05:41:00 PM PDT 24
Finished Jun 23 05:41:01 PM PDT 24
Peak memory 199068 kb
Host smart-93f91c39-e331-43fe-af24-cdf05b925e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420133591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.1420133591
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.2414513825
Short name T789
Test name
Test status
Simulation time 88957893810 ps
CPU time 170.56 seconds
Started Jun 23 05:40:55 PM PDT 24
Finished Jun 23 05:43:45 PM PDT 24
Peak memory 200664 kb
Host smart-c9a881c8-46fc-4b39-8eca-d1cc328634b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414513825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.2414513825
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.4028641070
Short name T330
Test name
Test status
Simulation time 828548484 ps
CPU time 2.67 seconds
Started Jun 23 05:40:50 PM PDT 24
Finished Jun 23 05:40:53 PM PDT 24
Peak memory 199692 kb
Host smart-1a166195-dfe6-4f58-857e-d1f48dbfc09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028641070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.4028641070
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.597357968
Short name T732
Test name
Test status
Simulation time 13071122048 ps
CPU time 5.71 seconds
Started Jun 23 05:40:50 PM PDT 24
Finished Jun 23 05:40:56 PM PDT 24
Peak memory 200628 kb
Host smart-bec60ab1-c838-4ffb-ae08-ca96921e4813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597357968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.597357968
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.3107874301
Short name T1007
Test name
Test status
Simulation time 141649457687 ps
CPU time 219.52 seconds
Started Jun 23 05:44:45 PM PDT 24
Finished Jun 23 05:48:25 PM PDT 24
Peak memory 200640 kb
Host smart-a21ad820-0ef1-4b2f-b7c3-b167e36d1118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107874301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.3107874301
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.401605058
Short name T290
Test name
Test status
Simulation time 47690608750 ps
CPU time 88.82 seconds
Started Jun 23 05:44:45 PM PDT 24
Finished Jun 23 05:46:14 PM PDT 24
Peak memory 200752 kb
Host smart-94b4f07f-77e0-4daa-9afe-60e05abd91c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401605058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.401605058
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.3345339810
Short name T470
Test name
Test status
Simulation time 23942902101 ps
CPU time 42.05 seconds
Started Jun 23 05:44:43 PM PDT 24
Finished Jun 23 05:45:26 PM PDT 24
Peak memory 200652 kb
Host smart-e189858d-32fb-4053-ae5c-f5228968bccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345339810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.3345339810
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.3341852513
Short name T740
Test name
Test status
Simulation time 31185468026 ps
CPU time 19.35 seconds
Started Jun 23 05:44:47 PM PDT 24
Finished Jun 23 05:45:07 PM PDT 24
Peak memory 200832 kb
Host smart-c5f65d50-e1e9-434e-8568-daa654288a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341852513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.3341852513
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.4034958111
Short name T485
Test name
Test status
Simulation time 562990358816 ps
CPU time 104.96 seconds
Started Jun 23 05:44:47 PM PDT 24
Finished Jun 23 05:46:32 PM PDT 24
Peak memory 200692 kb
Host smart-2406689d-0fd7-4e9e-94f3-92c4029a16ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034958111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.4034958111
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.2894227715
Short name T198
Test name
Test status
Simulation time 87765418948 ps
CPU time 260.89 seconds
Started Jun 23 05:44:48 PM PDT 24
Finished Jun 23 05:49:10 PM PDT 24
Peak memory 200704 kb
Host smart-8eeb5ba6-c06f-4e4e-ab74-947125d3f856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894227715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.2894227715
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.1758555799
Short name T942
Test name
Test status
Simulation time 92607821483 ps
CPU time 147.46 seconds
Started Jun 23 05:44:46 PM PDT 24
Finished Jun 23 05:47:14 PM PDT 24
Peak memory 200724 kb
Host smart-3c9f2221-1939-4e31-8be3-2f1e52115366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758555799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.1758555799
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.4003644789
Short name T150
Test name
Test status
Simulation time 13368918404 ps
CPU time 24.43 seconds
Started Jun 23 05:44:44 PM PDT 24
Finished Jun 23 05:45:09 PM PDT 24
Peak memory 200688 kb
Host smart-0518e77b-0c50-4de0-9659-bd2dba47897f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003644789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.4003644789
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.4078358676
Short name T98
Test name
Test status
Simulation time 256986102679 ps
CPU time 52.33 seconds
Started Jun 23 05:44:43 PM PDT 24
Finished Jun 23 05:45:35 PM PDT 24
Peak memory 200656 kb
Host smart-0eccedf0-14f2-4dd3-a0f5-733c83c0bc7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078358676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.4078358676
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.2305591704
Short name T803
Test name
Test status
Simulation time 44979232 ps
CPU time 0.56 seconds
Started Jun 23 05:41:01 PM PDT 24
Finished Jun 23 05:41:02 PM PDT 24
Peak memory 196252 kb
Host smart-c691e9e5-e407-4559-8162-b1b0d41082b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305591704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.2305591704
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.1404044947
Short name T273
Test name
Test status
Simulation time 104676832109 ps
CPU time 148.99 seconds
Started Jun 23 05:40:55 PM PDT 24
Finished Jun 23 05:43:24 PM PDT 24
Peak memory 200668 kb
Host smart-c54e1563-3f04-4f11-8244-fc6f7b85c4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404044947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.1404044947
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.2484083973
Short name T642
Test name
Test status
Simulation time 8289644023 ps
CPU time 14.12 seconds
Started Jun 23 05:40:59 PM PDT 24
Finished Jun 23 05:41:13 PM PDT 24
Peak memory 199192 kb
Host smart-bc87ff1c-751a-41fe-b1c9-6e13ea94a5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484083973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.2484083973
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_intr.2215179025
Short name T989
Test name
Test status
Simulation time 54243434084 ps
CPU time 30.6 seconds
Started Jun 23 05:40:59 PM PDT 24
Finished Jun 23 05:41:30 PM PDT 24
Peak memory 200704 kb
Host smart-18f52b18-140c-41c8-be7f-3e532eff8fde
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215179025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.2215179025
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.2969175961
Short name T617
Test name
Test status
Simulation time 85341065205 ps
CPU time 123.63 seconds
Started Jun 23 05:40:58 PM PDT 24
Finished Jun 23 05:43:02 PM PDT 24
Peak memory 200664 kb
Host smart-9572b2ce-7a80-46ed-944d-ca26b53ae3c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2969175961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.2969175961
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.606413560
Short name T89
Test name
Test status
Simulation time 8897467029 ps
CPU time 12.56 seconds
Started Jun 23 05:41:08 PM PDT 24
Finished Jun 23 05:41:21 PM PDT 24
Peak memory 200572 kb
Host smart-32ddaa7f-d0f5-4428-bbe3-5b89c5dec1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606413560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.606413560
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.1022675940
Short name T22
Test name
Test status
Simulation time 6316196172 ps
CPU time 31.72 seconds
Started Jun 23 05:40:57 PM PDT 24
Finished Jun 23 05:41:29 PM PDT 24
Peak memory 199892 kb
Host smart-5d166515-1483-4006-9cd4-076b6a6635c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1022675940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.1022675940
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.1773908105
Short name T995
Test name
Test status
Simulation time 213701760281 ps
CPU time 422.06 seconds
Started Jun 23 05:41:01 PM PDT 24
Finished Jun 23 05:48:03 PM PDT 24
Peak memory 200584 kb
Host smart-51f82633-1ce4-4237-9112-6dcb5e7e78ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773908105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.1773908105
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.1165899377
Short name T540
Test name
Test status
Simulation time 42630527864 ps
CPU time 26.25 seconds
Started Jun 23 05:41:08 PM PDT 24
Finished Jun 23 05:41:34 PM PDT 24
Peak memory 196788 kb
Host smart-63792d2a-bbd3-4d30-ac59-63b25de55d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165899377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.1165899377
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.3893055279
Short name T516
Test name
Test status
Simulation time 5577239869 ps
CPU time 22.34 seconds
Started Jun 23 05:40:57 PM PDT 24
Finished Jun 23 05:41:19 PM PDT 24
Peak memory 200672 kb
Host smart-e25d820e-6793-4c82-bc7b-413328556c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893055279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.3893055279
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.2109039666
Short name T294
Test name
Test status
Simulation time 182881167057 ps
CPU time 164.78 seconds
Started Jun 23 05:41:03 PM PDT 24
Finished Jun 23 05:43:48 PM PDT 24
Peak memory 200664 kb
Host smart-af42d379-a0cf-4646-9a75-0a9c188bd639
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109039666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.2109039666
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.2057583588
Short name T813
Test name
Test status
Simulation time 330970333 ps
CPU time 1.34 seconds
Started Jun 23 05:40:58 PM PDT 24
Finished Jun 23 05:40:59 PM PDT 24
Peak memory 197612 kb
Host smart-a38e8e2b-351f-4c32-ab1a-0780d036ede9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057583588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.2057583588
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.418984200
Short name T999
Test name
Test status
Simulation time 39088367310 ps
CPU time 19.08 seconds
Started Jun 23 05:40:55 PM PDT 24
Finished Jun 23 05:41:14 PM PDT 24
Peak memory 200712 kb
Host smart-d35f6bca-fbf5-4d8a-993a-1678a636724f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418984200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.418984200
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.3732336551
Short name T10
Test name
Test status
Simulation time 54954892796 ps
CPU time 24.9 seconds
Started Jun 23 05:44:44 PM PDT 24
Finished Jun 23 05:45:09 PM PDT 24
Peak memory 200776 kb
Host smart-ba4ca87f-6b3a-452f-a5b4-515449e03a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732336551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.3732336551
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.1698776935
Short name T425
Test name
Test status
Simulation time 19089501507 ps
CPU time 28.28 seconds
Started Jun 23 05:44:44 PM PDT 24
Finished Jun 23 05:45:13 PM PDT 24
Peak memory 200700 kb
Host smart-31012995-36a2-4504-aa40-c618bfd92cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698776935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.1698776935
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.3970733515
Short name T117
Test name
Test status
Simulation time 17559725275 ps
CPU time 28.65 seconds
Started Jun 23 05:44:44 PM PDT 24
Finished Jun 23 05:45:13 PM PDT 24
Peak memory 200760 kb
Host smart-2b6a19cb-cdb1-4f42-bd2d-ab2e7fead547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970733515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.3970733515
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.2763586585
Short name T843
Test name
Test status
Simulation time 32681624912 ps
CPU time 17.58 seconds
Started Jun 23 05:44:46 PM PDT 24
Finished Jun 23 05:45:05 PM PDT 24
Peak memory 200728 kb
Host smart-24668a4d-a29b-45a9-9eef-a6f692d7d876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763586585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.2763586585
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.641231651
Short name T569
Test name
Test status
Simulation time 10700885820 ps
CPU time 15.58 seconds
Started Jun 23 05:44:47 PM PDT 24
Finished Jun 23 05:45:03 PM PDT 24
Peak memory 200748 kb
Host smart-d0a723da-0733-4915-8f93-b03d5173af81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641231651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.641231651
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.206668679
Short name T915
Test name
Test status
Simulation time 21845817534 ps
CPU time 33.81 seconds
Started Jun 23 05:44:45 PM PDT 24
Finished Jun 23 05:45:20 PM PDT 24
Peak memory 200920 kb
Host smart-2c323db2-709c-4442-ab9d-d35bc63604e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206668679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.206668679
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.502759752
Short name T868
Test name
Test status
Simulation time 31498458330 ps
CPU time 64.02 seconds
Started Jun 23 05:44:45 PM PDT 24
Finished Jun 23 05:45:49 PM PDT 24
Peak memory 200724 kb
Host smart-5caca5df-acb9-453b-97b1-b440383c50e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502759752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.502759752
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.3801739954
Short name T1047
Test name
Test status
Simulation time 22139122008 ps
CPU time 58.16 seconds
Started Jun 23 05:44:50 PM PDT 24
Finished Jun 23 05:45:49 PM PDT 24
Peak memory 200760 kb
Host smart-c0f5907b-c5b4-47d0-ae1a-64687aa7254e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801739954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.3801739954
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.1501429949
Short name T216
Test name
Test status
Simulation time 137466819686 ps
CPU time 50.11 seconds
Started Jun 23 05:44:50 PM PDT 24
Finished Jun 23 05:45:40 PM PDT 24
Peak memory 200688 kb
Host smart-e09d4945-ed31-4fec-a65a-cbcd532e575d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501429949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.1501429949
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.1902763205
Short name T964
Test name
Test status
Simulation time 48190147890 ps
CPU time 73.65 seconds
Started Jun 23 05:44:48 PM PDT 24
Finished Jun 23 05:46:02 PM PDT 24
Peak memory 200688 kb
Host smart-737c4f49-f197-4d2e-8bca-1fd15976bc0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902763205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.1902763205
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.480499461
Short name T528
Test name
Test status
Simulation time 12762089 ps
CPU time 0.56 seconds
Started Jun 23 05:41:05 PM PDT 24
Finished Jun 23 05:41:06 PM PDT 24
Peak memory 196088 kb
Host smart-495dbfcb-4c6d-48d8-8868-9cc6dae4388d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480499461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.480499461
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.3225501657
Short name T1080
Test name
Test status
Simulation time 108827149274 ps
CPU time 173.65 seconds
Started Jun 23 05:40:58 PM PDT 24
Finished Jun 23 05:43:53 PM PDT 24
Peak memory 200688 kb
Host smart-bcc2d453-69cf-4e3e-9ae4-4b9e8709635c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225501657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.3225501657
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.3740269247
Short name T435
Test name
Test status
Simulation time 79271831041 ps
CPU time 121.42 seconds
Started Jun 23 05:41:00 PM PDT 24
Finished Jun 23 05:43:02 PM PDT 24
Peak memory 200676 kb
Host smart-6eab38c0-e8cf-4928-8c1b-3adfd9f45bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740269247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.3740269247
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.502999410
Short name T659
Test name
Test status
Simulation time 73089108958 ps
CPU time 76.12 seconds
Started Jun 23 05:41:01 PM PDT 24
Finished Jun 23 05:42:18 PM PDT 24
Peak memory 200760 kb
Host smart-c6e4b3ca-69a2-4045-b7f5-6a919ce12aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502999410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.502999410
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.3605067654
Short name T86
Test name
Test status
Simulation time 29391714269 ps
CPU time 45.79 seconds
Started Jun 23 05:41:08 PM PDT 24
Finished Jun 23 05:41:54 PM PDT 24
Peak memory 198172 kb
Host smart-fe66286b-3793-4abc-a8c2-c8b1461aff46
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605067654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.3605067654
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.3480599157
Short name T277
Test name
Test status
Simulation time 87831064669 ps
CPU time 484.14 seconds
Started Jun 23 05:41:04 PM PDT 24
Finished Jun 23 05:49:08 PM PDT 24
Peak memory 200644 kb
Host smart-40bbeb9d-147b-40a5-a9e4-9572fef23c29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3480599157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.3480599157
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.2363707682
Short name T326
Test name
Test status
Simulation time 6860079166 ps
CPU time 5.57 seconds
Started Jun 23 05:41:05 PM PDT 24
Finished Jun 23 05:41:11 PM PDT 24
Peak memory 200316 kb
Host smart-712f7cc9-22ae-476d-965b-6f45e755b9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363707682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.2363707682
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_perf.860689958
Short name T247
Test name
Test status
Simulation time 38435506079 ps
CPU time 311.58 seconds
Started Jun 23 05:41:02 PM PDT 24
Finished Jun 23 05:46:14 PM PDT 24
Peak memory 200616 kb
Host smart-04ff7ee4-feed-4eb8-b251-9d8a5fd61176
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=860689958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.860689958
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.2880969345
Short name T718
Test name
Test status
Simulation time 3503247129 ps
CPU time 2.06 seconds
Started Jun 23 05:41:00 PM PDT 24
Finished Jun 23 05:41:02 PM PDT 24
Peak memory 199368 kb
Host smart-fb3ba6bc-f7a1-4114-bef0-6bef1b980e00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2880969345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.2880969345
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.3581728426
Short name T816
Test name
Test status
Simulation time 66146413202 ps
CPU time 28.53 seconds
Started Jun 23 05:41:03 PM PDT 24
Finished Jun 23 05:41:31 PM PDT 24
Peak memory 200692 kb
Host smart-d6a1d494-fa11-4733-9c7e-fb4a8425df7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581728426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.3581728426
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.2286717253
Short name T547
Test name
Test status
Simulation time 2328287700 ps
CPU time 2.42 seconds
Started Jun 23 05:41:06 PM PDT 24
Finished Jun 23 05:41:09 PM PDT 24
Peak memory 196344 kb
Host smart-2ebb0c4c-0563-4a17-92f3-6149734020d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286717253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.2286717253
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.1758140476
Short name T538
Test name
Test status
Simulation time 461882376 ps
CPU time 2.3 seconds
Started Jun 23 05:41:01 PM PDT 24
Finished Jun 23 05:41:03 PM PDT 24
Peak memory 199116 kb
Host smart-71e5dff4-c3b9-4111-8917-887a4c24041f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758140476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.1758140476
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.1933914180
Short name T839
Test name
Test status
Simulation time 234811652876 ps
CPU time 325.22 seconds
Started Jun 23 05:41:02 PM PDT 24
Finished Jun 23 05:46:28 PM PDT 24
Peak memory 200652 kb
Host smart-81aa62f1-abbc-4da3-94f4-1fb640d1b265
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933914180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.1933914180
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.1378531239
Short name T720
Test name
Test status
Simulation time 97814105948 ps
CPU time 585.73 seconds
Started Jun 23 05:41:01 PM PDT 24
Finished Jun 23 05:50:47 PM PDT 24
Peak memory 208884 kb
Host smart-e4543239-8777-4315-ad12-fd5be8a75637
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378531239 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.1378531239
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.3644349652
Short name T917
Test name
Test status
Simulation time 6390502052 ps
CPU time 20.54 seconds
Started Jun 23 05:41:06 PM PDT 24
Finished Jun 23 05:41:26 PM PDT 24
Peak memory 200648 kb
Host smart-6028ff19-2ed4-491b-a2e3-6e0dbe724182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644349652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.3644349652
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.1111027770
Short name T392
Test name
Test status
Simulation time 24268932506 ps
CPU time 12.86 seconds
Started Jun 23 05:40:58 PM PDT 24
Finished Jun 23 05:41:12 PM PDT 24
Peak memory 200704 kb
Host smart-2898236f-a47e-475a-8fbd-f90db7a1c313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111027770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.1111027770
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.3357608199
Short name T735
Test name
Test status
Simulation time 22716010298 ps
CPU time 33.65 seconds
Started Jun 23 05:44:50 PM PDT 24
Finished Jun 23 05:45:24 PM PDT 24
Peak memory 200760 kb
Host smart-5ba6d15f-61c1-4fde-a37d-932399bda194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357608199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.3357608199
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.1710209910
Short name T530
Test name
Test status
Simulation time 9192192199 ps
CPU time 16.02 seconds
Started Jun 23 05:44:49 PM PDT 24
Finished Jun 23 05:45:05 PM PDT 24
Peak memory 200268 kb
Host smart-5409e32e-fff5-4636-ba0d-d570a37d0171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710209910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.1710209910
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.1495683325
Short name T171
Test name
Test status
Simulation time 97323541762 ps
CPU time 155.38 seconds
Started Jun 23 05:44:52 PM PDT 24
Finished Jun 23 05:47:28 PM PDT 24
Peak memory 200696 kb
Host smart-0bc1bf19-5841-4431-94c4-bff00e83191a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495683325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.1495683325
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.3303559690
Short name T173
Test name
Test status
Simulation time 13002076104 ps
CPU time 15.55 seconds
Started Jun 23 05:44:49 PM PDT 24
Finished Jun 23 05:45:05 PM PDT 24
Peak memory 200760 kb
Host smart-d63e0294-1db1-47f1-a0ef-4884da539ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303559690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.3303559690
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.1277198749
Short name T378
Test name
Test status
Simulation time 42706480068 ps
CPU time 17.17 seconds
Started Jun 23 05:44:49 PM PDT 24
Finished Jun 23 05:45:06 PM PDT 24
Peak memory 200700 kb
Host smart-94656751-519f-4721-9942-da0371bd1304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277198749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.1277198749
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.663212835
Short name T317
Test name
Test status
Simulation time 9977139457 ps
CPU time 8.92 seconds
Started Jun 23 05:44:49 PM PDT 24
Finished Jun 23 05:44:58 PM PDT 24
Peak memory 200348 kb
Host smart-c53b2820-8781-41a6-9941-8094ac945ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663212835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.663212835
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.190627614
Short name T162
Test name
Test status
Simulation time 32595058579 ps
CPU time 54.12 seconds
Started Jun 23 05:44:50 PM PDT 24
Finished Jun 23 05:45:44 PM PDT 24
Peak memory 200744 kb
Host smart-60131680-e7e1-4ad1-8376-097d9d04d80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190627614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.190627614
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.3790531606
Short name T822
Test name
Test status
Simulation time 62345705935 ps
CPU time 48.04 seconds
Started Jun 23 05:44:49 PM PDT 24
Finished Jun 23 05:45:37 PM PDT 24
Peak memory 200624 kb
Host smart-130102e3-4551-4c23-bfbe-09cd1c77aa0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790531606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.3790531606
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.985190786
Short name T184
Test name
Test status
Simulation time 185408757312 ps
CPU time 64.77 seconds
Started Jun 23 05:44:48 PM PDT 24
Finished Jun 23 05:45:53 PM PDT 24
Peak memory 200692 kb
Host smart-352e9a25-518f-4c8f-9950-b0991924c207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985190786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.985190786
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.2931103878
Short name T338
Test name
Test status
Simulation time 13526472 ps
CPU time 0.58 seconds
Started Jun 23 05:41:09 PM PDT 24
Finished Jun 23 05:41:10 PM PDT 24
Peak memory 196036 kb
Host smart-1f21ea52-f4ef-4ea1-84ac-2d737634d65a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931103878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.2931103878
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.2969550950
Short name T953
Test name
Test status
Simulation time 17590883837 ps
CPU time 25.03 seconds
Started Jun 23 05:41:09 PM PDT 24
Finished Jun 23 05:41:35 PM PDT 24
Peak memory 200716 kb
Host smart-0dc7aacc-2088-4f87-996f-8d69357b0e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969550950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.2969550950
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.13541769
Short name T143
Test name
Test status
Simulation time 51465088950 ps
CPU time 22.54 seconds
Started Jun 23 05:41:11 PM PDT 24
Finished Jun 23 05:41:34 PM PDT 24
Peak memory 200656 kb
Host smart-ce054c13-b980-4402-ad1c-478d8681db81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13541769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.13541769
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.2262920771
Short name T13
Test name
Test status
Simulation time 24133848324 ps
CPU time 10.85 seconds
Started Jun 23 05:41:08 PM PDT 24
Finished Jun 23 05:41:19 PM PDT 24
Peak memory 200692 kb
Host smart-acc493ea-00db-4d02-b5cd-08a04225dd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262920771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.2262920771
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.4211480409
Short name T873
Test name
Test status
Simulation time 39304266112 ps
CPU time 5.2 seconds
Started Jun 23 05:41:12 PM PDT 24
Finished Jun 23 05:41:18 PM PDT 24
Peak memory 198840 kb
Host smart-c5c1dc07-2926-406b-95c1-3e7d33dd02b4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211480409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.4211480409
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.16873496
Short name T679
Test name
Test status
Simulation time 194240449503 ps
CPU time 380.99 seconds
Started Jun 23 05:41:09 PM PDT 24
Finished Jun 23 05:47:30 PM PDT 24
Peak memory 200684 kb
Host smart-16b26504-4938-4202-a1ef-04615a6f94c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=16873496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.16873496
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.3154779735
Short name T467
Test name
Test status
Simulation time 5920629703 ps
CPU time 5.38 seconds
Started Jun 23 05:41:08 PM PDT 24
Finished Jun 23 05:41:14 PM PDT 24
Peak memory 199636 kb
Host smart-09f76018-1ed4-4e70-852a-96d0bc305092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154779735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.3154779735
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_perf.472809971
Short name T350
Test name
Test status
Simulation time 15311054153 ps
CPU time 71.56 seconds
Started Jun 23 05:41:08 PM PDT 24
Finished Jun 23 05:42:20 PM PDT 24
Peak memory 200704 kb
Host smart-d466c51f-08a8-4165-8c6f-a6110cf4bc02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=472809971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.472809971
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.1072246078
Short name T815
Test name
Test status
Simulation time 6632888892 ps
CPU time 29.72 seconds
Started Jun 23 05:41:09 PM PDT 24
Finished Jun 23 05:41:39 PM PDT 24
Peak memory 198988 kb
Host smart-520f240e-aa0a-4448-a92a-9be9a2f2c704
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1072246078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.1072246078
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.735118822
Short name T394
Test name
Test status
Simulation time 91427464485 ps
CPU time 130.84 seconds
Started Jun 23 05:41:10 PM PDT 24
Finished Jun 23 05:43:21 PM PDT 24
Peak memory 200700 kb
Host smart-691ce984-8355-4376-9dd3-13e0924e7630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735118822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.735118822
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.1814419096
Short name T497
Test name
Test status
Simulation time 3370240937 ps
CPU time 1.94 seconds
Started Jun 23 05:41:06 PM PDT 24
Finished Jun 23 05:41:08 PM PDT 24
Peak memory 196808 kb
Host smart-bcba9e2c-04ac-44c3-9dc5-aa75626beed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814419096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.1814419096
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.2780113742
Short name T364
Test name
Test status
Simulation time 453639040 ps
CPU time 1.7 seconds
Started Jun 23 05:41:05 PM PDT 24
Finished Jun 23 05:41:07 PM PDT 24
Peak memory 200608 kb
Host smart-34c795be-684f-4398-bc9a-42b36e42e476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780113742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.2780113742
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.332270846
Short name T949
Test name
Test status
Simulation time 297364531710 ps
CPU time 645.29 seconds
Started Jun 23 05:41:09 PM PDT 24
Finished Jun 23 05:51:55 PM PDT 24
Peak memory 200644 kb
Host smart-d2cd2655-68a7-4f3a-a040-246f9fb5fa0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332270846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.332270846
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.413401668
Short name T46
Test name
Test status
Simulation time 75791958680 ps
CPU time 481.26 seconds
Started Jun 23 05:41:07 PM PDT 24
Finished Jun 23 05:49:09 PM PDT 24
Peak memory 217120 kb
Host smart-b39bb004-4141-4b7c-b7c9-5d8d25f1eeb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413401668 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.413401668
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.3553519296
Short name T342
Test name
Test status
Simulation time 7074632221 ps
CPU time 18.92 seconds
Started Jun 23 05:41:10 PM PDT 24
Finished Jun 23 05:41:30 PM PDT 24
Peak memory 200652 kb
Host smart-9dea2ce7-eb15-40da-9a68-6ae02d419087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553519296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.3553519296
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.1262813277
Short name T1084
Test name
Test status
Simulation time 19696402848 ps
CPU time 16.35 seconds
Started Jun 23 05:41:04 PM PDT 24
Finished Jun 23 05:41:21 PM PDT 24
Peak memory 200760 kb
Host smart-2c712b72-4663-4ce2-aa56-2ab5f656597b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262813277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.1262813277
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.1632181743
Short name T133
Test name
Test status
Simulation time 101931047346 ps
CPU time 165.17 seconds
Started Jun 23 05:44:53 PM PDT 24
Finished Jun 23 05:47:39 PM PDT 24
Peak memory 200668 kb
Host smart-f3fff0da-45e8-4d49-bf52-e42539712ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632181743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.1632181743
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.835132293
Short name T564
Test name
Test status
Simulation time 40515706291 ps
CPU time 65.09 seconds
Started Jun 23 05:44:52 PM PDT 24
Finished Jun 23 05:45:58 PM PDT 24
Peak memory 200760 kb
Host smart-3380406f-0818-4ee7-ab75-db5713d35958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835132293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.835132293
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.1095027790
Short name T174
Test name
Test status
Simulation time 51272738505 ps
CPU time 72.05 seconds
Started Jun 23 05:44:56 PM PDT 24
Finished Jun 23 05:46:08 PM PDT 24
Peak memory 200728 kb
Host smart-839635d3-f26a-4155-abcd-d3227ca67bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095027790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.1095027790
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.3808093621
Short name T215
Test name
Test status
Simulation time 39027585118 ps
CPU time 16.84 seconds
Started Jun 23 05:44:59 PM PDT 24
Finished Jun 23 05:45:16 PM PDT 24
Peak memory 200664 kb
Host smart-39a4fdd6-7442-4262-8d39-8aa1e01bfea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808093621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.3808093621
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.1621719874
Short name T319
Test name
Test status
Simulation time 70998445986 ps
CPU time 113.69 seconds
Started Jun 23 05:44:52 PM PDT 24
Finished Jun 23 05:46:45 PM PDT 24
Peak memory 200648 kb
Host smart-3b240b2e-0187-4391-a493-80ef69eb5c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621719874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.1621719874
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.2944658207
Short name T315
Test name
Test status
Simulation time 41278651861 ps
CPU time 30.14 seconds
Started Jun 23 05:44:55 PM PDT 24
Finished Jun 23 05:45:25 PM PDT 24
Peak memory 200612 kb
Host smart-8bfcf52f-320f-43d6-8aa2-e1d89aed7a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944658207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.2944658207
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.231519236
Short name T590
Test name
Test status
Simulation time 14680469918 ps
CPU time 18 seconds
Started Jun 23 05:44:54 PM PDT 24
Finished Jun 23 05:45:13 PM PDT 24
Peak memory 200488 kb
Host smart-c03a27d8-b19f-47a3-8f70-fb193201fedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231519236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.231519236
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.2288390410
Short name T176
Test name
Test status
Simulation time 13802752005 ps
CPU time 21.69 seconds
Started Jun 23 05:44:51 PM PDT 24
Finished Jun 23 05:45:13 PM PDT 24
Peak memory 200724 kb
Host smart-1091b4bc-7a1b-4779-8f8e-b00c6d7c55eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288390410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.2288390410
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.2355966203
Short name T400
Test name
Test status
Simulation time 9170279172 ps
CPU time 14.81 seconds
Started Jun 23 05:44:54 PM PDT 24
Finished Jun 23 05:45:09 PM PDT 24
Peak memory 200692 kb
Host smart-ff046921-6e09-4a9a-b7a5-7b1d3cd96567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355966203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.2355966203
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.1476902871
Short name T793
Test name
Test status
Simulation time 101315596975 ps
CPU time 151.26 seconds
Started Jun 23 05:44:53 PM PDT 24
Finished Jun 23 05:47:24 PM PDT 24
Peak memory 200676 kb
Host smart-48bf1b7e-5950-4528-8a3a-04b01e0cf3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476902871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.1476902871
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.414637783
Short name T773
Test name
Test status
Simulation time 22983658 ps
CPU time 0.57 seconds
Started Jun 23 05:39:54 PM PDT 24
Finished Jun 23 05:39:55 PM PDT 24
Peak memory 195040 kb
Host smart-29583bfb-46ad-4573-a834-26fa65188e1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414637783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.414637783
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.2518810782
Short name T455
Test name
Test status
Simulation time 41504841393 ps
CPU time 20.13 seconds
Started Jun 23 05:39:49 PM PDT 24
Finished Jun 23 05:40:09 PM PDT 24
Peak memory 200696 kb
Host smart-b50a27f4-40e0-4eff-9d04-810504346f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518810782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.2518810782
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.2894002891
Short name T395
Test name
Test status
Simulation time 12702189080 ps
CPU time 21.53 seconds
Started Jun 23 05:39:50 PM PDT 24
Finished Jun 23 05:40:12 PM PDT 24
Peak memory 200520 kb
Host smart-aa2d72a0-7d26-410a-a0b2-98f8ab665636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894002891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.2894002891
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.2281252815
Short name T87
Test name
Test status
Simulation time 22264340067 ps
CPU time 17.41 seconds
Started Jun 23 05:39:51 PM PDT 24
Finished Jun 23 05:40:09 PM PDT 24
Peak memory 199784 kb
Host smart-360ca9a6-05f8-4675-8ef3-588b43140053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281252815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.2281252815
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.2360138695
Short name T733
Test name
Test status
Simulation time 24847444256 ps
CPU time 45.49 seconds
Started Jun 23 05:39:51 PM PDT 24
Finished Jun 23 05:40:37 PM PDT 24
Peak memory 200264 kb
Host smart-ec653eba-3e75-4f1b-83e1-fb67848a9546
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360138695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.2360138695
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.1167903100
Short name T352
Test name
Test status
Simulation time 60639675479 ps
CPU time 643.32 seconds
Started Jun 23 05:39:54 PM PDT 24
Finished Jun 23 05:50:37 PM PDT 24
Peak memory 200680 kb
Host smart-b2f8a5ee-11b5-4d1e-b59a-cc6f1ba3874f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1167903100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.1167903100
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.2679915135
Short name T690
Test name
Test status
Simulation time 2724534622 ps
CPU time 4.22 seconds
Started Jun 23 05:39:54 PM PDT 24
Finished Jun 23 05:39:59 PM PDT 24
Peak memory 199728 kb
Host smart-7fa69e5d-ab01-426d-8016-8b59f9c96028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679915135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.2679915135
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_perf.1982301558
Short name T440
Test name
Test status
Simulation time 17602227409 ps
CPU time 1008.55 seconds
Started Jun 23 05:39:54 PM PDT 24
Finished Jun 23 05:56:43 PM PDT 24
Peak memory 200676 kb
Host smart-f571a22d-2dc7-47b4-a64d-cbf9449f485e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1982301558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.1982301558
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.3953390652
Short name T795
Test name
Test status
Simulation time 2889870623 ps
CPU time 4.64 seconds
Started Jun 23 05:39:48 PM PDT 24
Finished Jun 23 05:39:53 PM PDT 24
Peak memory 199916 kb
Host smart-0959f820-c018-4aef-a15b-0d6c63802a83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3953390652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.3953390652
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.3221504921
Short name T503
Test name
Test status
Simulation time 145910931019 ps
CPU time 62.33 seconds
Started Jun 23 05:39:49 PM PDT 24
Finished Jun 23 05:40:51 PM PDT 24
Peak memory 200796 kb
Host smart-c8ae9671-1f13-450a-a274-a7c739ab7981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221504921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.3221504921
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.3479179215
Short name T580
Test name
Test status
Simulation time 6540284743 ps
CPU time 10.94 seconds
Started Jun 23 05:39:50 PM PDT 24
Finished Jun 23 05:40:01 PM PDT 24
Peak memory 196784 kb
Host smart-169cf5bb-1ec6-44f6-9fbd-ba52ca90a2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479179215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.3479179215
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.2102835035
Short name T25
Test name
Test status
Simulation time 98993230 ps
CPU time 0.78 seconds
Started Jun 23 05:39:54 PM PDT 24
Finished Jun 23 05:39:55 PM PDT 24
Peak memory 219120 kb
Host smart-508c020b-d401-4622-b6c0-c896bdb5591e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102835035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.2102835035
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.2264500650
Short name T719
Test name
Test status
Simulation time 642809277 ps
CPU time 2.24 seconds
Started Jun 23 05:39:49 PM PDT 24
Finished Jun 23 05:39:52 PM PDT 24
Peak memory 199436 kb
Host smart-7957f7f0-2d6d-4a92-8900-55bef8eb8035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264500650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.2264500650
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.3775591449
Short name T45
Test name
Test status
Simulation time 160054832019 ps
CPU time 693.78 seconds
Started Jun 23 05:39:54 PM PDT 24
Finished Jun 23 05:51:28 PM PDT 24
Peak memory 214612 kb
Host smart-7e4a20a3-2661-41ea-a34e-e6758f41150f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775591449 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.3775591449
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.1643644617
Short name T996
Test name
Test status
Simulation time 8282790157 ps
CPU time 11.81 seconds
Started Jun 23 05:39:54 PM PDT 24
Finished Jun 23 05:40:06 PM PDT 24
Peak memory 200648 kb
Host smart-9377ae8c-a537-42b1-aecf-cde930efef89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643644617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.1643644617
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.2695376696
Short name T544
Test name
Test status
Simulation time 62545467072 ps
CPU time 101.55 seconds
Started Jun 23 05:39:51 PM PDT 24
Finished Jun 23 05:41:33 PM PDT 24
Peak memory 200668 kb
Host smart-9b18d4ba-30c6-4c46-b5aa-6c3978ef0915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695376696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.2695376696
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.967243447
Short name T856
Test name
Test status
Simulation time 11692072 ps
CPU time 0.55 seconds
Started Jun 23 05:41:12 PM PDT 24
Finished Jun 23 05:41:13 PM PDT 24
Peak memory 195032 kb
Host smart-3db358e9-8be4-483e-ac58-a363f8714d95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967243447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.967243447
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.1403110552
Short name T432
Test name
Test status
Simulation time 47153983205 ps
CPU time 82.74 seconds
Started Jun 23 05:41:12 PM PDT 24
Finished Jun 23 05:42:35 PM PDT 24
Peak memory 200896 kb
Host smart-54b3274c-4353-42c9-b7e7-d469480315cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403110552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.1403110552
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.568866837
Short name T608
Test name
Test status
Simulation time 316155230835 ps
CPU time 70.44 seconds
Started Jun 23 05:41:14 PM PDT 24
Finished Jun 23 05:42:25 PM PDT 24
Peak memory 200700 kb
Host smart-3d3d9c05-0ab8-4885-b594-9fc349f0c54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568866837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.568866837
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.2122261642
Short name T699
Test name
Test status
Simulation time 32340624053 ps
CPU time 23.91 seconds
Started Jun 23 05:41:12 PM PDT 24
Finished Jun 23 05:41:36 PM PDT 24
Peak memory 200688 kb
Host smart-09f5afff-6133-42df-a834-424a20fc34c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122261642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.2122261642
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.3792704929
Short name T722
Test name
Test status
Simulation time 71239012203 ps
CPU time 44.39 seconds
Started Jun 23 05:41:15 PM PDT 24
Finished Jun 23 05:42:00 PM PDT 24
Peak memory 200740 kb
Host smart-e84ec864-d734-4a11-ab56-19fc0859c079
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792704929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.3792704929
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.3208103785
Short name T376
Test name
Test status
Simulation time 89388264823 ps
CPU time 252.63 seconds
Started Jun 23 05:41:13 PM PDT 24
Finished Jun 23 05:45:26 PM PDT 24
Peak memory 200740 kb
Host smart-c38ccfc2-5791-4634-bc16-4ddff0d5a813
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3208103785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.3208103785
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.1767742743
Short name T683
Test name
Test status
Simulation time 3436898277 ps
CPU time 7.64 seconds
Started Jun 23 05:41:13 PM PDT 24
Finished Jun 23 05:41:21 PM PDT 24
Peak memory 200644 kb
Host smart-4d97e076-c249-468c-8387-e7c5678dcef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767742743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.1767742743
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.3798989720
Short name T585
Test name
Test status
Simulation time 3671079256 ps
CPU time 5.29 seconds
Started Jun 23 05:41:14 PM PDT 24
Finished Jun 23 05:41:20 PM PDT 24
Peak memory 197824 kb
Host smart-0dcf5bef-6a4b-4b8c-9ef4-ed5b0004cc73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798989720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.3798989720
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.927654352
Short name T765
Test name
Test status
Simulation time 11538266148 ps
CPU time 64.57 seconds
Started Jun 23 05:41:14 PM PDT 24
Finished Jun 23 05:42:19 PM PDT 24
Peak memory 200668 kb
Host smart-0c32248b-23d7-4ca9-b9a6-39687eb03c27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=927654352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.927654352
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.1126917787
Short name T363
Test name
Test status
Simulation time 1479541557 ps
CPU time 6.19 seconds
Started Jun 23 05:41:13 PM PDT 24
Finished Jun 23 05:41:20 PM PDT 24
Peak memory 198968 kb
Host smart-e6fd15f8-fb94-4349-8a06-f9991cd002ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1126917787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.1126917787
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.3059459109
Short name T697
Test name
Test status
Simulation time 97886276951 ps
CPU time 159.31 seconds
Started Jun 23 05:41:15 PM PDT 24
Finished Jun 23 05:43:55 PM PDT 24
Peak memory 200708 kb
Host smart-e0748568-98cb-490d-a20a-cbf2ff856592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059459109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.3059459109
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.4180566461
Short name T1064
Test name
Test status
Simulation time 4866309468 ps
CPU time 1.5 seconds
Started Jun 23 05:41:16 PM PDT 24
Finished Jun 23 05:41:18 PM PDT 24
Peak memory 197516 kb
Host smart-d956d46f-e92d-4c34-be78-5c757012d50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180566461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.4180566461
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.3482977010
Short name T2
Test name
Test status
Simulation time 536269811 ps
CPU time 2.55 seconds
Started Jun 23 05:41:12 PM PDT 24
Finished Jun 23 05:41:15 PM PDT 24
Peak memory 200552 kb
Host smart-0022f080-bd87-444b-885e-dd359052e468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482977010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.3482977010
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.3708918537
Short name T518
Test name
Test status
Simulation time 104700878855 ps
CPU time 531.55 seconds
Started Jun 23 05:41:14 PM PDT 24
Finished Jun 23 05:50:06 PM PDT 24
Peak memory 216796 kb
Host smart-991d6e3e-c968-4669-a503-c63a95ead2cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708918537 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.3708918537
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.2823672152
Short name T410
Test name
Test status
Simulation time 1337193566 ps
CPU time 2.03 seconds
Started Jun 23 05:41:14 PM PDT 24
Finished Jun 23 05:41:17 PM PDT 24
Peak memory 199720 kb
Host smart-074c910e-3094-4dc4-a265-80d85346880a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823672152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.2823672152
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.41941056
Short name T763
Test name
Test status
Simulation time 92173817954 ps
CPU time 137.91 seconds
Started Jun 23 05:41:08 PM PDT 24
Finished Jun 23 05:43:27 PM PDT 24
Peak memory 200736 kb
Host smart-a539de5b-74dc-4284-9f33-4bf21c58ac10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41941056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.41941056
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.3963182276
Short name T471
Test name
Test status
Simulation time 46575628474 ps
CPU time 76.42 seconds
Started Jun 23 05:44:56 PM PDT 24
Finished Jun 23 05:46:12 PM PDT 24
Peak memory 200788 kb
Host smart-7e4b750e-5a7f-47f6-9eb1-a6c6f7f18d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963182276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.3963182276
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.3235262053
Short name T127
Test name
Test status
Simulation time 76933952127 ps
CPU time 32.56 seconds
Started Jun 23 05:45:00 PM PDT 24
Finished Jun 23 05:45:33 PM PDT 24
Peak memory 200752 kb
Host smart-9a181753-a265-4a51-9b5c-f3da5eeb031a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235262053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.3235262053
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.1883658554
Short name T672
Test name
Test status
Simulation time 33624340726 ps
CPU time 53.97 seconds
Started Jun 23 05:44:59 PM PDT 24
Finished Jun 23 05:45:53 PM PDT 24
Peak memory 200760 kb
Host smart-114f8229-2360-4c2e-85af-98cc4f53ff2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883658554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.1883658554
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.3037288259
Short name T267
Test name
Test status
Simulation time 141541531793 ps
CPU time 213.6 seconds
Started Jun 23 05:44:59 PM PDT 24
Finished Jun 23 05:48:32 PM PDT 24
Peak memory 200892 kb
Host smart-fe05e692-ca0b-42c8-ad55-a94d2f25389e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037288259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.3037288259
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.1170968817
Short name T957
Test name
Test status
Simulation time 193077446307 ps
CPU time 52.33 seconds
Started Jun 23 05:44:55 PM PDT 24
Finished Jun 23 05:45:48 PM PDT 24
Peak memory 200580 kb
Host smart-9e327128-7f47-45ea-8304-31e50ce574cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170968817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.1170968817
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.1150398947
Short name T368
Test name
Test status
Simulation time 12175875041 ps
CPU time 14.36 seconds
Started Jun 23 05:44:59 PM PDT 24
Finished Jun 23 05:45:13 PM PDT 24
Peak memory 200688 kb
Host smart-fb116787-5643-4afe-868c-f5bd2d96567e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150398947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.1150398947
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.4133636339
Short name T324
Test name
Test status
Simulation time 72878358960 ps
CPU time 26.87 seconds
Started Jun 23 05:44:58 PM PDT 24
Finished Jun 23 05:45:25 PM PDT 24
Peak memory 200288 kb
Host smart-01243d48-2060-4dfc-a7f7-4142c93b65b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133636339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.4133636339
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.1514016038
Short name T135
Test name
Test status
Simulation time 133825849384 ps
CPU time 46.76 seconds
Started Jun 23 05:45:00 PM PDT 24
Finished Jun 23 05:45:47 PM PDT 24
Peak memory 200676 kb
Host smart-8da2e215-f7f1-43e6-a9a0-d0191a467252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514016038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.1514016038
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.2110733285
Short name T206
Test name
Test status
Simulation time 100894643640 ps
CPU time 133.74 seconds
Started Jun 23 05:44:59 PM PDT 24
Finished Jun 23 05:47:13 PM PDT 24
Peak memory 200788 kb
Host smart-7c9ad93f-a89d-46ca-a272-a3d8583c78e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110733285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.2110733285
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.559537678
Short name T522
Test name
Test status
Simulation time 31530033 ps
CPU time 0.55 seconds
Started Jun 23 05:41:24 PM PDT 24
Finished Jun 23 05:41:25 PM PDT 24
Peak memory 196396 kb
Host smart-586a60ef-f3e6-4a08-888e-be5e263a85af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559537678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.559537678
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.3556638499
Short name T958
Test name
Test status
Simulation time 116027958295 ps
CPU time 196.36 seconds
Started Jun 23 05:41:18 PM PDT 24
Finished Jun 23 05:44:35 PM PDT 24
Peak memory 200700 kb
Host smart-a779fb1f-b827-48ac-8362-ff02081a1e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556638499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.3556638499
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.3967508071
Short name T694
Test name
Test status
Simulation time 7720134297 ps
CPU time 13.82 seconds
Started Jun 23 05:41:19 PM PDT 24
Finished Jun 23 05:41:34 PM PDT 24
Peak memory 200672 kb
Host smart-68e22113-f349-46d7-a849-a4af7ea7715f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967508071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.3967508071
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.440853367
Short name T1040
Test name
Test status
Simulation time 41002494206 ps
CPU time 21.83 seconds
Started Jun 23 05:41:21 PM PDT 24
Finished Jun 23 05:41:43 PM PDT 24
Peak memory 200696 kb
Host smart-626bb704-c6b5-4a8f-94db-27fb20cb1a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440853367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.440853367
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.3969750637
Short name T495
Test name
Test status
Simulation time 42229271794 ps
CPU time 17.77 seconds
Started Jun 23 05:41:19 PM PDT 24
Finished Jun 23 05:41:37 PM PDT 24
Peak memory 200700 kb
Host smart-e644656d-a261-478f-80cd-d2f0da98f377
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969750637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.3969750637
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.518172868
Short name T781
Test name
Test status
Simulation time 92464211717 ps
CPU time 268.94 seconds
Started Jun 23 05:41:27 PM PDT 24
Finished Jun 23 05:45:57 PM PDT 24
Peak memory 200728 kb
Host smart-ff89d91e-a9f2-4605-9dc8-5077a0a1ccfe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=518172868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.518172868
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.2555497323
Short name T875
Test name
Test status
Simulation time 142766291 ps
CPU time 0.66 seconds
Started Jun 23 05:41:35 PM PDT 24
Finished Jun 23 05:41:36 PM PDT 24
Peak memory 196668 kb
Host smart-0e3c26dd-bf72-43cb-b241-79ae4f3b7d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555497323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.2555497323
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.4292755335
Short name T236
Test name
Test status
Simulation time 50795464388 ps
CPU time 95.18 seconds
Started Jun 23 05:41:20 PM PDT 24
Finished Jun 23 05:42:55 PM PDT 24
Peak memory 200704 kb
Host smart-c319a74f-262e-4751-b957-26db959afb37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292755335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.4292755335
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.4119829682
Short name T872
Test name
Test status
Simulation time 26864597240 ps
CPU time 327.48 seconds
Started Jun 23 05:41:19 PM PDT 24
Finished Jun 23 05:46:47 PM PDT 24
Peak memory 200736 kb
Host smart-38911b1d-6ab6-4b5b-aa07-7547d8361b6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4119829682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.4119829682
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.1106975943
Short name T664
Test name
Test status
Simulation time 7465309537 ps
CPU time 4.61 seconds
Started Jun 23 05:41:23 PM PDT 24
Finished Jun 23 05:41:27 PM PDT 24
Peak memory 198872 kb
Host smart-91e314da-d165-43e4-99d6-9478525c5533
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1106975943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.1106975943
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.1195438667
Short name T956
Test name
Test status
Simulation time 9868968131 ps
CPU time 15.56 seconds
Started Jun 23 05:41:19 PM PDT 24
Finished Jun 23 05:41:35 PM PDT 24
Peak memory 200624 kb
Host smart-cc73e810-2c0f-4493-9d56-2e94ad45d549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195438667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.1195438667
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.769329836
Short name T285
Test name
Test status
Simulation time 49528870544 ps
CPU time 69.37 seconds
Started Jun 23 05:41:22 PM PDT 24
Finished Jun 23 05:42:32 PM PDT 24
Peak memory 196720 kb
Host smart-60fbb3b5-1aa8-42ee-a1d2-391e93c8fbde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769329836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.769329836
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.292058513
Short name T502
Test name
Test status
Simulation time 505978499 ps
CPU time 1.06 seconds
Started Jun 23 05:41:14 PM PDT 24
Finished Jun 23 05:41:16 PM PDT 24
Peak memory 199140 kb
Host smart-e50346bf-a992-4718-90b1-5cfa2fc20d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292058513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.292058513
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.3292918402
Short name T295
Test name
Test status
Simulation time 137373501311 ps
CPU time 338.73 seconds
Started Jun 23 05:41:24 PM PDT 24
Finished Jun 23 05:47:03 PM PDT 24
Peak memory 200752 kb
Host smart-1df4f8ac-742a-4a24-b931-e6ec3599f245
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292918402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.3292918402
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.2100600379
Short name T633
Test name
Test status
Simulation time 148739419067 ps
CPU time 713.88 seconds
Started Jun 23 05:41:23 PM PDT 24
Finished Jun 23 05:53:17 PM PDT 24
Peak memory 217040 kb
Host smart-d48c2169-ff94-4294-b1ff-71f79ac5af03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100600379 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.2100600379
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.3114413464
Short name T944
Test name
Test status
Simulation time 2911382096 ps
CPU time 2.21 seconds
Started Jun 23 05:41:21 PM PDT 24
Finished Jun 23 05:41:23 PM PDT 24
Peak memory 199632 kb
Host smart-fca83490-f290-42dc-a166-0401ccd49b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114413464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.3114413464
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.3732378097
Short name T758
Test name
Test status
Simulation time 46365094307 ps
CPU time 41.32 seconds
Started Jun 23 05:41:15 PM PDT 24
Finished Jun 23 05:41:57 PM PDT 24
Peak memory 200732 kb
Host smart-f8e2f7aa-697f-4930-85b6-f3d6a08ca683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732378097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.3732378097
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.3266733837
Short name T1056
Test name
Test status
Simulation time 95654155929 ps
CPU time 32.8 seconds
Started Jun 23 05:45:03 PM PDT 24
Finished Jun 23 05:45:36 PM PDT 24
Peak memory 200752 kb
Host smart-0164feee-6470-42d1-b12a-9f99323195a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266733837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.3266733837
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.2921772148
Short name T193
Test name
Test status
Simulation time 40631011052 ps
CPU time 36.29 seconds
Started Jun 23 05:45:02 PM PDT 24
Finished Jun 23 05:45:39 PM PDT 24
Peak memory 200708 kb
Host smart-ad2be933-777f-42f4-9e60-98d67743163e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921772148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.2921772148
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.44909227
Short name T584
Test name
Test status
Simulation time 115516448723 ps
CPU time 24.48 seconds
Started Jun 23 05:45:03 PM PDT 24
Finished Jun 23 05:45:28 PM PDT 24
Peak memory 200752 kb
Host smart-907f6d12-b1eb-451f-a4bc-083994c0645c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44909227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.44909227
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.4233604134
Short name T217
Test name
Test status
Simulation time 101570949076 ps
CPU time 46.89 seconds
Started Jun 23 05:45:04 PM PDT 24
Finished Jun 23 05:45:51 PM PDT 24
Peak memory 200708 kb
Host smart-b58fcf9a-868a-4ee7-88fe-8b01307d5927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233604134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.4233604134
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.3524400744
Short name T235
Test name
Test status
Simulation time 48910845649 ps
CPU time 69.23 seconds
Started Jun 23 05:45:03 PM PDT 24
Finished Jun 23 05:46:12 PM PDT 24
Peak memory 200772 kb
Host smart-b40ef138-dd22-49a5-ad2c-d2a7fe9d472f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524400744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.3524400744
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.3839385767
Short name T181
Test name
Test status
Simulation time 86050736542 ps
CPU time 31.13 seconds
Started Jun 23 05:45:06 PM PDT 24
Finished Jun 23 05:45:37 PM PDT 24
Peak memory 200760 kb
Host smart-26f8f6a4-3558-49d6-a44d-1f1d0d9e7b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839385767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.3839385767
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.1162756579
Short name T189
Test name
Test status
Simulation time 86681903121 ps
CPU time 43.28 seconds
Started Jun 23 05:45:05 PM PDT 24
Finished Jun 23 05:45:49 PM PDT 24
Peak memory 200700 kb
Host smart-81bfc9fd-315d-4138-8d1b-90352e38de53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162756579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.1162756579
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.3577559269
Short name T604
Test name
Test status
Simulation time 142753800667 ps
CPU time 34.39 seconds
Started Jun 23 05:45:06 PM PDT 24
Finished Jun 23 05:45:40 PM PDT 24
Peak memory 200684 kb
Host smart-6323a8e5-61ea-4b4b-9c57-b8a9fbe413a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577559269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.3577559269
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.4247162361
Short name T204
Test name
Test status
Simulation time 63051628969 ps
CPU time 47.04 seconds
Started Jun 23 05:45:02 PM PDT 24
Finished Jun 23 05:45:50 PM PDT 24
Peak memory 200748 kb
Host smart-8a1d85ae-9f51-4edc-b3f7-475d71ca66ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247162361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.4247162361
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.1297740701
Short name T619
Test name
Test status
Simulation time 43222839 ps
CPU time 0.55 seconds
Started Jun 23 05:41:26 PM PDT 24
Finished Jun 23 05:41:27 PM PDT 24
Peak memory 196108 kb
Host smart-de66d148-f2df-49c5-b3d3-aac89d7890a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297740701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.1297740701
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.3689790122
Short name T1006
Test name
Test status
Simulation time 73671049102 ps
CPU time 30.09 seconds
Started Jun 23 05:41:28 PM PDT 24
Finished Jun 23 05:41:58 PM PDT 24
Peak memory 200688 kb
Host smart-468d8e02-95b1-430e-9bc1-ea2b11f9a639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689790122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.3689790122
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.573390945
Short name T404
Test name
Test status
Simulation time 117979830906 ps
CPU time 89.24 seconds
Started Jun 23 05:41:28 PM PDT 24
Finished Jun 23 05:42:58 PM PDT 24
Peak memory 200748 kb
Host smart-5f549d47-f8ca-4cdf-ab97-e02e76878766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573390945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.573390945
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.2781766188
Short name T178
Test name
Test status
Simulation time 94893752012 ps
CPU time 151.79 seconds
Started Jun 23 05:41:23 PM PDT 24
Finished Jun 23 05:43:55 PM PDT 24
Peak memory 200728 kb
Host smart-22002309-6e4e-45f9-9eb4-b6db063b0735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781766188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.2781766188
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.1960343918
Short name T1031
Test name
Test status
Simulation time 24545753073 ps
CPU time 43.13 seconds
Started Jun 23 05:41:23 PM PDT 24
Finished Jun 23 05:42:07 PM PDT 24
Peak memory 200688 kb
Host smart-b8239b42-0e61-4b6d-afc7-a93e380fe4d4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960343918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.1960343918
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.1375344466
Short name T601
Test name
Test status
Simulation time 128114448723 ps
CPU time 433.1 seconds
Started Jun 23 05:41:31 PM PDT 24
Finished Jun 23 05:48:44 PM PDT 24
Peak memory 200676 kb
Host smart-79958bb2-0f15-45e1-84a6-d757d47e4048
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1375344466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.1375344466
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.2933381813
Short name T357
Test name
Test status
Simulation time 1145580653 ps
CPU time 1.17 seconds
Started Jun 23 05:41:28 PM PDT 24
Finished Jun 23 05:41:29 PM PDT 24
Peak memory 198164 kb
Host smart-1aaabee5-7ea9-462a-ab66-40e0a4ace429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933381813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.2933381813
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_perf.1794259732
Short name T948
Test name
Test status
Simulation time 12526113629 ps
CPU time 661.31 seconds
Started Jun 23 05:41:27 PM PDT 24
Finished Jun 23 05:52:29 PM PDT 24
Peak memory 200616 kb
Host smart-b15d34a4-20f8-425f-9ccc-7919ba29cfeb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1794259732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.1794259732
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.3197597977
Short name T791
Test name
Test status
Simulation time 2416311413 ps
CPU time 9.37 seconds
Started Jun 23 05:41:25 PM PDT 24
Finished Jun 23 05:41:34 PM PDT 24
Peak memory 198796 kb
Host smart-8b6a8ff8-4504-435c-bf64-6625a70ad525
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3197597977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.3197597977
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.2234907809
Short name T474
Test name
Test status
Simulation time 162580754416 ps
CPU time 18.43 seconds
Started Jun 23 05:41:27 PM PDT 24
Finished Jun 23 05:41:46 PM PDT 24
Peak memory 200492 kb
Host smart-c796945f-8318-41b9-b0ad-f7de5bd159f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234907809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.2234907809
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.4271380535
Short name T21
Test name
Test status
Simulation time 6577783841 ps
CPU time 1.55 seconds
Started Jun 23 05:41:27 PM PDT 24
Finished Jun 23 05:41:28 PM PDT 24
Peak memory 196760 kb
Host smart-5a504095-903b-40c1-ab40-37f855a6b8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271380535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.4271380535
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.233539807
Short name T391
Test name
Test status
Simulation time 464065592 ps
CPU time 1.6 seconds
Started Jun 23 05:41:28 PM PDT 24
Finished Jun 23 05:41:30 PM PDT 24
Peak memory 199116 kb
Host smart-2352eb4d-ba93-4a58-99e2-2b886a21d89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233539807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.233539807
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.2622671606
Short name T983
Test name
Test status
Simulation time 1887569100 ps
CPU time 1.5 seconds
Started Jun 23 05:41:23 PM PDT 24
Finished Jun 23 05:41:25 PM PDT 24
Peak memory 199024 kb
Host smart-e02e9029-c170-4da3-97b3-1b2bc7a94be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622671606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.2622671606
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.1889818164
Short name T484
Test name
Test status
Simulation time 132919668024 ps
CPU time 162.63 seconds
Started Jun 23 05:45:03 PM PDT 24
Finished Jun 23 05:47:46 PM PDT 24
Peak memory 200672 kb
Host smart-59c0b04a-7f6c-4bd6-ad22-31194755a434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889818164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.1889818164
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.2106281975
Short name T321
Test name
Test status
Simulation time 110089317336 ps
CPU time 48.37 seconds
Started Jun 23 05:45:06 PM PDT 24
Finished Jun 23 05:45:55 PM PDT 24
Peak memory 200692 kb
Host smart-9dcffec4-cca9-4e0b-b124-80f371e2d309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106281975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.2106281975
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.151206681
Short name T505
Test name
Test status
Simulation time 158541568791 ps
CPU time 16.94 seconds
Started Jun 23 05:45:09 PM PDT 24
Finished Jun 23 05:45:26 PM PDT 24
Peak memory 200620 kb
Host smart-f85ca91b-e175-4125-84c8-0630d211d2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151206681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.151206681
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.2784537074
Short name T213
Test name
Test status
Simulation time 107709190376 ps
CPU time 52.57 seconds
Started Jun 23 05:45:16 PM PDT 24
Finished Jun 23 05:46:08 PM PDT 24
Peak memory 200644 kb
Host smart-d4e17c4c-6d3a-4ceb-a33a-87f4e0819cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784537074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.2784537074
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.2540884965
Short name T187
Test name
Test status
Simulation time 125800271209 ps
CPU time 35 seconds
Started Jun 23 05:45:06 PM PDT 24
Finished Jun 23 05:45:42 PM PDT 24
Peak memory 200640 kb
Host smart-158926ac-37ef-45a3-9991-748ccbb1c465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540884965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.2540884965
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.2350200813
Short name T609
Test name
Test status
Simulation time 47384409324 ps
CPU time 14.85 seconds
Started Jun 23 05:45:05 PM PDT 24
Finished Jun 23 05:45:20 PM PDT 24
Peak memory 200740 kb
Host smart-03a9f5a5-9953-4c0d-aa26-ccf0ff1ff5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350200813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.2350200813
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.1527008074
Short name T165
Test name
Test status
Simulation time 12440462718 ps
CPU time 21.03 seconds
Started Jun 23 05:45:14 PM PDT 24
Finished Jun 23 05:45:36 PM PDT 24
Peak memory 200644 kb
Host smart-b15380f6-1d2e-41af-95d8-5e2a12a0c938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527008074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.1527008074
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.3624137776
Short name T790
Test name
Test status
Simulation time 27992354136 ps
CPU time 34.25 seconds
Started Jun 23 05:45:15 PM PDT 24
Finished Jun 23 05:45:50 PM PDT 24
Peak memory 200704 kb
Host smart-b82e9994-f283-4bc7-a8ff-e18e6e3db70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624137776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.3624137776
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.1659547636
Short name T1065
Test name
Test status
Simulation time 25484282149 ps
CPU time 40.82 seconds
Started Jun 23 05:45:11 PM PDT 24
Finished Jun 23 05:45:53 PM PDT 24
Peak memory 200564 kb
Host smart-0a65a131-813d-4b64-b099-0df3548fe014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659547636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.1659547636
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.2090666644
Short name T144
Test name
Test status
Simulation time 19640207763 ps
CPU time 32.81 seconds
Started Jun 23 05:45:16 PM PDT 24
Finished Jun 23 05:45:49 PM PDT 24
Peak memory 200728 kb
Host smart-0b18c589-8b2b-4421-af90-c4b4ab02ee43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090666644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.2090666644
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.537933029
Short name T388
Test name
Test status
Simulation time 11357068 ps
CPU time 0.55 seconds
Started Jun 23 05:41:32 PM PDT 24
Finished Jun 23 05:41:33 PM PDT 24
Peak memory 196064 kb
Host smart-35d2b9fa-21be-4bcd-9214-d903d718320c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537933029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.537933029
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.212876150
Short name T358
Test name
Test status
Simulation time 180175145455 ps
CPU time 206.43 seconds
Started Jun 23 05:41:26 PM PDT 24
Finished Jun 23 05:44:53 PM PDT 24
Peak memory 200668 kb
Host smart-0ae63d68-4e88-4838-9770-7789414cd05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212876150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.212876150
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.229518294
Short name T796
Test name
Test status
Simulation time 34038620391 ps
CPU time 16.24 seconds
Started Jun 23 05:41:27 PM PDT 24
Finished Jun 23 05:41:44 PM PDT 24
Peak memory 198096 kb
Host smart-38bc1f1f-1adb-4403-9fdb-48d897dacfb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229518294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.229518294
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.852609576
Short name T812
Test name
Test status
Simulation time 82635447449 ps
CPU time 80.57 seconds
Started Jun 23 05:41:29 PM PDT 24
Finished Jun 23 05:42:50 PM PDT 24
Peak memory 200676 kb
Host smart-ceaefa65-67b0-4671-879e-70b12bd42fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852609576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.852609576
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.2347461409
Short name T677
Test name
Test status
Simulation time 197200164484 ps
CPU time 108.7 seconds
Started Jun 23 05:41:32 PM PDT 24
Finished Jun 23 05:43:21 PM PDT 24
Peak memory 200584 kb
Host smart-a3eb6821-a9f6-4f73-a935-7628011d1ec9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347461409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.2347461409
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.3552999192
Short name T606
Test name
Test status
Simulation time 126126807837 ps
CPU time 187.41 seconds
Started Jun 23 05:41:34 PM PDT 24
Finished Jun 23 05:44:42 PM PDT 24
Peak memory 200700 kb
Host smart-8dfb4ecf-9c52-44a8-a344-163abe3664a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3552999192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.3552999192
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.1187035765
Short name T988
Test name
Test status
Simulation time 6695305789 ps
CPU time 5.32 seconds
Started Jun 23 05:41:31 PM PDT 24
Finished Jun 23 05:41:37 PM PDT 24
Peak memory 200360 kb
Host smart-d581838d-f968-4f0a-b6ab-27636ddeca06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187035765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.1187035765
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_perf.4006867503
Short name T861
Test name
Test status
Simulation time 10198555293 ps
CPU time 575.49 seconds
Started Jun 23 05:41:34 PM PDT 24
Finished Jun 23 05:51:10 PM PDT 24
Peak memory 200660 kb
Host smart-06aa0b80-9e51-435e-80b1-18aa160d41d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4006867503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.4006867503
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.2671299275
Short name T611
Test name
Test status
Simulation time 4433376095 ps
CPU time 40.76 seconds
Started Jun 23 05:41:25 PM PDT 24
Finished Jun 23 05:42:06 PM PDT 24
Peak memory 199692 kb
Host smart-97d37380-4689-4d41-90d9-a0794ac78565
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2671299275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.2671299275
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.1047326322
Short name T41
Test name
Test status
Simulation time 86816015926 ps
CPU time 62.49 seconds
Started Jun 23 05:41:29 PM PDT 24
Finished Jun 23 05:42:32 PM PDT 24
Peak memory 200588 kb
Host smart-b36e216d-c947-4088-8d28-7257e4da0c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047326322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.1047326322
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.1892195433
Short name T635
Test name
Test status
Simulation time 3125004579 ps
CPU time 2.65 seconds
Started Jun 23 05:41:28 PM PDT 24
Finished Jun 23 05:41:31 PM PDT 24
Peak memory 196724 kb
Host smart-a43deed0-e96c-4bcc-ac13-72a9f1597518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892195433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.1892195433
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.4134888832
Short name T406
Test name
Test status
Simulation time 268780127 ps
CPU time 1.68 seconds
Started Jun 23 05:41:29 PM PDT 24
Finished Jun 23 05:41:31 PM PDT 24
Peak memory 199360 kb
Host smart-88b8eca5-930a-4445-982e-70ec1d911cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134888832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.4134888832
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.93552622
Short name T1020
Test name
Test status
Simulation time 103525958525 ps
CPU time 411.84 seconds
Started Jun 23 05:41:33 PM PDT 24
Finished Jun 23 05:48:25 PM PDT 24
Peak memory 209056 kb
Host smart-556a2b55-d18b-4a68-9aa3-d116b3d1dcfc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93552622 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.93552622
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.99388648
Short name T383
Test name
Test status
Simulation time 2341694556 ps
CPU time 1.95 seconds
Started Jun 23 05:41:31 PM PDT 24
Finished Jun 23 05:41:34 PM PDT 24
Peak memory 199448 kb
Host smart-91a7f951-c76e-4e18-b69d-72c33ba18eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99388648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.99388648
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.2492007802
Short name T653
Test name
Test status
Simulation time 32961683369 ps
CPU time 12.51 seconds
Started Jun 23 05:41:25 PM PDT 24
Finished Jun 23 05:41:37 PM PDT 24
Peak memory 200764 kb
Host smart-cd981b6b-4d42-46f2-8b81-36e7eac288a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492007802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.2492007802
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.674721326
Short name T1005
Test name
Test status
Simulation time 43212035901 ps
CPU time 7.84 seconds
Started Jun 23 05:45:16 PM PDT 24
Finished Jun 23 05:45:24 PM PDT 24
Peak memory 200704 kb
Host smart-8b1bd890-77c7-4d78-b43f-4608eb34645d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674721326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.674721326
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.3559887716
Short name T200
Test name
Test status
Simulation time 98580681685 ps
CPU time 260.15 seconds
Started Jun 23 05:45:06 PM PDT 24
Finished Jun 23 05:49:26 PM PDT 24
Peak memory 200900 kb
Host smart-f5c4c378-87b6-488d-aa09-3bd9a300793e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559887716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.3559887716
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.1223689200
Short name T686
Test name
Test status
Simulation time 17443977898 ps
CPU time 33.19 seconds
Started Jun 23 05:45:11 PM PDT 24
Finished Jun 23 05:45:45 PM PDT 24
Peak memory 200700 kb
Host smart-5a9918e2-f024-4f56-83f6-9ae5d608ebde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223689200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.1223689200
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.1250423649
Short name T896
Test name
Test status
Simulation time 35366000729 ps
CPU time 67.86 seconds
Started Jun 23 05:45:13 PM PDT 24
Finished Jun 23 05:46:21 PM PDT 24
Peak memory 200700 kb
Host smart-de12e1c7-ef5c-4fef-a8a7-0947d26aaa3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250423649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.1250423649
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.242880608
Short name T1087
Test name
Test status
Simulation time 20369699272 ps
CPU time 34.01 seconds
Started Jun 23 05:45:12 PM PDT 24
Finished Jun 23 05:45:47 PM PDT 24
Peak memory 200472 kb
Host smart-1ec005c0-91e6-4df4-b79f-0a50798fad71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242880608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.242880608
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.2343439113
Short name T721
Test name
Test status
Simulation time 135842926544 ps
CPU time 58.49 seconds
Started Jun 23 05:45:17 PM PDT 24
Finished Jun 23 05:46:16 PM PDT 24
Peak memory 200664 kb
Host smart-f92c52a5-a911-4665-95e2-f218e3d8b51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343439113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.2343439113
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.4264351009
Short name T849
Test name
Test status
Simulation time 175143069783 ps
CPU time 59.16 seconds
Started Jun 23 05:45:13 PM PDT 24
Finished Jun 23 05:46:12 PM PDT 24
Peak memory 200344 kb
Host smart-0fc49497-c9da-43df-bc59-a0a8f6aabf11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264351009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.4264351009
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.4024047329
Short name T1073
Test name
Test status
Simulation time 25264756 ps
CPU time 0.55 seconds
Started Jun 23 05:41:38 PM PDT 24
Finished Jun 23 05:41:39 PM PDT 24
Peak memory 195060 kb
Host smart-e4c3a60d-739c-48db-acfd-21e8995e0191
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024047329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.4024047329
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.1733947069
Short name T1021
Test name
Test status
Simulation time 290567536011 ps
CPU time 52.2 seconds
Started Jun 23 05:41:33 PM PDT 24
Finished Jun 23 05:42:26 PM PDT 24
Peak memory 200700 kb
Host smart-64da28cc-083b-42fd-8014-a1d9aa060d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733947069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.1733947069
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.4277366502
Short name T814
Test name
Test status
Simulation time 18229641835 ps
CPU time 6.35 seconds
Started Jun 23 05:41:32 PM PDT 24
Finished Jun 23 05:41:39 PM PDT 24
Peak memory 200632 kb
Host smart-b2b8d463-b38e-46f4-bbb3-dd5b6750734f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277366502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.4277366502
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_intr.1790992079
Short name T904
Test name
Test status
Simulation time 65363028030 ps
CPU time 127.12 seconds
Started Jun 23 05:41:37 PM PDT 24
Finished Jun 23 05:43:44 PM PDT 24
Peak memory 200688 kb
Host smart-75658e1d-6af0-409d-b960-3d6526a0f032
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790992079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.1790992079
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.3013111689
Short name T265
Test name
Test status
Simulation time 106730022308 ps
CPU time 205.42 seconds
Started Jun 23 05:41:37 PM PDT 24
Finished Jun 23 05:45:03 PM PDT 24
Peak memory 200712 kb
Host smart-e894039d-f355-474a-a3e7-d4f80a498441
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3013111689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.3013111689
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.1186486777
Short name T805
Test name
Test status
Simulation time 5871899896 ps
CPU time 3.14 seconds
Started Jun 23 05:41:37 PM PDT 24
Finished Jun 23 05:41:40 PM PDT 24
Peak memory 200012 kb
Host smart-f1603f99-341d-4af1-86a2-861ed932e929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186486777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.1186486777
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_perf.3452319511
Short name T689
Test name
Test status
Simulation time 23217733391 ps
CPU time 237.93 seconds
Started Jun 23 05:41:36 PM PDT 24
Finished Jun 23 05:45:34 PM PDT 24
Peak memory 200736 kb
Host smart-5b221926-01e3-4a87-953c-3b5b3add1325
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3452319511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.3452319511
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.2857465924
Short name T327
Test name
Test status
Simulation time 3586552309 ps
CPU time 6.89 seconds
Started Jun 23 05:41:34 PM PDT 24
Finished Jun 23 05:41:42 PM PDT 24
Peak memory 198884 kb
Host smart-7d599a8e-c629-452c-8f9a-11c7d227267e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2857465924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.2857465924
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.3109354996
Short name T266
Test name
Test status
Simulation time 156409796241 ps
CPU time 57.89 seconds
Started Jun 23 05:41:37 PM PDT 24
Finished Jun 23 05:42:35 PM PDT 24
Peak memory 200692 kb
Host smart-92f765b4-d8ff-4951-8711-b153cf8b7a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109354996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.3109354996
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.545917362
Short name T501
Test name
Test status
Simulation time 32178070363 ps
CPU time 47.45 seconds
Started Jun 23 05:41:39 PM PDT 24
Finished Jun 23 05:42:27 PM PDT 24
Peak memory 196828 kb
Host smart-063201f3-7b4f-4e82-b1e4-8d98f3149501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545917362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.545917362
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.3305430829
Short name T927
Test name
Test status
Simulation time 407643508 ps
CPU time 2.53 seconds
Started Jun 23 05:41:32 PM PDT 24
Finished Jun 23 05:41:35 PM PDT 24
Peak memory 200700 kb
Host smart-75952323-1d20-41ee-a188-cea28e37b366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305430829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.3305430829
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.4208017351
Short name T576
Test name
Test status
Simulation time 76979960369 ps
CPU time 197.33 seconds
Started Jun 23 05:41:38 PM PDT 24
Finished Jun 23 05:44:56 PM PDT 24
Peak memory 200736 kb
Host smart-af44a87f-a278-4fe9-8b57-079e3278b277
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208017351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.4208017351
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.1377327155
Short name T345
Test name
Test status
Simulation time 934349094 ps
CPU time 2.28 seconds
Started Jun 23 05:41:37 PM PDT 24
Finished Jun 23 05:41:40 PM PDT 24
Peak memory 199224 kb
Host smart-7f71f5fc-8a59-4856-8196-c303516ded74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377327155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.1377327155
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.2515854475
Short name T670
Test name
Test status
Simulation time 8208378881 ps
CPU time 13.11 seconds
Started Jun 23 05:41:33 PM PDT 24
Finished Jun 23 05:41:47 PM PDT 24
Peak memory 199420 kb
Host smart-ff7ba0c9-86b2-4d18-8b10-aff6ea314809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515854475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.2515854475
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.3314402648
Short name T985
Test name
Test status
Simulation time 126180215931 ps
CPU time 11.1 seconds
Started Jun 23 05:45:13 PM PDT 24
Finished Jun 23 05:45:25 PM PDT 24
Peak memory 200396 kb
Host smart-e242de02-afd9-42ad-b45a-42bdf3ba3c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314402648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.3314402648
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.2655716959
Short name T121
Test name
Test status
Simulation time 6626698073 ps
CPU time 11.37 seconds
Started Jun 23 05:45:17 PM PDT 24
Finished Jun 23 05:45:28 PM PDT 24
Peak memory 200760 kb
Host smart-e5f01cfc-9368-48cb-89b4-4f37f17b264f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655716959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.2655716959
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.3658586505
Short name T748
Test name
Test status
Simulation time 23355137781 ps
CPU time 27.11 seconds
Started Jun 23 05:45:15 PM PDT 24
Finished Jun 23 05:45:43 PM PDT 24
Peak memory 200720 kb
Host smart-7cdfcb1b-06fd-4063-b43f-40079bd6f5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658586505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.3658586505
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.2642909230
Short name T929
Test name
Test status
Simulation time 51195879153 ps
CPU time 21.08 seconds
Started Jun 23 05:45:16 PM PDT 24
Finished Jun 23 05:45:37 PM PDT 24
Peak memory 200724 kb
Host smart-dcf88565-61f0-48ef-8567-ace093ddd609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642909230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.2642909230
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.3646216238
Short name T560
Test name
Test status
Simulation time 89147886319 ps
CPU time 49.9 seconds
Started Jun 23 05:45:20 PM PDT 24
Finished Jun 23 05:46:10 PM PDT 24
Peak memory 200700 kb
Host smart-dd124cbe-d37f-4d5a-9273-475ff7a7711c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646216238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.3646216238
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.3640462583
Short name T592
Test name
Test status
Simulation time 58383653604 ps
CPU time 38.48 seconds
Started Jun 23 05:45:18 PM PDT 24
Finished Jun 23 05:45:57 PM PDT 24
Peak memory 200704 kb
Host smart-fe88042b-91f6-4d59-b283-72e779e5bd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640462583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.3640462583
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.3170240530
Short name T472
Test name
Test status
Simulation time 146110869045 ps
CPU time 81.69 seconds
Started Jun 23 05:45:18 PM PDT 24
Finished Jun 23 05:46:40 PM PDT 24
Peak memory 200644 kb
Host smart-99f2ce44-c909-4619-b4fe-cefc6dfc5e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170240530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.3170240530
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.3130535707
Short name T509
Test name
Test status
Simulation time 106699743782 ps
CPU time 161.72 seconds
Started Jun 23 05:45:20 PM PDT 24
Finished Jun 23 05:48:02 PM PDT 24
Peak memory 200692 kb
Host smart-dff5e00a-d18f-408e-abae-4b97c891cb07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130535707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.3130535707
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.3469679628
Short name T575
Test name
Test status
Simulation time 12894481 ps
CPU time 0.54 seconds
Started Jun 23 05:41:41 PM PDT 24
Finished Jun 23 05:41:42 PM PDT 24
Peak memory 195012 kb
Host smart-c819c7e3-9fff-4fdf-b8ee-fa49be8bfde9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469679628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.3469679628
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.1370815589
Short name T776
Test name
Test status
Simulation time 147617710041 ps
CPU time 53.87 seconds
Started Jun 23 05:41:37 PM PDT 24
Finished Jun 23 05:42:32 PM PDT 24
Peak memory 200720 kb
Host smart-f2fc349f-2414-4e58-abaf-65b0788f7dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370815589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.1370815589
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.698963509
Short name T972
Test name
Test status
Simulation time 24623862282 ps
CPU time 9.95 seconds
Started Jun 23 05:41:39 PM PDT 24
Finished Jun 23 05:41:49 PM PDT 24
Peak memory 200732 kb
Host smart-0abe2c64-a607-4a03-b0db-af4fbcf29b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698963509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.698963509
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.3254524460
Short name T932
Test name
Test status
Simulation time 39840961160 ps
CPU time 20.52 seconds
Started Jun 23 05:41:40 PM PDT 24
Finished Jun 23 05:42:00 PM PDT 24
Peak memory 200668 kb
Host smart-63bceafa-d9d2-4998-bb18-616ac3618a73
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254524460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.3254524460
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.1481254187
Short name T479
Test name
Test status
Simulation time 300546237959 ps
CPU time 386.79 seconds
Started Jun 23 05:41:41 PM PDT 24
Finished Jun 23 05:48:08 PM PDT 24
Peak memory 200628 kb
Host smart-c1cd5869-d865-4934-9ddf-0e15b297c24d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1481254187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.1481254187
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.3182176204
Short name T768
Test name
Test status
Simulation time 9864686057 ps
CPU time 3.93 seconds
Started Jun 23 05:41:42 PM PDT 24
Finished Jun 23 05:41:46 PM PDT 24
Peak memory 200132 kb
Host smart-b03ea730-9b4e-4c82-a7d7-af19d40d80d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182176204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.3182176204
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_perf.4166090292
Short name T280
Test name
Test status
Simulation time 26659467521 ps
CPU time 90.69 seconds
Started Jun 23 05:41:43 PM PDT 24
Finished Jun 23 05:43:14 PM PDT 24
Peak memory 200844 kb
Host smart-cdb9542a-f09d-4d54-9663-3950ee6ed77a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4166090292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.4166090292
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.2087396127
Short name T912
Test name
Test status
Simulation time 3542443111 ps
CPU time 7.04 seconds
Started Jun 23 05:41:41 PM PDT 24
Finished Jun 23 05:41:49 PM PDT 24
Peak memory 198828 kb
Host smart-f1f4580c-3c04-4944-8504-3bd5913a2e17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2087396127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.2087396127
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.3646602015
Short name T112
Test name
Test status
Simulation time 28129908579 ps
CPU time 41.83 seconds
Started Jun 23 05:41:43 PM PDT 24
Finished Jun 23 05:42:25 PM PDT 24
Peak memory 200784 kb
Host smart-aea0664f-1651-4c2b-b766-f58f40565a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646602015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.3646602015
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.1826795295
Short name T807
Test name
Test status
Simulation time 3889272648 ps
CPU time 6.54 seconds
Started Jun 23 05:41:42 PM PDT 24
Finished Jun 23 05:41:49 PM PDT 24
Peak memory 197252 kb
Host smart-536af287-b03d-43ab-9793-ac8b7b371745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826795295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.1826795295
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.590193768
Short name T382
Test name
Test status
Simulation time 665162199 ps
CPU time 1.36 seconds
Started Jun 23 05:41:38 PM PDT 24
Finished Jun 23 05:41:39 PM PDT 24
Peak memory 199032 kb
Host smart-8d5418bb-d390-4593-b125-084fb81b92f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590193768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.590193768
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.4267851542
Short name T454
Test name
Test status
Simulation time 24075426080 ps
CPU time 491.72 seconds
Started Jun 23 05:41:48 PM PDT 24
Finished Jun 23 05:50:00 PM PDT 24
Peak memory 217184 kb
Host smart-099513b4-ad58-434e-b73b-a888982d787b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267851542 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.4267851542
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.3245930484
Short name T925
Test name
Test status
Simulation time 6043507422 ps
CPU time 15.72 seconds
Started Jun 23 05:41:40 PM PDT 24
Finished Jun 23 05:41:56 PM PDT 24
Peak memory 200108 kb
Host smart-c99f2188-cb3d-4ab0-8123-c147da2555e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245930484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.3245930484
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.2701341132
Short name T513
Test name
Test status
Simulation time 5018076810 ps
CPU time 8 seconds
Started Jun 23 05:41:37 PM PDT 24
Finished Jun 23 05:41:46 PM PDT 24
Peak memory 197608 kb
Host smart-9afa3d33-5150-4585-917a-4ffc1de3da48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701341132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.2701341132
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.3802038823
Short name T209
Test name
Test status
Simulation time 20565575304 ps
CPU time 34.54 seconds
Started Jun 23 05:45:20 PM PDT 24
Finished Jun 23 05:45:55 PM PDT 24
Peak memory 200592 kb
Host smart-e59dd51d-922a-40d6-b8f3-b9cb7cc96ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802038823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.3802038823
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.359542728
Short name T921
Test name
Test status
Simulation time 32879451773 ps
CPU time 27.55 seconds
Started Jun 23 05:45:18 PM PDT 24
Finished Jun 23 05:45:46 PM PDT 24
Peak memory 200760 kb
Host smart-312131ce-071e-4a10-8dc7-23f1a56bde18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359542728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.359542728
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.3791871083
Short name T668
Test name
Test status
Simulation time 24123260189 ps
CPU time 40.45 seconds
Started Jun 23 05:45:15 PM PDT 24
Finished Jun 23 05:45:55 PM PDT 24
Peak memory 200840 kb
Host smart-c226a0e6-3456-491b-bac4-887adc43633b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791871083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.3791871083
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.1173329138
Short name T490
Test name
Test status
Simulation time 28202538855 ps
CPU time 14.53 seconds
Started Jun 23 05:45:22 PM PDT 24
Finished Jun 23 05:45:36 PM PDT 24
Peak memory 200752 kb
Host smart-350fec1d-ef34-4ce7-aa1a-3710602c92b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173329138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.1173329138
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.1721514307
Short name T248
Test name
Test status
Simulation time 109873453164 ps
CPU time 123.35 seconds
Started Jun 23 05:45:21 PM PDT 24
Finished Jun 23 05:47:25 PM PDT 24
Peak memory 200612 kb
Host smart-6537a3be-4302-4ab4-90f7-a98467090a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721514307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.1721514307
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.4231575631
Short name T801
Test name
Test status
Simulation time 86285564162 ps
CPU time 35.84 seconds
Started Jun 23 05:45:21 PM PDT 24
Finished Jun 23 05:45:57 PM PDT 24
Peak memory 200664 kb
Host smart-d78fc026-b8dc-47a6-83e5-81281756dc56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231575631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.4231575631
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.1918937013
Short name T827
Test name
Test status
Simulation time 150276340823 ps
CPU time 227.08 seconds
Started Jun 23 05:45:21 PM PDT 24
Finished Jun 23 05:49:09 PM PDT 24
Peak memory 200760 kb
Host smart-619bde78-9eb0-4a6e-8f1c-a16d50203d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918937013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.1918937013
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.2783766853
Short name T23
Test name
Test status
Simulation time 11604968 ps
CPU time 0.6 seconds
Started Jun 23 05:41:47 PM PDT 24
Finished Jun 23 05:41:48 PM PDT 24
Peak memory 196100 kb
Host smart-dd110ebb-3ea9-49de-a419-82cd32931d84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783766853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.2783766853
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.3221994062
Short name T742
Test name
Test status
Simulation time 138061574783 ps
CPU time 394.54 seconds
Started Jun 23 05:41:47 PM PDT 24
Finished Jun 23 05:48:22 PM PDT 24
Peak memory 200704 kb
Host smart-2a0ca914-1291-4f58-94ed-9595ab47b388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221994062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.3221994062
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.3148793449
Short name T675
Test name
Test status
Simulation time 30401619906 ps
CPU time 6.49 seconds
Started Jun 23 05:41:44 PM PDT 24
Finished Jun 23 05:41:51 PM PDT 24
Peak memory 200532 kb
Host smart-28397468-bc57-4394-bcfd-3114840cc7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148793449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.3148793449
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_intr.3115163390
Short name T586
Test name
Test status
Simulation time 4741059417 ps
CPU time 7.39 seconds
Started Jun 23 05:41:47 PM PDT 24
Finished Jun 23 05:41:55 PM PDT 24
Peak memory 197364 kb
Host smart-98d81cb2-1b2a-4d70-bced-43caca1951b6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115163390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.3115163390
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.2443535676
Short name T456
Test name
Test status
Simulation time 63397547127 ps
CPU time 299 seconds
Started Jun 23 05:41:47 PM PDT 24
Finished Jun 23 05:46:47 PM PDT 24
Peak memory 200688 kb
Host smart-5702aeb4-88ea-4694-a7ab-d5b83e64b58e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2443535676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.2443535676
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.796323096
Short name T340
Test name
Test status
Simulation time 7561167787 ps
CPU time 11.49 seconds
Started Jun 23 05:41:48 PM PDT 24
Finished Jun 23 05:42:00 PM PDT 24
Peak memory 200276 kb
Host smart-364d3bee-01de-496b-85f8-9ec0ff99766a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796323096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.796323096
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_perf.2693417212
Short name T493
Test name
Test status
Simulation time 19291626174 ps
CPU time 94.15 seconds
Started Jun 23 05:41:47 PM PDT 24
Finished Jun 23 05:43:22 PM PDT 24
Peak memory 200760 kb
Host smart-4da0c660-86cc-4cb8-acee-6cc0b6721445
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2693417212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.2693417212
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.56119578
Short name T832
Test name
Test status
Simulation time 6752290263 ps
CPU time 8.93 seconds
Started Jun 23 05:41:47 PM PDT 24
Finished Jun 23 05:41:56 PM PDT 24
Peak memory 198816 kb
Host smart-03f79408-e090-4049-95ec-0302a09886d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=56119578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.56119578
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.1357029885
Short name T1004
Test name
Test status
Simulation time 208608311954 ps
CPU time 106.2 seconds
Started Jun 23 05:41:44 PM PDT 24
Finished Jun 23 05:43:31 PM PDT 24
Peak memory 200724 kb
Host smart-12be5961-dcbf-4533-8a28-51ef71b9b1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357029885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.1357029885
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.3034703782
Short name T755
Test name
Test status
Simulation time 447228688 ps
CPU time 1.32 seconds
Started Jun 23 05:41:47 PM PDT 24
Finished Jun 23 05:41:49 PM PDT 24
Peak memory 196396 kb
Host smart-2521e3ea-95a1-4b84-bc5c-013d4b96fe06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034703782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.3034703782
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.781750002
Short name T623
Test name
Test status
Simulation time 11595598715 ps
CPU time 13.5 seconds
Started Jun 23 05:41:44 PM PDT 24
Finished Jun 23 05:41:58 PM PDT 24
Peak memory 200624 kb
Host smart-fb5d2d21-e803-433b-a67b-6ba083163d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781750002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.781750002
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.2740076862
Short name T753
Test name
Test status
Simulation time 26918334605 ps
CPU time 300.75 seconds
Started Jun 23 05:41:46 PM PDT 24
Finished Jun 23 05:46:47 PM PDT 24
Peak memory 208984 kb
Host smart-74a90fdf-8188-4f86-ae59-b44737c2101e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740076862 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.2740076862
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.2442633972
Short name T674
Test name
Test status
Simulation time 6581694813 ps
CPU time 26.51 seconds
Started Jun 23 05:41:46 PM PDT 24
Finished Jun 23 05:42:12 PM PDT 24
Peak memory 200652 kb
Host smart-ac5aa06b-c633-4440-8b54-3be0a7deb85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442633972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.2442633972
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.210023934
Short name T35
Test name
Test status
Simulation time 33943941805 ps
CPU time 23.81 seconds
Started Jun 23 05:41:41 PM PDT 24
Finished Jun 23 05:42:05 PM PDT 24
Peak memory 200704 kb
Host smart-1ec34785-c04a-4499-8467-8f8d38d4f1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210023934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.210023934
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.2889106391
Short name T147
Test name
Test status
Simulation time 60869253164 ps
CPU time 44.88 seconds
Started Jun 23 05:45:23 PM PDT 24
Finished Jun 23 05:46:08 PM PDT 24
Peak memory 200716 kb
Host smart-a8d75eca-11f3-40e4-b127-9ff57abbc770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889106391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.2889106391
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.553549845
Short name T519
Test name
Test status
Simulation time 108988224434 ps
CPU time 44.98 seconds
Started Jun 23 05:45:21 PM PDT 24
Finished Jun 23 05:46:06 PM PDT 24
Peak memory 200644 kb
Host smart-903083ce-cdab-4336-9d60-996ea8b080ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553549845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.553549845
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.1568008220
Short name T444
Test name
Test status
Simulation time 180434521547 ps
CPU time 296.24 seconds
Started Jun 23 05:45:23 PM PDT 24
Finished Jun 23 05:50:19 PM PDT 24
Peak memory 200708 kb
Host smart-c834ab04-5b1a-47ae-9e5d-31a27192b5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568008220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.1568008220
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.2687800030
Short name T453
Test name
Test status
Simulation time 7627368848 ps
CPU time 11.64 seconds
Started Jun 23 05:45:22 PM PDT 24
Finished Jun 23 05:45:34 PM PDT 24
Peak memory 200152 kb
Host smart-b325c576-5575-47ed-ae39-2f2dc305ccf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687800030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.2687800030
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.792060602
Short name T824
Test name
Test status
Simulation time 79215844394 ps
CPU time 32.8 seconds
Started Jun 23 05:45:21 PM PDT 24
Finished Jun 23 05:45:54 PM PDT 24
Peak memory 200652 kb
Host smart-e900b88d-9ffb-4af6-8a63-243f1ddd6480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792060602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.792060602
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.1051981012
Short name T223
Test name
Test status
Simulation time 83164671119 ps
CPU time 34.86 seconds
Started Jun 23 05:45:22 PM PDT 24
Finished Jun 23 05:45:57 PM PDT 24
Peak memory 200700 kb
Host smart-36fb23b6-0b8e-4677-add0-9cbe1a400543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051981012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.1051981012
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.2017956386
Short name T1049
Test name
Test status
Simulation time 20508802908 ps
CPU time 38.21 seconds
Started Jun 23 05:45:24 PM PDT 24
Finished Jun 23 05:46:02 PM PDT 24
Peak memory 200772 kb
Host smart-3266e541-16b5-4717-8db9-69d48b181e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017956386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.2017956386
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.19668498
Short name T637
Test name
Test status
Simulation time 38299690522 ps
CPU time 25.27 seconds
Started Jun 23 05:45:24 PM PDT 24
Finished Jun 23 05:45:49 PM PDT 24
Peak memory 200752 kb
Host smart-ab14dcb3-c820-40cc-8922-937d7994e7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19668498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.19668498
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.2380336023
Short name T1039
Test name
Test status
Simulation time 105238012144 ps
CPU time 16.93 seconds
Started Jun 23 05:45:22 PM PDT 24
Finished Jun 23 05:45:39 PM PDT 24
Peak memory 200720 kb
Host smart-73a1c776-da07-4e78-baae-944bcfb0e716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380336023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.2380336023
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.3363789773
Short name T480
Test name
Test status
Simulation time 81053967329 ps
CPU time 14.48 seconds
Started Jun 23 05:45:19 PM PDT 24
Finished Jun 23 05:45:34 PM PDT 24
Peak memory 200684 kb
Host smart-c9930e61-12b9-42e4-9cb4-59b39ca385e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363789773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.3363789773
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.3108700352
Short name T648
Test name
Test status
Simulation time 61718469 ps
CPU time 0.54 seconds
Started Jun 23 05:41:52 PM PDT 24
Finished Jun 23 05:41:52 PM PDT 24
Peak memory 195036 kb
Host smart-16effb28-0c16-41c7-8f70-36f4f22e45d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108700352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.3108700352
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.816785477
Short name T662
Test name
Test status
Simulation time 53236594404 ps
CPU time 15.89 seconds
Started Jun 23 05:41:45 PM PDT 24
Finished Jun 23 05:42:02 PM PDT 24
Peak memory 200688 kb
Host smart-7dfef0ab-5787-47e9-813b-43e34548d91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816785477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.816785477
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.385595398
Short name T476
Test name
Test status
Simulation time 134429308626 ps
CPU time 21.46 seconds
Started Jun 23 05:41:48 PM PDT 24
Finished Jun 23 05:42:10 PM PDT 24
Peak memory 200628 kb
Host smart-b77d6442-6ad4-4432-a64f-1b8cfbfd90e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385595398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.385595398
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.1596860384
Short name T838
Test name
Test status
Simulation time 8697179955 ps
CPU time 16.04 seconds
Started Jun 23 05:41:54 PM PDT 24
Finished Jun 23 05:42:11 PM PDT 24
Peak memory 200756 kb
Host smart-62414c44-31cb-4199-8e11-c34ca37cc2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596860384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.1596860384
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.1301905384
Short name T757
Test name
Test status
Simulation time 40907738213 ps
CPU time 29.69 seconds
Started Jun 23 05:41:49 PM PDT 24
Finished Jun 23 05:42:19 PM PDT 24
Peak memory 200404 kb
Host smart-f9838a3b-f8ab-4d53-b633-9fca21685e0e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301905384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.1301905384
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_loopback.3840757405
Short name T897
Test name
Test status
Simulation time 2430856791 ps
CPU time 1.4 seconds
Started Jun 23 05:41:52 PM PDT 24
Finished Jun 23 05:41:54 PM PDT 24
Peak memory 199524 kb
Host smart-ba0c7a4c-e19b-43f1-ab08-871aca1b58f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840757405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.3840757405
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_perf.92072062
Short name T283
Test name
Test status
Simulation time 15955076664 ps
CPU time 142.69 seconds
Started Jun 23 05:41:52 PM PDT 24
Finished Jun 23 05:44:15 PM PDT 24
Peak memory 200692 kb
Host smart-964db29c-ec62-430c-acd8-91589f5a43c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=92072062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.92072062
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.3561348603
Short name T866
Test name
Test status
Simulation time 1879776711 ps
CPU time 4.8 seconds
Started Jun 23 05:41:54 PM PDT 24
Finished Jun 23 05:41:59 PM PDT 24
Peak memory 199384 kb
Host smart-3b8836c6-222b-4e59-9bc0-b8566f269bd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3561348603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.3561348603
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.2348459118
Short name T1091
Test name
Test status
Simulation time 16682316547 ps
CPU time 23.07 seconds
Started Jun 23 05:41:51 PM PDT 24
Finished Jun 23 05:42:14 PM PDT 24
Peak memory 199764 kb
Host smart-622f0a61-3bfa-40a3-b8c3-01bec5ae68c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348459118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.2348459118
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.2940406737
Short name T433
Test name
Test status
Simulation time 1785622954 ps
CPU time 1.88 seconds
Started Jun 23 05:41:54 PM PDT 24
Finished Jun 23 05:41:56 PM PDT 24
Peak memory 196136 kb
Host smart-c422f469-d954-402c-af2f-a7cc66cffc7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940406737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.2940406737
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.2015127503
Short name T933
Test name
Test status
Simulation time 507971129 ps
CPU time 2.2 seconds
Started Jun 23 05:41:47 PM PDT 24
Finished Jun 23 05:41:50 PM PDT 24
Peak memory 199600 kb
Host smart-7a9aeb73-12e7-4ef6-a773-92b850e10e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015127503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.2015127503
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.729143231
Short name T463
Test name
Test status
Simulation time 72790229864 ps
CPU time 369.54 seconds
Started Jun 23 05:41:49 PM PDT 24
Finished Jun 23 05:47:59 PM PDT 24
Peak memory 200692 kb
Host smart-603a6d2f-948f-49ff-90b7-5919f823e266
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729143231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.729143231
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.2546602812
Short name T464
Test name
Test status
Simulation time 142060312228 ps
CPU time 843.84 seconds
Started Jun 23 05:41:50 PM PDT 24
Finished Jun 23 05:55:55 PM PDT 24
Peak memory 225332 kb
Host smart-57211b3a-eda2-4bc0-b595-29fa7dfb583d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546602812 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.2546602812
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.1002281499
Short name T939
Test name
Test status
Simulation time 13883011038 ps
CPU time 16.98 seconds
Started Jun 23 05:41:54 PM PDT 24
Finished Jun 23 05:42:11 PM PDT 24
Peak memory 200488 kb
Host smart-acf65e8f-ab34-4340-8865-c5308fddfa50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002281499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.1002281499
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.3411769948
Short name T884
Test name
Test status
Simulation time 30104748524 ps
CPU time 46.26 seconds
Started Jun 23 05:41:47 PM PDT 24
Finished Jun 23 05:42:34 PM PDT 24
Peak memory 200624 kb
Host smart-03f5e688-5f3e-446a-a08d-578b93893105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411769948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.3411769948
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.32652810
Short name T536
Test name
Test status
Simulation time 40615055189 ps
CPU time 75.07 seconds
Started Jun 23 05:45:21 PM PDT 24
Finished Jun 23 05:46:37 PM PDT 24
Peak memory 200688 kb
Host smart-e416de1b-0c7e-48ed-bbbc-e501c0f86314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32652810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.32652810
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.399096599
Short name T1071
Test name
Test status
Simulation time 312539296583 ps
CPU time 213.09 seconds
Started Jun 23 05:45:26 PM PDT 24
Finished Jun 23 05:49:00 PM PDT 24
Peak memory 200752 kb
Host smart-3069fc74-1a4a-45cd-a542-4df41fe7f9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399096599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.399096599
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.3765266160
Short name T779
Test name
Test status
Simulation time 29609508403 ps
CPU time 29.33 seconds
Started Jun 23 05:45:27 PM PDT 24
Finished Jun 23 05:45:57 PM PDT 24
Peak memory 200664 kb
Host smart-d3a517d5-afd3-4dd4-90de-c4dd6f04e0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765266160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.3765266160
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.1593378042
Short name T362
Test name
Test status
Simulation time 41594987195 ps
CPU time 70.16 seconds
Started Jun 23 05:45:27 PM PDT 24
Finished Jun 23 05:46:38 PM PDT 24
Peak memory 200708 kb
Host smart-d98394aa-25d5-4dcc-a288-d372e933aeaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593378042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.1593378042
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.1140345331
Short name T705
Test name
Test status
Simulation time 75648267136 ps
CPU time 45.86 seconds
Started Jun 23 05:45:26 PM PDT 24
Finished Jun 23 05:46:12 PM PDT 24
Peak memory 200760 kb
Host smart-60cd6c75-c317-476b-851c-fbb6edfacd0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140345331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.1140345331
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.2389870508
Short name T657
Test name
Test status
Simulation time 47054622516 ps
CPU time 266.1 seconds
Started Jun 23 05:45:28 PM PDT 24
Finished Jun 23 05:49:55 PM PDT 24
Peak memory 200564 kb
Host smart-b4a36a4c-da5c-42fb-9f34-67454e6326ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389870508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.2389870508
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.2928728920
Short name T891
Test name
Test status
Simulation time 158093130121 ps
CPU time 180.47 seconds
Started Jun 23 05:45:25 PM PDT 24
Finished Jun 23 05:48:26 PM PDT 24
Peak memory 200688 kb
Host smart-451568b4-197f-470d-b41f-7ff1fa302ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928728920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.2928728920
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.3561950782
Short name T1053
Test name
Test status
Simulation time 107335067585 ps
CPU time 138.76 seconds
Started Jun 23 05:45:28 PM PDT 24
Finished Jun 23 05:47:47 PM PDT 24
Peak memory 200664 kb
Host smart-1a8e868e-6a3f-4d02-b9a7-6ad863e0d2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561950782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.3561950782
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.2754311420
Short name T967
Test name
Test status
Simulation time 13887859 ps
CPU time 0.59 seconds
Started Jun 23 05:42:03 PM PDT 24
Finished Jun 23 05:42:04 PM PDT 24
Peak memory 196052 kb
Host smart-9d94e754-f502-4813-92d7-6a7ce5ea5dc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754311420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.2754311420
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.1822074052
Short name T163
Test name
Test status
Simulation time 27182813771 ps
CPU time 49.9 seconds
Started Jun 23 05:41:53 PM PDT 24
Finished Jun 23 05:42:43 PM PDT 24
Peak memory 200748 kb
Host smart-a0d1a673-bc3f-4c21-8f84-9299a0d8f2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822074052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.1822074052
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.184055039
Short name T902
Test name
Test status
Simulation time 28063058079 ps
CPU time 7.17 seconds
Started Jun 23 05:41:54 PM PDT 24
Finished Jun 23 05:42:02 PM PDT 24
Peak memory 200716 kb
Host smart-e3836ff6-269d-4581-b515-8efb570e2558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184055039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.184055039
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.3147212290
Short name T660
Test name
Test status
Simulation time 98622023594 ps
CPU time 29.32 seconds
Started Jun 23 05:41:57 PM PDT 24
Finished Jun 23 05:42:26 PM PDT 24
Peak memory 200556 kb
Host smart-660604e3-803e-49c1-954b-0e5606450ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147212290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.3147212290
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.907980443
Short name T226
Test name
Test status
Simulation time 219176961445 ps
CPU time 297.97 seconds
Started Jun 23 05:41:55 PM PDT 24
Finished Jun 23 05:46:53 PM PDT 24
Peak memory 200424 kb
Host smart-778d9c15-7571-424a-bb93-cfa62c376e0d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907980443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.907980443
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.1413844118
Short name T930
Test name
Test status
Simulation time 38555239076 ps
CPU time 237.04 seconds
Started Jun 23 05:41:56 PM PDT 24
Finished Jun 23 05:45:53 PM PDT 24
Peak memory 200748 kb
Host smart-17a82137-b888-462b-bca0-a24dcf338af1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1413844118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.1413844118
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.3090129655
Short name T481
Test name
Test status
Simulation time 5182903205 ps
CPU time 17.99 seconds
Started Jun 23 05:41:58 PM PDT 24
Finished Jun 23 05:42:16 PM PDT 24
Peak memory 200312 kb
Host smart-ea5b8765-c54b-4e94-aa9e-fccaaacf7a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090129655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.3090129655
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_perf.1421668599
Short name T238
Test name
Test status
Simulation time 14402708805 ps
CPU time 27.89 seconds
Started Jun 23 05:41:59 PM PDT 24
Finished Jun 23 05:42:27 PM PDT 24
Peak memory 200732 kb
Host smart-944707db-09ce-4ff4-b479-30b52a1e9f44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1421668599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.1421668599
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.266981274
Short name T305
Test name
Test status
Simulation time 1705589405 ps
CPU time 5.01 seconds
Started Jun 23 05:41:54 PM PDT 24
Finished Jun 23 05:42:00 PM PDT 24
Peak memory 199940 kb
Host smart-10d73974-8cf5-46e1-a318-54a2d936ea62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=266981274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.266981274
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.2712435771
Short name T787
Test name
Test status
Simulation time 104129532625 ps
CPU time 168.15 seconds
Started Jun 23 05:41:59 PM PDT 24
Finished Jun 23 05:44:48 PM PDT 24
Peak memory 200724 kb
Host smart-cbae5c3c-658e-4c26-a3bf-c720171da431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712435771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.2712435771
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.2463422367
Short name T850
Test name
Test status
Simulation time 49727628230 ps
CPU time 8.26 seconds
Started Jun 23 05:41:55 PM PDT 24
Finished Jun 23 05:42:04 PM PDT 24
Peak memory 196756 kb
Host smart-76754788-c77c-49c3-a639-4414add4fc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463422367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.2463422367
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.819513417
Short name T946
Test name
Test status
Simulation time 110097389 ps
CPU time 0.98 seconds
Started Jun 23 05:41:55 PM PDT 24
Finished Jun 23 05:41:56 PM PDT 24
Peak memory 198964 kb
Host smart-cef4c9c1-4d9d-4e31-ac8b-bfe89628279e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819513417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.819513417
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.2199928317
Short name T877
Test name
Test status
Simulation time 6956251179 ps
CPU time 16 seconds
Started Jun 23 05:41:54 PM PDT 24
Finished Jun 23 05:42:11 PM PDT 24
Peak memory 200700 kb
Host smart-719369f3-1a60-421c-8d26-ba9b9de0d866
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199928317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.2199928317
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.658536678
Short name T688
Test name
Test status
Simulation time 33091225127 ps
CPU time 272 seconds
Started Jun 23 05:41:56 PM PDT 24
Finished Jun 23 05:46:29 PM PDT 24
Peak memory 216136 kb
Host smart-0f5e9df1-012b-4812-8f35-17659040907e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658536678 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.658536678
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.2905986872
Short name T809
Test name
Test status
Simulation time 5894897900 ps
CPU time 15.64 seconds
Started Jun 23 05:41:55 PM PDT 24
Finished Jun 23 05:42:11 PM PDT 24
Peak memory 200676 kb
Host smart-7d325ab3-95ed-4618-94ee-3cfb63d96b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905986872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.2905986872
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.1827468872
Short name T628
Test name
Test status
Simulation time 112715695740 ps
CPU time 20.3 seconds
Started Jun 23 05:41:53 PM PDT 24
Finished Jun 23 05:42:14 PM PDT 24
Peak memory 200704 kb
Host smart-98e377ff-20a8-4f3d-a0df-7e657cfd3485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827468872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.1827468872
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.2844777226
Short name T423
Test name
Test status
Simulation time 92685512113 ps
CPU time 19.84 seconds
Started Jun 23 05:45:31 PM PDT 24
Finished Jun 23 05:45:52 PM PDT 24
Peak memory 200476 kb
Host smart-1ad323d4-15f2-447b-85dc-d9f4e8f06cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844777226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.2844777226
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.3001308270
Short name T743
Test name
Test status
Simulation time 102895930059 ps
CPU time 390.91 seconds
Started Jun 23 05:45:32 PM PDT 24
Finished Jun 23 05:52:03 PM PDT 24
Peak memory 200760 kb
Host smart-417a206f-db68-410e-b676-9ba6037cb5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001308270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.3001308270
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.3967898277
Short name T134
Test name
Test status
Simulation time 105415889234 ps
CPU time 230.56 seconds
Started Jun 23 05:45:30 PM PDT 24
Finished Jun 23 05:49:21 PM PDT 24
Peak memory 200760 kb
Host smart-bf27319c-feee-40b8-98dc-2b98aa91e973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967898277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.3967898277
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.3176747121
Short name T892
Test name
Test status
Simulation time 14199774079 ps
CPU time 23.93 seconds
Started Jun 23 05:45:32 PM PDT 24
Finished Jun 23 05:45:56 PM PDT 24
Peak memory 200760 kb
Host smart-64f0c01c-f5d9-4483-ac47-8b4615b056ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176747121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.3176747121
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.1589346914
Short name T437
Test name
Test status
Simulation time 31175088071 ps
CPU time 33.45 seconds
Started Jun 23 05:45:32 PM PDT 24
Finished Jun 23 05:46:06 PM PDT 24
Peak memory 200720 kb
Host smart-37c3b9d1-14f8-4e5e-a1ba-f09ca3b8bebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589346914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.1589346914
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.3000865362
Short name T903
Test name
Test status
Simulation time 61857143370 ps
CPU time 147.05 seconds
Started Jun 23 05:45:32 PM PDT 24
Finished Jun 23 05:48:00 PM PDT 24
Peak memory 200740 kb
Host smart-a1cf06d0-6839-4207-bb45-fcbeda16e082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000865362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.3000865362
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.2187941500
Short name T172
Test name
Test status
Simulation time 20086379546 ps
CPU time 45.09 seconds
Started Jun 23 05:45:31 PM PDT 24
Finished Jun 23 05:46:17 PM PDT 24
Peak memory 200760 kb
Host smart-77b45a61-e890-455a-be49-c8bb246d8d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187941500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.2187941500
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.813870322
Short name T151
Test name
Test status
Simulation time 105262852202 ps
CPU time 43.07 seconds
Started Jun 23 05:45:31 PM PDT 24
Finished Jun 23 05:46:15 PM PDT 24
Peak memory 200728 kb
Host smart-fe8f7eb0-9e7a-4134-96cd-714a6f64cfc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813870322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.813870322
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.3294687213
Short name T417
Test name
Test status
Simulation time 140869523483 ps
CPU time 197.37 seconds
Started Jun 23 05:45:34 PM PDT 24
Finished Jun 23 05:48:52 PM PDT 24
Peak memory 200692 kb
Host smart-36c6ffc6-fa65-4217-a318-a6ddf839a9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294687213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.3294687213
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.1683293476
Short name T990
Test name
Test status
Simulation time 15117889 ps
CPU time 0.55 seconds
Started Jun 23 05:41:58 PM PDT 24
Finished Jun 23 05:41:59 PM PDT 24
Peak memory 195564 kb
Host smart-02ae9ae7-ad97-4525-afe0-8b42fd17652f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683293476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.1683293476
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.2886736129
Short name T155
Test name
Test status
Simulation time 9132120562 ps
CPU time 12.61 seconds
Started Jun 23 05:41:59 PM PDT 24
Finished Jun 23 05:42:12 PM PDT 24
Peak memory 200756 kb
Host smart-cf5c0427-b8a4-42de-a73a-30e140b4e5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886736129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.2886736129
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.515904984
Short name T860
Test name
Test status
Simulation time 33645379519 ps
CPU time 15.07 seconds
Started Jun 23 05:42:02 PM PDT 24
Finished Jun 23 05:42:17 PM PDT 24
Peak memory 200196 kb
Host smart-2c8dfb28-2fa1-4420-aea8-103ef09a3f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515904984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.515904984
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.788352102
Short name T100
Test name
Test status
Simulation time 130799430836 ps
CPU time 192.08 seconds
Started Jun 23 05:42:00 PM PDT 24
Finished Jun 23 05:45:12 PM PDT 24
Peak memory 200668 kb
Host smart-cbcaa832-6f61-4859-b59a-128a00155796
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788352102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.788352102
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.3284352127
Short name T1000
Test name
Test status
Simulation time 91700294299 ps
CPU time 254.92 seconds
Started Jun 23 05:42:00 PM PDT 24
Finished Jun 23 05:46:15 PM PDT 24
Peak memory 200708 kb
Host smart-1f2977de-e1c7-44c5-8357-a6b3b72184af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3284352127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.3284352127
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.455788329
Short name T568
Test name
Test status
Simulation time 6006066283 ps
CPU time 11.43 seconds
Started Jun 23 05:42:03 PM PDT 24
Finished Jun 23 05:42:15 PM PDT 24
Peak memory 198984 kb
Host smart-e2b7ac6c-3d33-40ff-88e9-2955bc6ea46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455788329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.455788329
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_perf.2622691182
Short name T411
Test name
Test status
Simulation time 19025459887 ps
CPU time 515.39 seconds
Started Jun 23 05:42:01 PM PDT 24
Finished Jun 23 05:50:37 PM PDT 24
Peak memory 200676 kb
Host smart-d5ed124e-08ed-4813-b9b1-661c01e88aa3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2622691182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.2622691182
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.1757915561
Short name T918
Test name
Test status
Simulation time 2230072176 ps
CPU time 9.14 seconds
Started Jun 23 05:42:05 PM PDT 24
Finished Jun 23 05:42:14 PM PDT 24
Peak memory 198728 kb
Host smart-68c75d37-713f-4e57-9c58-473f590bc5b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1757915561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.1757915561
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.2262964739
Short name T587
Test name
Test status
Simulation time 125096557941 ps
CPU time 122.07 seconds
Started Jun 23 05:42:04 PM PDT 24
Finished Jun 23 05:44:07 PM PDT 24
Peak memory 200612 kb
Host smart-23ab390e-b7d5-410b-9fca-699bc8bed36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262964739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.2262964739
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.3241190243
Short name T666
Test name
Test status
Simulation time 5050090690 ps
CPU time 4.84 seconds
Started Jun 23 05:42:03 PM PDT 24
Finished Jun 23 05:42:08 PM PDT 24
Peak memory 196816 kb
Host smart-9a37c04b-b0ef-4dab-a629-1575fa586b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241190243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.3241190243
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.1299735002
Short name T963
Test name
Test status
Simulation time 659904535 ps
CPU time 1.99 seconds
Started Jun 23 05:41:54 PM PDT 24
Finished Jun 23 05:41:56 PM PDT 24
Peak memory 200572 kb
Host smart-ebc68dc8-e608-4c93-9aa5-c79dfc453194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299735002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.1299735002
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.1226383606
Short name T649
Test name
Test status
Simulation time 240781706427 ps
CPU time 810.89 seconds
Started Jun 23 05:42:04 PM PDT 24
Finished Jun 23 05:55:36 PM PDT 24
Peak memory 200632 kb
Host smart-04e0af5b-eeaa-4329-bad6-762f5ae05402
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226383606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.1226383606
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.1815147963
Short name T766
Test name
Test status
Simulation time 158575527298 ps
CPU time 231.16 seconds
Started Jun 23 05:42:01 PM PDT 24
Finished Jun 23 05:45:53 PM PDT 24
Peak memory 216896 kb
Host smart-b5244d22-5abd-470c-8ead-c5198f5a9fc4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815147963 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.1815147963
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.1368131580
Short name T335
Test name
Test status
Simulation time 1587640747 ps
CPU time 2.88 seconds
Started Jun 23 05:42:03 PM PDT 24
Finished Jun 23 05:42:06 PM PDT 24
Peak memory 199696 kb
Host smart-d0d657c0-95d5-4eed-b429-c38a8838ceb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368131580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.1368131580
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.2305592996
Short name T885
Test name
Test status
Simulation time 72894666155 ps
CPU time 56.75 seconds
Started Jun 23 05:41:59 PM PDT 24
Finished Jun 23 05:42:56 PM PDT 24
Peak memory 200704 kb
Host smart-43a91d6e-e70b-48d9-9192-36a167138e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305592996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.2305592996
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.1764553472
Short name T612
Test name
Test status
Simulation time 140593898770 ps
CPU time 234.43 seconds
Started Jun 23 05:45:37 PM PDT 24
Finished Jun 23 05:49:32 PM PDT 24
Peak memory 200724 kb
Host smart-5e00dd31-9508-4c03-8d45-594dc2d07fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764553472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.1764553472
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.1049513164
Short name T242
Test name
Test status
Simulation time 13468904599 ps
CPU time 8.03 seconds
Started Jun 23 05:45:37 PM PDT 24
Finished Jun 23 05:45:46 PM PDT 24
Peak memory 200720 kb
Host smart-6ed815e9-9c90-4418-a561-27af1c32aba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049513164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.1049513164
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.3144724259
Short name T775
Test name
Test status
Simulation time 44567611426 ps
CPU time 18.66 seconds
Started Jun 23 05:45:38 PM PDT 24
Finished Jun 23 05:45:57 PM PDT 24
Peak memory 200784 kb
Host smart-702f90c5-3958-4de0-8fab-410a7a72dd2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144724259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.3144724259
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.2091733210
Short name T954
Test name
Test status
Simulation time 16634325041 ps
CPU time 20.33 seconds
Started Jun 23 05:45:36 PM PDT 24
Finished Jun 23 05:45:57 PM PDT 24
Peak memory 200696 kb
Host smart-a012ed13-2f74-473e-9f65-2d2b8d68c513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091733210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.2091733210
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.3595781499
Short name T810
Test name
Test status
Simulation time 47592843720 ps
CPU time 49.07 seconds
Started Jun 23 05:45:40 PM PDT 24
Finished Jun 23 05:46:30 PM PDT 24
Peak memory 200760 kb
Host smart-0d42edf9-a809-4e4f-98b5-db9fe2abe803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595781499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.3595781499
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.1925056529
Short name T1032
Test name
Test status
Simulation time 143857561866 ps
CPU time 124.05 seconds
Started Jun 23 05:45:40 PM PDT 24
Finished Jun 23 05:47:45 PM PDT 24
Peak memory 200732 kb
Host smart-bc5e619f-dddc-4643-8d53-8bd68d2539c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925056529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.1925056529
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.3007177505
Short name T129
Test name
Test status
Simulation time 26693571159 ps
CPU time 30.03 seconds
Started Jun 23 05:45:37 PM PDT 24
Finished Jun 23 05:46:08 PM PDT 24
Peak memory 200604 kb
Host smart-b908fd23-1619-4240-b82d-2355f1164682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007177505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.3007177505
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.3770681451
Short name T286
Test name
Test status
Simulation time 13114838514 ps
CPU time 21.45 seconds
Started Jun 23 05:45:38 PM PDT 24
Finished Jun 23 05:45:59 PM PDT 24
Peak memory 200716 kb
Host smart-31b67e43-9710-4e2d-a8eb-b690e7bedaed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770681451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.3770681451
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.225117512
Short name T1035
Test name
Test status
Simulation time 11219469 ps
CPU time 0.55 seconds
Started Jun 23 05:40:03 PM PDT 24
Finished Jun 23 05:40:04 PM PDT 24
Peak memory 196072 kb
Host smart-c45977f1-dd92-4192-8d81-1f9689172d38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225117512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.225117512
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.544735453
Short name T1076
Test name
Test status
Simulation time 32293262019 ps
CPU time 31.68 seconds
Started Jun 23 05:39:54 PM PDT 24
Finished Jun 23 05:40:26 PM PDT 24
Peak memory 200716 kb
Host smart-e17aab0b-d814-4c8b-a500-3b3e295a825e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544735453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.544735453
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.993394884
Short name T729
Test name
Test status
Simulation time 18239135322 ps
CPU time 15.1 seconds
Started Jun 23 05:39:53 PM PDT 24
Finished Jun 23 05:40:08 PM PDT 24
Peak memory 200432 kb
Host smart-22aa11b4-cc1d-4644-9682-040f5417307a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993394884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.993394884
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.789650928
Short name T573
Test name
Test status
Simulation time 12495687683 ps
CPU time 19.72 seconds
Started Jun 23 05:39:52 PM PDT 24
Finished Jun 23 05:40:12 PM PDT 24
Peak memory 200636 kb
Host smart-5ae8da0f-fd4d-4747-9eb3-b69c00af2b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789650928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.789650928
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.1767420338
Short name T874
Test name
Test status
Simulation time 24942740322 ps
CPU time 43.67 seconds
Started Jun 23 05:39:54 PM PDT 24
Finished Jun 23 05:40:38 PM PDT 24
Peak memory 200624 kb
Host smart-c5c1dad4-9909-494d-a395-b77b5bacc617
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767420338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.1767420338
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.1212108498
Short name T234
Test name
Test status
Simulation time 73993188549 ps
CPU time 684.59 seconds
Started Jun 23 05:39:59 PM PDT 24
Finished Jun 23 05:51:24 PM PDT 24
Peak memory 200616 kb
Host smart-5d20dc21-c6d1-4561-bf64-3770a2792e39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1212108498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.1212108498
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.3866089501
Short name T361
Test name
Test status
Simulation time 3591759812 ps
CPU time 8.4 seconds
Started Jun 23 05:39:52 PM PDT 24
Finished Jun 23 05:40:01 PM PDT 24
Peak memory 200264 kb
Host smart-9f5c1cc4-77ac-4442-b594-5ea2b5d178d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866089501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.3866089501
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_perf.1867798315
Short name T1
Test name
Test status
Simulation time 11664911038 ps
CPU time 274.84 seconds
Started Jun 23 05:39:59 PM PDT 24
Finished Jun 23 05:44:34 PM PDT 24
Peak memory 200616 kb
Host smart-e57de524-acae-490f-8b1e-e83281bdb5a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1867798315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.1867798315
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.3602107554
Short name T724
Test name
Test status
Simulation time 1590339540 ps
CPU time 6.56 seconds
Started Jun 23 05:39:54 PM PDT 24
Finished Jun 23 05:40:01 PM PDT 24
Peak memory 198840 kb
Host smart-4e8e13e4-5596-4a10-8341-193eff088b2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3602107554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3602107554
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.589232641
Short name T1019
Test name
Test status
Simulation time 6125036790 ps
CPU time 9.61 seconds
Started Jun 23 05:39:52 PM PDT 24
Finished Jun 23 05:40:02 PM PDT 24
Peak memory 198964 kb
Host smart-ad869bd0-3d53-4b04-8510-54ca3abefefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589232641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.589232641
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.2091095067
Short name T355
Test name
Test status
Simulation time 820307729 ps
CPU time 1.02 seconds
Started Jun 23 05:39:53 PM PDT 24
Finished Jun 23 05:39:55 PM PDT 24
Peak memory 196176 kb
Host smart-5a3450c9-cde9-45b6-8a07-be416df7cf97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091095067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.2091095067
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.1124831687
Short name T26
Test name
Test status
Simulation time 39833103 ps
CPU time 0.8 seconds
Started Jun 23 05:39:58 PM PDT 24
Finished Jun 23 05:39:59 PM PDT 24
Peak memory 218888 kb
Host smart-2f69fe36-f4af-4e9d-8f4f-44c5b9956488
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124831687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.1124831687
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.3952404459
Short name T750
Test name
Test status
Simulation time 485823447 ps
CPU time 1.85 seconds
Started Jun 23 05:39:55 PM PDT 24
Finished Jun 23 05:39:57 PM PDT 24
Peak memory 199288 kb
Host smart-71f3b156-55ec-4257-b42d-eddbf3117fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952404459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.3952404459
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.3877714135
Short name T665
Test name
Test status
Simulation time 126122030129 ps
CPU time 103.74 seconds
Started Jun 23 05:39:58 PM PDT 24
Finished Jun 23 05:41:42 PM PDT 24
Peak memory 200680 kb
Host smart-08f5aff6-7cec-40c0-93e1-6e4a59a12457
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877714135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.3877714135
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.590105512
Short name T431
Test name
Test status
Simulation time 1103066750 ps
CPU time 1.66 seconds
Started Jun 23 05:39:53 PM PDT 24
Finished Jun 23 05:39:55 PM PDT 24
Peak memory 199576 kb
Host smart-c713c63c-f4b6-43f5-b824-b769be2612c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590105512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.590105512
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.3630039787
Short name T806
Test name
Test status
Simulation time 8480673519 ps
CPU time 12.59 seconds
Started Jun 23 05:39:56 PM PDT 24
Finished Jun 23 05:40:09 PM PDT 24
Peak memory 200652 kb
Host smart-54c2ebe3-4ec0-46c8-bd95-c3bc193071f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630039787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.3630039787
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.1172255464
Short name T537
Test name
Test status
Simulation time 37249175 ps
CPU time 0.55 seconds
Started Jun 23 05:42:09 PM PDT 24
Finished Jun 23 05:42:09 PM PDT 24
Peak memory 195072 kb
Host smart-9409ced2-59bf-4621-876e-ba7e32ae3a74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172255464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.1172255464
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.2753273829
Short name T487
Test name
Test status
Simulation time 95763576424 ps
CPU time 27.86 seconds
Started Jun 23 05:42:04 PM PDT 24
Finished Jun 23 05:42:32 PM PDT 24
Peak memory 200688 kb
Host smart-c55fb65f-a923-4917-a722-1d96cd7af80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753273829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.2753273829
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.1379006667
Short name T488
Test name
Test status
Simulation time 48588411420 ps
CPU time 19.23 seconds
Started Jun 23 05:42:03 PM PDT 24
Finished Jun 23 05:42:23 PM PDT 24
Peak memory 200768 kb
Host smart-842c735d-9ed4-4316-b035-2fde7b818139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379006667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.1379006667
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.3938145356
Short name T314
Test name
Test status
Simulation time 16070048479 ps
CPU time 24.81 seconds
Started Jun 23 05:42:07 PM PDT 24
Finished Jun 23 05:42:32 PM PDT 24
Peak memory 198248 kb
Host smart-3966ea2e-7340-44b7-8188-d98e7ab10810
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938145356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.3938145356
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.2467348824
Short name T11
Test name
Test status
Simulation time 173979243163 ps
CPU time 292.42 seconds
Started Jun 23 05:42:05 PM PDT 24
Finished Jun 23 05:46:58 PM PDT 24
Peak memory 200636 kb
Host smart-a3cea4be-2fd3-4a4b-ac7f-7cd86fb3514a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2467348824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.2467348824
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.134258359
Short name T346
Test name
Test status
Simulation time 10639367028 ps
CPU time 15.68 seconds
Started Jun 23 05:42:09 PM PDT 24
Finished Jun 23 05:42:25 PM PDT 24
Peak memory 200696 kb
Host smart-8ecbbe8a-5d32-4103-a6ea-c6e8397fa808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134258359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.134258359
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_perf.4199423702
Short name T593
Test name
Test status
Simulation time 16785144425 ps
CPU time 509.14 seconds
Started Jun 23 05:42:16 PM PDT 24
Finished Jun 23 05:50:46 PM PDT 24
Peak memory 200672 kb
Host smart-e4c6812a-afa3-495f-893c-7bf9d94fa920
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4199423702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.4199423702
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.1681785817
Short name T418
Test name
Test status
Simulation time 1986569786 ps
CPU time 8.36 seconds
Started Jun 23 05:42:11 PM PDT 24
Finished Jun 23 05:42:20 PM PDT 24
Peak memory 198732 kb
Host smart-1aeb9a03-b3b7-4897-ba6b-a2af374929bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1681785817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.1681785817
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.3394145230
Short name T987
Test name
Test status
Simulation time 15031979268 ps
CPU time 12.32 seconds
Started Jun 23 05:42:10 PM PDT 24
Finished Jun 23 05:42:24 PM PDT 24
Peak memory 200752 kb
Host smart-5a3305aa-ab1a-4987-a539-9bb06286829c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394145230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.3394145230
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.2003553314
Short name T599
Test name
Test status
Simulation time 3237426707 ps
CPU time 2.91 seconds
Started Jun 23 05:42:07 PM PDT 24
Finished Jun 23 05:42:10 PM PDT 24
Peak memory 196928 kb
Host smart-1c13fa26-ad55-463f-b9fa-49ecdb3fea48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003553314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.2003553314
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.1795889240
Short name T971
Test name
Test status
Simulation time 681533198 ps
CPU time 1.86 seconds
Started Jun 23 05:42:06 PM PDT 24
Finished Jun 23 05:42:09 PM PDT 24
Peak memory 199088 kb
Host smart-a719f725-1585-4a38-9752-e9641159738b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795889240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.1795889240
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.2863288569
Short name T1077
Test name
Test status
Simulation time 238266545573 ps
CPU time 236.95 seconds
Started Jun 23 05:42:06 PM PDT 24
Finished Jun 23 05:46:04 PM PDT 24
Peak memory 200664 kb
Host smart-b5440a15-00c5-499b-be72-eeb31024217d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863288569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.2863288569
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.3592280787
Short name T442
Test name
Test status
Simulation time 12334575011 ps
CPU time 153.86 seconds
Started Jun 23 05:42:09 PM PDT 24
Finished Jun 23 05:44:43 PM PDT 24
Peak memory 217116 kb
Host smart-d006a38b-1458-44b4-9cfe-33d841eb85cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592280787 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.3592280787
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.2082800997
Short name T636
Test name
Test status
Simulation time 6527013510 ps
CPU time 17.37 seconds
Started Jun 23 05:42:07 PM PDT 24
Finished Jun 23 05:42:25 PM PDT 24
Peak memory 200744 kb
Host smart-952f052d-cc6f-4c47-9d25-b421ebcb3c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082800997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.2082800997
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.3564061132
Short name T857
Test name
Test status
Simulation time 79120417680 ps
CPU time 27.93 seconds
Started Jun 23 05:42:07 PM PDT 24
Finished Jun 23 05:42:36 PM PDT 24
Peak memory 200612 kb
Host smart-69eeb29e-deb3-4700-89af-c4f9a2a3cc95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564061132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.3564061132
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.289628820
Short name T339
Test name
Test status
Simulation time 14509949 ps
CPU time 0.54 seconds
Started Jun 23 05:42:10 PM PDT 24
Finished Jun 23 05:42:11 PM PDT 24
Peak memory 196096 kb
Host smart-557c520a-e785-46db-ba0a-97dad2678f98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289628820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.289628820
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.1659778112
Short name T767
Test name
Test status
Simulation time 47060138371 ps
CPU time 84.45 seconds
Started Jun 23 05:42:04 PM PDT 24
Finished Jun 23 05:43:29 PM PDT 24
Peak memory 200664 kb
Host smart-7c40fe62-9761-4f9b-9c5f-8242e5539699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659778112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.1659778112
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.2749936746
Short name T647
Test name
Test status
Simulation time 21767505739 ps
CPU time 36.23 seconds
Started Jun 23 05:42:16 PM PDT 24
Finished Jun 23 05:42:53 PM PDT 24
Peak memory 200696 kb
Host smart-921bfb0f-f04b-4ee5-9b86-e23db01f23c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749936746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.2749936746
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.270961069
Short name T108
Test name
Test status
Simulation time 56704991473 ps
CPU time 40.63 seconds
Started Jun 23 05:42:10 PM PDT 24
Finished Jun 23 05:42:52 PM PDT 24
Peak memory 200668 kb
Host smart-06b3e608-9949-47cd-9d5b-c66a7a203ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270961069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.270961069
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.692688283
Short name T811
Test name
Test status
Simulation time 366562945122 ps
CPU time 646.15 seconds
Started Jun 23 05:42:06 PM PDT 24
Finished Jun 23 05:52:53 PM PDT 24
Peak memory 200008 kb
Host smart-18a3b589-0899-4cdf-bda8-ec7cddefa7b4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692688283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.692688283
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.2122154166
Short name T542
Test name
Test status
Simulation time 60122854730 ps
CPU time 419.45 seconds
Started Jun 23 05:42:16 PM PDT 24
Finished Jun 23 05:49:16 PM PDT 24
Peak memory 200740 kb
Host smart-1ebe79ed-a460-403b-af59-d13917e49ca4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2122154166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.2122154166
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.703563047
Short name T923
Test name
Test status
Simulation time 4468001622 ps
CPU time 11.23 seconds
Started Jun 23 05:42:08 PM PDT 24
Finished Jun 23 05:42:20 PM PDT 24
Peak memory 200524 kb
Host smart-3a064842-1788-44e1-9070-51068401b18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703563047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.703563047
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_perf.788044060
Short name T715
Test name
Test status
Simulation time 28598030959 ps
CPU time 1451.48 seconds
Started Jun 23 05:42:16 PM PDT 24
Finished Jun 23 06:06:28 PM PDT 24
Peak memory 200676 kb
Host smart-999a631f-4085-4829-84ed-114d36560e46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=788044060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.788044060
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.969559659
Short name T556
Test name
Test status
Simulation time 7393061090 ps
CPU time 16.78 seconds
Started Jun 23 05:42:11 PM PDT 24
Finished Jun 23 05:42:28 PM PDT 24
Peak memory 198892 kb
Host smart-7833dc72-a810-4390-adf4-225183b3409c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=969559659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.969559659
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.4125881141
Short name T794
Test name
Test status
Simulation time 25501685067 ps
CPU time 20.97 seconds
Started Jun 23 05:42:11 PM PDT 24
Finished Jun 23 05:42:33 PM PDT 24
Peak memory 200672 kb
Host smart-5c8a58db-1f89-4362-80d3-a626def43c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125881141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.4125881141
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.3863651351
Short name T588
Test name
Test status
Simulation time 30823251967 ps
CPU time 36.95 seconds
Started Jun 23 05:42:12 PM PDT 24
Finished Jun 23 05:42:49 PM PDT 24
Peak memory 196536 kb
Host smart-47aaf9b1-1e9b-4f57-9ee9-6aa109bf2211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863651351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.3863651351
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.1303992645
Short name T591
Test name
Test status
Simulation time 1016887889 ps
CPU time 1.32 seconds
Started Jun 23 05:42:10 PM PDT 24
Finished Jun 23 05:42:12 PM PDT 24
Peak memory 200276 kb
Host smart-30b4ac0b-35e6-48e8-8ef2-be9fb775e541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303992645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.1303992645
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.22714114
Short name T798
Test name
Test status
Simulation time 138853823619 ps
CPU time 189.38 seconds
Started Jun 23 05:42:12 PM PDT 24
Finished Jun 23 05:45:22 PM PDT 24
Peak memory 200648 kb
Host smart-8c22fc8b-a9ec-41ad-b3fc-bb81a559f430
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22714114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.22714114
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.1267678818
Short name T888
Test name
Test status
Simulation time 376432918173 ps
CPU time 742.15 seconds
Started Jun 23 05:42:08 PM PDT 24
Finished Jun 23 05:54:31 PM PDT 24
Peak memory 217092 kb
Host smart-d839bb8d-0cbd-4b95-a41c-5f54ebf89540
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267678818 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.1267678818
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.1856115861
Short name T298
Test name
Test status
Simulation time 6200169239 ps
CPU time 19.31 seconds
Started Jun 23 05:42:10 PM PDT 24
Finished Jun 23 05:42:31 PM PDT 24
Peak memory 200704 kb
Host smart-fa434ef0-0280-45f5-84f5-69aedbf10210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856115861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1856115861
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.3835499664
Short name T935
Test name
Test status
Simulation time 199609767990 ps
CPU time 57 seconds
Started Jun 23 05:42:09 PM PDT 24
Finished Jun 23 05:43:06 PM PDT 24
Peak memory 200756 kb
Host smart-6e79119c-6c3f-4470-93d0-58d65915b176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835499664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.3835499664
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.1753213044
Short name T389
Test name
Test status
Simulation time 34468690 ps
CPU time 0.55 seconds
Started Jun 23 05:42:14 PM PDT 24
Finished Jun 23 05:42:15 PM PDT 24
Peak memory 196036 kb
Host smart-78409a71-ac64-4376-8266-c386603b4764
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753213044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.1753213044
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.234252454
Short name T630
Test name
Test status
Simulation time 105380071482 ps
CPU time 22.87 seconds
Started Jun 23 05:42:16 PM PDT 24
Finished Jun 23 05:42:39 PM PDT 24
Peak memory 200696 kb
Host smart-fd462894-41fb-46f0-8374-7bd028413be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234252454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.234252454
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.4013310011
Short name T1025
Test name
Test status
Simulation time 179592698113 ps
CPU time 16.02 seconds
Started Jun 23 05:42:10 PM PDT 24
Finished Jun 23 05:42:27 PM PDT 24
Peak memory 200476 kb
Host smart-27d38b4a-957c-418d-b232-6d338c7b6e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013310011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.4013310011
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.12179351
Short name T1094
Test name
Test status
Simulation time 62423333010 ps
CPU time 22.62 seconds
Started Jun 23 05:42:12 PM PDT 24
Finished Jun 23 05:42:35 PM PDT 24
Peak memory 200760 kb
Host smart-28638056-93e5-4c0a-82c0-ee0966b2c495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12179351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.12179351
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.479208319
Short name T258
Test name
Test status
Simulation time 23532972304 ps
CPU time 20.6 seconds
Started Jun 23 05:42:12 PM PDT 24
Finished Jun 23 05:42:33 PM PDT 24
Peak memory 200736 kb
Host smart-e10efc1d-b3dd-47b1-99d4-f86df4e32f9a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479208319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.479208319
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.432957136
Short name T562
Test name
Test status
Simulation time 106479750636 ps
CPU time 769.82 seconds
Started Jun 23 05:42:13 PM PDT 24
Finished Jun 23 05:55:04 PM PDT 24
Peak memory 200736 kb
Host smart-e22dcfa2-fc0c-40b3-a1b0-0240ea6de575
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=432957136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.432957136
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.2669441719
Short name T950
Test name
Test status
Simulation time 2464738269 ps
CPU time 2.1 seconds
Started Jun 23 05:42:12 PM PDT 24
Finished Jun 23 05:42:15 PM PDT 24
Peak memory 199572 kb
Host smart-b39d84f5-7d20-4055-a9b1-e6f416cfb8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669441719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.2669441719
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_perf.3081014050
Short name T517
Test name
Test status
Simulation time 7064416087 ps
CPU time 104.92 seconds
Started Jun 23 05:42:14 PM PDT 24
Finished Jun 23 05:44:00 PM PDT 24
Peak memory 200744 kb
Host smart-85da8d50-13d7-440d-a780-6dbec4b47bf3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3081014050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.3081014050
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.2203760824
Short name T760
Test name
Test status
Simulation time 1505451448 ps
CPU time 2.78 seconds
Started Jun 23 05:42:09 PM PDT 24
Finished Jun 23 05:42:12 PM PDT 24
Peak memory 198632 kb
Host smart-a0b3a87a-b2f6-4413-9867-fa7c192a536d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2203760824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.2203760824
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.2644814923
Short name T931
Test name
Test status
Simulation time 14271878978 ps
CPU time 22.6 seconds
Started Jun 23 05:42:16 PM PDT 24
Finished Jun 23 05:42:38 PM PDT 24
Peak memory 200520 kb
Host smart-1034fb48-e191-4d1b-aaa2-b58eb3e959ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644814923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.2644814923
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.1245583202
Short name T663
Test name
Test status
Simulation time 2445988297 ps
CPU time 4.25 seconds
Started Jun 23 05:42:08 PM PDT 24
Finished Jun 23 05:42:13 PM PDT 24
Peak memory 197188 kb
Host smart-f8c8110f-5ec7-4ffc-a2db-5af7f61a5dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245583202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.1245583202
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.3520381381
Short name T262
Test name
Test status
Simulation time 291188281 ps
CPU time 0.95 seconds
Started Jun 23 05:42:11 PM PDT 24
Finished Jun 23 05:42:13 PM PDT 24
Peak memory 199384 kb
Host smart-c364441f-df2a-4ea6-a56a-2a202d8d728b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520381381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.3520381381
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.2915928916
Short name T673
Test name
Test status
Simulation time 229070521709 ps
CPU time 265.53 seconds
Started Jun 23 05:42:15 PM PDT 24
Finished Jun 23 05:46:41 PM PDT 24
Peak memory 200696 kb
Host smart-8e62d42f-e041-4d65-b46a-8abf5dc2bcce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915928916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.2915928916
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.2295738267
Short name T696
Test name
Test status
Simulation time 395385807 ps
CPU time 1.58 seconds
Started Jun 23 05:42:13 PM PDT 24
Finished Jun 23 05:42:15 PM PDT 24
Peak memory 198708 kb
Host smart-dea09a4e-4684-4926-827e-4f58e94660ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295738267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.2295738267
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.2363729810
Short name T652
Test name
Test status
Simulation time 97654679645 ps
CPU time 50.07 seconds
Started Jun 23 05:42:11 PM PDT 24
Finished Jun 23 05:43:02 PM PDT 24
Peak memory 200624 kb
Host smart-05efbcee-a607-457f-8a0e-0a08b9297643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363729810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.2363729810
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.3672276087
Short name T828
Test name
Test status
Simulation time 25187439 ps
CPU time 0.57 seconds
Started Jun 23 05:42:17 PM PDT 24
Finished Jun 23 05:42:18 PM PDT 24
Peak memory 196056 kb
Host smart-8af7a600-ba02-472b-9205-bd3b2235303d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672276087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.3672276087
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.2024075787
Short name T1026
Test name
Test status
Simulation time 28220819564 ps
CPU time 36.82 seconds
Started Jun 23 05:42:14 PM PDT 24
Finished Jun 23 05:42:51 PM PDT 24
Peak memory 200688 kb
Host smart-dfc76451-470a-47f8-929e-fc5dd1c3fd75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024075787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.2024075787
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.3651625219
Short name T940
Test name
Test status
Simulation time 20223740961 ps
CPU time 36.02 seconds
Started Jun 23 05:42:14 PM PDT 24
Finished Jun 23 05:42:50 PM PDT 24
Peak memory 200724 kb
Host smart-c052de97-9c9d-4b2f-8b52-87022f58d690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651625219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.3651625219
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.1312878471
Short name T76
Test name
Test status
Simulation time 26393589496 ps
CPU time 59.61 seconds
Started Jun 23 05:42:16 PM PDT 24
Finished Jun 23 05:43:16 PM PDT 24
Peak memory 200912 kb
Host smart-e679221c-8af6-45b4-867c-9d6163e0f422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312878471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.1312878471
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.2249762389
Short name T414
Test name
Test status
Simulation time 296054141863 ps
CPU time 509.44 seconds
Started Jun 23 05:42:15 PM PDT 24
Finished Jun 23 05:50:45 PM PDT 24
Peak memory 200496 kb
Host smart-dae80c75-d70f-43e1-8f15-68f1f6b80de1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249762389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.2249762389
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.4290182585
Short name T348
Test name
Test status
Simulation time 135813906683 ps
CPU time 852.42 seconds
Started Jun 23 05:42:19 PM PDT 24
Finished Jun 23 05:56:32 PM PDT 24
Peak memory 200732 kb
Host smart-7728deef-6b59-40c3-9692-65c9a74f934a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4290182585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.4290182585
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.2906330213
Short name T867
Test name
Test status
Simulation time 10311198937 ps
CPU time 11.22 seconds
Started Jun 23 05:42:14 PM PDT 24
Finished Jun 23 05:42:26 PM PDT 24
Peak memory 200480 kb
Host smart-263a56c7-a3e6-49fc-8752-51295bfd7370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906330213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.2906330213
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_perf.2249097140
Short name T341
Test name
Test status
Simulation time 11860821514 ps
CPU time 643.89 seconds
Started Jun 23 05:42:16 PM PDT 24
Finished Jun 23 05:53:00 PM PDT 24
Peak memory 200696 kb
Host smart-3450fb41-850d-44ba-88bf-e993e966eb6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2249097140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.2249097140
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.1405089394
Short name T329
Test name
Test status
Simulation time 4992133432 ps
CPU time 13.28 seconds
Started Jun 23 05:42:14 PM PDT 24
Finished Jun 23 05:42:28 PM PDT 24
Peak memory 198932 kb
Host smart-4b901713-6ee7-45e6-b8a7-d30634e30672
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1405089394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.1405089394
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.4152715074
Short name T344
Test name
Test status
Simulation time 88674157216 ps
CPU time 57.77 seconds
Started Jun 23 05:42:12 PM PDT 24
Finished Jun 23 05:43:11 PM PDT 24
Peak memory 200776 kb
Host smart-ad42f5d4-4f17-4946-a0da-b57b334bb6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152715074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.4152715074
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.1343342047
Short name T736
Test name
Test status
Simulation time 1910849913 ps
CPU time 3.33 seconds
Started Jun 23 05:42:13 PM PDT 24
Finished Jun 23 05:42:17 PM PDT 24
Peak memory 196368 kb
Host smart-e2710d4a-2ac4-47b4-a586-9ef498cf64f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343342047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.1343342047
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.994727365
Short name T876
Test name
Test status
Simulation time 532872565 ps
CPU time 2.32 seconds
Started Jun 23 05:42:13 PM PDT 24
Finished Jun 23 05:42:16 PM PDT 24
Peak memory 199752 kb
Host smart-f4f61697-aa5b-48e6-88f0-f4b3654e7cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994727365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.994727365
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.1792439867
Short name T257
Test name
Test status
Simulation time 5969297931 ps
CPU time 3.73 seconds
Started Jun 23 05:42:20 PM PDT 24
Finished Jun 23 05:42:24 PM PDT 24
Peak memory 200676 kb
Host smart-c21b652a-cb33-4e7b-9d1e-e914225450dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792439867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.1792439867
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.3311635001
Short name T1078
Test name
Test status
Simulation time 3769146133 ps
CPU time 1.71 seconds
Started Jun 23 05:42:16 PM PDT 24
Finished Jun 23 05:42:19 PM PDT 24
Peak memory 199604 kb
Host smart-548ab7f4-02c6-47e9-bba3-5d8f77af54d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311635001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.3311635001
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.964356267
Short name T966
Test name
Test status
Simulation time 100441905336 ps
CPU time 129.92 seconds
Started Jun 23 05:42:14 PM PDT 24
Finished Jun 23 05:44:24 PM PDT 24
Peak memory 200692 kb
Host smart-e9c3d564-52d1-49f0-a493-35b0081cff7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964356267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.964356267
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.2765796400
Short name T379
Test name
Test status
Simulation time 15384795 ps
CPU time 0.57 seconds
Started Jun 23 05:42:25 PM PDT 24
Finished Jun 23 05:42:26 PM PDT 24
Peak memory 196100 kb
Host smart-6226166a-47ad-43e4-b461-4243fba865fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765796400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.2765796400
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.3249336474
Short name T771
Test name
Test status
Simulation time 24712851059 ps
CPU time 60.53 seconds
Started Jun 23 05:42:19 PM PDT 24
Finished Jun 23 05:43:20 PM PDT 24
Peak memory 200748 kb
Host smart-4156a3e7-277f-49a8-aa12-c58f66d0684e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249336474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.3249336474
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.3097360688
Short name T829
Test name
Test status
Simulation time 135988059462 ps
CPU time 202.45 seconds
Started Jun 23 05:42:17 PM PDT 24
Finished Jun 23 05:45:40 PM PDT 24
Peak memory 200504 kb
Host smart-9462a9b8-341f-4cf8-9251-4b551c152db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097360688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.3097360688
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.4130773654
Short name T550
Test name
Test status
Simulation time 116841082555 ps
CPU time 144.9 seconds
Started Jun 23 05:42:18 PM PDT 24
Finished Jun 23 05:44:44 PM PDT 24
Peak memory 200756 kb
Host smart-c7c4209b-9809-4ae8-b59f-52f4f0f6480f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130773654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.4130773654
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.2093908430
Short name T645
Test name
Test status
Simulation time 41370067003 ps
CPU time 55.83 seconds
Started Jun 23 05:42:26 PM PDT 24
Finished Jun 23 05:43:22 PM PDT 24
Peak memory 200224 kb
Host smart-805b0550-2da1-4745-97e6-f5544cffb893
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093908430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.2093908430
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.2431103295
Short name T928
Test name
Test status
Simulation time 155572775307 ps
CPU time 1285.9 seconds
Started Jun 23 05:42:25 PM PDT 24
Finished Jun 23 06:03:51 PM PDT 24
Peak memory 200708 kb
Host smart-efebe82d-5251-4508-9173-72fb77a51f64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2431103295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.2431103295
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.3320783314
Short name T579
Test name
Test status
Simulation time 9059133553 ps
CPU time 17.9 seconds
Started Jun 23 05:42:25 PM PDT 24
Finished Jun 23 05:42:44 PM PDT 24
Peak memory 200536 kb
Host smart-287efe03-ee25-40a0-ba4c-ae08f0a6947c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320783314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.3320783314
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_perf.942999148
Short name T830
Test name
Test status
Simulation time 8234528782 ps
CPU time 429.99 seconds
Started Jun 23 05:42:24 PM PDT 24
Finished Jun 23 05:49:34 PM PDT 24
Peak memory 200688 kb
Host smart-0b74936c-f513-409b-8f65-d6fc17b58df5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=942999148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.942999148
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.2929920823
Short name T650
Test name
Test status
Simulation time 6821770665 ps
CPU time 15.24 seconds
Started Jun 23 05:42:35 PM PDT 24
Finished Jun 23 05:42:51 PM PDT 24
Peak memory 199600 kb
Host smart-7cac6f64-51be-4ba1-b47d-fce027711976
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2929920823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.2929920823
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.2399788032
Short name T527
Test name
Test status
Simulation time 23546330999 ps
CPU time 18.71 seconds
Started Jun 23 05:42:25 PM PDT 24
Finished Jun 23 05:42:44 PM PDT 24
Peak memory 199056 kb
Host smart-fc991cfa-c5c2-46c4-b85b-1814e1e019cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399788032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.2399788032
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.1020311247
Short name T1043
Test name
Test status
Simulation time 4346193565 ps
CPU time 4.08 seconds
Started Jun 23 05:42:25 PM PDT 24
Finished Jun 23 05:42:30 PM PDT 24
Peak memory 196756 kb
Host smart-f83e77c7-52aa-4c51-94e1-765e90911fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020311247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.1020311247
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.723034942
Short name T466
Test name
Test status
Simulation time 670685260 ps
CPU time 3.21 seconds
Started Jun 23 05:42:18 PM PDT 24
Finished Jun 23 05:42:21 PM PDT 24
Peak memory 200496 kb
Host smart-095901c7-a62b-4128-9231-81cea0fc6186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723034942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.723034942
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.2622337122
Short name T1052
Test name
Test status
Simulation time 81891312506 ps
CPU time 1160.52 seconds
Started Jun 23 05:42:24 PM PDT 24
Finished Jun 23 06:01:45 PM PDT 24
Peak memory 217188 kb
Host smart-f1f2e3e6-2ba3-4638-992a-b0ee98efa9e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622337122 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.2622337122
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.1215050101
Short name T250
Test name
Test status
Simulation time 8401137633 ps
CPU time 8.59 seconds
Started Jun 23 05:42:24 PM PDT 24
Finished Jun 23 05:42:33 PM PDT 24
Peak memory 200688 kb
Host smart-634c0a8c-6840-4013-ab68-9cbf030a692f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215050101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.1215050101
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.3532874778
Short name T998
Test name
Test status
Simulation time 49850575413 ps
CPU time 11.16 seconds
Started Jun 23 05:42:21 PM PDT 24
Finished Jun 23 05:42:32 PM PDT 24
Peak memory 200696 kb
Host smart-cc1df548-17ff-4404-b1eb-a24c2187a616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532874778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.3532874778
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.3531714382
Short name T691
Test name
Test status
Simulation time 22307743 ps
CPU time 0.6 seconds
Started Jun 23 05:42:34 PM PDT 24
Finished Jun 23 05:42:35 PM PDT 24
Peak memory 196080 kb
Host smart-5fe3afac-daa5-41bf-ac68-355f370cc251
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531714382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.3531714382
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.292476723
Short name T1067
Test name
Test status
Simulation time 59619134188 ps
CPU time 56.32 seconds
Started Jun 23 05:42:29 PM PDT 24
Finished Jun 23 05:43:26 PM PDT 24
Peak memory 200688 kb
Host smart-f378611b-1ba0-41df-bfcf-18d9872bed1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292476723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.292476723
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.1701887759
Short name T229
Test name
Test status
Simulation time 133665495382 ps
CPU time 63.06 seconds
Started Jun 23 05:42:30 PM PDT 24
Finished Jun 23 05:43:33 PM PDT 24
Peak memory 200688 kb
Host smart-28ec772b-8da3-45fb-9fe6-8d93b68f890b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701887759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.1701887759
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.1568513964
Short name T221
Test name
Test status
Simulation time 40584586063 ps
CPU time 32.52 seconds
Started Jun 23 05:42:32 PM PDT 24
Finished Jun 23 05:43:05 PM PDT 24
Peak memory 200752 kb
Host smart-9c5066e7-88e7-4593-a42f-3f1134adeae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568513964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.1568513964
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.4201699294
Short name T926
Test name
Test status
Simulation time 4884130636 ps
CPU time 10.07 seconds
Started Jun 23 05:42:28 PM PDT 24
Finished Jun 23 05:42:39 PM PDT 24
Peak memory 200600 kb
Host smart-62e4787d-8297-49dd-a4af-d31d88b133f5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201699294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.4201699294
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.2944508919
Short name T752
Test name
Test status
Simulation time 107020575830 ps
CPU time 386.45 seconds
Started Jun 23 05:42:28 PM PDT 24
Finished Jun 23 05:48:55 PM PDT 24
Peak memory 200692 kb
Host smart-3f282f45-7dd4-4b46-9055-87aa8aea0a9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2944508919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.2944508919
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.355668399
Short name T577
Test name
Test status
Simulation time 22487091 ps
CPU time 0.62 seconds
Started Jun 23 05:42:32 PM PDT 24
Finished Jun 23 05:42:33 PM PDT 24
Peak memory 196492 kb
Host smart-75572831-66ad-44cd-8daa-3332f6d3fd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355668399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.355668399
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_perf.1188477472
Short name T846
Test name
Test status
Simulation time 15263257842 ps
CPU time 338.16 seconds
Started Jun 23 05:42:28 PM PDT 24
Finished Jun 23 05:48:06 PM PDT 24
Peak memory 200560 kb
Host smart-834d2037-fb3d-4681-9c07-443dea48c4fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1188477472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.1188477472
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.3369854677
Short name T959
Test name
Test status
Simulation time 4252786440 ps
CPU time 31.89 seconds
Started Jun 23 05:42:29 PM PDT 24
Finished Jun 23 05:43:01 PM PDT 24
Peak memory 199432 kb
Host smart-31768c42-7cbb-4ade-84b3-648fb52d5166
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3369854677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.3369854677
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.31868211
Short name T1002
Test name
Test status
Simulation time 105677807919 ps
CPU time 52.73 seconds
Started Jun 23 05:42:32 PM PDT 24
Finished Jun 23 05:43:25 PM PDT 24
Peak memory 200664 kb
Host smart-b4ec2f6b-bef2-406a-ad89-09630114fa4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31868211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.31868211
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.1076142405
Short name T945
Test name
Test status
Simulation time 3071819667 ps
CPU time 1.8 seconds
Started Jun 23 05:42:32 PM PDT 24
Finished Jun 23 05:42:34 PM PDT 24
Peak memory 197012 kb
Host smart-4d7e3ec1-1fa6-4904-a347-45ed0e05bd9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076142405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.1076142405
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.2214971126
Short name T723
Test name
Test status
Simulation time 5736245615 ps
CPU time 8.17 seconds
Started Jun 23 05:42:29 PM PDT 24
Finished Jun 23 05:42:38 PM PDT 24
Peak memory 200480 kb
Host smart-9b4cd3ed-0b99-4e37-9faf-3976fadd7804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214971126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.2214971126
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.533948175
Short name T559
Test name
Test status
Simulation time 1156912146 ps
CPU time 3.26 seconds
Started Jun 23 05:42:29 PM PDT 24
Finished Jun 23 05:42:33 PM PDT 24
Peak memory 200464 kb
Host smart-0eafb77f-2e4d-43e0-8c57-f7149a6a9ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533948175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.533948175
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.3146687566
Short name T557
Test name
Test status
Simulation time 125886923049 ps
CPU time 19.94 seconds
Started Jun 23 05:42:29 PM PDT 24
Finished Jun 23 05:42:49 PM PDT 24
Peak memory 200724 kb
Host smart-93ea097f-0d24-49d2-b85a-dd9c888ebb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146687566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.3146687566
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.3587629829
Short name T460
Test name
Test status
Simulation time 15181709 ps
CPU time 0.54 seconds
Started Jun 23 05:42:39 PM PDT 24
Finished Jun 23 05:42:40 PM PDT 24
Peak memory 195068 kb
Host smart-eea457e9-693e-433f-9f99-4de8b3a1121c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587629829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.3587629829
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.1496189089
Short name T465
Test name
Test status
Simulation time 18451481156 ps
CPU time 32.59 seconds
Started Jun 23 05:42:34 PM PDT 24
Finished Jun 23 05:43:07 PM PDT 24
Peak memory 200476 kb
Host smart-6d94e12e-a180-44b5-b6da-38e4d955e163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496189089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.1496189089
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.3806702526
Short name T589
Test name
Test status
Simulation time 96704630718 ps
CPU time 44.09 seconds
Started Jun 23 05:42:34 PM PDT 24
Finished Jun 23 05:43:19 PM PDT 24
Peak memory 200668 kb
Host smart-3179e0ae-63f3-478f-9488-bba6536dc832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806702526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.3806702526
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_intr.2105973824
Short name T730
Test name
Test status
Simulation time 22254442846 ps
CPU time 7.11 seconds
Started Jun 23 05:42:34 PM PDT 24
Finished Jun 23 05:42:41 PM PDT 24
Peak memory 198460 kb
Host smart-28990b62-f7bd-44f0-96de-12b2febadda9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105973824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.2105973824
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.333363671
Short name T1029
Test name
Test status
Simulation time 64113862191 ps
CPU time 362.47 seconds
Started Jun 23 05:42:35 PM PDT 24
Finished Jun 23 05:48:38 PM PDT 24
Peak memory 200668 kb
Host smart-f2364e16-a8ef-4a14-8118-1b1e42ca6970
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=333363671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.333363671
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.2292767733
Short name T373
Test name
Test status
Simulation time 625825841 ps
CPU time 1.28 seconds
Started Jun 23 05:42:39 PM PDT 24
Finished Jun 23 05:42:41 PM PDT 24
Peak memory 199104 kb
Host smart-ec0e2feb-109c-4721-9139-a71d3085b853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292767733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.2292767733
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_perf.612360814
Short name T297
Test name
Test status
Simulation time 16826669027 ps
CPU time 228.06 seconds
Started Jun 23 05:42:38 PM PDT 24
Finished Jun 23 05:46:27 PM PDT 24
Peak memory 200716 kb
Host smart-f385f862-a25f-46d1-8e3e-0d5d90df964c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=612360814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.612360814
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.3648335152
Short name T682
Test name
Test status
Simulation time 2338876995 ps
CPU time 18.63 seconds
Started Jun 23 05:42:34 PM PDT 24
Finished Jun 23 05:42:53 PM PDT 24
Peak memory 199812 kb
Host smart-39ff33b5-f035-4e36-bb23-17109a4a532d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3648335152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.3648335152
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.3967586959
Short name T132
Test name
Test status
Simulation time 68524393443 ps
CPU time 176.44 seconds
Started Jun 23 05:42:33 PM PDT 24
Finished Jun 23 05:45:30 PM PDT 24
Peak memory 200756 kb
Host smart-5a77eff4-86ef-4d78-a88c-968b4b61d7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967586959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.3967586959
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.1443059121
Short name T420
Test name
Test status
Simulation time 3204073275 ps
CPU time 5.64 seconds
Started Jun 23 05:42:33 PM PDT 24
Finished Jun 23 05:42:39 PM PDT 24
Peak memory 196608 kb
Host smart-1806489b-2d44-41c2-b127-5b6de2cc8380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443059121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.1443059121
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.3122521369
Short name T656
Test name
Test status
Simulation time 506033269 ps
CPU time 3.83 seconds
Started Jun 23 05:42:31 PM PDT 24
Finished Jun 23 05:42:35 PM PDT 24
Peak memory 199376 kb
Host smart-c80ba85a-cdf8-41a1-8d87-7d1436e32dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122521369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.3122521369
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.1915297975
Short name T44
Test name
Test status
Simulation time 192588990918 ps
CPU time 247.05 seconds
Started Jun 23 05:42:39 PM PDT 24
Finished Jun 23 05:46:47 PM PDT 24
Peak memory 217128 kb
Host smart-e5ed9b5c-6de5-41eb-ace0-7f4d0d6c8a49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915297975 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.1915297975
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.2964726312
Short name T632
Test name
Test status
Simulation time 6938705624 ps
CPU time 15.73 seconds
Started Jun 23 05:42:36 PM PDT 24
Finished Jun 23 05:42:52 PM PDT 24
Peak memory 200200 kb
Host smart-332608cb-3a83-4f43-a83c-27ea9850548a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964726312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.2964726312
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.1753360064
Short name T834
Test name
Test status
Simulation time 116776035440 ps
CPU time 28.79 seconds
Started Jun 23 05:42:34 PM PDT 24
Finished Jun 23 05:43:03 PM PDT 24
Peak memory 200640 kb
Host smart-6053d32f-c766-4723-a1c4-89f1e6f77a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753360064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.1753360064
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.4102503179
Short name T24
Test name
Test status
Simulation time 14947570 ps
CPU time 0.56 seconds
Started Jun 23 05:42:49 PM PDT 24
Finished Jun 23 05:42:50 PM PDT 24
Peak memory 196036 kb
Host smart-b621092d-30f2-4978-80ed-deeb39e27bb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102503179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.4102503179
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.3677436345
Short name T251
Test name
Test status
Simulation time 96042322072 ps
CPU time 43.55 seconds
Started Jun 23 05:42:37 PM PDT 24
Finished Jun 23 05:43:21 PM PDT 24
Peak memory 200748 kb
Host smart-96aa5676-c683-47df-9bda-bec2fa51b93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677436345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.3677436345
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.935596607
Short name T749
Test name
Test status
Simulation time 88489385786 ps
CPU time 60.95 seconds
Started Jun 23 05:42:36 PM PDT 24
Finished Jun 23 05:43:38 PM PDT 24
Peak memory 200572 kb
Host smart-dc8d1149-6aa6-4bf2-8f19-32d42da8f0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935596607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.935596607
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.160674346
Short name T182
Test name
Test status
Simulation time 88778797671 ps
CPU time 82.09 seconds
Started Jun 23 05:42:39 PM PDT 24
Finished Jun 23 05:44:02 PM PDT 24
Peak memory 200644 kb
Host smart-7a363158-b0f0-42ff-9dbb-80ef333c306b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160674346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.160674346
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.1022852037
Short name T99
Test name
Test status
Simulation time 41366172669 ps
CPU time 40.25 seconds
Started Jun 23 05:42:35 PM PDT 24
Finished Jun 23 05:43:16 PM PDT 24
Peak memory 200672 kb
Host smart-7b6e6971-4661-4838-805a-20a048bff79f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022852037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.1022852037
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.2572004215
Short name T287
Test name
Test status
Simulation time 116758913950 ps
CPU time 446.5 seconds
Started Jun 23 05:42:43 PM PDT 24
Finished Jun 23 05:50:11 PM PDT 24
Peak memory 200744 kb
Host smart-5b11cf7e-b712-456f-95b9-bf01074ed4b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2572004215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.2572004215
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.2185204081
Short name T306
Test name
Test status
Simulation time 2753964949 ps
CPU time 4.81 seconds
Started Jun 23 05:42:45 PM PDT 24
Finished Jun 23 05:42:50 PM PDT 24
Peak memory 200016 kb
Host smart-58bc6fda-0254-4492-8d9c-f44a8de073b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185204081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.2185204081
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.3809762006
Short name T477
Test name
Test status
Simulation time 7293572651 ps
CPU time 12.3 seconds
Started Jun 23 05:42:40 PM PDT 24
Finished Jun 23 05:42:53 PM PDT 24
Peak memory 200308 kb
Host smart-63a64d9e-7224-49ea-a0f5-ec9a907c232d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809762006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.3809762006
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.268531357
Short name T817
Test name
Test status
Simulation time 23553152110 ps
CPU time 1046.37 seconds
Started Jun 23 05:42:42 PM PDT 24
Finished Jun 23 06:00:09 PM PDT 24
Peak memory 200644 kb
Host smart-7b203fdc-b028-48dc-a6cf-ec3bed5a4476
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=268531357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.268531357
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.3988455762
Short name T337
Test name
Test status
Simulation time 3095504295 ps
CPU time 6.27 seconds
Started Jun 23 05:42:38 PM PDT 24
Finished Jun 23 05:42:45 PM PDT 24
Peak memory 198956 kb
Host smart-f4b4bc34-5600-4ada-8102-938e4a812060
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3988455762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.3988455762
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.3620512130
Short name T366
Test name
Test status
Simulation time 41835136825 ps
CPU time 71.86 seconds
Started Jun 23 05:42:42 PM PDT 24
Finished Jun 23 05:43:55 PM PDT 24
Peak memory 200720 kb
Host smart-476ac0d8-4428-4e2c-9e4e-a6c261aba529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620512130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.3620512130
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.1167697516
Short name T886
Test name
Test status
Simulation time 54243363475 ps
CPU time 43.5 seconds
Started Jun 23 05:42:43 PM PDT 24
Finished Jun 23 05:43:27 PM PDT 24
Peak memory 196516 kb
Host smart-fcbdddfd-075e-4043-bf77-f5176cfef248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167697516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.1167697516
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.3076440603
Short name T359
Test name
Test status
Simulation time 430553682 ps
CPU time 1.78 seconds
Started Jun 23 05:42:38 PM PDT 24
Finished Jun 23 05:42:40 PM PDT 24
Peak memory 200696 kb
Host smart-3b4c5938-f490-4bd9-9fa6-9f24adecf591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076440603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.3076440603
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.1425279626
Short name T1061
Test name
Test status
Simulation time 2412040590 ps
CPU time 1.69 seconds
Started Jun 23 05:42:42 PM PDT 24
Finished Jun 23 05:42:44 PM PDT 24
Peak memory 197956 kb
Host smart-9425cbf8-8493-4a20-b65f-5ec34548be27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425279626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.1425279626
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.2565838130
Short name T475
Test name
Test status
Simulation time 125909986024 ps
CPU time 212.89 seconds
Started Jun 23 05:42:39 PM PDT 24
Finished Jun 23 05:46:13 PM PDT 24
Peak memory 200704 kb
Host smart-0a4f78d7-3ffe-433c-bf8d-0765dcefd914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565838130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.2565838130
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.3617384586
Short name T372
Test name
Test status
Simulation time 45410073 ps
CPU time 0.6 seconds
Started Jun 23 05:42:52 PM PDT 24
Finished Jun 23 05:42:53 PM PDT 24
Peak memory 196096 kb
Host smart-7fbe13b1-b5c6-4be4-b789-0dea5d1253d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617384586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.3617384586
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.3036411500
Short name T1017
Test name
Test status
Simulation time 73286230771 ps
CPU time 33.21 seconds
Started Jun 23 05:42:48 PM PDT 24
Finished Jun 23 05:43:21 PM PDT 24
Peak memory 200672 kb
Host smart-8cdb0111-967c-4993-9b79-e7bc78805490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036411500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.3036411500
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.100332266
Short name T110
Test name
Test status
Simulation time 20536775311 ps
CPU time 35.01 seconds
Started Jun 23 05:42:45 PM PDT 24
Finished Jun 23 05:43:20 PM PDT 24
Peak memory 200732 kb
Host smart-d9a47a25-7ed9-4c24-b261-cef3b444c44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100332266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.100332266
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.3537560530
Short name T780
Test name
Test status
Simulation time 67293983361 ps
CPU time 25.93 seconds
Started Jun 23 05:42:47 PM PDT 24
Finished Jun 23 05:43:13 PM PDT 24
Peak memory 200640 kb
Host smart-1d183bfa-9e1a-42ba-a938-65e59549988f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537560530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.3537560530
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.3346876655
Short name T19
Test name
Test status
Simulation time 58289264819 ps
CPU time 29.14 seconds
Started Jun 23 05:42:47 PM PDT 24
Finished Jun 23 05:43:16 PM PDT 24
Peak memory 200620 kb
Host smart-00790d31-918b-4788-90a6-10685c4fd2ee
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346876655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.3346876655
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.325296147
Short name T486
Test name
Test status
Simulation time 106036582964 ps
CPU time 411.73 seconds
Started Jun 23 05:42:51 PM PDT 24
Finished Jun 23 05:49:43 PM PDT 24
Peak memory 200728 kb
Host smart-4d4884f9-6a23-4cef-8eca-a184be2e010d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=325296147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.325296147
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.1492367011
Short name T310
Test name
Test status
Simulation time 12199554563 ps
CPU time 20.11 seconds
Started Jun 23 05:42:53 PM PDT 24
Finished Jun 23 05:43:13 PM PDT 24
Peak memory 200436 kb
Host smart-40099300-303b-48ed-96fc-c7b557bb710c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492367011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.1492367011
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_perf.1876150396
Short name T511
Test name
Test status
Simulation time 31382600802 ps
CPU time 1393.33 seconds
Started Jun 23 05:42:54 PM PDT 24
Finished Jun 23 06:06:07 PM PDT 24
Peak memory 200656 kb
Host smart-428d3a72-fd06-48f3-8fc8-a88c1b432029
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1876150396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.1876150396
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.519624187
Short name T980
Test name
Test status
Simulation time 4546867740 ps
CPU time 9.52 seconds
Started Jun 23 05:42:47 PM PDT 24
Finished Jun 23 05:42:57 PM PDT 24
Peak memory 200008 kb
Host smart-563beb7e-d4cc-4890-b1c1-92b05a94cf8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=519624187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.519624187
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.2858734518
Short name T1054
Test name
Test status
Simulation time 147342833459 ps
CPU time 39.85 seconds
Started Jun 23 05:42:45 PM PDT 24
Finished Jun 23 05:43:25 PM PDT 24
Peak memory 200756 kb
Host smart-cd169080-7f85-4d4a-9705-a053e24cddd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858734518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.2858734518
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.1609653510
Short name T707
Test name
Test status
Simulation time 1974104288 ps
CPU time 1.5 seconds
Started Jun 23 05:42:49 PM PDT 24
Finished Jun 23 05:42:51 PM PDT 24
Peak memory 196156 kb
Host smart-bb286369-c7c3-4b81-9c7d-3a4ba3898c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609653510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.1609653510
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.1340653321
Short name T349
Test name
Test status
Simulation time 5574563571 ps
CPU time 5.66 seconds
Started Jun 23 05:42:47 PM PDT 24
Finished Jun 23 05:42:53 PM PDT 24
Peak memory 200704 kb
Host smart-0fa9d990-2fda-47af-8ad0-33f8c76f9112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340653321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.1340653321
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.4162429493
Short name T227
Test name
Test status
Simulation time 348509629258 ps
CPU time 596.62 seconds
Started Jun 23 05:42:52 PM PDT 24
Finished Jun 23 05:52:49 PM PDT 24
Peak memory 200732 kb
Host smart-89bcaf9d-f3e3-406f-ae37-f4b4c6dfdf73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162429493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.4162429493
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.3999957870
Short name T974
Test name
Test status
Simulation time 114775142945 ps
CPU time 693.93 seconds
Started Jun 23 05:42:50 PM PDT 24
Finished Jun 23 05:54:24 PM PDT 24
Peak memory 217188 kb
Host smart-9f00b87e-c5b4-41c7-b3bd-4afc7244ee0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999957870 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.3999957870
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.110529775
Short name T738
Test name
Test status
Simulation time 8311231130 ps
CPU time 6 seconds
Started Jun 23 05:42:52 PM PDT 24
Finished Jun 23 05:42:58 PM PDT 24
Peak memory 200604 kb
Host smart-cddfac14-c5ff-4dd2-a47a-96180dfcbcec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110529775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.110529775
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.3530011015
Short name T937
Test name
Test status
Simulation time 21958572923 ps
CPU time 34.26 seconds
Started Jun 23 05:42:49 PM PDT 24
Finished Jun 23 05:43:24 PM PDT 24
Peak memory 200688 kb
Host smart-08157e78-d72e-47f2-acc9-af37636f9791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530011015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.3530011015
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.1040723926
Short name T797
Test name
Test status
Simulation time 13534775 ps
CPU time 0.56 seconds
Started Jun 23 05:43:08 PM PDT 24
Finished Jun 23 05:43:09 PM PDT 24
Peak memory 196088 kb
Host smart-3f2b983f-31e6-490f-b842-059dad82fa8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040723926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.1040723926
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.2493645093
Short name T831
Test name
Test status
Simulation time 148493855072 ps
CPU time 56.36 seconds
Started Jun 23 05:42:55 PM PDT 24
Finished Jun 23 05:43:52 PM PDT 24
Peak memory 200620 kb
Host smart-bc68a209-30f7-410d-b416-0ba899290fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493645093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.2493645093
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.3980885707
Short name T111
Test name
Test status
Simulation time 196339759956 ps
CPU time 65.72 seconds
Started Jun 23 05:43:07 PM PDT 24
Finished Jun 23 05:44:13 PM PDT 24
Peak memory 200716 kb
Host smart-8a023c60-bd91-4e2e-a610-9654ba690b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980885707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.3980885707
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.2276693125
Short name T1015
Test name
Test status
Simulation time 130285895284 ps
CPU time 40 seconds
Started Jun 23 05:42:58 PM PDT 24
Finished Jun 23 05:43:38 PM PDT 24
Peak memory 200756 kb
Host smart-7a826852-05ba-4fde-ba2a-4a020cce8515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276693125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.2276693125
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.2490925467
Short name T610
Test name
Test status
Simulation time 9958664170 ps
CPU time 19.15 seconds
Started Jun 23 05:43:00 PM PDT 24
Finished Jun 23 05:43:19 PM PDT 24
Peak memory 200704 kb
Host smart-466067ad-09bc-4acf-a2e4-a3aa7f763b7f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490925467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.2490925467
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.2375597792
Short name T38
Test name
Test status
Simulation time 102527697013 ps
CPU time 977.66 seconds
Started Jun 23 05:43:02 PM PDT 24
Finished Jun 23 05:59:20 PM PDT 24
Peak memory 200632 kb
Host smart-062261b7-85c5-43f2-bca7-70e57ce32598
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2375597792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.2375597792
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.2712028373
Short name T631
Test name
Test status
Simulation time 1584848118 ps
CPU time 1.96 seconds
Started Jun 23 05:43:01 PM PDT 24
Finished Jun 23 05:43:03 PM PDT 24
Peak memory 199304 kb
Host smart-55b73e52-9644-482b-8982-729e306cb2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712028373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.2712028373
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.567815944
Short name T316
Test name
Test status
Simulation time 46785140243 ps
CPU time 39.57 seconds
Started Jun 23 05:43:01 PM PDT 24
Finished Jun 23 05:43:41 PM PDT 24
Peak memory 200760 kb
Host smart-d50f0b3e-a7c4-4da3-a18e-7007bc612fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567815944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.567815944
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.3338427198
Short name T492
Test name
Test status
Simulation time 13489249742 ps
CPU time 60.95 seconds
Started Jun 23 05:43:01 PM PDT 24
Finished Jun 23 05:44:02 PM PDT 24
Peak memory 200732 kb
Host smart-70518dc6-fb46-46ee-b1a1-6a4f03b824ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3338427198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.3338427198
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.1190577886
Short name T1068
Test name
Test status
Simulation time 5496841898 ps
CPU time 46.31 seconds
Started Jun 23 05:42:57 PM PDT 24
Finished Jun 23 05:43:44 PM PDT 24
Peak memory 200004 kb
Host smart-4dcd04a2-84a3-4014-9614-441fc198d6b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1190577886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.1190577886
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.2406422208
Short name T571
Test name
Test status
Simulation time 265560288908 ps
CPU time 25.49 seconds
Started Jun 23 05:43:06 PM PDT 24
Finished Jun 23 05:43:32 PM PDT 24
Peak memory 200424 kb
Host smart-7d52e672-bca8-455e-bd57-a44122fe9f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406422208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.2406422208
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.1347646546
Short name T889
Test name
Test status
Simulation time 3612319683 ps
CPU time 2.26 seconds
Started Jun 23 05:43:02 PM PDT 24
Finished Jun 23 05:43:04 PM PDT 24
Peak memory 197456 kb
Host smart-c3fb9682-a39e-44fc-82fc-93fc832b9479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347646546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.1347646546
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.2258596350
Short name T494
Test name
Test status
Simulation time 252140843 ps
CPU time 1.16 seconds
Started Jun 23 05:42:53 PM PDT 24
Finished Jun 23 05:42:55 PM PDT 24
Peak memory 200152 kb
Host smart-e666c899-fa6f-4dec-b567-7b3915c0e1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258596350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.2258596350
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.2890993611
Short name T422
Test name
Test status
Simulation time 131101896632 ps
CPU time 157.43 seconds
Started Jun 23 05:43:14 PM PDT 24
Finished Jun 23 05:45:52 PM PDT 24
Peak memory 200728 kb
Host smart-eb66e872-9a3b-480e-a26f-a1d80a2fac2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890993611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.2890993611
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.3189144831
Short name T596
Test name
Test status
Simulation time 1893618849 ps
CPU time 2.36 seconds
Started Jun 23 05:43:02 PM PDT 24
Finished Jun 23 05:43:05 PM PDT 24
Peak memory 199528 kb
Host smart-e99e6bdd-86bf-4e2b-865e-9f04ccbe4ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189144831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.3189144831
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.334626169
Short name T658
Test name
Test status
Simulation time 54880891721 ps
CPU time 74.97 seconds
Started Jun 23 05:42:56 PM PDT 24
Finished Jun 23 05:44:11 PM PDT 24
Peak memory 200752 kb
Host smart-606823fe-16c6-44f9-a0fe-b1a9be90d327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334626169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.334626169
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.3089196894
Short name T994
Test name
Test status
Simulation time 35494227 ps
CPU time 0.53 seconds
Started Jun 23 05:40:04 PM PDT 24
Finished Jun 23 05:40:04 PM PDT 24
Peak memory 195280 kb
Host smart-888ec418-19b1-4ef6-b003-9f6515a27e87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089196894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.3089196894
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.1375438176
Short name T862
Test name
Test status
Simulation time 34780923473 ps
CPU time 15.36 seconds
Started Jun 23 05:39:59 PM PDT 24
Finished Jun 23 05:40:15 PM PDT 24
Peak memory 200696 kb
Host smart-c40def3f-dbcb-43d6-9a64-690d63e28dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375438176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.1375438176
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.111320618
Short name T231
Test name
Test status
Simulation time 92183113883 ps
CPU time 129.43 seconds
Started Jun 23 05:40:03 PM PDT 24
Finished Jun 23 05:42:13 PM PDT 24
Peak memory 200696 kb
Host smart-248c9464-4758-4f15-bb99-2f6fa1983ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111320618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.111320618
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.3712951350
Short name T469
Test name
Test status
Simulation time 84773589989 ps
CPU time 84.82 seconds
Started Jun 23 05:40:01 PM PDT 24
Finished Jun 23 05:41:26 PM PDT 24
Peak memory 200732 kb
Host smart-d11a27c9-99ce-4d2b-ab5a-66469325a804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712951350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.3712951350
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.2913196781
Short name T626
Test name
Test status
Simulation time 79139477380 ps
CPU time 31.91 seconds
Started Jun 23 05:39:59 PM PDT 24
Finished Jun 23 05:40:32 PM PDT 24
Peak memory 200620 kb
Host smart-dcb68fbb-8e20-432d-ae0f-3d2cc6560178
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913196781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.2913196781
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.4054131640
Short name T607
Test name
Test status
Simulation time 109980224684 ps
CPU time 314.56 seconds
Started Jun 23 05:40:02 PM PDT 24
Finished Jun 23 05:45:17 PM PDT 24
Peak memory 200736 kb
Host smart-cb5926b8-04e3-4a55-aa4a-22e89d07da44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4054131640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.4054131640
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.3546111526
Short name T836
Test name
Test status
Simulation time 8995176500 ps
CPU time 24.74 seconds
Started Jun 23 05:39:58 PM PDT 24
Finished Jun 23 05:40:23 PM PDT 24
Peak memory 199892 kb
Host smart-9aefcf0d-9668-4534-8b89-494495689cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546111526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.3546111526
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_perf.3947954718
Short name T907
Test name
Test status
Simulation time 26112937493 ps
CPU time 136.53 seconds
Started Jun 23 05:40:02 PM PDT 24
Finished Jun 23 05:42:19 PM PDT 24
Peak memory 200764 kb
Host smart-ad59e09b-204f-4150-b9ac-23146af96f3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3947954718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.3947954718
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.2640010626
Short name T462
Test name
Test status
Simulation time 7161353321 ps
CPU time 62.28 seconds
Started Jun 23 05:39:59 PM PDT 24
Finished Jun 23 05:41:01 PM PDT 24
Peak memory 198912 kb
Host smart-98b7d34e-87f0-431d-b9fd-c0abd73427c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2640010626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.2640010626
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.2156801646
Short name T1085
Test name
Test status
Simulation time 45806841699 ps
CPU time 77.65 seconds
Started Jun 23 05:40:00 PM PDT 24
Finished Jun 23 05:41:18 PM PDT 24
Peak memory 200752 kb
Host smart-0ccd6fcc-fb21-4234-8b92-ad90f12235a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156801646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2156801646
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.860564724
Short name T426
Test name
Test status
Simulation time 3464405767 ps
CPU time 5.72 seconds
Started Jun 23 05:40:02 PM PDT 24
Finished Jun 23 05:40:08 PM PDT 24
Peak memory 197016 kb
Host smart-464c40b2-3539-4ec2-9503-5963b4dbfb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860564724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.860564724
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.236429756
Short name T75
Test name
Test status
Simulation time 248578174 ps
CPU time 0.85 seconds
Started Jun 23 05:40:06 PM PDT 24
Finished Jun 23 05:40:07 PM PDT 24
Peak memory 219084 kb
Host smart-5cc6ec01-7bf2-4fe6-921d-af331896126e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236429756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.236429756
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.1685629830
Short name T370
Test name
Test status
Simulation time 5683917760 ps
CPU time 4.26 seconds
Started Jun 23 05:39:58 PM PDT 24
Finished Jun 23 05:40:03 PM PDT 24
Peak memory 200476 kb
Host smart-65de64f2-74c6-47b8-a7de-235795adc8e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685629830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.1685629830
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.836424414
Short name T643
Test name
Test status
Simulation time 121434856398 ps
CPU time 225.66 seconds
Started Jun 23 05:40:05 PM PDT 24
Finished Jun 23 05:43:51 PM PDT 24
Peak memory 200748 kb
Host smart-ec69c319-ea06-4cf3-adfc-0143fc5052d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836424414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.836424414
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.3013778852
Short name T716
Test name
Test status
Simulation time 828471605 ps
CPU time 3.1 seconds
Started Jun 23 05:39:59 PM PDT 24
Finished Jun 23 05:40:02 PM PDT 24
Peak memory 199120 kb
Host smart-4b786299-ba89-4129-9c48-2f23c97c7f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013778852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.3013778852
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.1006048681
Short name T237
Test name
Test status
Simulation time 17919079880 ps
CPU time 29.97 seconds
Started Jun 23 05:39:57 PM PDT 24
Finished Jun 23 05:40:27 PM PDT 24
Peak memory 200648 kb
Host smart-2df13114-2676-4310-845d-87ceff4c3fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006048681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.1006048681
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.410220433
Short name T943
Test name
Test status
Simulation time 39951013 ps
CPU time 0.55 seconds
Started Jun 23 05:43:06 PM PDT 24
Finished Jun 23 05:43:07 PM PDT 24
Peak memory 196040 kb
Host smart-3021fa5c-ca0d-4399-a1b0-567a594823b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410220433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.410220433
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.2746158840
Short name T458
Test name
Test status
Simulation time 235322606459 ps
CPU time 32.39 seconds
Started Jun 23 05:43:10 PM PDT 24
Finished Jun 23 05:43:43 PM PDT 24
Peak memory 200804 kb
Host smart-3a9857a4-1191-4d26-a5dc-f86eb862b614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746158840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.2746158840
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.3087315386
Short name T356
Test name
Test status
Simulation time 26179636327 ps
CPU time 37.35 seconds
Started Jun 23 05:43:07 PM PDT 24
Finished Jun 23 05:43:45 PM PDT 24
Peak memory 200756 kb
Host smart-b0579f2f-4250-4a3f-b823-0704339dd4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087315386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.3087315386
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.1698777977
Short name T381
Test name
Test status
Simulation time 14657973233 ps
CPU time 25.94 seconds
Started Jun 23 05:43:06 PM PDT 24
Finished Jun 23 05:43:33 PM PDT 24
Peak memory 200696 kb
Host smart-9791a955-b806-48eb-af63-95dc89cced30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698777977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.1698777977
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.3713820324
Short name T701
Test name
Test status
Simulation time 237270789802 ps
CPU time 534.83 seconds
Started Jun 23 05:43:14 PM PDT 24
Finished Jun 23 05:52:09 PM PDT 24
Peak memory 200460 kb
Host smart-7b54970d-4a5b-4c83-8866-c368dae6d429
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713820324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.3713820324
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.2421237226
Short name T835
Test name
Test status
Simulation time 130310332252 ps
CPU time 524.7 seconds
Started Jun 23 05:43:08 PM PDT 24
Finished Jun 23 05:51:53 PM PDT 24
Peak memory 200648 kb
Host smart-b6ed565c-1dca-4592-93c8-1872ab9a75f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2421237226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.2421237226
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.3548661816
Short name T402
Test name
Test status
Simulation time 4686734220 ps
CPU time 7.06 seconds
Started Jun 23 05:43:11 PM PDT 24
Finished Jun 23 05:43:19 PM PDT 24
Peak memory 200788 kb
Host smart-5aaf2a67-9831-4fd1-8482-930951b45466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548661816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.3548661816
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_perf.1468262233
Short name T468
Test name
Test status
Simulation time 25009739449 ps
CPU time 285.98 seconds
Started Jun 23 05:43:07 PM PDT 24
Finished Jun 23 05:47:54 PM PDT 24
Peak memory 200664 kb
Host smart-50cb636a-2c88-45fb-a55a-2660360bd073
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1468262233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.1468262233
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.1674664523
Short name T684
Test name
Test status
Simulation time 1376384198 ps
CPU time 5.9 seconds
Started Jun 23 05:43:03 PM PDT 24
Finished Jun 23 05:43:09 PM PDT 24
Peak memory 198840 kb
Host smart-ff84b572-f28f-430f-941c-e718f408e195
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1674664523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.1674664523
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.251729651
Short name T878
Test name
Test status
Simulation time 89020252968 ps
CPU time 125.08 seconds
Started Jun 23 05:43:11 PM PDT 24
Finished Jun 23 05:45:17 PM PDT 24
Peak memory 200900 kb
Host smart-c24fb5e0-d257-4600-a2a0-3e514ca4daef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251729651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.251729651
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.779330292
Short name T1097
Test name
Test status
Simulation time 6909659965 ps
CPU time 2.95 seconds
Started Jun 23 05:43:10 PM PDT 24
Finished Jun 23 05:43:14 PM PDT 24
Peak memory 196912 kb
Host smart-052dd714-1c7b-4f23-84c4-7b3028bcd95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779330292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.779330292
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.3195587908
Short name T507
Test name
Test status
Simulation time 921563027 ps
CPU time 1.6 seconds
Started Jun 23 05:43:04 PM PDT 24
Finished Jun 23 05:43:06 PM PDT 24
Peak memory 200288 kb
Host smart-d760ac90-4a63-4578-a3c8-ebaa9cec606c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195587908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.3195587908
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.14843339
Short name T77
Test name
Test status
Simulation time 37488415411 ps
CPU time 85.71 seconds
Started Jun 23 05:43:05 PM PDT 24
Finished Jun 23 05:44:32 PM PDT 24
Peak memory 200756 kb
Host smart-a33c977e-d825-441f-b210-d88c58f26143
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14843339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.14843339
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.765062742
Short name T482
Test name
Test status
Simulation time 222127694 ps
CPU time 1.12 seconds
Started Jun 23 05:43:05 PM PDT 24
Finished Jun 23 05:43:07 PM PDT 24
Peak memory 198484 kb
Host smart-f0548be5-608d-49da-9234-ad20f63677f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765062742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.765062742
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.1048863991
Short name T788
Test name
Test status
Simulation time 67251833393 ps
CPU time 116.7 seconds
Started Jun 23 05:43:14 PM PDT 24
Finished Jun 23 05:45:11 PM PDT 24
Peak memory 200756 kb
Host smart-7b5e3d60-69e4-4936-acd0-6dc5d0a43c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048863991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.1048863991
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.2897930411
Short name T920
Test name
Test status
Simulation time 22466420 ps
CPU time 0.57 seconds
Started Jun 23 05:43:15 PM PDT 24
Finished Jun 23 05:43:16 PM PDT 24
Peak memory 196096 kb
Host smart-7255b3be-7319-487d-97c6-745010b83769
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897930411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.2897930411
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.2449824995
Short name T600
Test name
Test status
Simulation time 17828629668 ps
CPU time 34.64 seconds
Started Jun 23 05:43:08 PM PDT 24
Finished Jun 23 05:43:43 PM PDT 24
Peak memory 200688 kb
Host smart-0cbb8ade-4483-4e54-891e-7b622607f639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449824995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.2449824995
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.3127447702
Short name T452
Test name
Test status
Simulation time 36797047532 ps
CPU time 60.78 seconds
Started Jun 23 05:43:11 PM PDT 24
Finished Jun 23 05:44:12 PM PDT 24
Peak memory 200656 kb
Host smart-1776ff00-9ff2-4f9f-8e32-7dba8aee9caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127447702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.3127447702
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.4166881056
Short name T177
Test name
Test status
Simulation time 152510592984 ps
CPU time 232.03 seconds
Started Jun 23 05:43:12 PM PDT 24
Finished Jun 23 05:47:05 PM PDT 24
Peak memory 200756 kb
Host smart-210bee10-4e9b-4865-b29c-726521177e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166881056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.4166881056
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.2221323931
Short name T489
Test name
Test status
Simulation time 71216810725 ps
CPU time 128.45 seconds
Started Jun 23 05:43:09 PM PDT 24
Finished Jun 23 05:45:18 PM PDT 24
Peak memory 200656 kb
Host smart-733bc7cd-84bf-4ed3-9ea5-c471258f1981
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221323931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.2221323931
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.2303983073
Short name T1048
Test name
Test status
Simulation time 67043959311 ps
CPU time 107.4 seconds
Started Jun 23 05:43:19 PM PDT 24
Finished Jun 23 05:45:07 PM PDT 24
Peak memory 200632 kb
Host smart-0b746d2c-f784-4e18-9da6-d7fa6631acca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2303983073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.2303983073
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.1786847554
Short name T762
Test name
Test status
Simulation time 4307066177 ps
CPU time 7.4 seconds
Started Jun 23 05:43:10 PM PDT 24
Finished Jun 23 05:43:18 PM PDT 24
Peak memory 198604 kb
Host smart-c7c99965-ddea-476e-bb10-8869031fe0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786847554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.1786847554
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_perf.1632457134
Short name T534
Test name
Test status
Simulation time 12887198501 ps
CPU time 254.58 seconds
Started Jun 23 05:43:11 PM PDT 24
Finished Jun 23 05:47:26 PM PDT 24
Peak memory 200640 kb
Host smart-67c23ecd-e345-4885-8f2c-4187760bc453
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1632457134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.1632457134
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.1504567235
Short name T333
Test name
Test status
Simulation time 6785460435 ps
CPU time 14.57 seconds
Started Jun 23 05:43:08 PM PDT 24
Finished Jun 23 05:43:23 PM PDT 24
Peak memory 200104 kb
Host smart-d9473f90-848d-4ae0-8f49-61714a6e1e69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1504567235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.1504567235
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.640389
Short name T965
Test name
Test status
Simulation time 138779953980 ps
CPU time 75.1 seconds
Started Jun 23 05:43:11 PM PDT 24
Finished Jun 23 05:44:26 PM PDT 24
Peak memory 200588 kb
Host smart-ef9dbfa1-44a4-40dd-a9a2-542bed308b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.640389
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.908577019
Short name T1011
Test name
Test status
Simulation time 33483236582 ps
CPU time 13.39 seconds
Started Jun 23 05:43:10 PM PDT 24
Finished Jun 23 05:43:23 PM PDT 24
Peak memory 196920 kb
Host smart-cac9cc64-4dfb-4124-b78a-abe331b24d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908577019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.908577019
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.829296768
Short name T232
Test name
Test status
Simulation time 5370303209 ps
CPU time 7.7 seconds
Started Jun 23 05:43:10 PM PDT 24
Finished Jun 23 05:43:19 PM PDT 24
Peak memory 200284 kb
Host smart-e980038d-337a-4b6c-9aaa-9e877f8b4ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829296768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.829296768
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.3014774649
Short name T826
Test name
Test status
Simulation time 204685511718 ps
CPU time 438.7 seconds
Started Jun 23 05:43:19 PM PDT 24
Finished Jun 23 05:50:38 PM PDT 24
Peak memory 200736 kb
Host smart-ee824214-817e-46df-a375-6a8121ac0e29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014774649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.3014774649
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.3950080431
Short name T303
Test name
Test status
Simulation time 21346748276 ps
CPU time 472 seconds
Started Jun 23 05:43:20 PM PDT 24
Finished Jun 23 05:51:12 PM PDT 24
Peak memory 216360 kb
Host smart-e925f7d9-889c-425b-a7f2-9ef39d66b1b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950080431 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.3950080431
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.869493006
Short name T336
Test name
Test status
Simulation time 1767741661 ps
CPU time 1.77 seconds
Started Jun 23 05:43:12 PM PDT 24
Finished Jun 23 05:43:14 PM PDT 24
Peak memory 199148 kb
Host smart-063fcb32-9004-4889-9760-092bcb04c29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869493006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.869493006
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.3348370646
Short name T293
Test name
Test status
Simulation time 62849664430 ps
CPU time 60.23 seconds
Started Jun 23 05:43:12 PM PDT 24
Finished Jun 23 05:44:13 PM PDT 24
Peak memory 200792 kb
Host smart-4667f204-9138-4256-b306-8cdd19eee3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348370646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.3348370646
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.2619371221
Short name T639
Test name
Test status
Simulation time 11849530 ps
CPU time 0.57 seconds
Started Jun 23 05:43:18 PM PDT 24
Finished Jun 23 05:43:19 PM PDT 24
Peak memory 196036 kb
Host smart-36c8da78-1dc2-4752-968d-6272b3602588
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619371221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.2619371221
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.2506210275
Short name T756
Test name
Test status
Simulation time 53821194518 ps
CPU time 49.05 seconds
Started Jun 23 05:43:16 PM PDT 24
Finished Jun 23 05:44:06 PM PDT 24
Peak memory 200784 kb
Host smart-505db129-20d0-4096-aae7-16d076893da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506210275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.2506210275
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.1063828641
Short name T582
Test name
Test status
Simulation time 71125058640 ps
CPU time 99.88 seconds
Started Jun 23 05:43:17 PM PDT 24
Finished Jun 23 05:44:58 PM PDT 24
Peak memory 200840 kb
Host smart-92cca160-da40-4f4c-bd6b-8f09f4b51ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063828641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.1063828641
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_intr.2121579999
Short name T894
Test name
Test status
Simulation time 199255239939 ps
CPU time 258.95 seconds
Started Jun 23 05:43:17 PM PDT 24
Finished Jun 23 05:47:36 PM PDT 24
Peak memory 200600 kb
Host smart-cfed1147-08ae-4c15-b5d3-6de01f87a254
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121579999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.2121579999
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.2988256389
Short name T676
Test name
Test status
Simulation time 107978969991 ps
CPU time 1172.79 seconds
Started Jun 23 05:43:21 PM PDT 24
Finished Jun 23 06:02:54 PM PDT 24
Peak memory 200684 kb
Host smart-e00cf59e-b9e1-4bd7-abf3-04c2b93d4da8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2988256389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.2988256389
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.1460350458
Short name T504
Test name
Test status
Simulation time 76235834 ps
CPU time 0.75 seconds
Started Jun 23 05:43:15 PM PDT 24
Finished Jun 23 05:43:16 PM PDT 24
Peak memory 196652 kb
Host smart-40f3d3b7-ed12-41cc-80ab-58222f04f98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460350458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.1460350458
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_perf.400229948
Short name T429
Test name
Test status
Simulation time 18737069860 ps
CPU time 110.23 seconds
Started Jun 23 05:43:21 PM PDT 24
Finished Jun 23 05:45:11 PM PDT 24
Peak memory 200752 kb
Host smart-8f22c740-6b32-46b4-a88a-4325045450d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=400229948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.400229948
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.1646156862
Short name T976
Test name
Test status
Simulation time 7470088723 ps
CPU time 33.18 seconds
Started Jun 23 05:43:16 PM PDT 24
Finished Jun 23 05:43:50 PM PDT 24
Peak memory 198916 kb
Host smart-f566fe22-6762-4146-bd21-4c0aab672e02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1646156862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.1646156862
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.2017108911
Short name T698
Test name
Test status
Simulation time 46150129072 ps
CPU time 15.94 seconds
Started Jun 23 05:43:14 PM PDT 24
Finished Jun 23 05:43:30 PM PDT 24
Peak memory 200748 kb
Host smart-d640f555-569f-43c8-a238-cdcb8b49979b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017108911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.2017108911
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.3091050386
Short name T1045
Test name
Test status
Simulation time 701449179 ps
CPU time 0.95 seconds
Started Jun 23 05:43:17 PM PDT 24
Finished Jun 23 05:43:18 PM PDT 24
Peak memory 196156 kb
Host smart-a54de22a-b95a-47ab-83b8-fab0d6322557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091050386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.3091050386
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.3867918215
Short name T459
Test name
Test status
Simulation time 6051551216 ps
CPU time 9.85 seconds
Started Jun 23 05:43:16 PM PDT 24
Finished Jun 23 05:43:26 PM PDT 24
Peak memory 200752 kb
Host smart-7c65f1b5-9d9c-4bee-8a70-82368092dc52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867918215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.3867918215
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.3998725938
Short name T905
Test name
Test status
Simulation time 900078200 ps
CPU time 2.56 seconds
Started Jun 23 05:43:19 PM PDT 24
Finished Jun 23 05:43:22 PM PDT 24
Peak memory 198948 kb
Host smart-972190a2-711c-4930-aeb5-0feb4f1d3e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998725938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.3998725938
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.2193894401
Short name T1059
Test name
Test status
Simulation time 96914419171 ps
CPU time 195.71 seconds
Started Jun 23 05:43:20 PM PDT 24
Finished Jun 23 05:46:36 PM PDT 24
Peak memory 200764 kb
Host smart-da3bf3e2-7ec2-4994-8b72-c6d81bd0ddfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193894401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.2193894401
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.564182374
Short name T553
Test name
Test status
Simulation time 18606739 ps
CPU time 0.59 seconds
Started Jun 23 05:43:26 PM PDT 24
Finished Jun 23 05:43:27 PM PDT 24
Peak memory 196036 kb
Host smart-b218abcf-eade-45bd-9a1f-08dba7092d15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564182374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.564182374
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.3985078026
Short name T288
Test name
Test status
Simulation time 43639287362 ps
CPU time 66.86 seconds
Started Jun 23 05:43:21 PM PDT 24
Finished Jun 23 05:44:28 PM PDT 24
Peak memory 200688 kb
Host smart-9918a1f2-f4d0-49e8-b2bc-a4b4ee208e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985078026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.3985078026
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.1536260438
Short name T300
Test name
Test status
Simulation time 86520699052 ps
CPU time 147.28 seconds
Started Jun 23 05:43:18 PM PDT 24
Finished Jun 23 05:45:45 PM PDT 24
Peak memory 200664 kb
Host smart-f05c2a96-13eb-444e-8e94-73027e600283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536260438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.1536260438
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.3920214698
Short name T759
Test name
Test status
Simulation time 50424401377 ps
CPU time 14.75 seconds
Started Jun 23 05:43:18 PM PDT 24
Finished Jun 23 05:43:33 PM PDT 24
Peak memory 200648 kb
Host smart-440b7e55-37f2-47f0-8b44-e12f012216a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920214698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.3920214698
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.207332360
Short name T301
Test name
Test status
Simulation time 20656421669 ps
CPU time 31.28 seconds
Started Jun 23 05:43:25 PM PDT 24
Finished Jun 23 05:43:56 PM PDT 24
Peak memory 198212 kb
Host smart-c40e4591-ac13-4e25-9ce6-480d7ccafdc8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207332360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.207332360
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.519624714
Short name T567
Test name
Test status
Simulation time 72114379169 ps
CPU time 148.69 seconds
Started Jun 23 05:43:25 PM PDT 24
Finished Jun 23 05:45:54 PM PDT 24
Peak memory 200704 kb
Host smart-582fe53a-8270-4edb-b411-c63abf3e2854
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=519624714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.519624714
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.969400809
Short name T20
Test name
Test status
Simulation time 6868751737 ps
CPU time 16.45 seconds
Started Jun 23 05:43:25 PM PDT 24
Finished Jun 23 05:43:42 PM PDT 24
Peak memory 200268 kb
Host smart-0f8bf990-bff7-45a0-a731-ec6ec6683d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969400809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.969400809
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_perf.435775392
Short name T1075
Test name
Test status
Simulation time 24495660344 ps
CPU time 307.12 seconds
Started Jun 23 05:43:27 PM PDT 24
Finished Jun 23 05:48:34 PM PDT 24
Peak memory 200704 kb
Host smart-23c09fd2-1741-4c50-9a91-bb6a1667f240
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=435775392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.435775392
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.1490187932
Short name T496
Test name
Test status
Simulation time 3704239135 ps
CPU time 6.7 seconds
Started Jun 23 05:43:19 PM PDT 24
Finished Jun 23 05:43:26 PM PDT 24
Peak memory 199716 kb
Host smart-804436cc-0bd0-41ca-830b-a3bba0ea7152
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1490187932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.1490187932
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.350625953
Short name T687
Test name
Test status
Simulation time 545210899 ps
CPU time 1.12 seconds
Started Jun 23 05:43:29 PM PDT 24
Finished Jun 23 05:43:31 PM PDT 24
Peak memory 196188 kb
Host smart-2f9714cf-ca94-486e-9437-37bbbb4ccaa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350625953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.350625953
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.1818667053
Short name T270
Test name
Test status
Simulation time 699688535 ps
CPU time 2.94 seconds
Started Jun 23 05:43:20 PM PDT 24
Finished Jun 23 05:43:23 PM PDT 24
Peak memory 200600 kb
Host smart-b758e781-d885-44f1-8b88-bfc2b597fc74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818667053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.1818667053
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.1081155566
Short name T1093
Test name
Test status
Simulation time 180174414513 ps
CPU time 170.66 seconds
Started Jun 23 05:43:28 PM PDT 24
Finished Jun 23 05:46:19 PM PDT 24
Peak memory 200844 kb
Host smart-6dc2ab56-7806-44e9-845b-566ae80737d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081155566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.1081155566
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.2319807667
Short name T278
Test name
Test status
Simulation time 1738462601 ps
CPU time 2.37 seconds
Started Jun 23 05:43:26 PM PDT 24
Finished Jun 23 05:43:29 PM PDT 24
Peak memory 199512 kb
Host smart-0cf6d46c-97d4-448b-b5a3-8f87c1885ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319807667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.2319807667
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.3249676849
Short name T997
Test name
Test status
Simulation time 34653759601 ps
CPU time 52.38 seconds
Started Jun 23 05:43:20 PM PDT 24
Finished Jun 23 05:44:13 PM PDT 24
Peak memory 200704 kb
Host smart-4cc11676-a1d1-4d77-b502-bfbc149345d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249676849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.3249676849
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.1066205767
Short name T786
Test name
Test status
Simulation time 31754559 ps
CPU time 0.53 seconds
Started Jun 23 05:43:29 PM PDT 24
Finished Jun 23 05:43:30 PM PDT 24
Peak memory 195076 kb
Host smart-f51a4410-1270-4308-a8f3-676bb15c599a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066205767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.1066205767
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.390305101
Short name T1036
Test name
Test status
Simulation time 22713895165 ps
CPU time 18.97 seconds
Started Jun 23 05:43:28 PM PDT 24
Finished Jun 23 05:43:47 PM PDT 24
Peak memory 200640 kb
Host smart-9a4b9306-bbba-4f2e-aba3-93365f5f6efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390305101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.390305101
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.3319342858
Short name T119
Test name
Test status
Simulation time 183369426698 ps
CPU time 203.1 seconds
Started Jun 23 05:43:27 PM PDT 24
Finished Jun 23 05:46:50 PM PDT 24
Peak memory 200600 kb
Host smart-35d76fdb-db50-466a-b9f7-f8c8b24b3941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319342858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.3319342858
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.2584733208
Short name T1051
Test name
Test status
Simulation time 14390467507 ps
CPU time 21.94 seconds
Started Jun 23 05:43:27 PM PDT 24
Finished Jun 23 05:43:49 PM PDT 24
Peak memory 200652 kb
Host smart-f4e1bb78-48ad-42e0-aed6-3e0ea925ac08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584733208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.2584733208
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.2010495887
Short name T992
Test name
Test status
Simulation time 192516609754 ps
CPU time 245.31 seconds
Started Jun 23 05:43:24 PM PDT 24
Finished Jun 23 05:47:30 PM PDT 24
Peak memory 198012 kb
Host smart-3fdf3a77-f199-4e33-b24e-711eec118be6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010495887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.2010495887
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.1361157356
Short name T240
Test name
Test status
Simulation time 63145146861 ps
CPU time 431.21 seconds
Started Jun 23 05:43:24 PM PDT 24
Finished Jun 23 05:50:36 PM PDT 24
Peak memory 200740 kb
Host smart-33b0cb9d-293c-4690-9981-5faea8be57fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1361157356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.1361157356
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.1045550006
Short name T685
Test name
Test status
Simulation time 10640557541 ps
CPU time 7.57 seconds
Started Jun 23 05:43:27 PM PDT 24
Finished Jun 23 05:43:35 PM PDT 24
Peak memory 199688 kb
Host smart-89c0b137-dd6a-4097-9d7c-29b5a5118a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045550006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.1045550006
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_perf.787939364
Short name T252
Test name
Test status
Simulation time 11894341850 ps
CPU time 649.57 seconds
Started Jun 23 05:43:27 PM PDT 24
Finished Jun 23 05:54:17 PM PDT 24
Peak memory 200676 kb
Host smart-8e10a13d-49e4-4362-9ccc-c278b5316c25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=787939364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.787939364
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.2168365001
Short name T387
Test name
Test status
Simulation time 3274741042 ps
CPU time 9.21 seconds
Started Jun 23 05:43:28 PM PDT 24
Finished Jun 23 05:43:38 PM PDT 24
Peak memory 199100 kb
Host smart-2266828c-bc31-41ba-a1fb-1853d4850ad2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2168365001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.2168365001
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.3203524257
Short name T170
Test name
Test status
Simulation time 160485879495 ps
CPU time 247.49 seconds
Started Jun 23 05:43:29 PM PDT 24
Finished Jun 23 05:47:37 PM PDT 24
Peak memory 200760 kb
Host smart-d2d7a976-1a4f-415c-bf53-d1321a05bc73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203524257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.3203524257
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.1666370796
Short name T973
Test name
Test status
Simulation time 35993452903 ps
CPU time 8.78 seconds
Started Jun 23 05:43:27 PM PDT 24
Finished Jun 23 05:43:36 PM PDT 24
Peak memory 196664 kb
Host smart-ff2bb680-8eab-4385-9cd2-639d01dd1965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666370796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.1666370796
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.620774471
Short name T783
Test name
Test status
Simulation time 5549307121 ps
CPU time 18.69 seconds
Started Jun 23 05:43:26 PM PDT 24
Finished Jun 23 05:43:45 PM PDT 24
Peak memory 200548 kb
Host smart-853e587d-6f12-4588-ac8a-c381a824cf7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620774471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.620774471
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.3541098383
Short name T784
Test name
Test status
Simulation time 376766767794 ps
CPU time 314.87 seconds
Started Jun 23 05:43:28 PM PDT 24
Finished Jun 23 05:48:43 PM PDT 24
Peak memory 200676 kb
Host smart-6e83422c-4322-49a2-bcbd-3cc626ae6757
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541098383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.3541098383
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.1758294076
Short name T17
Test name
Test status
Simulation time 6278058288 ps
CPU time 19.27 seconds
Started Jun 23 05:43:29 PM PDT 24
Finished Jun 23 05:43:49 PM PDT 24
Peak memory 200708 kb
Host smart-73e1d79f-f507-46ad-94ad-3f4d594372a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758294076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.1758294076
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.1968744176
Short name T545
Test name
Test status
Simulation time 56037782854 ps
CPU time 41.01 seconds
Started Jun 23 05:43:29 PM PDT 24
Finished Jun 23 05:44:10 PM PDT 24
Peak memory 199712 kb
Host smart-cfbd6b28-0d7a-47c9-a181-cc81b0d93344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968744176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.1968744176
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.1419783122
Short name T1030
Test name
Test status
Simulation time 33526563 ps
CPU time 0.56 seconds
Started Jun 23 05:43:36 PM PDT 24
Finished Jun 23 05:43:37 PM PDT 24
Peak memory 196096 kb
Host smart-ec0717ea-7f3c-4a2c-83f8-2b1ed2fbde34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419783122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.1419783122
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.231270346
Short name T914
Test name
Test status
Simulation time 243115752590 ps
CPU time 153.99 seconds
Started Jun 23 05:43:38 PM PDT 24
Finished Jun 23 05:46:13 PM PDT 24
Peak memory 200716 kb
Host smart-985573a9-86a9-4a89-ae49-0ea716736978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231270346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.231270346
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.3402023480
Short name T37
Test name
Test status
Simulation time 29861844806 ps
CPU time 46.41 seconds
Started Jun 23 05:43:37 PM PDT 24
Finished Jun 23 05:44:24 PM PDT 24
Peak memory 200768 kb
Host smart-1585d425-0e25-44d4-8655-8a961c6a50be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402023480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.3402023480
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.4073105136
Short name T820
Test name
Test status
Simulation time 267949158929 ps
CPU time 76.18 seconds
Started Jun 23 05:43:29 PM PDT 24
Finished Jun 23 05:44:45 PM PDT 24
Peak memory 200736 kb
Host smart-517a2075-75e2-4c35-abdf-1352fc6233a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073105136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.4073105136
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.1758327745
Short name T450
Test name
Test status
Simulation time 3241782754 ps
CPU time 1.6 seconds
Started Jun 23 05:43:42 PM PDT 24
Finished Jun 23 05:43:44 PM PDT 24
Peak memory 200700 kb
Host smart-176b0241-c89d-475e-a7b6-95cadb7f7b60
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758327745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.1758327745
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.3534084024
Short name T703
Test name
Test status
Simulation time 136859629713 ps
CPU time 104.48 seconds
Started Jun 23 05:43:39 PM PDT 24
Finished Jun 23 05:45:24 PM PDT 24
Peak memory 200740 kb
Host smart-922716d7-cb8c-42d1-a37e-f178d0337c4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3534084024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.3534084024
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.1373012385
Short name T979
Test name
Test status
Simulation time 5969720577 ps
CPU time 3.67 seconds
Started Jun 23 05:43:39 PM PDT 24
Finished Jun 23 05:43:43 PM PDT 24
Peak memory 200152 kb
Host smart-5209ae27-9f6d-4159-a0f8-3e118bb5dc52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373012385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.1373012385
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_perf.3975627338
Short name T520
Test name
Test status
Simulation time 10118110053 ps
CPU time 598.22 seconds
Started Jun 23 05:43:30 PM PDT 24
Finished Jun 23 05:53:28 PM PDT 24
Peak memory 200724 kb
Host smart-976c64d9-9d0c-4d71-a687-4ad42b0e5ad4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3975627338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.3975627338
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.1377288034
Short name T613
Test name
Test status
Simulation time 1898112216 ps
CPU time 3.06 seconds
Started Jun 23 05:43:28 PM PDT 24
Finished Jun 23 05:43:32 PM PDT 24
Peak memory 198756 kb
Host smart-7a454b88-9037-40ef-870e-e379ce7e2a56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1377288034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.1377288034
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.1571926833
Short name T430
Test name
Test status
Simulation time 33079050693 ps
CPU time 13.95 seconds
Started Jun 23 05:43:33 PM PDT 24
Finished Jun 23 05:43:47 PM PDT 24
Peak memory 200652 kb
Host smart-f6f3973f-8e65-48d0-a465-631b5f866304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571926833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.1571926833
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.492379156
Short name T353
Test name
Test status
Simulation time 2260744940 ps
CPU time 1.44 seconds
Started Jun 23 05:43:39 PM PDT 24
Finished Jun 23 05:43:41 PM PDT 24
Peak memory 196392 kb
Host smart-32ae7e5f-d36c-497d-ba1d-a1ddd11d532e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492379156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.492379156
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.3627323120
Short name T1070
Test name
Test status
Simulation time 115672113 ps
CPU time 0.93 seconds
Started Jun 23 05:43:29 PM PDT 24
Finished Jun 23 05:43:30 PM PDT 24
Peak memory 198704 kb
Host smart-c8d93540-bf9f-4570-bdcd-ae0f17405639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627323120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.3627323120
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.3003706816
Short name T1090
Test name
Test status
Simulation time 75218495595 ps
CPU time 206.34 seconds
Started Jun 23 05:43:41 PM PDT 24
Finished Jun 23 05:47:08 PM PDT 24
Peak memory 216656 kb
Host smart-95a07beb-db43-477f-a9f1-54ef11dea1ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003706816 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.3003706816
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.3722241182
Short name T565
Test name
Test status
Simulation time 7293469559 ps
CPU time 8.85 seconds
Started Jun 23 05:43:37 PM PDT 24
Finished Jun 23 05:43:46 PM PDT 24
Peak memory 200008 kb
Host smart-3e357a88-ccc2-477c-a005-83eb8fa396db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722241182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.3722241182
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.2648646369
Short name T594
Test name
Test status
Simulation time 60888294782 ps
CPU time 17.22 seconds
Started Jun 23 05:43:26 PM PDT 24
Finished Jun 23 05:43:43 PM PDT 24
Peak memory 200708 kb
Host smart-0a835f64-06a0-407d-a628-5c0ddefd81a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648646369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.2648646369
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.491992923
Short name T624
Test name
Test status
Simulation time 13847075 ps
CPU time 0.54 seconds
Started Jun 23 05:43:37 PM PDT 24
Finished Jun 23 05:43:38 PM PDT 24
Peak memory 195540 kb
Host smart-0d7a13dd-e8eb-4dbd-9d1f-83eba4bdee9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491992923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.491992923
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.2900699845
Short name T446
Test name
Test status
Simulation time 61757625907 ps
CPU time 48.02 seconds
Started Jun 23 05:43:30 PM PDT 24
Finished Jun 23 05:44:18 PM PDT 24
Peak memory 200640 kb
Host smart-7f359d86-235c-4f92-97c8-95617dfac065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900699845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.2900699845
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.3411379015
Short name T299
Test name
Test status
Simulation time 17756809739 ps
CPU time 30.88 seconds
Started Jun 23 05:43:37 PM PDT 24
Finished Jun 23 05:44:08 PM PDT 24
Peak memory 200628 kb
Host smart-dbad654b-c96d-410d-933a-6437ec0cc375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411379015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.3411379015
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.3038025943
Short name T713
Test name
Test status
Simulation time 23200220372 ps
CPU time 39.16 seconds
Started Jun 23 05:43:39 PM PDT 24
Finished Jun 23 05:44:19 PM PDT 24
Peak memory 200744 kb
Host smart-664ad65b-3596-400f-bc2a-19124443b169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038025943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.3038025943
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.271942812
Short name T365
Test name
Test status
Simulation time 9661077323 ps
CPU time 7.21 seconds
Started Jun 23 05:43:37 PM PDT 24
Finished Jun 23 05:43:44 PM PDT 24
Peak memory 200704 kb
Host smart-ec9dde91-8a9d-4d0f-9a8d-3e3ec69d0046
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271942812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.271942812
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.3088806006
Short name T385
Test name
Test status
Simulation time 43003844706 ps
CPU time 333.5 seconds
Started Jun 23 05:43:38 PM PDT 24
Finished Jun 23 05:49:13 PM PDT 24
Peak memory 200740 kb
Host smart-44c8d341-2943-4bb7-8238-d1e5a978704f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3088806006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.3088806006
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.316608885
Short name T991
Test name
Test status
Simulation time 7147033784 ps
CPU time 8.99 seconds
Started Jun 23 05:43:36 PM PDT 24
Finished Jun 23 05:43:45 PM PDT 24
Peak memory 199824 kb
Host smart-c1a71fe7-e7ab-46b9-8667-eea52f4f1389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316608885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.316608885
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_perf.3188290668
Short name T975
Test name
Test status
Simulation time 12187213562 ps
CPU time 83.39 seconds
Started Jun 23 05:43:41 PM PDT 24
Finished Jun 23 05:45:05 PM PDT 24
Peak memory 200676 kb
Host smart-0b106934-5613-415a-8df6-3e6ebc0c9f79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3188290668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.3188290668
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.4155948403
Short name T514
Test name
Test status
Simulation time 5758931980 ps
CPU time 13.3 seconds
Started Jun 23 05:43:31 PM PDT 24
Finished Jun 23 05:43:45 PM PDT 24
Peak memory 199508 kb
Host smart-6a35df5b-0aa8-4f90-93fc-41b8ef9c5823
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4155948403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.4155948403
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.1578273629
Short name T510
Test name
Test status
Simulation time 73574266834 ps
CPU time 110.52 seconds
Started Jun 23 05:43:41 PM PDT 24
Finished Jun 23 05:45:33 PM PDT 24
Peak memory 200528 kb
Host smart-474783ba-0dbd-4ed7-a4f0-e8df1528000c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578273629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.1578273629
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.69427677
Short name T1088
Test name
Test status
Simulation time 5180413855 ps
CPU time 8.22 seconds
Started Jun 23 05:43:40 PM PDT 24
Finished Jun 23 05:43:49 PM PDT 24
Peak memory 196776 kb
Host smart-8092fbff-21bc-4bf0-912e-73b572720586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69427677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.69427677
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.3263989974
Short name T264
Test name
Test status
Simulation time 626939000 ps
CPU time 2.68 seconds
Started Jun 23 05:43:31 PM PDT 24
Finished Jun 23 05:43:34 PM PDT 24
Peak memory 200556 kb
Host smart-e50d3557-d1b0-438f-b249-424b34bf6ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263989974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.3263989974
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.3847254938
Short name T508
Test name
Test status
Simulation time 91735356810 ps
CPU time 229.17 seconds
Started Jun 23 05:43:38 PM PDT 24
Finished Jun 23 05:47:28 PM PDT 24
Peak memory 216284 kb
Host smart-edb14547-d46c-4e98-9fa2-09652c10844d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847254938 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.3847254938
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.2729121428
Short name T334
Test name
Test status
Simulation time 765741213 ps
CPU time 2.46 seconds
Started Jun 23 05:43:39 PM PDT 24
Finished Jun 23 05:43:42 PM PDT 24
Peak memory 199256 kb
Host smart-febe68b2-d6b9-4e85-afa1-744f8934c1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729121428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.2729121428
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.2181700619
Short name T622
Test name
Test status
Simulation time 54269265263 ps
CPU time 90.27 seconds
Started Jun 23 05:43:28 PM PDT 24
Finished Jun 23 05:44:58 PM PDT 24
Peak memory 200784 kb
Host smart-a7c3c600-0de0-48cb-babe-745b528922c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181700619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.2181700619
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.2976589028
Short name T924
Test name
Test status
Simulation time 28279419 ps
CPU time 0.56 seconds
Started Jun 23 05:43:41 PM PDT 24
Finished Jun 23 05:43:43 PM PDT 24
Peak memory 196096 kb
Host smart-070f4cc5-fb1a-43cc-9018-3296071f2f82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976589028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.2976589028
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.1209089913
Short name T90
Test name
Test status
Simulation time 138369839464 ps
CPU time 34.23 seconds
Started Jun 23 05:43:38 PM PDT 24
Finished Jun 23 05:44:13 PM PDT 24
Peak memory 200700 kb
Host smart-b5982d06-cf77-4a3f-b39a-bc0f97a116ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209089913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.1209089913
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.1734550518
Short name T97
Test name
Test status
Simulation time 58614397554 ps
CPU time 28.47 seconds
Started Jun 23 05:43:41 PM PDT 24
Finished Jun 23 05:44:11 PM PDT 24
Peak memory 200724 kb
Host smart-ecb2f7cb-6cb0-40cd-a1c0-b786e4a594d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734550518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.1734550518
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.3842102794
Short name T984
Test name
Test status
Simulation time 41256072182 ps
CPU time 19.54 seconds
Started Jun 23 05:43:40 PM PDT 24
Finished Jun 23 05:44:00 PM PDT 24
Peak memory 200768 kb
Host smart-a631f270-b942-408b-99fd-bdc901067f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842102794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.3842102794
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.2549060859
Short name T680
Test name
Test status
Simulation time 24997573209 ps
CPU time 13.76 seconds
Started Jun 23 05:43:40 PM PDT 24
Finished Jun 23 05:43:54 PM PDT 24
Peak memory 200680 kb
Host smart-5d057bf3-6db8-41e0-8c35-385f62f68df3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549060859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.2549060859
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.2273116701
Short name T936
Test name
Test status
Simulation time 245875818799 ps
CPU time 220.43 seconds
Started Jun 23 05:43:41 PM PDT 24
Finished Jun 23 05:47:22 PM PDT 24
Peak memory 200644 kb
Host smart-4d5dfdee-37b1-46ab-b88a-f58b58f41074
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2273116701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.2273116701
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.2828716498
Short name T332
Test name
Test status
Simulation time 9449312165 ps
CPU time 9.61 seconds
Started Jun 23 05:43:42 PM PDT 24
Finished Jun 23 05:43:52 PM PDT 24
Peak memory 200664 kb
Host smart-b605c9a6-e985-4307-b21a-b64db579228d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828716498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.2828716498
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_perf.4004752201
Short name T367
Test name
Test status
Simulation time 10374285151 ps
CPU time 116.02 seconds
Started Jun 23 05:43:40 PM PDT 24
Finished Jun 23 05:45:37 PM PDT 24
Peak memory 200632 kb
Host smart-a4717e71-f98e-4da9-863b-c8477a87180d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4004752201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.4004752201
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.2115376025
Short name T543
Test name
Test status
Simulation time 2110086366 ps
CPU time 6.41 seconds
Started Jun 23 05:43:42 PM PDT 24
Finished Jun 23 05:43:50 PM PDT 24
Peak memory 199800 kb
Host smart-80ffb636-2e75-488b-859d-a1f40715caf9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2115376025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.2115376025
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.2434207334
Short name T269
Test name
Test status
Simulation time 15115062226 ps
CPU time 7.15 seconds
Started Jun 23 05:43:40 PM PDT 24
Finished Jun 23 05:43:47 PM PDT 24
Peak memory 199896 kb
Host smart-4d09c7d0-54c3-4819-b0f1-5282bdfa0587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434207334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.2434207334
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.3996461875
Short name T620
Test name
Test status
Simulation time 5715921508 ps
CPU time 8.57 seconds
Started Jun 23 05:43:44 PM PDT 24
Finished Jun 23 05:43:53 PM PDT 24
Peak memory 196792 kb
Host smart-89d4561a-41c1-4899-8534-05dd827d8896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996461875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.3996461875
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.1886047327
Short name T566
Test name
Test status
Simulation time 557050103 ps
CPU time 1.79 seconds
Started Jun 23 05:43:42 PM PDT 24
Finished Jun 23 05:43:44 PM PDT 24
Peak memory 199644 kb
Host smart-0b39a4aa-437e-44e2-b67e-4ad7a6b79760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886047327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.1886047327
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.1210999268
Short name T375
Test name
Test status
Simulation time 37971433618 ps
CPU time 33.06 seconds
Started Jun 23 05:43:41 PM PDT 24
Finished Jun 23 05:44:15 PM PDT 24
Peak memory 200644 kb
Host smart-c4d17277-2526-40f4-874c-628489a1a6fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210999268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.1210999268
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.2529413125
Short name T970
Test name
Test status
Simulation time 43025471623 ps
CPU time 1303.02 seconds
Started Jun 23 05:43:39 PM PDT 24
Finished Jun 23 06:05:23 PM PDT 24
Peak memory 210552 kb
Host smart-1ab52695-04f5-484c-b01b-e161064c1a69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529413125 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.2529413125
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.3743376047
Short name T275
Test name
Test status
Simulation time 5986196909 ps
CPU time 22.53 seconds
Started Jun 23 05:43:39 PM PDT 24
Finished Jun 23 05:44:03 PM PDT 24
Peak memory 200744 kb
Host smart-7e647d7c-5a78-4703-b202-a2fc32d96564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743376047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.3743376047
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.143909090
Short name T871
Test name
Test status
Simulation time 35581672261 ps
CPU time 20.2 seconds
Started Jun 23 05:43:38 PM PDT 24
Finished Jun 23 05:43:58 PM PDT 24
Peak memory 200624 kb
Host smart-6fa134b2-69c6-4dda-8905-4cbc713672e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143909090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.143909090
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.4261632557
Short name T853
Test name
Test status
Simulation time 20807933 ps
CPU time 0.55 seconds
Started Jun 23 05:43:45 PM PDT 24
Finished Jun 23 05:43:46 PM PDT 24
Peak memory 196096 kb
Host smart-20312404-dc49-450c-bc55-4508223a665e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261632557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.4261632557
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.158170240
Short name T728
Test name
Test status
Simulation time 88234185755 ps
CPU time 16.33 seconds
Started Jun 23 05:43:43 PM PDT 24
Finished Jun 23 05:44:00 PM PDT 24
Peak memory 200696 kb
Host smart-ae3e170b-023a-4fa4-b9e1-036f6c887c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158170240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.158170240
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.1759957764
Short name T952
Test name
Test status
Simulation time 93784093188 ps
CPU time 34.97 seconds
Started Jun 23 05:43:42 PM PDT 24
Finished Jun 23 05:44:18 PM PDT 24
Peak memory 200780 kb
Host smart-0f515b34-9388-4e76-89fc-57186249a1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759957764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.1759957764
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.821886449
Short name T225
Test name
Test status
Simulation time 69947843924 ps
CPU time 13.75 seconds
Started Jun 23 05:43:41 PM PDT 24
Finished Jun 23 05:43:56 PM PDT 24
Peak memory 200636 kb
Host smart-e58bfe6c-e4e9-42d0-845e-888c5d82f867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821886449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.821886449
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.2579967994
Short name T369
Test name
Test status
Simulation time 17222322009 ps
CPU time 6.85 seconds
Started Jun 23 05:43:40 PM PDT 24
Finished Jun 23 05:43:48 PM PDT 24
Peak memory 196692 kb
Host smart-947c8fef-026a-4828-b17a-9800ed83e789
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579967994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.2579967994
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.335714222
Short name T360
Test name
Test status
Simulation time 101711565994 ps
CPU time 272.94 seconds
Started Jun 23 05:43:42 PM PDT 24
Finished Jun 23 05:48:16 PM PDT 24
Peak memory 200704 kb
Host smart-b1307676-3516-47c6-8c69-2f2a18a960b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=335714222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.335714222
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.153278402
Short name T893
Test name
Test status
Simulation time 3472520597 ps
CPU time 2.71 seconds
Started Jun 23 05:43:43 PM PDT 24
Finished Jun 23 05:43:46 PM PDT 24
Peak memory 199548 kb
Host smart-6f51e33e-4983-4ba4-b3bc-4eaa3d302550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153278402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.153278402
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_perf.3080424565
Short name T1012
Test name
Test status
Simulation time 16280111375 ps
CPU time 255.46 seconds
Started Jun 23 05:43:44 PM PDT 24
Finished Jun 23 05:48:00 PM PDT 24
Peak memory 200700 kb
Host smart-ee8d9551-292a-4e87-bd35-399d41815070
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3080424565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.3080424565
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.1720792018
Short name T304
Test name
Test status
Simulation time 5756056271 ps
CPU time 25.92 seconds
Started Jun 23 05:43:38 PM PDT 24
Finished Jun 23 05:44:05 PM PDT 24
Peak memory 199788 kb
Host smart-ce89aa75-0e40-4994-9055-717c348c90da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1720792018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.1720792018
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.467278616
Short name T962
Test name
Test status
Simulation time 67842682360 ps
CPU time 17.02 seconds
Started Jun 23 05:43:45 PM PDT 24
Finished Jun 23 05:44:03 PM PDT 24
Peak memory 200744 kb
Host smart-8bb2af79-6abb-4086-bd03-545b287bbcc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467278616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.467278616
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.3420785774
Short name T808
Test name
Test status
Simulation time 3378584080 ps
CPU time 3.52 seconds
Started Jun 23 05:43:42 PM PDT 24
Finished Jun 23 05:43:46 PM PDT 24
Peak memory 197260 kb
Host smart-295c7404-af34-4f9b-9335-a131cd450e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420785774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.3420785774
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.2403760761
Short name T895
Test name
Test status
Simulation time 518536108 ps
CPU time 1.25 seconds
Started Jun 23 05:43:38 PM PDT 24
Finished Jun 23 05:43:40 PM PDT 24
Peak memory 199420 kb
Host smart-01a630f3-df42-4267-bc12-b4d934b1e085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403760761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.2403760761
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.1101181183
Short name T572
Test name
Test status
Simulation time 115118719980 ps
CPU time 85.36 seconds
Started Jun 23 05:43:45 PM PDT 24
Finished Jun 23 05:45:11 PM PDT 24
Peak memory 200728 kb
Host smart-64c1b362-85de-4d22-9311-071eb6ec49ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101181183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.1101181183
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.1319210674
Short name T521
Test name
Test status
Simulation time 758998891 ps
CPU time 1.04 seconds
Started Jun 23 05:43:44 PM PDT 24
Finished Jun 23 05:43:46 PM PDT 24
Peak memory 197804 kb
Host smart-be792ae6-d866-45dd-8a6b-b85cf395e5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319210674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.1319210674
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.2870288802
Short name T844
Test name
Test status
Simulation time 58740211105 ps
CPU time 51.02 seconds
Started Jun 23 05:43:45 PM PDT 24
Finished Jun 23 05:44:37 PM PDT 24
Peak memory 200764 kb
Host smart-c256af50-b37c-43cc-93d9-20928c6c0302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870288802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.2870288802
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.2099526500
Short name T515
Test name
Test status
Simulation time 11791112 ps
CPU time 0.54 seconds
Started Jun 23 05:43:52 PM PDT 24
Finished Jun 23 05:43:53 PM PDT 24
Peak memory 196096 kb
Host smart-e1c4222b-7f35-4223-8fc3-b3cf6e7d2766
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099526500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.2099526500
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.862497805
Short name T254
Test name
Test status
Simulation time 113446173361 ps
CPU time 92.99 seconds
Started Jun 23 05:43:44 PM PDT 24
Finished Jun 23 05:45:18 PM PDT 24
Peak memory 200680 kb
Host smart-1603e9ab-9a47-4dc4-a72b-c192eb8c38e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862497805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.862497805
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.1952600183
Short name T197
Test name
Test status
Simulation time 52198692832 ps
CPU time 53.08 seconds
Started Jun 23 05:43:48 PM PDT 24
Finished Jun 23 05:44:41 PM PDT 24
Peak memory 200724 kb
Host smart-7aa6863c-ef1d-4b82-bfde-8233a98ead6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952600183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.1952600183
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.3096702359
Short name T14
Test name
Test status
Simulation time 35673435833 ps
CPU time 49.22 seconds
Started Jun 23 05:43:51 PM PDT 24
Finished Jun 23 05:44:40 PM PDT 24
Peak memory 200604 kb
Host smart-38ff4ebd-b1ee-41cb-8560-4054f6b25389
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096702359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.3096702359
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.4246711761
Short name T603
Test name
Test status
Simulation time 74006222771 ps
CPU time 205.97 seconds
Started Jun 23 05:43:52 PM PDT 24
Finished Jun 23 05:47:19 PM PDT 24
Peak memory 200680 kb
Host smart-ac007faf-a1b0-48f3-bf64-478c0f3eb232
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4246711761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.4246711761
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.3987905754
Short name T981
Test name
Test status
Simulation time 5446611695 ps
CPU time 9.67 seconds
Started Jun 23 05:43:50 PM PDT 24
Finished Jun 23 05:44:00 PM PDT 24
Peak memory 199884 kb
Host smart-3e069d5c-067c-4089-af9e-6dc3c3aa117b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987905754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.3987905754
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_perf.417459670
Short name T263
Test name
Test status
Simulation time 7130243321 ps
CPU time 315.1 seconds
Started Jun 23 05:43:50 PM PDT 24
Finished Jun 23 05:49:06 PM PDT 24
Peak memory 200664 kb
Host smart-10336550-3e15-46ee-81d4-f6cf8fd294f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=417459670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.417459670
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.3852894114
Short name T847
Test name
Test status
Simulation time 3707380318 ps
CPU time 32.08 seconds
Started Jun 23 05:43:50 PM PDT 24
Finished Jun 23 05:44:22 PM PDT 24
Peak memory 199144 kb
Host smart-86f17f02-f6a3-4f2c-a52d-0ab535a39a3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3852894114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.3852894114
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.32404126
Short name T629
Test name
Test status
Simulation time 243989433947 ps
CPU time 231.37 seconds
Started Jun 23 05:43:47 PM PDT 24
Finished Jun 23 05:47:39 PM PDT 24
Peak memory 200736 kb
Host smart-8fc27416-2f2f-40a5-94e8-3eec6adceac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32404126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.32404126
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.3810785434
Short name T478
Test name
Test status
Simulation time 4035279661 ps
CPU time 6.02 seconds
Started Jun 23 05:43:48 PM PDT 24
Finished Jun 23 05:43:55 PM PDT 24
Peak memory 196828 kb
Host smart-36f98f39-8b59-4295-9265-df514f3c5a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810785434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.3810785434
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.4029416095
Short name T296
Test name
Test status
Simulation time 647595840 ps
CPU time 2 seconds
Started Jun 23 05:43:43 PM PDT 24
Finished Jun 23 05:43:45 PM PDT 24
Peak memory 200572 kb
Host smart-68025e8e-9287-4938-a7b0-be5ea50b38eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029416095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.4029416095
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.1820738344
Short name T428
Test name
Test status
Simulation time 189971446316 ps
CPU time 705.42 seconds
Started Jun 23 05:43:49 PM PDT 24
Finished Jun 23 05:55:34 PM PDT 24
Peak memory 217184 kb
Host smart-e9735de3-151c-46f2-b623-4d6916cc2e84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820738344 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.1820738344
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.1778366977
Short name T282
Test name
Test status
Simulation time 706239204 ps
CPU time 1.25 seconds
Started Jun 23 05:43:51 PM PDT 24
Finished Jun 23 05:43:52 PM PDT 24
Peak memory 197856 kb
Host smart-cda8fe76-5a50-455e-8a7d-71624bec8e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778366977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.1778366977
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.3528467441
Short name T712
Test name
Test status
Simulation time 77828649477 ps
CPU time 32.24 seconds
Started Jun 23 05:43:43 PM PDT 24
Finished Jun 23 05:44:15 PM PDT 24
Peak memory 200736 kb
Host smart-5c4f5f16-e389-467f-9fe6-463d6b6b3a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528467441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.3528467441
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.128807867
Short name T1024
Test name
Test status
Simulation time 27950994 ps
CPU time 0.55 seconds
Started Jun 23 05:40:04 PM PDT 24
Finished Jun 23 05:40:05 PM PDT 24
Peak memory 196096 kb
Host smart-d449d5f5-6199-467d-95c2-e9fb6f169624
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128807867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.128807867
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.688355509
Short name T541
Test name
Test status
Simulation time 42250290692 ps
CPU time 32.94 seconds
Started Jun 23 05:40:04 PM PDT 24
Finished Jun 23 05:40:37 PM PDT 24
Peak memory 200652 kb
Host smart-525337d8-4d8a-4ef1-ac70-bd797a63e93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688355509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.688355509
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.2521518539
Short name T710
Test name
Test status
Simulation time 104403334131 ps
CPU time 36.66 seconds
Started Jun 23 05:40:02 PM PDT 24
Finished Jun 23 05:40:39 PM PDT 24
Peak memory 200652 kb
Host smart-a6d6c58b-36a9-4f53-8e80-d7004c24241a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521518539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.2521518539
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.769363742
Short name T186
Test name
Test status
Simulation time 167529367516 ps
CPU time 122.07 seconds
Started Jun 23 05:40:06 PM PDT 24
Finished Jun 23 05:42:09 PM PDT 24
Peak memory 200696 kb
Host smart-99815000-2089-43c6-8a78-9c4b4d0c838d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769363742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.769363742
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.2880831931
Short name T678
Test name
Test status
Simulation time 41116901073 ps
CPU time 74.58 seconds
Started Jun 23 05:40:06 PM PDT 24
Finished Jun 23 05:41:21 PM PDT 24
Peak memory 200644 kb
Host smart-4514ca4f-5608-4517-809a-d98735bc8ed9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880831931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.2880831931
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.2195972043
Short name T1041
Test name
Test status
Simulation time 94739333061 ps
CPU time 722.14 seconds
Started Jun 23 05:40:01 PM PDT 24
Finished Jun 23 05:52:03 PM PDT 24
Peak memory 200776 kb
Host smart-acad47e1-3788-4346-b802-20772f0fabd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2195972043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.2195972043
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.1944425835
Short name T412
Test name
Test status
Simulation time 9899546328 ps
CPU time 7 seconds
Started Jun 23 05:40:06 PM PDT 24
Finished Jun 23 05:40:14 PM PDT 24
Peak memory 199968 kb
Host smart-c80b63db-99c3-422a-a595-6ed652c02ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944425835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.1944425835
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_perf.4104430150
Short name T1072
Test name
Test status
Simulation time 13871859880 ps
CPU time 375.97 seconds
Started Jun 23 05:40:02 PM PDT 24
Finished Jun 23 05:46:18 PM PDT 24
Peak memory 200736 kb
Host smart-137c802e-5ae4-485b-b643-d826c9e37942
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4104430150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.4104430150
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.3948467202
Short name T661
Test name
Test status
Simulation time 6290623604 ps
CPU time 5.97 seconds
Started Jun 23 05:40:05 PM PDT 24
Finished Jun 23 05:40:11 PM PDT 24
Peak memory 200060 kb
Host smart-5bfdd6c4-e03a-4e01-b34f-caa74381a705
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3948467202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.3948467202
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.37918890
Short name T1018
Test name
Test status
Simulation time 15565570543 ps
CPU time 8.54 seconds
Started Jun 23 05:40:03 PM PDT 24
Finished Jun 23 05:40:12 PM PDT 24
Peak memory 200452 kb
Host smart-d6592a5e-790b-465b-b29e-cdfe364ce648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37918890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.37918890
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.3385044684
Short name T717
Test name
Test status
Simulation time 2871076604 ps
CPU time 1.91 seconds
Started Jun 23 05:40:03 PM PDT 24
Finished Jun 23 05:40:05 PM PDT 24
Peak memory 196548 kb
Host smart-1926cec4-3a45-4885-9a68-6dba826e72da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385044684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.3385044684
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.1424337995
Short name T434
Test name
Test status
Simulation time 457984849 ps
CPU time 1.54 seconds
Started Jun 23 05:40:04 PM PDT 24
Finished Jun 23 05:40:06 PM PDT 24
Peak memory 199060 kb
Host smart-d201f37c-a973-4f21-89b9-6c5b1e5ebac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424337995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.1424337995
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.2690258284
Short name T1057
Test name
Test status
Simulation time 155068421464 ps
CPU time 309.08 seconds
Started Jun 23 05:40:03 PM PDT 24
Finished Jun 23 05:45:12 PM PDT 24
Peak memory 200600 kb
Host smart-b679a569-bbee-4695-83fe-c4d03e8c8643
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690258284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.2690258284
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.53624200
Short name T449
Test name
Test status
Simulation time 8374896743 ps
CPU time 12.44 seconds
Started Jun 23 05:40:03 PM PDT 24
Finished Jun 23 05:40:16 PM PDT 24
Peak memory 200616 kb
Host smart-c528815b-0915-41e6-9677-2fff12cad096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53624200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.53624200
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.1579581011
Short name T865
Test name
Test status
Simulation time 1379860392 ps
CPU time 2.79 seconds
Started Jun 23 05:40:02 PM PDT 24
Finished Jun 23 05:40:05 PM PDT 24
Peak memory 197356 kb
Host smart-9e1e93cf-bca6-4f9a-a105-1ab9741d2b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579581011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.1579581011
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.1433619930
Short name T772
Test name
Test status
Simulation time 42014330451 ps
CPU time 68.05 seconds
Started Jun 23 05:43:55 PM PDT 24
Finished Jun 23 05:45:03 PM PDT 24
Peak memory 200748 kb
Host smart-d1d37537-b12d-4d6c-9bd7-d4a45920febe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433619930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.1433619930
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.1260324551
Short name T34
Test name
Test status
Simulation time 30872003289 ps
CPU time 350.61 seconds
Started Jun 23 05:43:52 PM PDT 24
Finished Jun 23 05:49:43 PM PDT 24
Peak memory 216524 kb
Host smart-9e865caf-1ff8-49ec-9329-0488c6f7ff19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260324551 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.1260324551
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.4132237379
Short name T196
Test name
Test status
Simulation time 15554466201 ps
CPU time 15.89 seconds
Started Jun 23 05:43:53 PM PDT 24
Finished Jun 23 05:44:10 PM PDT 24
Peak memory 200692 kb
Host smart-5fc8a350-e6f8-4b7d-aea6-09022aef3cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132237379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.4132237379
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.1799627111
Short name T526
Test name
Test status
Simulation time 97304041279 ps
CPU time 222.93 seconds
Started Jun 23 05:43:56 PM PDT 24
Finished Jun 23 05:47:39 PM PDT 24
Peak memory 200716 kb
Host smart-1069edc0-a923-4ec7-bcc0-5c11773cc176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799627111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.1799627111
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.1733674940
Short name T671
Test name
Test status
Simulation time 274695140878 ps
CPU time 46.73 seconds
Started Jun 23 05:43:54 PM PDT 24
Finished Jun 23 05:44:41 PM PDT 24
Peak memory 200752 kb
Host smart-6bc94595-f983-4283-84ae-25fbd1189313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733674940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.1733674940
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.107613572
Short name T774
Test name
Test status
Simulation time 870955715843 ps
CPU time 1200.36 seconds
Started Jun 23 05:43:54 PM PDT 24
Finished Jun 23 06:03:55 PM PDT 24
Peak memory 217360 kb
Host smart-32e875ae-f56b-4423-9798-8aa3e11c2d87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107613572 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.107613572
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.2613568722
Short name T879
Test name
Test status
Simulation time 24797439965 ps
CPU time 24.24 seconds
Started Jun 23 05:43:58 PM PDT 24
Finished Jun 23 05:44:23 PM PDT 24
Peak memory 200696 kb
Host smart-f9532c6a-23ee-4fc7-b27f-a21894ef47fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613568722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.2613568722
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.1589901648
Short name T210
Test name
Test status
Simulation time 20707769585 ps
CPU time 15.63 seconds
Started Jun 23 05:43:57 PM PDT 24
Finished Jun 23 05:44:13 PM PDT 24
Peak memory 200696 kb
Host smart-7addf344-b5be-4203-9605-c0c73f43ea1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589901648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.1589901648
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.1302817526
Short name T1055
Test name
Test status
Simulation time 10294430164 ps
CPU time 107.73 seconds
Started Jun 23 05:44:02 PM PDT 24
Finished Jun 23 05:45:50 PM PDT 24
Peak memory 200832 kb
Host smart-84aefbaf-493b-4269-a33a-f30c54567643
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302817526 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.1302817526
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.4108728319
Short name T289
Test name
Test status
Simulation time 13243581251 ps
CPU time 16.94 seconds
Started Jun 23 05:43:55 PM PDT 24
Finished Jun 23 05:44:12 PM PDT 24
Peak memory 200492 kb
Host smart-4ada821a-6c18-4f10-8a02-410201eaeaeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108728319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.4108728319
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.2548238074
Short name T581
Test name
Test status
Simulation time 79353916461 ps
CPU time 19.24 seconds
Started Jun 23 05:43:54 PM PDT 24
Finished Jun 23 05:44:14 PM PDT 24
Peak memory 200752 kb
Host smart-35c788b9-2af2-4e23-b5d6-77e6170e5a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548238074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.2548238074
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.3587900184
Short name T911
Test name
Test status
Simulation time 28851564745 ps
CPU time 354.37 seconds
Started Jun 23 05:43:53 PM PDT 24
Finished Jun 23 05:49:48 PM PDT 24
Peak memory 217124 kb
Host smart-743e179f-febb-46df-ab15-72c40ce91816
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587900184 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.3587900184
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.1751858729
Short name T142
Test name
Test status
Simulation time 10165577893 ps
CPU time 14.65 seconds
Started Jun 23 05:43:57 PM PDT 24
Finished Jun 23 05:44:12 PM PDT 24
Peak memory 200748 kb
Host smart-2f89f732-4570-48fb-9d93-393e0046bd21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751858729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.1751858729
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.1775132444
Short name T616
Test name
Test status
Simulation time 20239169074 ps
CPU time 35.03 seconds
Started Jun 23 05:43:57 PM PDT 24
Finished Jun 23 05:44:32 PM PDT 24
Peak memory 200588 kb
Host smart-05cad7e2-b2b8-4377-aa0e-91d5478be615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775132444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.1775132444
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.1982488010
Short name T384
Test name
Test status
Simulation time 72724573997 ps
CPU time 193.39 seconds
Started Jun 23 05:43:56 PM PDT 24
Finished Jun 23 05:47:09 PM PDT 24
Peak memory 216432 kb
Host smart-1b1d0ffa-fbdc-47df-9d98-4e149bc1dd74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982488010 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.1982488010
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.902379655
Short name T880
Test name
Test status
Simulation time 12666298 ps
CPU time 0.53 seconds
Started Jun 23 05:40:07 PM PDT 24
Finished Jun 23 05:40:08 PM PDT 24
Peak memory 195548 kb
Host smart-cc588f90-c150-4dd7-99f9-19a517bf2e19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902379655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.902379655
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.2751759952
Short name T141
Test name
Test status
Simulation time 170608488166 ps
CPU time 70.34 seconds
Started Jun 23 05:40:08 PM PDT 24
Finished Jun 23 05:41:19 PM PDT 24
Peak memory 200696 kb
Host smart-41e69e8c-dd15-4a6e-9e9b-d075d34eb075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751759952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.2751759952
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.261059522
Short name T1069
Test name
Test status
Simulation time 64737917738 ps
CPU time 100.98 seconds
Started Jun 23 05:40:07 PM PDT 24
Finished Jun 23 05:41:49 PM PDT 24
Peak memory 200660 kb
Host smart-426b85bf-dab7-471c-9d74-b1fba5b21d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261059522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.261059522
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.4215857233
Short name T212
Test name
Test status
Simulation time 23906554887 ps
CPU time 13.91 seconds
Started Jun 23 05:40:08 PM PDT 24
Finished Jun 23 05:40:22 PM PDT 24
Peak memory 200748 kb
Host smart-92b5bb31-2219-4e3f-8d64-5590db182f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215857233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.4215857233
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.602125692
Short name T312
Test name
Test status
Simulation time 73904611518 ps
CPU time 30.35 seconds
Started Jun 23 05:40:05 PM PDT 24
Finished Jun 23 05:40:36 PM PDT 24
Peak memory 200720 kb
Host smart-66500fed-272c-4cdf-85c7-e2cf115a1456
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602125692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.602125692
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.410275486
Short name T909
Test name
Test status
Simulation time 109203716641 ps
CPU time 268.16 seconds
Started Jun 23 05:40:06 PM PDT 24
Finished Jun 23 05:44:35 PM PDT 24
Peak memory 200636 kb
Host smart-69bf9ee0-06bd-4b46-9217-a01f5d129ed1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=410275486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.410275486
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.1515898719
Short name T1089
Test name
Test status
Simulation time 4152454298 ps
CPU time 2.37 seconds
Started Jun 23 05:40:06 PM PDT 24
Finished Jun 23 05:40:09 PM PDT 24
Peak memory 199552 kb
Host smart-20442ad3-cf47-446e-bad9-66c18bf7bf32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515898719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.1515898719
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_perf.1142604376
Short name T644
Test name
Test status
Simulation time 11480358993 ps
CPU time 698.52 seconds
Started Jun 23 05:40:06 PM PDT 24
Finished Jun 23 05:51:46 PM PDT 24
Peak memory 200692 kb
Host smart-1c28e658-534c-468a-9665-e5bef4557a5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1142604376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.1142604376
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.1653951228
Short name T922
Test name
Test status
Simulation time 3272266229 ps
CPU time 24.88 seconds
Started Jun 23 05:40:06 PM PDT 24
Finished Jun 23 05:40:32 PM PDT 24
Peak memory 198952 kb
Host smart-397ede12-6868-4f5e-a7ed-6fdf257f0720
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1653951228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.1653951228
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.1594719469
Short name T1092
Test name
Test status
Simulation time 114514853532 ps
CPU time 49.65 seconds
Started Jun 23 05:40:07 PM PDT 24
Finished Jun 23 05:40:57 PM PDT 24
Peak memory 200284 kb
Host smart-ebc77852-1eef-4b7b-8b8b-d19a4623f361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594719469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.1594719469
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.399811013
Short name T692
Test name
Test status
Simulation time 6053639871 ps
CPU time 10.62 seconds
Started Jun 23 05:40:06 PM PDT 24
Finished Jun 23 05:40:17 PM PDT 24
Peak memory 197208 kb
Host smart-12d292c2-5587-42de-a923-dfef8aae202c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399811013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.399811013
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.375268565
Short name T852
Test name
Test status
Simulation time 448560217 ps
CPU time 2.2 seconds
Started Jun 23 05:40:01 PM PDT 24
Finished Jun 23 05:40:03 PM PDT 24
Peak memory 199084 kb
Host smart-f0b896b2-ea88-4d81-9de7-687a3ee5b2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375268565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.375268565
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.4246723886
Short name T1066
Test name
Test status
Simulation time 309480447982 ps
CPU time 122.93 seconds
Started Jun 23 05:40:06 PM PDT 24
Finished Jun 23 05:42:10 PM PDT 24
Peak memory 200728 kb
Host smart-c1509c50-03eb-478b-a113-3c4ef60b0496
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246723886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.4246723886
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.1734172359
Short name T233
Test name
Test status
Simulation time 11791036762 ps
CPU time 5.02 seconds
Started Jun 23 05:40:07 PM PDT 24
Finished Jun 23 05:40:12 PM PDT 24
Peak memory 200364 kb
Host smart-0992c8f8-bdb6-4973-88d2-f2592d8255d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734172359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.1734172359
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.175796035
Short name T79
Test name
Test status
Simulation time 56461964705 ps
CPU time 143.75 seconds
Started Jun 23 05:40:09 PM PDT 24
Finished Jun 23 05:42:33 PM PDT 24
Peak memory 200656 kb
Host smart-f09aee1e-b71f-4c9e-8372-9393a2bbfea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175796035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.175796035
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.3092433507
Short name T840
Test name
Test status
Simulation time 105906577556 ps
CPU time 10.73 seconds
Started Jun 23 05:43:58 PM PDT 24
Finished Jun 23 05:44:09 PM PDT 24
Peak memory 200756 kb
Host smart-b3f83a36-60be-4ae1-b5fa-41d495b64458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092433507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.3092433507
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.960052681
Short name T498
Test name
Test status
Simulation time 341245822696 ps
CPU time 86.79 seconds
Started Jun 23 05:43:56 PM PDT 24
Finished Jun 23 05:45:23 PM PDT 24
Peak memory 200692 kb
Host smart-4164a1a9-6608-4508-9e16-5ad72cdf2a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960052681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.960052681
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.1502956955
Short name T80
Test name
Test status
Simulation time 23136016535 ps
CPU time 292.02 seconds
Started Jun 23 05:43:58 PM PDT 24
Finished Jun 23 05:48:51 PM PDT 24
Peak memory 209052 kb
Host smart-c8cc0270-4205-432d-a865-416f034002ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502956955 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.1502956955
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.3460164697
Short name T641
Test name
Test status
Simulation time 159668939965 ps
CPU time 244.47 seconds
Started Jun 23 05:43:58 PM PDT 24
Finished Jun 23 05:48:03 PM PDT 24
Peak memory 200680 kb
Host smart-c38b1d4f-ac82-4980-afb9-edb847c372d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460164697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.3460164697
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.3109157936
Short name T745
Test name
Test status
Simulation time 55326201007 ps
CPU time 1151.04 seconds
Started Jun 23 05:43:58 PM PDT 24
Finished Jun 23 06:03:10 PM PDT 24
Peak memory 217192 kb
Host smart-20b9d5ea-dad5-4dcc-9ef6-a05921ee8de0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109157936 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.3109157936
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.1940577572
Short name T255
Test name
Test status
Simulation time 107138773920 ps
CPU time 29.59 seconds
Started Jun 23 05:43:58 PM PDT 24
Finished Jun 23 05:44:28 PM PDT 24
Peak memory 200656 kb
Host smart-47fbf431-9518-4d61-987b-9aef48f0a404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940577572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.1940577572
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.332387345
Short name T535
Test name
Test status
Simulation time 14008306949 ps
CPU time 192.6 seconds
Started Jun 23 05:43:58 PM PDT 24
Finished Jun 23 05:47:11 PM PDT 24
Peak memory 217180 kb
Host smart-03a3ec93-2ea4-4b06-bf50-8972f3151cf5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332387345 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.332387345
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.2448341292
Short name T118
Test name
Test status
Simulation time 37682995817 ps
CPU time 31.54 seconds
Started Jun 23 05:43:59 PM PDT 24
Finished Jun 23 05:44:30 PM PDT 24
Peak memory 200704 kb
Host smart-9cc6536d-d0c7-44a6-893b-47a3a87186fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448341292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.2448341292
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.1396748169
Short name T754
Test name
Test status
Simulation time 181834609725 ps
CPU time 588.36 seconds
Started Jun 23 05:44:00 PM PDT 24
Finished Jun 23 05:53:49 PM PDT 24
Peak memory 217148 kb
Host smart-08c81e8f-101e-4d9c-8582-02254a533d42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396748169 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.1396748169
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.3092892860
Short name T268
Test name
Test status
Simulation time 19667053082 ps
CPU time 28.13 seconds
Started Jun 23 05:44:00 PM PDT 24
Finished Jun 23 05:44:28 PM PDT 24
Peak memory 200720 kb
Host smart-e11d56b5-de97-4469-a211-5c5c6a6905c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092892860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.3092892860
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.3474181226
Short name T347
Test name
Test status
Simulation time 15867192524 ps
CPU time 7.28 seconds
Started Jun 23 05:43:58 PM PDT 24
Finished Jun 23 05:44:06 PM PDT 24
Peak memory 200688 kb
Host smart-0c0533d5-9d41-4283-9fbf-fe02c5de1156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474181226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.3474181226
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.2323153230
Short name T243
Test name
Test status
Simulation time 29137311960 ps
CPU time 14.7 seconds
Started Jun 23 05:43:56 PM PDT 24
Finished Jun 23 05:44:11 PM PDT 24
Peak memory 200704 kb
Host smart-ccbe80be-aea5-4134-b646-2498d435c88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323153230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.2323153230
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.2961567171
Short name T561
Test name
Test status
Simulation time 104431692313 ps
CPU time 148.68 seconds
Started Jun 23 05:44:02 PM PDT 24
Finished Jun 23 05:46:31 PM PDT 24
Peak memory 200680 kb
Host smart-1586ce66-e3d2-4c96-839a-758d6efdd44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961567171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.2961567171
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.1505557817
Short name T84
Test name
Test status
Simulation time 35497752629 ps
CPU time 307.21 seconds
Started Jun 23 05:44:02 PM PDT 24
Finished Jun 23 05:49:09 PM PDT 24
Peak memory 217104 kb
Host smart-a6da0d2a-7a46-47aa-9377-f4e11ce38bb0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505557817 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.1505557817
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.1937160822
Short name T211
Test name
Test status
Simulation time 40373048493 ps
CPU time 56.79 seconds
Started Jun 23 05:44:09 PM PDT 24
Finished Jun 23 05:45:06 PM PDT 24
Peak memory 200772 kb
Host smart-2faae088-d0f6-4bab-a39a-53f41ab48818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937160822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.1937160822
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.2835307860
Short name T968
Test name
Test status
Simulation time 551814871229 ps
CPU time 1057.16 seconds
Started Jun 23 05:44:04 PM PDT 24
Finished Jun 23 06:01:41 PM PDT 24
Peak memory 217156 kb
Host smart-d40dd101-b92b-4f91-af15-05f27c0b9750
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835307860 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.2835307860
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.3816068722
Short name T1023
Test name
Test status
Simulation time 12551740 ps
CPU time 0.55 seconds
Started Jun 23 05:40:15 PM PDT 24
Finished Jun 23 05:40:16 PM PDT 24
Peak memory 196100 kb
Host smart-8b785110-36cc-4a9f-9ec3-b96756429396
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816068722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.3816068722
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.629329617
Short name T115
Test name
Test status
Simulation time 37690640279 ps
CPU time 15.49 seconds
Started Jun 23 05:40:14 PM PDT 24
Finished Jun 23 05:40:30 PM PDT 24
Peak memory 200728 kb
Host smart-f49f6442-fcfd-464a-95bc-5d449f869e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629329617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.629329617
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.4294339347
Short name T261
Test name
Test status
Simulation time 43129989167 ps
CPU time 81.78 seconds
Started Jun 23 05:40:16 PM PDT 24
Finished Jun 23 05:41:39 PM PDT 24
Peak memory 200628 kb
Host smart-629f273a-b699-49de-9243-0c525397017d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294339347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.4294339347
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_intr.1342961626
Short name T302
Test name
Test status
Simulation time 189105399944 ps
CPU time 131.77 seconds
Started Jun 23 05:40:11 PM PDT 24
Finished Jun 23 05:42:24 PM PDT 24
Peak memory 200044 kb
Host smart-46a893d9-2877-417d-a526-f3d3d3885f74
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342961626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.1342961626
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.2271332199
Short name T539
Test name
Test status
Simulation time 55680472659 ps
CPU time 249.12 seconds
Started Jun 23 05:40:14 PM PDT 24
Finished Jun 23 05:44:23 PM PDT 24
Peak memory 200600 kb
Host smart-0e462dca-7639-4320-b355-643d7ea907b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2271332199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.2271332199
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.3451479342
Short name T421
Test name
Test status
Simulation time 1948805171 ps
CPU time 3.77 seconds
Started Jun 23 05:40:12 PM PDT 24
Finished Jun 23 05:40:16 PM PDT 24
Peak memory 198680 kb
Host smart-7e246cf1-485f-496a-a37c-ae5951be818b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451479342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.3451479342
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_perf.3002168385
Short name T1038
Test name
Test status
Simulation time 15825532807 ps
CPU time 228.41 seconds
Started Jun 23 05:40:13 PM PDT 24
Finished Jun 23 05:44:02 PM PDT 24
Peak memory 200696 kb
Host smart-28c96db8-c799-4a1a-85ec-391a83bf3a9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3002168385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.3002168385
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.515331432
Short name T328
Test name
Test status
Simulation time 3186409898 ps
CPU time 4.62 seconds
Started Jun 23 05:40:11 PM PDT 24
Finished Jun 23 05:40:17 PM PDT 24
Peak memory 199724 kb
Host smart-fabe975c-87dc-463d-9cac-7821a6586965
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=515331432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.515331432
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.4289885630
Short name T1079
Test name
Test status
Simulation time 30736160909 ps
CPU time 21.66 seconds
Started Jun 23 05:40:19 PM PDT 24
Finished Jun 23 05:40:42 PM PDT 24
Peak memory 200672 kb
Host smart-319c1f95-645e-4317-ad2d-1998d610a5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289885630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.4289885630
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.1312076843
Short name T887
Test name
Test status
Simulation time 2039141832 ps
CPU time 3.42 seconds
Started Jun 23 05:40:12 PM PDT 24
Finished Jun 23 05:40:16 PM PDT 24
Peak memory 196132 kb
Host smart-b4a113ba-c465-4368-91a2-c1b220de7633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312076843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.1312076843
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.129700443
Short name T938
Test name
Test status
Simulation time 11574072398 ps
CPU time 40.5 seconds
Started Jun 23 05:40:06 PM PDT 24
Finished Jun 23 05:40:47 PM PDT 24
Peak memory 200584 kb
Host smart-7d6eecae-984f-4ff3-bc08-5343f360a2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129700443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.129700443
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.3397209155
Short name T152
Test name
Test status
Simulation time 482769335095 ps
CPU time 503.93 seconds
Started Jun 23 05:40:12 PM PDT 24
Finished Jun 23 05:48:37 PM PDT 24
Peak memory 200628 kb
Host smart-3350a32c-f2e5-4056-9b7d-c08625cae972
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397209155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.3397209155
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.2870091004
Short name T29
Test name
Test status
Simulation time 93366605470 ps
CPU time 282.36 seconds
Started Jun 23 05:40:13 PM PDT 24
Finished Jun 23 05:44:56 PM PDT 24
Peak memory 209364 kb
Host smart-806549a7-1093-47e0-be1e-136381f0c413
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870091004 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.2870091004
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.2020203792
Short name T855
Test name
Test status
Simulation time 721208140 ps
CPU time 2.5 seconds
Started Jun 23 05:40:10 PM PDT 24
Finished Jun 23 05:40:13 PM PDT 24
Peak memory 199472 kb
Host smart-bb19493c-b172-4b74-bccc-06fe201cbe48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020203792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.2020203792
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.1794610940
Short name T407
Test name
Test status
Simulation time 59501412310 ps
CPU time 99.86 seconds
Started Jun 23 05:40:07 PM PDT 24
Finished Jun 23 05:41:47 PM PDT 24
Peak memory 200760 kb
Host smart-0d657da2-fe51-4838-b57d-1f55207015a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794610940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.1794610940
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.1012117313
Short name T220
Test name
Test status
Simulation time 55346405051 ps
CPU time 16.2 seconds
Started Jun 23 05:44:02 PM PDT 24
Finished Jun 23 05:44:19 PM PDT 24
Peak memory 200716 kb
Host smart-eb4b3d68-bc1e-4acb-9dd5-a45e0f99364f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012117313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.1012117313
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.1963132171
Short name T102
Test name
Test status
Simulation time 62869771381 ps
CPU time 232.44 seconds
Started Jun 23 05:44:04 PM PDT 24
Finished Jun 23 05:47:57 PM PDT 24
Peak memory 210024 kb
Host smart-ea88b88e-f650-4080-a5a8-c5e59ae720ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963132171 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.1963132171
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.2075148904
Short name T782
Test name
Test status
Simulation time 122769176419 ps
CPU time 37.1 seconds
Started Jun 23 05:44:04 PM PDT 24
Finished Jun 23 05:44:41 PM PDT 24
Peak memory 200548 kb
Host smart-a493541d-ebc5-4fe7-a6ed-c41bd5ac0c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075148904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.2075148904
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.3023109783
Short name T160
Test name
Test status
Simulation time 33147351348 ps
CPU time 10.6 seconds
Started Jun 23 05:44:03 PM PDT 24
Finished Jun 23 05:44:14 PM PDT 24
Peak memory 200724 kb
Host smart-8b1cb07a-d572-41a6-9d22-43ad77545a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023109783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.3023109783
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.3681762961
Short name T1028
Test name
Test status
Simulation time 74912339307 ps
CPU time 34.77 seconds
Started Jun 23 05:44:01 PM PDT 24
Finished Jun 23 05:44:36 PM PDT 24
Peak memory 200580 kb
Host smart-c203085a-10e7-4684-8d9d-4b241f6b1517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681762961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.3681762961
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.3406192202
Short name T842
Test name
Test status
Simulation time 77770867750 ps
CPU time 901.69 seconds
Started Jun 23 05:44:09 PM PDT 24
Finished Jun 23 05:59:11 PM PDT 24
Peak memory 217320 kb
Host smart-b65dfcbf-4446-4666-8891-41626e4d8378
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406192202 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.3406192202
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.2243078582
Short name T558
Test name
Test status
Simulation time 26349238910 ps
CPU time 17.52 seconds
Started Jun 23 05:44:04 PM PDT 24
Finished Jun 23 05:44:21 PM PDT 24
Peak memory 200640 kb
Host smart-7f18da6f-5d25-4f66-8066-39c8f925a069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243078582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.2243078582
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.319280857
Short name T101
Test name
Test status
Simulation time 43504076462 ps
CPU time 514.16 seconds
Started Jun 23 05:44:01 PM PDT 24
Finished Jun 23 05:52:36 PM PDT 24
Peak memory 214492 kb
Host smart-9b91eed1-4436-4edb-99ef-110ff7c785ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319280857 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.319280857
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.3756554096
Short name T1009
Test name
Test status
Simulation time 161555001004 ps
CPU time 127.14 seconds
Started Jun 23 05:44:04 PM PDT 24
Finished Jun 23 05:46:11 PM PDT 24
Peak memory 200716 kb
Host smart-2ce6e361-668d-4b0a-ab99-e3cc9c555b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756554096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.3756554096
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.882732103
Short name T913
Test name
Test status
Simulation time 10423463251 ps
CPU time 18.09 seconds
Started Jun 23 05:44:09 PM PDT 24
Finished Jun 23 05:44:27 PM PDT 24
Peak memory 200704 kb
Host smart-cf290ab7-3bc0-4d28-b9f9-3efd6112dba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882732103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.882732103
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.807168322
Short name T136
Test name
Test status
Simulation time 22386433078 ps
CPU time 14.75 seconds
Started Jun 23 05:44:12 PM PDT 24
Finished Jun 23 05:44:27 PM PDT 24
Peak memory 200752 kb
Host smart-cfc5a5b1-3cc0-40f2-8cad-3901069c11ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807168322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.807168322
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.2504286096
Short name T18
Test name
Test status
Simulation time 71327551131 ps
CPU time 439.16 seconds
Started Jun 23 05:44:12 PM PDT 24
Finished Jun 23 05:51:31 PM PDT 24
Peak memory 211532 kb
Host smart-592185f5-fb65-4f54-9310-f75361f3024a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504286096 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.2504286096
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.1803573402
Short name T122
Test name
Test status
Simulation time 200654413259 ps
CPU time 208.83 seconds
Started Jun 23 05:44:09 PM PDT 24
Finished Jun 23 05:47:38 PM PDT 24
Peak memory 200716 kb
Host smart-5d77a1ed-7d70-42c5-8fdc-c2b3a8616568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803573402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.1803573402
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.554456748
Short name T709
Test name
Test status
Simulation time 52826069556 ps
CPU time 546.91 seconds
Started Jun 23 05:44:09 PM PDT 24
Finished Jun 23 05:53:16 PM PDT 24
Peak memory 209000 kb
Host smart-7b76d1a2-5456-48b7-b8cd-cbfba7962793
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554456748 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.554456748
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.1166140721
Short name T415
Test name
Test status
Simulation time 37646192482 ps
CPU time 13.34 seconds
Started Jun 23 05:44:10 PM PDT 24
Finished Jun 23 05:44:24 PM PDT 24
Peak memory 200756 kb
Host smart-b17f1471-c62c-46ab-89e9-9513d7f646e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166140721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.1166140721
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.1649978294
Short name T483
Test name
Test status
Simulation time 13879765 ps
CPU time 0.58 seconds
Started Jun 23 05:40:09 PM PDT 24
Finished Jun 23 05:40:09 PM PDT 24
Peak memory 196136 kb
Host smart-34dfa560-e5a0-4ff6-b1f7-2826d2850241
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649978294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.1649978294
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.366446479
Short name T393
Test name
Test status
Simulation time 22336256012 ps
CPU time 35.01 seconds
Started Jun 23 05:40:13 PM PDT 24
Finished Jun 23 05:40:48 PM PDT 24
Peak memory 200664 kb
Host smart-77ebbd26-a3f0-47c7-a3be-693d29ce6c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366446479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.366446479
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.2766523367
Short name T621
Test name
Test status
Simulation time 39471150846 ps
CPU time 17.89 seconds
Started Jun 23 05:40:17 PM PDT 24
Finished Jun 23 05:40:36 PM PDT 24
Peak memory 200660 kb
Host smart-a9779c22-4b4b-453c-ac49-136e5aeff588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766523367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.2766523367
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.1742697789
Short name T1013
Test name
Test status
Simulation time 124290938052 ps
CPU time 112.32 seconds
Started Jun 23 05:40:11 PM PDT 24
Finished Jun 23 05:42:05 PM PDT 24
Peak memory 200664 kb
Host smart-b26de150-42f5-4d0b-a03e-70d2be250e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742697789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.1742697789
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.3429638755
Short name T640
Test name
Test status
Simulation time 12161275060 ps
CPU time 6.63 seconds
Started Jun 23 05:40:10 PM PDT 24
Finished Jun 23 05:40:17 PM PDT 24
Peak memory 200620 kb
Host smart-df6136fa-5cf4-4e52-81cb-f5da32945853
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429638755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.3429638755
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.2971683361
Short name T1003
Test name
Test status
Simulation time 172195648569 ps
CPU time 109.88 seconds
Started Jun 23 05:40:17 PM PDT 24
Finished Jun 23 05:42:08 PM PDT 24
Peak memory 200632 kb
Host smart-cfabb843-54ca-4f8a-abf4-3f4f5436cf49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2971683361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.2971683361
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.852530425
Short name T802
Test name
Test status
Simulation time 8633298123 ps
CPU time 4.55 seconds
Started Jun 23 05:40:20 PM PDT 24
Finished Jun 23 05:40:25 PM PDT 24
Peak memory 199172 kb
Host smart-6950b2dd-d9ee-405a-ab99-6d86d35d7718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852530425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.852530425
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_perf.3253553461
Short name T1001
Test name
Test status
Simulation time 29073168325 ps
CPU time 355.21 seconds
Started Jun 23 05:40:13 PM PDT 24
Finished Jun 23 05:46:09 PM PDT 24
Peak memory 200580 kb
Host smart-c4562cfc-2f5f-4bb6-929b-61c8146d3573
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3253553461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.3253553461
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.99042874
Short name T898
Test name
Test status
Simulation time 3695328637 ps
CPU time 15.14 seconds
Started Jun 23 05:40:13 PM PDT 24
Finished Jun 23 05:40:29 PM PDT 24
Peak memory 199028 kb
Host smart-6b6dc969-01ff-48c8-92fc-e67337ec48c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=99042874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.99042874
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.757717694
Short name T1062
Test name
Test status
Simulation time 41236965557 ps
CPU time 4.49 seconds
Started Jun 23 05:40:13 PM PDT 24
Finished Jun 23 05:40:18 PM PDT 24
Peak memory 199108 kb
Host smart-32f07553-4c4e-4c55-b1d6-7d80c5e85cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757717694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.757717694
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.2568585713
Short name T244
Test name
Test status
Simulation time 2646422671 ps
CPU time 5.04 seconds
Started Jun 23 05:40:18 PM PDT 24
Finished Jun 23 05:40:24 PM PDT 24
Peak memory 196432 kb
Host smart-4f306f33-4117-4584-82b8-993e418617c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568585713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.2568585713
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.2342884084
Short name T343
Test name
Test status
Simulation time 5541565222 ps
CPU time 6.83 seconds
Started Jun 23 05:40:10 PM PDT 24
Finished Jun 23 05:40:18 PM PDT 24
Peak memory 200480 kb
Host smart-ba725fc1-236e-4428-bcdf-7d251f840f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342884084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.2342884084
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.1270097207
Short name T863
Test name
Test status
Simulation time 358404482555 ps
CPU time 234.31 seconds
Started Jun 23 05:40:11 PM PDT 24
Finished Jun 23 05:44:05 PM PDT 24
Peak memory 200680 kb
Host smart-a11006a7-897a-4e8f-bd2b-2fe40b7455a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270097207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.1270097207
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.644679633
Short name T551
Test name
Test status
Simulation time 63335847941 ps
CPU time 763.44 seconds
Started Jun 23 05:40:17 PM PDT 24
Finished Jun 23 05:53:01 PM PDT 24
Peak memory 216124 kb
Host smart-2c01b378-2f53-4f45-b0a2-a1f391a51ec8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644679633 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.644679633
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.1363202552
Short name T331
Test name
Test status
Simulation time 930104383 ps
CPU time 2.65 seconds
Started Jun 23 05:40:16 PM PDT 24
Finished Jun 23 05:40:19 PM PDT 24
Peak memory 199008 kb
Host smart-c2e2b43b-c94d-49a8-ac41-9082eb0fb105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363202552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.1363202552
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.1866704186
Short name T246
Test name
Test status
Simulation time 236752364638 ps
CPU time 50.14 seconds
Started Jun 23 05:40:12 PM PDT 24
Finished Jun 23 05:41:02 PM PDT 24
Peak memory 200720 kb
Host smart-0556dce9-db4b-4f8c-9dab-37de16a8b5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866704186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.1866704186
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.206557772
Short name T500
Test name
Test status
Simulation time 51671855359 ps
CPU time 24.6 seconds
Started Jun 23 05:44:09 PM PDT 24
Finished Jun 23 05:44:34 PM PDT 24
Peak memory 200760 kb
Host smart-964eb0b4-f0d7-4017-aff6-dcee10bb83cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206557772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.206557772
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.3575103327
Short name T49
Test name
Test status
Simulation time 59347969589 ps
CPU time 286.89 seconds
Started Jun 23 05:44:10 PM PDT 24
Finished Jun 23 05:48:58 PM PDT 24
Peak memory 210612 kb
Host smart-ffba0c39-4d21-40a6-92bf-2b47a1f123f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575103327 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.3575103327
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.3987831959
Short name T870
Test name
Test status
Simulation time 41073085694 ps
CPU time 77.84 seconds
Started Jun 23 05:44:12 PM PDT 24
Finished Jun 23 05:45:30 PM PDT 24
Peak memory 200688 kb
Host smart-78b4cc99-97a2-4d01-aa61-6e4e7c593c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987831959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.3987831959
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.427975300
Short name T986
Test name
Test status
Simulation time 10774640317 ps
CPU time 116.33 seconds
Started Jun 23 05:44:12 PM PDT 24
Finished Jun 23 05:46:09 PM PDT 24
Peak memory 209016 kb
Host smart-e06b42e4-ff58-4d4c-81b9-ca5d58869d13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427975300 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.427975300
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.3420724377
Short name T179
Test name
Test status
Simulation time 12810689455 ps
CPU time 26.22 seconds
Started Jun 23 05:44:10 PM PDT 24
Finished Jun 23 05:44:36 PM PDT 24
Peak memory 200696 kb
Host smart-2cceaef4-69a1-4a3e-beb9-4617ffc26528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420724377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.3420724377
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.416062612
Short name T1096
Test name
Test status
Simulation time 117249155539 ps
CPU time 58.98 seconds
Started Jun 23 05:44:13 PM PDT 24
Finished Jun 23 05:45:13 PM PDT 24
Peak memory 200752 kb
Host smart-c2e3dfea-de81-4dfa-82fe-5fc72ea2c206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416062612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.416062612
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.3072073277
Short name T499
Test name
Test status
Simulation time 23120651120 ps
CPU time 233.52 seconds
Started Jun 23 05:44:16 PM PDT 24
Finished Jun 23 05:48:10 PM PDT 24
Peak memory 217040 kb
Host smart-8c25a1f2-7f1e-4d83-9a5f-b70b37f2cf43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072073277 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.3072073277
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.1798284375
Short name T416
Test name
Test status
Simulation time 25502329014 ps
CPU time 22.34 seconds
Started Jun 23 05:44:11 PM PDT 24
Finished Jun 23 05:44:34 PM PDT 24
Peak memory 200660 kb
Host smart-a4220e85-a9be-4a78-a861-c7899f4fc53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798284375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.1798284375
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.2111291573
Short name T761
Test name
Test status
Simulation time 108308699611 ps
CPU time 1152.76 seconds
Started Jun 23 05:44:12 PM PDT 24
Finished Jun 23 06:03:25 PM PDT 24
Peak memory 215164 kb
Host smart-3c144880-b121-4b80-a184-080601b31d2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111291573 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.2111291573
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.2071545157
Short name T441
Test name
Test status
Simulation time 108221070618 ps
CPU time 35.65 seconds
Started Jun 23 05:44:14 PM PDT 24
Finished Jun 23 05:44:50 PM PDT 24
Peak memory 200736 kb
Host smart-5ef89d4b-3fff-40db-bda6-c57ee4ccfc86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071545157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.2071545157
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.1281105716
Short name T529
Test name
Test status
Simulation time 23303520344 ps
CPU time 230.19 seconds
Started Jun 23 05:44:15 PM PDT 24
Finished Jun 23 05:48:06 PM PDT 24
Peak memory 217140 kb
Host smart-50d44f4a-8bf2-42d4-a012-9bda07354885
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281105716 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.1281105716
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.170882565
Short name T555
Test name
Test status
Simulation time 25028891972 ps
CPU time 16.65 seconds
Started Jun 23 05:44:12 PM PDT 24
Finished Jun 23 05:44:29 PM PDT 24
Peak memory 200764 kb
Host smart-7833ea18-16ff-4324-a576-e0658a379067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170882565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.170882565
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.482347032
Short name T47
Test name
Test status
Simulation time 73497488433 ps
CPU time 1112.47 seconds
Started Jun 23 05:44:20 PM PDT 24
Finished Jun 23 06:02:53 PM PDT 24
Peak memory 225348 kb
Host smart-1759a03e-c46c-442e-81e5-199c1d272560
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482347032 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.482347032
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.2476648861
Short name T700
Test name
Test status
Simulation time 9086447373 ps
CPU time 15.53 seconds
Started Jun 23 05:44:24 PM PDT 24
Finished Jun 23 05:44:40 PM PDT 24
Peak memory 200896 kb
Host smart-8cdb4ed8-07e1-4760-a7e7-015da398bddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476648861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.2476648861
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.509623644
Short name T825
Test name
Test status
Simulation time 153400780868 ps
CPU time 106.53 seconds
Started Jun 23 05:44:16 PM PDT 24
Finished Jun 23 05:46:03 PM PDT 24
Peak memory 200720 kb
Host smart-a97f5b09-09af-4c6e-b2d7-2a0d2104f992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509623644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.509623644
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.1328456127
Short name T28
Test name
Test status
Simulation time 42391318394 ps
CPU time 387.26 seconds
Started Jun 23 05:44:14 PM PDT 24
Finished Jun 23 05:50:42 PM PDT 24
Peak memory 217080 kb
Host smart-106f0055-807d-4a55-adda-63b70240f4a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328456127 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.1328456127
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_fifo_full.883612100
Short name T405
Test name
Test status
Simulation time 20828273463 ps
CPU time 13.16 seconds
Started Jun 23 05:40:18 PM PDT 24
Finished Jun 23 05:40:33 PM PDT 24
Peak memory 200736 kb
Host smart-51e2262d-74ea-4b6d-bc89-a77e39f8547e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883612100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.883612100
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.3914146691
Short name T473
Test name
Test status
Simulation time 115197215390 ps
CPU time 50.46 seconds
Started Jun 23 05:40:18 PM PDT 24
Finished Jun 23 05:41:09 PM PDT 24
Peak memory 200708 kb
Host smart-e88db3a1-f5d9-4391-b8a7-132261a6d406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914146691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.3914146691
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.2791362056
Short name T1099
Test name
Test status
Simulation time 17618215554 ps
CPU time 27.12 seconds
Started Jun 23 05:40:19 PM PDT 24
Finished Jun 23 05:40:47 PM PDT 24
Peak memory 200756 kb
Host smart-bbbbd706-cb10-445d-b5af-990073a5a65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791362056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.2791362056
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.3548239817
Short name T448
Test name
Test status
Simulation time 50716081161 ps
CPU time 74.85 seconds
Started Jun 23 05:40:17 PM PDT 24
Finished Jun 23 05:41:32 PM PDT 24
Peak memory 200672 kb
Host smart-3aa3c5b9-ccfe-4165-b081-0bacfb1f4267
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548239817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.3548239817
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.531673302
Short name T377
Test name
Test status
Simulation time 176323369751 ps
CPU time 331.29 seconds
Started Jun 23 05:40:19 PM PDT 24
Finished Jun 23 05:45:51 PM PDT 24
Peak memory 200616 kb
Host smart-e65b41a3-6ce1-40ee-bd95-41e382c089d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=531673302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.531673302
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.3748553639
Short name T351
Test name
Test status
Simulation time 10069388984 ps
CPU time 7.86 seconds
Started Jun 23 05:40:17 PM PDT 24
Finished Jun 23 05:40:25 PM PDT 24
Peak memory 199208 kb
Host smart-b1cc403a-746e-4dc5-bebe-3af61c3fb2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748553639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.3748553639
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_perf.623750
Short name T934
Test name
Test status
Simulation time 8704969189 ps
CPU time 240.04 seconds
Started Jun 23 05:40:20 PM PDT 24
Finished Jun 23 05:44:21 PM PDT 24
Peak memory 200736 kb
Host smart-7b6eb461-ae27-46ed-9497-a26f28f88227
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=623750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.623750
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.427681619
Short name T1014
Test name
Test status
Simulation time 7071048749 ps
CPU time 17.56 seconds
Started Jun 23 05:40:16 PM PDT 24
Finished Jun 23 05:40:34 PM PDT 24
Peak memory 200100 kb
Host smart-b88f3df2-9158-48c6-8153-6a2fad16cf06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=427681619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.427681619
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.2451921113
Short name T169
Test name
Test status
Simulation time 17491426331 ps
CPU time 14.51 seconds
Started Jun 23 05:40:20 PM PDT 24
Finished Jun 23 05:40:35 PM PDT 24
Peak memory 199680 kb
Host smart-87bb354d-a9f4-499d-ab4f-979a8379f06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451921113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.2451921113
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.4020306867
Short name T1022
Test name
Test status
Simulation time 4358543485 ps
CPU time 6.24 seconds
Started Jun 23 05:40:17 PM PDT 24
Finished Jun 23 05:40:24 PM PDT 24
Peak memory 196812 kb
Host smart-c1ac7b71-d67a-4dc1-9381-a0bb183e5f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020306867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.4020306867
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.1111451552
Short name T858
Test name
Test status
Simulation time 578314649 ps
CPU time 1.57 seconds
Started Jun 23 05:40:11 PM PDT 24
Finished Jun 23 05:40:13 PM PDT 24
Peak memory 200656 kb
Host smart-ecd0818d-9b79-4753-bd59-9139e28142ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111451552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.1111451552
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.1029402656
Short name T313
Test name
Test status
Simulation time 156774712235 ps
CPU time 548.32 seconds
Started Jun 23 05:40:18 PM PDT 24
Finished Jun 23 05:49:27 PM PDT 24
Peak memory 200872 kb
Host smart-cb7dacff-b7aa-4d3c-b6b8-1f3be1f9e7d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029402656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.1029402656
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.1480544013
Short name T311
Test name
Test status
Simulation time 87104153328 ps
CPU time 474.39 seconds
Started Jun 23 05:40:21 PM PDT 24
Finished Jun 23 05:48:16 PM PDT 24
Peak memory 217172 kb
Host smart-b673ece6-1c68-47c6-976b-04293ed7d251
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480544013 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.1480544013
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.1720235402
Short name T271
Test name
Test status
Simulation time 6657301749 ps
CPU time 16.74 seconds
Started Jun 23 05:40:19 PM PDT 24
Finished Jun 23 05:40:37 PM PDT 24
Peak memory 200176 kb
Host smart-cb58e157-9656-4438-97d8-700ba41a7259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720235402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.1720235402
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.3845922630
Short name T292
Test name
Test status
Simulation time 167847657802 ps
CPU time 78.46 seconds
Started Jun 23 05:40:09 PM PDT 24
Finished Jun 23 05:41:28 PM PDT 24
Peak memory 200700 kb
Host smart-114e92a7-3b3a-4215-b9ad-d31f4afe232f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845922630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.3845922630
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.2701183655
Short name T597
Test name
Test status
Simulation time 103178837470 ps
CPU time 458.88 seconds
Started Jun 23 05:44:16 PM PDT 24
Finished Jun 23 05:51:56 PM PDT 24
Peak memory 216824 kb
Host smart-031879d8-c4e5-4b86-a09f-6cf428a56fc4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701183655 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.2701183655
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.3390131301
Short name T203
Test name
Test status
Simulation time 168283401552 ps
CPU time 19.22 seconds
Started Jun 23 05:44:16 PM PDT 24
Finished Jun 23 05:44:36 PM PDT 24
Peak memory 200716 kb
Host smart-693a9a01-9c7b-4da2-9c8d-b929c7baddd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390131301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.3390131301
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.216884018
Short name T249
Test name
Test status
Simulation time 32543043821 ps
CPU time 466.45 seconds
Started Jun 23 05:44:18 PM PDT 24
Finished Jun 23 05:52:05 PM PDT 24
Peak memory 217188 kb
Host smart-1329b350-2c9f-443f-a89b-66032d5341cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216884018 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.216884018
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.1215577625
Short name T859
Test name
Test status
Simulation time 104145765376 ps
CPU time 46.08 seconds
Started Jun 23 05:44:25 PM PDT 24
Finished Jun 23 05:45:12 PM PDT 24
Peak memory 200836 kb
Host smart-214c711f-9c08-4fae-a762-ec0d3680daed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215577625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.1215577625
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.2564321626
Short name T854
Test name
Test status
Simulation time 100907681661 ps
CPU time 1134.67 seconds
Started Jun 23 05:44:15 PM PDT 24
Finished Jun 23 06:03:10 PM PDT 24
Peak memory 225328 kb
Host smart-f306f06c-2971-42f6-aca7-5641bc7ed9c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564321626 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.2564321626
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.116067131
Short name T955
Test name
Test status
Simulation time 115569003311 ps
CPU time 168.27 seconds
Started Jun 23 05:44:24 PM PDT 24
Finished Jun 23 05:47:13 PM PDT 24
Peak memory 200884 kb
Host smart-77174426-417a-43c3-8572-654c31d3b070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116067131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.116067131
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.980536461
Short name T960
Test name
Test status
Simulation time 10131617017 ps
CPU time 98.95 seconds
Started Jun 23 05:44:24 PM PDT 24
Finished Jun 23 05:46:03 PM PDT 24
Peak memory 216440 kb
Host smart-d2867f39-24b4-477b-bf8a-4204ca1aff99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980536461 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.980536461
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.3183271526
Short name T848
Test name
Test status
Simulation time 219795101996 ps
CPU time 158.53 seconds
Started Jun 23 05:44:17 PM PDT 24
Finished Jun 23 05:46:56 PM PDT 24
Peak memory 200712 kb
Host smart-266a8295-3a06-46cf-996c-31a7b4b1e475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183271526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.3183271526
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.772822548
Short name T195
Test name
Test status
Simulation time 233998475515 ps
CPU time 1042.77 seconds
Started Jun 23 05:44:17 PM PDT 24
Finished Jun 23 06:01:40 PM PDT 24
Peak memory 217148 kb
Host smart-d48a649d-9bb4-4837-8328-77556bdfaaa7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772822548 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.772822548
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.1535858745
Short name T941
Test name
Test status
Simulation time 129298279235 ps
CPU time 55.07 seconds
Started Jun 23 05:44:14 PM PDT 24
Finished Jun 23 05:45:09 PM PDT 24
Peak memory 200748 kb
Host smart-64c68cf0-8110-4bfc-b115-33a9fd6c5c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535858745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.1535858745
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.133135671
Short name T443
Test name
Test status
Simulation time 27214154010 ps
CPU time 259.66 seconds
Started Jun 23 05:44:20 PM PDT 24
Finished Jun 23 05:48:40 PM PDT 24
Peak memory 217080 kb
Host smart-8483440c-18c1-4ab5-b9e6-ef5b743a5812
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133135671 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.133135671
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.1505338602
Short name T323
Test name
Test status
Simulation time 123968518152 ps
CPU time 61.7 seconds
Started Jun 23 05:44:15 PM PDT 24
Finished Jun 23 05:45:17 PM PDT 24
Peak memory 200740 kb
Host smart-c98e0c98-bbe7-48f3-8b37-ce1858d723c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505338602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.1505338602
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.1087139211
Short name T145
Test name
Test status
Simulation time 172831491339 ps
CPU time 691.02 seconds
Started Jun 23 05:44:17 PM PDT 24
Finished Jun 23 05:55:49 PM PDT 24
Peak memory 217124 kb
Host smart-ce3319cf-1a47-436f-b241-64287c344d14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087139211 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.1087139211
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.1986151615
Short name T125
Test name
Test status
Simulation time 37537088232 ps
CPU time 17.19 seconds
Started Jun 23 05:44:14 PM PDT 24
Finished Jun 23 05:44:32 PM PDT 24
Peak memory 200608 kb
Host smart-69ddf8c0-84ac-41fd-93ee-698bdd39c850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986151615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.1986151615
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.2079289349
Short name T30
Test name
Test status
Simulation time 84074565921 ps
CPU time 267.65 seconds
Started Jun 23 05:44:24 PM PDT 24
Finished Jun 23 05:48:53 PM PDT 24
Peak memory 217172 kb
Host smart-8d721eb2-d4b3-4bbe-8ec4-03565b4bb18b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079289349 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.2079289349
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.283034719
Short name T890
Test name
Test status
Simulation time 106589691926 ps
CPU time 161.77 seconds
Started Jun 23 05:44:21 PM PDT 24
Finished Jun 23 05:47:04 PM PDT 24
Peak memory 200704 kb
Host smart-9a5eb425-0e5b-4165-81b1-413a2bb39aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283034719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.283034719
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.1706509411
Short name T714
Test name
Test status
Simulation time 11920591081 ps
CPU time 109.27 seconds
Started Jun 23 05:44:19 PM PDT 24
Finished Jun 23 05:46:09 PM PDT 24
Peak memory 216332 kb
Host smart-f824671d-3fd6-42f7-a4e2-31d62d353d1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706509411 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.1706509411
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.1157622991
Short name T726
Test name
Test status
Simulation time 6715439282 ps
CPU time 6.13 seconds
Started Jun 23 05:44:24 PM PDT 24
Finished Jun 23 05:44:31 PM PDT 24
Peak memory 199040 kb
Host smart-365f6fc2-ef93-40aa-8c14-08ac25eb3f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157622991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.1157622991
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.3443912090
Short name T982
Test name
Test status
Simulation time 95101296378 ps
CPU time 260.36 seconds
Started Jun 23 05:44:24 PM PDT 24
Finished Jun 23 05:48:44 PM PDT 24
Peak memory 217188 kb
Host smart-339c1f0c-90df-4601-8b13-326545d7a663
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443912090 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.3443912090
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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