Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100496	1			T1	120		T2	12		T3	2
all_values[1]	100496	1			T1	120		T2	12		T3	2
all_values[2]	100496	1			T1	120		T2	12		T3	2
all_values[3]	100496	1			T1	120		T2	12		T3	2
all_values[4]	100496	1			T1	120		T2	12		T3	2
all_values[5]	100496	1			T1	120		T2	12		T3	2
all_values[6]	100496	1			T1	120		T2	12		T3	2
all_values[7]	100496	1			T1	120		T2	12		T3	2
all_values[8]	100496	1			T1	120		T2	12		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

450159

1

T1

388

T2

66

T3

18

auto[1]

454305

1

T1

692

T2

42

T4

589

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

823516

1

T1

1050

T2

91

T3

13

auto[1]

80948

1

T1

30

T2

17

T3

5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	30211	1			T1	4		T2	2		T4	4
all_values[0]	auto[0]	auto[1]	17539	1			T1	7		T2	8		T3	2
all_values[0]	auto[1]	auto[0]	30106	1			T1	103		T2	2		T4	23
all_values[0]	auto[1]	auto[1]	22640	1			T1	6		T4	41		T5	8
all_values[1]	auto[0]	auto[0]	48942	1			T1	115		T2	11		T3	2
all_values[1]	auto[0]	auto[1]	1663	1			T2	1		T4	26		T16	19
all_values[1]	auto[1]	auto[0]	48592	1			T1	2		T4	21		T5	19
all_values[1]	auto[1]	auto[1]	1299	1			T1	3		T4	24		T78	3
all_values[2]	auto[0]	auto[0]	47110	1			T1	5		T2	7		T3	1
all_values[2]	auto[0]	auto[1]	2224	1			T1	1		T2	5		T3	1
all_values[2]	auto[1]	auto[0]	49002	1			T1	111		T4	107		T5	1
all_values[2]	auto[1]	auto[1]	2160	1			T1	3		T4	4		T5	1
all_values[3]	auto[0]	auto[0]	49235	1			T1	109		T2	3		T3	2
all_values[3]	auto[0]	auto[1]	273	1			T4	4		T11	3		T12	2
all_values[3]	auto[1]	auto[0]	50713	1			T1	11		T2	9		T4	64
all_values[3]	auto[1]	auto[1]	275	1			T4	2		T14	6		T15	2
all_values[4]	auto[0]	auto[0]	50193	1			T2	10		T3	2		T4	52
all_values[4]	auto[0]	auto[1]	405	1			T4	3		T14	3		T19	8
all_values[4]	auto[1]	auto[0]	49485	1			T1	120		T2	2		T4	89
all_values[4]	auto[1]	auto[1]	413	1			T4	9		T15	4		T118	2
all_values[5]	auto[0]	auto[0]	52052	1			T1	114		T2	12		T3	2
all_values[5]	auto[0]	auto[1]	176	1			T4	2		T14	4		T15	2
all_values[5]	auto[1]	auto[0]	48110	1			T1	6		T4	12		T5	4
all_values[5]	auto[1]	auto[1]	158	1			T4	1		T14	2		T15	2
all_values[6]	auto[0]	auto[0]	52308	1			T1	11		T2	3		T3	2
all_values[6]	auto[0]	auto[1]	171	1			T4	1		T14	5		T15	2
all_values[6]	auto[1]	auto[0]	47866	1			T1	109		T2	9		T4	74
all_values[6]	auto[1]	auto[1]	151	1			T4	3		T15	3		T107	1
all_values[7]	auto[0]	auto[0]	50748	1			T1	5		T2	1		T3	2
all_values[7]	auto[0]	auto[1]	348	1			T4	1		T14	4		T15	3
all_values[7]	auto[1]	auto[0]	49090	1			T1	115		T2	11		T4	56
all_values[7]	auto[1]	auto[1]	310	1			T4	7		T12	2		T14	2
all_values[8]	auto[0]	auto[0]	32842	1			T1	7		T2	2		T4	36
all_values[8]	auto[0]	auto[1]	13719	1			T1	10		T2	1		T3	2
all_values[8]	auto[1]	auto[0]	36911	1			T1	103		T2	7		T4	10
all_values[8]	auto[1]	auto[1]	17024	1			T2	2		T4	42		T5	1