Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1933	1			T1	1		T2	1		T3	1
auto[BaudRate115200]	1783	1			T1	3		T2	1		T3	1
auto[BaudRate230400]	1736	1			T1	1		T2	1		T4	5
auto[BaudRate128Kbps]	1729	1			T1	1		T2	1		T4	7
auto[BaudRate256Kbps]	1945	1			T1	2		T2	1		T4	3
auto[BaudRate1Mbps]	1585	1			T2	1		T4	5		T7	1
auto[BaudRate1p5Mbps]	1176	1			T1	1		T2	2		T4	13

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1438	1			T7	2		T16	82		T13	8
freqs[25]	837	1			T36	6		T38	12		T285	2
freqs[48]	515	1			T2	8		T134	7		T289	8
freqs[50]	409	1			T5	9		T109	2		T114	7
freqs[100]	1076	1			T1	9		T78	5		T301	2

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	219	1			T7	1		T16	14		T13	8
auto[BaudRate9600]	freqs[25]	134	1			T38	12		T263	1		T154	2
auto[BaudRate9600]	freqs[48]	70	1			T2	1		T31	10		T33	10
auto[BaudRate9600]	freqs[50]	52	1			T5	1		T114	2		T256	1
auto[BaudRate9600]	freqs[100]	199	1			T1	1		T78	1		T115	1
auto[BaudRate115200]	freqs[24]	213	1			T16	7		T119	2		T159	1
auto[BaudRate115200]	freqs[25]	119	1			T36	1		T263	2		T42	1
auto[BaudRate115200]	freqs[48]	80	1			T2	1		T134	1		T289	3
auto[BaudRate115200]	freqs[50]	68	1			T5	1		T142	1		T256	1
auto[BaudRate115200]	freqs[100]	157	1			T1	3		T301	2		T252	1
auto[BaudRate230400]	freqs[24]	218	1			T16	15		T130	2		T119	3
auto[BaudRate230400]	freqs[25]	122	1			T42	1		T154	2		T195	2
auto[BaudRate230400]	freqs[48]	65	1			T2	1		T289	1		T31	12
auto[BaudRate230400]	freqs[50]	69	1			T5	3		T109	1		T114	1
auto[BaudRate230400]	freqs[100]	128	1			T1	1		T78	1		T252	1
auto[BaudRate128Kbps]	freqs[24]	170	1			T16	6		T130	1		T251	1
auto[BaudRate128Kbps]	freqs[25]	143	1			T263	1		T42	1		T154	1
auto[BaudRate128Kbps]	freqs[48]	76	1			T2	1		T31	16		T33	1
auto[BaudRate128Kbps]	freqs[50]	48	1			T5	1		T114	2		T333	6
auto[BaudRate128Kbps]	freqs[100]	130	1			T1	1		T78	2		T252	2
auto[BaudRate256Kbps]	freqs[24]	241	1			T16	6		T130	1		T283	1
auto[BaudRate256Kbps]	freqs[25]	128	1			T36	2		T263	2		T42	1
auto[BaudRate256Kbps]	freqs[48]	59	1			T2	1		T134	4		T289	1
auto[BaudRate256Kbps]	freqs[50]	63	1			T5	3		T114	2		T142	1
auto[BaudRate256Kbps]	freqs[100]	125	1			T1	2		T78	1		T252	2
auto[BaudRate1Mbps]	freqs[24]	224	1			T7	1		T16	21		T130	1
auto[BaudRate1Mbps]	freqs[25]	117	1			T36	3		T285	1		T263	1
auto[BaudRate1Mbps]	freqs[48]	76	1			T2	1		T134	1		T289	1
auto[BaudRate1Mbps]	freqs[50]	45	1			T109	1		T142	1		T333	3
auto[BaudRate1Mbps]	freqs[100]	172	1			T252	3		T39	2		T276	1
auto[BaudRate1p5Mbps]	freqs[25]	74	1			T285	1		T263	1		T154	1
auto[BaudRate1p5Mbps]	freqs[48]	89	1			T2	2		T134	1		T289	2
auto[BaudRate1p5Mbps]	freqs[50]	64	1			T142	1		T333	3		T256	3
auto[BaudRate1p5Mbps]	freqs[100]	165	1			T1	1		T252	1		T39	4

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded