Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.92	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	10	120	92.31

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	10	120	92.31	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	28872691	1			T1	299		T2	12		T4	11924
all_levels[1]	186713	1			T1	90		T2	4		T4	1
all_levels[2]	2229	1			T1	5		T16	11		T37	1
all_levels[3]	850	1			T5	1		T16	3		T37	1
all_levels[4]	577	1			T5	1		T6	1		T16	1
all_levels[5]	427	1			T6	1		T16	1		T37	2
all_levels[6]	344	1			T11	1		T130	1		T131	3
all_levels[7]	282	1			T2	1		T16	2		T78	2
all_levels[8]	223	1			T2	1		T6	1		T37	3
all_levels[9]	217	1			T37	1		T132	1		T15	2
all_levels[10]	192	1			T2	1		T78	2		T133	1
all_levels[11]	165	1			T37	1		T11	1		T134	1
all_levels[12]	146	1			T11	2		T135	1		T132	2
all_levels[13]	159	1			T4	1		T37	1		T11	2
all_levels[14]	119	1			T78	2		T11	1		T134	1
all_levels[15]	129	1			T2	1		T135	2		T132	1
all_levels[16]	94	1			T11	1		T136	1		T132	1
all_levels[17]	97	1			T136	2		T137	2		T119	2
all_levels[18]	66	1			T1	1		T115	1		T138	1
all_levels[19]	84	1			T37	2		T137	1		T120	1
all_levels[20]	72	1			T138	1		T125	1		T124	1
all_levels[21]	76	1			T137	1		T131	1		T139	3
all_levels[22]	61	1			T140	1		T141	1		T142	1
all_levels[23]	66	1			T2	3		T37	1		T11	1
all_levels[24]	48	1			T15	1		T140	1		T138	1
all_levels[25]	51	1			T4	1		T136	1		T130	1
all_levels[26]	51	1			T4	1		T5	1		T11	1
all_levels[27]	66	1			T5	3		T37	1		T11	1
all_levels[28]	38	1			T2	1		T4	1		T119	1
all_levels[29]	42	1			T133	1		T14	1		T15	1
all_levels[30]	39	1			T4	1		T14	2		T143	1
all_levels[31]	29	1			T130	1		T139	1		T144	1
all_levels[32]	26	1			T11	1		T130	1		T138	1
all_levels[33]	22	1			T1	1		T145	1		T138	1
all_levels[34]	25	1			T45	1		T146	1		T102	1
all_levels[35]	16	1			T125	1		T146	1		T147	1
all_levels[36]	15	1			T107	3		T148	2		T101	1
all_levels[37]	17	1			T145	1		T149	1		T150	1
all_levels[38]	19	1			T151	1		T152	1		T153	1
all_levels[39]	23	1			T154	1		T102	1		T155	1
all_levels[40]	19	1			T156	1		T148	1		T157	1
all_levels[41]	17	1			T11	2		T145	1		T158	1
all_levels[42]	20	1			T1	1		T4	1		T11	2
all_levels[43]	23	1			T139	1		T107	3		T138	2
all_levels[44]	13	1			T11	1		T159	1		T107	1
all_levels[45]	17	1			T16	1		T160	1		T161	1
all_levels[46]	10	1			T16	1		T11	1		T162	1
all_levels[47]	19	1			T134	1		T159	1		T163	1
all_levels[48]	14	1			T107	1		T164	1		T165	1
all_levels[49]	4	1			T136	1		T140	1		T166	1
all_levels[50]	13	1			T137	5		T167	1		T168	2
all_levels[51]	15	1			T50	1		T168	1		T169	1
all_levels[52]	8	1			T170	1		T171	1		T172	1
all_levels[53]	9	1			T173	4		T174	1		T175	1
all_levels[54]	13	1			T138	1		T158	1		T51	1
all_levels[55]	15	1			T176	1		T177	6		T178	2
all_levels[56]	2	1			T179	1		T56	1		-	-
all_levels[57]	8	1			T160	1		T138	1		T124	1
all_levels[58]	6	1			T124	1		T180	1		T181	1
all_levels[59]	4	1			T182	1		T180	1		T183	1
all_levels[60]	6	1			T49	1		T147	1		T184	1
all_levels[61]	13	1			T139	2		T185	1		T186	1
all_levels[62]	5	1			T187	2		T54	1		T188	2
all_levels[63]	7	1			T54	1		T189	2		T190	2
all_levels[64]	112	1			T11	2		T120	2		T191	2

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29062409

1

T1

397

T2

20

T4

11881

auto[1]

4589

1

T2

4

T4

50

T5

5

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	10	120	92.31	10

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[24]]	[auto[1]]	0	1	1
[all_levels[33]]	[auto[1]]	0	1	1
[all_levels[35]]	[auto[1]]	0	1	1
[all_levels[49]]	[auto[1]]	0	1	1
[all_levels[52]]	[auto[1]]	0	1	1
[all_levels[56] , all_levels[57] , all_levels[58] , all_levels[59] , all_levels[60]]	[auto[1]]	--	--	5

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	28868557	1			T1	299		T2	10		T4	11874
all_levels[0]	auto[1]	4134	1			T2	2		T4	50		T5	4
all_levels[1]	auto[0]	186653	1			T1	90		T2	4		T4	1
all_levels[1]	auto[1]	60	1			T119	1		T191	3		T192	1
all_levels[2]	auto[0]	2192	1			T1	5		T16	11		T37	1
all_levels[2]	auto[1]	37	1			T193	2		T194	1		T170	1
all_levels[3]	auto[0]	833	1			T5	1		T16	3		T37	1
all_levels[3]	auto[1]	17	1			T195	1		T107	1		T196	1
all_levels[4]	auto[0]	554	1			T5	1		T6	1		T16	1
all_levels[4]	auto[1]	23	1			T50	2		T102	1		T197	2
all_levels[5]	auto[0]	402	1			T6	1		T16	1		T37	1
all_levels[5]	auto[1]	25	1			T37	1		T144	2		T198	1
all_levels[6]	auto[0]	332	1			T11	1		T130	1		T131	2
all_levels[6]	auto[1]	12	1			T131	1		T199	1		T200	1
all_levels[7]	auto[0]	264	1			T2	1		T16	2		T78	2
all_levels[7]	auto[1]	18	1			T173	1		T157	1		T201	1
all_levels[8]	auto[0]	209	1			T2	1		T6	1		T37	1
all_levels[8]	auto[1]	14	1			T37	2		T195	1		T143	1
all_levels[9]	auto[0]	204	1			T37	1		T132	1		T15	2
all_levels[9]	auto[1]	13	1			T125	1		T202	1		T203	1
all_levels[10]	auto[0]	185	1			T2	1		T78	2		T133	1
all_levels[10]	auto[1]	7	1			T119	1		T204	3		T205	2
all_levels[11]	auto[0]	158	1			T37	1		T11	1		T134	1
all_levels[11]	auto[1]	7	1			T137	1		T195	1		T206	1
all_levels[12]	auto[0]	137	1			T11	2		T135	1		T132	2
all_levels[12]	auto[1]	9	1			T207	1		T208	3		T209	1
all_levels[13]	auto[0]	151	1			T4	1		T37	1		T11	2
all_levels[13]	auto[1]	8	1			T140	1		T210	1		T211	2
all_levels[14]	auto[0]	110	1			T78	2		T11	1		T134	1
all_levels[14]	auto[1]	9	1			T211	1		T212	1		T213	1
all_levels[15]	auto[0]	113	1			T2	1		T135	1		T132	1
all_levels[15]	auto[1]	16	1			T135	1		T198	1		T214	1
all_levels[16]	auto[0]	86	1			T11	1		T136	1		T132	1
all_levels[16]	auto[1]	8	1			T215	1		T90	2		T216	1
all_levels[17]	auto[0]	90	1			T136	1		T137	1		T119	1
all_levels[17]	auto[1]	7	1			T136	1		T137	1		T119	1
all_levels[18]	auto[0]	64	1			T1	1		T115	1		T138	1
all_levels[18]	auto[1]	2	1			T210	1		T90	1		-	-
all_levels[19]	auto[0]	78	1			T37	2		T137	1		T120	1
all_levels[19]	auto[1]	6	1			T217	1		T218	1		T174	1
all_levels[20]	auto[0]	67	1			T138	1		T125	1		T124	1
all_levels[20]	auto[1]	5	1			T219	4		T220	1		-	-
all_levels[21]	auto[0]	69	1			T137	1		T131	1		T139	3
all_levels[21]	auto[1]	7	1			T160	1		T208	1		T221	1
all_levels[22]	auto[0]	57	1			T140	1		T141	1		T142	1
all_levels[22]	auto[1]	4	1			T222	1		T223	1		T224	1
all_levels[23]	auto[0]	59	1			T2	1		T37	1		T11	1
all_levels[23]	auto[1]	7	1			T2	2		T131	1		T225	1
all_levels[24]	auto[0]	48	1			T15	1		T140	1		T138	1
all_levels[25]	auto[0]	45	1			T4	1		T136	1		T130	1
all_levels[25]	auto[1]	6	1			T140	2		T226	1		T227	1
all_levels[26]	auto[0]	41	1			T4	1		T5	1		T11	1
all_levels[26]	auto[1]	10	1			T152	2		T210	3		T187	1
all_levels[27]	auto[0]	54	1			T5	2		T37	1		T11	1
all_levels[27]	auto[1]	12	1			T5	1		T162	1		T228	3
all_levels[28]	auto[0]	30	1			T2	1		T4	1		T119	1
all_levels[28]	auto[1]	8	1			T229	4		T179	3		T230	1
all_levels[29]	auto[0]	37	1			T133	1		T14	1		T15	1
all_levels[29]	auto[1]	5	1			T231	2		T232	1		T233	2
all_levels[30]	auto[0]	36	1			T4	1		T14	1		T143	1
all_levels[30]	auto[1]	3	1			T14	1		T234	2		-	-
all_levels[31]	auto[0]	24	1			T130	1		T139	1		T144	1
all_levels[31]	auto[1]	5	1			T125	1		T235	1		T236	1
all_levels[32]	auto[0]	22	1			T11	1		T130	1		T138	1
all_levels[32]	auto[1]	4	1			T102	2		T171	2		-	-
all_levels[33]	auto[0]	22	1			T1	1		T145	1		T138	1
all_levels[34]	auto[0]	21	1			T45	1		T146	1		T102	1
all_levels[34]	auto[1]	4	1			T201	1		T237	1		T238	2
all_levels[35]	auto[0]	16	1			T125	1		T146	1		T147	1
all_levels[36]	auto[0]	13	1			T107	1		T148	2		T101	1
all_levels[36]	auto[1]	2	1			T107	2		-	-		-	-
all_levels[37]	auto[0]	16	1			T145	1		T149	1		T150	1
all_levels[37]	auto[1]	1	1			T239	1		-	-		-	-
all_levels[38]	auto[0]	18	1			T151	1		T152	1		T153	1
all_levels[38]	auto[1]	1	1			T240	1		-	-		-	-
all_levels[39]	auto[0]	16	1			T154	1		T102	1		T155	1
all_levels[39]	auto[1]	7	1			T197	2		T241	2		T55	2
all_levels[40]	auto[0]	18	1			T156	1		T148	1		T157	1
all_levels[40]	auto[1]	1	1			T242	1		-	-		-	-
all_levels[41]	auto[0]	16	1			T11	2		T145	1		T158	1
all_levels[41]	auto[1]	1	1			T183	1		-	-		-	-
all_levels[42]	auto[0]	18	1			T1	1		T4	1		T11	2
all_levels[42]	auto[1]	2	1			T171	1		T243	1		-	-
all_levels[43]	auto[0]	18	1			T139	1		T107	1		T138	2
all_levels[43]	auto[1]	5	1			T107	2		T155	1		T244	2
all_levels[44]	auto[0]	12	1			T11	1		T159	1		T107	1
all_levels[44]	auto[1]	1	1			T162	1		-	-		-	-
all_levels[45]	auto[0]	13	1			T16	1		T160	1		T161	1
all_levels[45]	auto[1]	4	1			T245	2		T246	2		-	-
all_levels[46]	auto[0]	9	1			T16	1		T11	1		T162	1
all_levels[46]	auto[1]	1	1			T247	1		-	-		-	-
all_levels[47]	auto[0]	15	1			T134	1		T159	1		T163	1
all_levels[47]	auto[1]	4	1			T171	4		-	-		-	-
all_levels[48]	auto[0]	12	1			T107	1		T164	1		T165	1
all_levels[48]	auto[1]	2	1			T248	2		-	-		-	-
all_levels[49]	auto[0]	4	1			T136	1		T140	1		T166	1
all_levels[50]	auto[0]	8	1			T137	1		T167	1		T168	1
all_levels[50]	auto[1]	5	1			T137	4		T168	1		-	-
all_levels[51]	auto[0]	9	1			T50	1		T168	1		T169	1
all_levels[51]	auto[1]	6	1			T249	4		T230	2		-	-
all_levels[52]	auto[0]	8	1			T170	1		T171	1		T172	1
all_levels[53]	auto[0]	6	1			T173	1		T174	1		T175	1
all_levels[53]	auto[1]	3	1			T173	3		-	-		-	-
all_levels[54]	auto[0]	10	1			T138	1		T158	1		T51	1
all_levels[54]	auto[1]	3	1			T247	3		-	-		-	-
all_levels[55]	auto[0]	9	1			T176	1		T177	1		T178	2
all_levels[55]	auto[1]	6	1			T177	5		T213	1		-	-
all_levels[56]	auto[0]	2	1			T179	1		T56	1		-	-
all_levels[57]	auto[0]	8	1			T160	1		T138	1		T124	1
all_levels[58]	auto[0]	6	1			T124	1		T180	1		T181	1
all_levels[59]	auto[0]	4	1			T182	1		T180	1		T183	1
all_levels[60]	auto[0]	6	1			T49	1		T147	1		T184	1
all_levels[61]	auto[0]	11	1			T139	1		T185	1		T186	1
all_levels[61]	auto[1]	2	1			T139	1		T179	1		-	-
all_levels[62]	auto[0]	3	1			T187	1		T54	1		T188	1
all_levels[62]	auto[1]	2	1			T187	1		T188	1		-	-
all_levels[63]	auto[0]	5	1			T54	1		T189	1		T190	1
all_levels[63]	auto[1]	2	1			T189	1		T190	1		-	-
all_levels[64]	auto[0]	96	1			T11	2		T120	1		T191	1
all_levels[64]	auto[1]	16	1			T120	1		T191	1		T250	2