Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100496	1			T1	120		T2	12		T3	2
all_pins[1]	100496	1			T1	120		T2	12		T3	2
all_pins[2]	100496	1			T1	120		T2	12		T3	2
all_pins[3]	100496	1			T1	120		T2	12		T3	2
all_pins[4]	100496	1			T1	120		T2	12		T3	2
all_pins[5]	100496	1			T1	120		T2	12		T3	2
all_pins[6]	100496	1			T1	120		T2	12		T3	2
all_pins[7]	100496	1			T1	120		T2	12		T3	2
all_pins[8]	100496	1			T1	120		T2	12		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	859218	1			T1	1068		T2	105		T3	18
values[0x1]	45246	1			T1	12		T2	3		T4	140
transitions[0x0=>0x1]	34543	1			T1	10		T2	3		T4	110
transitions[0x1=>0x0]	34354	1			T1	10		T2	3		T4	110

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	77779	1			T1	114		T2	12		T3	2
all_pins[0]	values[0x1]	22717	1			T1	6		T4	46		T5	8
all_pins[0]	transitions[0x0=>0x1]	22247	1			T1	6		T4	40		T5	8
all_pins[0]	transitions[0x1=>0x0]	829	1			T1	3		T4	18		T78	3
all_pins[1]	values[0x0]	99197	1			T1	117		T2	12		T3	2
all_pins[1]	values[0x1]	1299	1			T1	3		T4	24		T78	3
all_pins[1]	transitions[0x0=>0x1]	1192	1			T1	1		T4	23		T78	3
all_pins[1]	transitions[0x1=>0x0]	2095	1			T1	1		T4	3		T5	1
all_pins[2]	values[0x0]	98294	1			T1	117		T2	12		T3	2
all_pins[2]	values[0x1]	2202	1			T1	3		T4	4		T5	1
all_pins[2]	transitions[0x0=>0x1]	2132	1			T1	3		T4	3		T5	1
all_pins[2]	transitions[0x1=>0x0]	205	1			T4	1		T14	3		T15	2
all_pins[3]	values[0x0]	100221	1			T1	120		T2	12		T3	2
all_pins[3]	values[0x1]	275	1			T4	2		T14	6		T15	2
all_pins[3]	transitions[0x0=>0x1]	237	1			T4	1		T14	6		T193	2
all_pins[3]	transitions[0x1=>0x0]	374	1			T4	8		T15	2		T118	2
all_pins[4]	values[0x0]	100084	1			T1	120		T2	12		T3	2
all_pins[4]	values[0x1]	412	1			T4	9		T15	4		T118	2
all_pins[4]	transitions[0x0=>0x1]	358	1			T4	8		T15	3		T118	2
all_pins[4]	transitions[0x1=>0x0]	140	1			T14	2		T15	1		T19	2
all_pins[5]	values[0x0]	100302	1			T1	120		T2	12		T3	2
all_pins[5]	values[0x1]	194	1			T4	1		T14	2		T15	2
all_pins[5]	transitions[0x0=>0x1]	153	1			T14	2		T15	2		T19	2
all_pins[5]	transitions[0x1=>0x0]	712	1			T2	1		T4	4		T6	5
all_pins[6]	values[0x0]	99743	1			T1	120		T2	11		T3	2
all_pins[6]	values[0x1]	753	1			T2	1		T4	5		T6	5
all_pins[6]	transitions[0x0=>0x1]	711	1			T2	1		T4	3		T6	5
all_pins[6]	transitions[0x1=>0x0]	267	1			T4	5		T12	2		T14	2
all_pins[7]	values[0x0]	100187	1			T1	120		T2	12		T3	2
all_pins[7]	values[0x1]	309	1			T4	7		T12	2		T14	2
all_pins[7]	transitions[0x0=>0x1]	195	1			T4	4		T14	1		T118	2
all_pins[7]	transitions[0x1=>0x0]	16971	1			T2	2		T4	39		T5	1
all_pins[8]	values[0x0]	83411	1			T1	120		T2	10		T3	2
all_pins[8]	values[0x1]	17085	1			T2	2		T4	42		T5	1
all_pins[8]	transitions[0x0=>0x1]	7318	1			T2	2		T4	28		T16	6
all_pins[8]	transitions[0x1=>0x0]	12761	1			T1	6		T4	32		T5	6