Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	6603659	1			T1	23		T2	11		T4	52
all_levels[1]	1544670	1			T1	2		T4	3266		T5	1
all_levels[2]	200449	1			T4	2093		T6	296		T8	2
all_levels[3]	192333	1			T1	353		T4	5		T5	2
all_levels[4]	231870	1			T8	1		T16	621		T252	3744
all_levels[5]	316268	1			T1	2		T5	3		T16	19514
all_levels[6]	203323	1			T4	1		T5	2		T16	349
all_levels[7]	286723	1			T8	2		T16	590		T11	1
all_levels[8]	244744	1			T8	1		T16	568		T11	3
all_levels[9]	207659	1			T1	1		T4	2		T8	1
all_levels[10]	393556	1			T1	3		T5	2		T8	1
all_levels[11]	254141	1			T8	2		T16	573		T11	1
all_levels[12]	203198	1			T16	412		T78	1		T11	1
all_levels[13]	334104	1			T8	2		T16	497		T78	1
all_levels[14]	312935	1			T16	572		T11	2		T136	2
all_levels[15]	385765	1			T1	8		T4	18		T8	2
all_levels[16]	294159	1			T4	6444		T5	2		T16	302
all_levels[17]	175010	1			T1	1		T16	493		T252	3698
all_levels[18]	174796	1			T8	8		T16	579		T78	2
all_levels[19]	273929	1			T1	2		T4	2		T16	581
all_levels[20]	583781	1			T5	1		T8	2		T16	573
all_levels[21]	555515	1			T4	2		T16	560		T252	311942
all_levels[22]	427230	1			T16	311		T78	2		T252	3745
all_levels[23]	251664	1			T16	410		T252	3744		T133	2
all_levels[24]	223498	1			T5	2		T16	620		T252	3566
all_levels[25]	585838	1			T16	656		T11	2		T252	1470
all_levels[26]	209247	1			T4	1		T16	388		T252	1471
all_levels[27]	203645	1			T2	3		T4	2		T16	521
all_levels[28]	160470	1			T4	1		T16	665		T252	1477
all_levels[29]	161796	1			T16	1177		T252	1473		T14	2
all_levels[30]	556304	1			T4	6		T16	1010		T78	1
all_levels[31]	441401	1			T2	4		T16	631		T78	2
all_levels[32]	11872817	1			T1	2		T2	8		T4	31

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29062409

1

T1

397

T2

20

T4

11881

auto[1]

4088

1

T2

6

T4

45

T5

6

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	6601336	1			T1	23		T2	11		T4	22
all_levels[0]	auto[1]	2323	1			T4	30		T5	2		T6	2
all_levels[1]	auto[0]	1544425	1			T1	2		T4	3263		T5	1
all_levels[1]	auto[1]	245	1			T4	3		T37	1		T78	2
all_levels[2]	auto[0]	200415	1			T4	2093		T6	295		T8	2
all_levels[2]	auto[1]	34	1			T6	1		T36	2		T193	4
all_levels[3]	auto[0]	192199	1			T1	353		T4	5		T5	2
all_levels[3]	auto[1]	134	1			T217	2		T273	1		T140	1
all_levels[4]	auto[0]	231842	1			T8	1		T16	621		T252	3744
all_levels[4]	auto[1]	28	1			T251	2		T48	2		T101	1
all_levels[5]	auto[0]	316242	1			T1	2		T5	2		T16	19514
all_levels[5]	auto[1]	26	1			T5	1		T140	2		T144	2
all_levels[6]	auto[0]	203301	1			T4	1		T5	2		T16	349
all_levels[6]	auto[1]	22	1			T135	1		T114	1		T162	2
all_levels[7]	auto[0]	286609	1			T8	2		T16	590		T11	1
all_levels[7]	auto[1]	114	1			T137	2		T118	22		T316	1
all_levels[8]	auto[0]	244716	1			T8	1		T16	568		T11	3
all_levels[8]	auto[1]	28	1			T297	2		T170	2		T209	1
all_levels[9]	auto[0]	207641	1			T1	1		T4	2		T8	1
all_levels[9]	auto[1]	18	1			T195	1		T316	1		T334	1
all_levels[10]	auto[0]	393534	1			T1	3		T5	2		T8	1
all_levels[10]	auto[1]	22	1			T132	1		T191	1		T152	1
all_levels[11]	auto[0]	254119	1			T8	2		T16	573		T11	1
all_levels[11]	auto[1]	22	1			T160	1		T194	1		T269	1
all_levels[12]	auto[0]	203177	1			T16	412		T78	1		T11	1
all_levels[12]	auto[1]	21	1			T135	1		T119	1		T43	1
all_levels[13]	auto[0]	334079	1			T8	2		T16	497		T78	1
all_levels[13]	auto[1]	25	1			T14	1		T284	2		T217	2
all_levels[14]	auto[0]	312917	1			T16	572		T11	2		T136	1
all_levels[14]	auto[1]	18	1			T136	1		T107	1		T281	1
all_levels[15]	auto[0]	385640	1			T1	8		T4	6		T8	2
all_levels[15]	auto[1]	125	1			T4	12		T19	5		T154	1
all_levels[16]	auto[0]	294136	1			T4	6444		T5	2		T16	302
all_levels[16]	auto[1]	23	1			T126	2		T102	3		T335	2
all_levels[17]	auto[0]	174987	1			T1	1		T16	493		T252	3698
all_levels[17]	auto[1]	23	1			T217	1		T154	2		T50	1
all_levels[18]	auto[0]	174772	1			T8	8		T16	579		T78	2
all_levels[18]	auto[1]	24	1			T258	3		T48	1		T102	1
all_levels[19]	auto[0]	273909	1			T1	2		T4	2		T16	581
all_levels[19]	auto[1]	20	1			T130	2		T206	1		T258	4
all_levels[20]	auto[0]	583755	1			T5	1		T8	2		T16	573
all_levels[20]	auto[1]	26	1			T160	1		T200	1		T336	1
all_levels[21]	auto[0]	555474	1			T4	2		T16	560		T252	311942
all_levels[21]	auto[1]	41	1			T131	2		T144	2		T276	2
all_levels[22]	auto[0]	427207	1			T16	311		T78	2		T252	3745
all_levels[22]	auto[1]	23	1			T145	2		T164	1		T337	1
all_levels[23]	auto[0]	251647	1			T16	409		T252	3744		T133	2
all_levels[23]	auto[1]	17	1			T16	1		T107	2		T297	3
all_levels[24]	auto[0]	223484	1			T5	2		T16	620		T252	3566
all_levels[24]	auto[1]	14	1			T202	1		T338	1		T339	1
all_levels[25]	auto[0]	585820	1			T16	656		T11	2		T252	1470
all_levels[25]	auto[1]	18	1			T120	4		T195	1		T107	2
all_levels[26]	auto[0]	209219	1			T4	1		T16	388		T252	1471
all_levels[26]	auto[1]	28	1			T135	1		T137	2		T191	2
all_levels[27]	auto[0]	203627	1			T2	2		T4	2		T16	521
all_levels[27]	auto[1]	18	1			T2	1		T119	1		T255	1
all_levels[28]	auto[0]	160446	1			T4	1		T16	665		T252	1477
all_levels[28]	auto[1]	24	1			T140	3		T192	1		T215	1
all_levels[29]	auto[0]	161787	1			T16	1177		T252	1473		T14	2
all_levels[29]	auto[1]	9	1			T340	1		T200	2		T225	1
all_levels[30]	auto[0]	556286	1			T4	6		T16	1010		T78	1
all_levels[30]	auto[1]	18	1			T139	2		T161	1		T125	2
all_levels[31]	auto[0]	441383	1			T2	2		T16	631		T78	2
all_levels[31]	auto[1]	18	1			T2	2		T341	1		T288	3
all_levels[32]	auto[0]	11872278	1			T1	2		T2	5		T4	31
all_levels[32]	auto[1]	539	1			T2	3		T5	3		T6	1