Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	713	1			T4	7		T14	7		T15	7
all_values[1]	713	1			T4	7		T14	7		T15	7
all_values[2]	713	1			T4	7		T14	7		T15	7
all_values[3]	713	1			T4	7		T14	7		T15	7
all_values[4]	713	1			T4	7		T14	7		T15	7
all_values[5]	713	1			T4	7		T14	7		T15	7
all_values[6]	713	1			T4	7		T14	7		T15	7
all_values[7]	713	1			T4	7		T14	7		T15	7
all_values[8]	713	1			T4	7		T14	7		T15	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3528

1

T4

34

T14

36

T15

38

auto[1]

2889

1

T4

29

T14

27

T15

25

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2144

1

T4

15

T14

9

T15

18

auto[1]

4273

1

T4

48

T14

54

T15

45

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3794

1

T4

29

T14

30

T15

34

auto[1]

2623

1

T4

34

T14

33

T15

29

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	239	1			T4	2		T14	1		T15	4
all_values[0]	auto[0]	auto[1]	auto[1]	186	1			T4	1		T14	4		T107	3
all_values[0]	auto[1]	auto[0]	auto[1]	160	1			T4	3		T14	2		T15	2
all_values[0]	auto[1]	auto[1]	auto[1]	128	1			T4	1		T15	1		T107	1
all_values[1]	auto[0]	auto[0]	auto[0]	217	1			T4	2		T14	3		T15	1
all_values[1]	auto[0]	auto[1]	auto[0]	199	1			T4	1		T14	1		T15	2
all_values[1]	auto[1]	auto[0]	auto[1]	180	1			T4	3		T14	2		T15	1
all_values[1]	auto[1]	auto[1]	auto[1]	117	1			T4	1		T14	1		T15	3
all_values[2]	auto[0]	auto[0]	auto[0]	158	1			T4	1		T15	1		T34	1
all_values[2]	auto[0]	auto[0]	auto[1]	76	1			T4	1		T14	1		T107	1
all_values[2]	auto[0]	auto[1]	auto[0]	100	1			T15	2		T34	3		T124	6
all_values[2]	auto[0]	auto[1]	auto[1]	85	1			T14	2		T15	2		T107	1
all_values[2]	auto[1]	auto[0]	auto[1]	162	1			T4	3		T14	2		T15	2
all_values[2]	auto[1]	auto[1]	auto[1]	132	1			T4	2		T14	2		T107	2
all_values[3]	auto[0]	auto[0]	auto[0]	176	1			T4	3		T14	1		T15	4
all_values[3]	auto[0]	auto[0]	auto[1]	67	1			T107	1		T35	2		T124	1
all_values[3]	auto[0]	auto[1]	auto[0]	128	1			T4	2		T15	1		T107	1
all_values[3]	auto[0]	auto[1]	auto[1]	66	1			T14	3		T107	3		T125	2
all_values[3]	auto[1]	auto[0]	auto[1]	144	1			T107	1		T35	1		T126	1
all_values[3]	auto[1]	auto[1]	auto[1]	132	1			T4	2		T14	3		T15	2
all_values[4]	auto[0]	auto[0]	auto[0]	147	1			T4	1		T14	2		T15	2
all_values[4]	auto[0]	auto[0]	auto[1]	67	1			T4	1		T14	2		T125	2
all_values[4]	auto[0]	auto[1]	auto[0]	142	1			T107	3		T34	1		T35	5
all_values[4]	auto[0]	auto[1]	auto[1]	72	1			T15	2		T33	2		T34	3
all_values[4]	auto[1]	auto[0]	auto[1]	158	1			T4	3		T14	2		T15	1
all_values[4]	auto[1]	auto[1]	auto[1]	127	1			T4	2		T14	1		T15	2
all_values[5]	auto[0]	auto[0]	auto[0]	150	1			T15	2		T33	1		T125	1
all_values[5]	auto[0]	auto[0]	auto[1]	72	1			T14	2		T33	1		T34	1
all_values[5]	auto[0]	auto[1]	auto[0]	141	1			T4	3		T107	1		T33	3
all_values[5]	auto[0]	auto[1]	auto[1]	67	1			T14	1		T15	1		T107	3
all_values[5]	auto[1]	auto[0]	auto[1]	166	1			T4	2		T14	2		T15	4
all_values[5]	auto[1]	auto[1]	auto[1]	117	1			T4	2		T14	2		T107	2
all_values[6]	auto[0]	auto[0]	auto[0]	168	1			T14	2		T107	1		T33	3
all_values[6]	auto[0]	auto[0]	auto[1]	67	1			T14	1		T15	1		T107	1
all_values[6]	auto[0]	auto[1]	auto[0]	122	1			T4	1		T107	1		T33	1
all_values[6]	auto[0]	auto[1]	auto[1]	59	1			T4	1		T15	2		T107	1
all_values[6]	auto[1]	auto[0]	auto[1]	166	1			T4	2		T14	4		T15	1
all_values[6]	auto[1]	auto[1]	auto[1]	131	1			T4	3		T15	3		T107	1
all_values[7]	auto[0]	auto[0]	auto[0]	158	1			T4	1		T15	2		T107	3
all_values[7]	auto[0]	auto[0]	auto[1]	60	1			T4	1		T14	1		T15	1
all_values[7]	auto[0]	auto[1]	auto[0]	138	1			T15	1		T33	1		T34	1
all_values[7]	auto[0]	auto[1]	auto[1]	54	1			T4	2		T107	2		T125	1
all_values[7]	auto[1]	auto[0]	auto[1]	169	1			T4	2		T14	3		T15	3
all_values[7]	auto[1]	auto[1]	auto[1]	134	1			T4	1		T14	3		T107	2
all_values[8]	auto[0]	auto[0]	auto[1]	222	1			T4	2		T15	3		T107	1
all_values[8]	auto[0]	auto[1]	auto[1]	191	1			T4	3		T14	3		T107	1
all_values[8]	auto[1]	auto[0]	auto[1]	179	1			T4	1		T14	3		T15	3
all_values[8]	auto[1]	auto[1]	auto[1]	121	1			T4	1		T14	1		T15	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal