Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.11 99.10 97.65 100.00 98.38 100.00 99.55


Total test records in report: 1235
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T1036 /workspace/coverage/default/6.uart_long_xfer_wo_dly.3594780469 Jun 24 04:35:11 PM PDT 24 Jun 24 04:38:35 PM PDT 24 122684319203 ps
T1037 /workspace/coverage/default/25.uart_long_xfer_wo_dly.2873287082 Jun 24 04:35:58 PM PDT 24 Jun 24 04:44:36 PM PDT 24 138010163327 ps
T1038 /workspace/coverage/default/40.uart_intr.1617499944 Jun 24 04:36:53 PM PDT 24 Jun 24 04:38:28 PM PDT 24 87154854348 ps
T1039 /workspace/coverage/default/51.uart_fifo_reset.3457313779 Jun 24 04:38:02 PM PDT 24 Jun 24 04:39:27 PM PDT 24 116480574871 ps
T1040 /workspace/coverage/default/24.uart_fifo_full.2651938633 Jun 24 04:35:58 PM PDT 24 Jun 24 04:37:20 PM PDT 24 41495941478 ps
T1041 /workspace/coverage/default/16.uart_noise_filter.3422968564 Jun 24 04:35:39 PM PDT 24 Jun 24 04:35:49 PM PDT 24 5657363346 ps
T1042 /workspace/coverage/default/25.uart_smoke.759459568 Jun 24 04:35:59 PM PDT 24 Jun 24 04:36:20 PM PDT 24 265355234 ps
T1043 /workspace/coverage/default/29.uart_fifo_full.3922642845 Jun 24 04:36:07 PM PDT 24 Jun 24 04:37:37 PM PDT 24 135415080558 ps
T1044 /workspace/coverage/default/30.uart_rx_parity_err.2342405876 Jun 24 04:36:11 PM PDT 24 Jun 24 04:36:50 PM PDT 24 42678391180 ps
T1045 /workspace/coverage/default/138.uart_fifo_reset.1354034075 Jun 24 04:38:00 PM PDT 24 Jun 24 04:39:23 PM PDT 24 10420804774 ps
T1046 /workspace/coverage/default/37.uart_tx_rx.135721111 Jun 24 04:36:39 PM PDT 24 Jun 24 04:37:45 PM PDT 24 69728825872 ps
T1047 /workspace/coverage/default/37.uart_perf.103568117 Jun 24 04:36:37 PM PDT 24 Jun 24 04:42:39 PM PDT 24 27331279550 ps
T1048 /workspace/coverage/default/43.uart_alert_test.2039760525 Jun 24 04:37:21 PM PDT 24 Jun 24 04:38:05 PM PDT 24 44775557 ps
T1049 /workspace/coverage/default/35.uart_rx_parity_err.3726441459 Jun 24 04:36:36 PM PDT 24 Jun 24 04:37:33 PM PDT 24 26788866124 ps
T1050 /workspace/coverage/default/44.uart_long_xfer_wo_dly.291646260 Jun 24 04:37:22 PM PDT 24 Jun 24 04:45:17 PM PDT 24 105338236700 ps
T1051 /workspace/coverage/default/4.uart_tx_rx.3934364878 Jun 24 04:35:14 PM PDT 24 Jun 24 04:35:51 PM PDT 24 80846254660 ps
T1052 /workspace/coverage/default/48.uart_fifo_full.3864725517 Jun 24 04:37:19 PM PDT 24 Jun 24 04:39:17 PM PDT 24 137980702762 ps
T1053 /workspace/coverage/default/25.uart_alert_test.2715724973 Jun 24 04:36:02 PM PDT 24 Jun 24 04:36:24 PM PDT 24 23028966 ps
T1054 /workspace/coverage/default/62.uart_stress_all_with_rand_reset.3686124397 Jun 24 04:37:34 PM PDT 24 Jun 24 04:49:02 PM PDT 24 61743482574 ps
T1055 /workspace/coverage/default/283.uart_fifo_reset.2170705674 Jun 24 04:38:48 PM PDT 24 Jun 24 04:40:32 PM PDT 24 22575340019 ps
T220 /workspace/coverage/default/178.uart_fifo_reset.471966301 Jun 24 04:38:21 PM PDT 24 Jun 24 04:39:41 PM PDT 24 37957054528 ps
T1056 /workspace/coverage/default/8.uart_perf.461102088 Jun 24 04:35:28 PM PDT 24 Jun 24 04:43:23 PM PDT 24 8968208174 ps
T1057 /workspace/coverage/default/242.uart_fifo_reset.1332920587 Jun 24 04:38:34 PM PDT 24 Jun 24 04:43:56 PM PDT 24 144318475338 ps
T1058 /workspace/coverage/default/27.uart_stress_all_with_rand_reset.3045154858 Jun 24 04:36:04 PM PDT 24 Jun 24 04:43:24 PM PDT 24 269312724651 ps
T1059 /workspace/coverage/default/33.uart_smoke.1715142135 Jun 24 04:36:33 PM PDT 24 Jun 24 04:36:50 PM PDT 24 100665328 ps
T1060 /workspace/coverage/default/36.uart_tx_ovrd.1730474833 Jun 24 04:36:37 PM PDT 24 Jun 24 04:36:57 PM PDT 24 1917814981 ps
T1061 /workspace/coverage/default/238.uart_fifo_reset.2377557709 Jun 24 04:38:37 PM PDT 24 Jun 24 04:45:01 PM PDT 24 326411713065 ps
T1062 /workspace/coverage/default/8.uart_fifo_full.262735749 Jun 24 04:35:18 PM PDT 24 Jun 24 04:35:41 PM PDT 24 47590507677 ps
T1063 /workspace/coverage/default/212.uart_fifo_reset.3627669083 Jun 24 04:38:21 PM PDT 24 Jun 24 04:42:53 PM PDT 24 82911936781 ps
T1064 /workspace/coverage/default/44.uart_fifo_reset.3162654611 Jun 24 04:37:06 PM PDT 24 Jun 24 04:37:41 PM PDT 24 6043569521 ps
T1065 /workspace/coverage/default/37.uart_rx_oversample.2206052788 Jun 24 04:36:47 PM PDT 24 Jun 24 04:37:55 PM PDT 24 5381801875 ps
T248 /workspace/coverage/default/71.uart_fifo_reset.2634033209 Jun 24 04:37:45 PM PDT 24 Jun 24 04:40:13 PM PDT 24 84492495302 ps
T58 /workspace/coverage/default/92.uart_stress_all_with_rand_reset.3673979289 Jun 24 04:37:47 PM PDT 24 Jun 24 04:42:32 PM PDT 24 27470661333 ps
T1066 /workspace/coverage/default/21.uart_long_xfer_wo_dly.407804958 Jun 24 04:35:50 PM PDT 24 Jun 24 04:52:11 PM PDT 24 206046552918 ps
T1067 /workspace/coverage/default/11.uart_fifo_full.2904119991 Jun 24 04:35:24 PM PDT 24 Jun 24 04:35:39 PM PDT 24 36443842728 ps
T1068 /workspace/coverage/default/105.uart_fifo_reset.222113685 Jun 24 04:37:56 PM PDT 24 Jun 24 04:40:40 PM PDT 24 69374452898 ps
T1069 /workspace/coverage/default/31.uart_loopback.3745019893 Jun 24 04:36:25 PM PDT 24 Jun 24 04:36:56 PM PDT 24 6553497944 ps
T1070 /workspace/coverage/default/12.uart_fifo_full.2520993307 Jun 24 04:35:40 PM PDT 24 Jun 24 04:38:42 PM PDT 24 125441635841 ps
T1071 /workspace/coverage/default/13.uart_loopback.354156283 Jun 24 04:35:37 PM PDT 24 Jun 24 04:35:47 PM PDT 24 7884991681 ps
T230 /workspace/coverage/default/41.uart_stress_all.4200678214 Jun 24 04:36:55 PM PDT 24 Jun 24 04:38:42 PM PDT 24 43375732335 ps
T1072 /workspace/coverage/default/83.uart_stress_all_with_rand_reset.925023717 Jun 24 04:37:49 PM PDT 24 Jun 24 04:50:15 PM PDT 24 78051046432 ps
T1073 /workspace/coverage/default/28.uart_fifo_reset.2486335707 Jun 24 04:36:00 PM PDT 24 Jun 24 04:37:11 PM PDT 24 115545287967 ps
T1074 /workspace/coverage/default/225.uart_fifo_reset.159278782 Jun 24 04:38:26 PM PDT 24 Jun 24 04:50:53 PM PDT 24 169296241492 ps
T1075 /workspace/coverage/default/9.uart_fifo_reset.1439901324 Jun 24 04:35:19 PM PDT 24 Jun 24 04:35:34 PM PDT 24 30375468659 ps
T1076 /workspace/coverage/default/40.uart_rx_parity_err.1992089766 Jun 24 04:36:49 PM PDT 24 Jun 24 04:37:41 PM PDT 24 42809367867 ps
T1077 /workspace/coverage/default/7.uart_tx_rx.2990610718 Jun 24 04:35:16 PM PDT 24 Jun 24 04:35:29 PM PDT 24 15699712711 ps
T1078 /workspace/coverage/default/155.uart_fifo_reset.2692879281 Jun 24 04:38:07 PM PDT 24 Jun 24 04:39:38 PM PDT 24 130494912151 ps
T1079 /workspace/coverage/default/210.uart_fifo_reset.2122670062 Jun 24 04:38:21 PM PDT 24 Jun 24 04:41:06 PM PDT 24 167722156225 ps
T1080 /workspace/coverage/default/84.uart_fifo_reset.3615410916 Jun 24 04:37:47 PM PDT 24 Jun 24 04:42:50 PM PDT 24 124098435951 ps
T1081 /workspace/coverage/default/85.uart_fifo_reset.2019094905 Jun 24 04:37:46 PM PDT 24 Jun 24 04:39:39 PM PDT 24 34422856091 ps
T1082 /workspace/coverage/default/1.uart_smoke.1042304115 Jun 24 04:34:57 PM PDT 24 Jun 24 04:35:12 PM PDT 24 6068707641 ps
T1083 /workspace/coverage/default/47.uart_alert_test.3477894459 Jun 24 04:37:20 PM PDT 24 Jun 24 04:38:05 PM PDT 24 37175508 ps
T1084 /workspace/coverage/default/41.uart_long_xfer_wo_dly.2671432691 Jun 24 04:36:55 PM PDT 24 Jun 24 04:49:04 PM PDT 24 156062692643 ps
T1085 /workspace/coverage/default/2.uart_fifo_reset.3698594234 Jun 24 04:35:13 PM PDT 24 Jun 24 04:36:11 PM PDT 24 161302603937 ps
T1086 /workspace/coverage/default/20.uart_rx_parity_err.1510353157 Jun 24 04:35:45 PM PDT 24 Jun 24 04:35:59 PM PDT 24 9739190952 ps
T1087 /workspace/coverage/default/43.uart_tx_ovrd.2689272854 Jun 24 04:36:59 PM PDT 24 Jun 24 04:37:35 PM PDT 24 12308302770 ps
T1088 /workspace/coverage/default/30.uart_rx_oversample.3331796377 Jun 24 04:36:09 PM PDT 24 Jun 24 04:36:36 PM PDT 24 3059209287 ps
T1089 /workspace/coverage/default/18.uart_perf.803466444 Jun 24 04:35:42 PM PDT 24 Jun 24 04:37:30 PM PDT 24 3905859079 ps
T1090 /workspace/coverage/default/7.uart_smoke.2742406465 Jun 24 04:35:26 PM PDT 24 Jun 24 04:35:29 PM PDT 24 947986468 ps
T1091 /workspace/coverage/default/239.uart_fifo_reset.2871293420 Jun 24 04:38:34 PM PDT 24 Jun 24 04:40:53 PM PDT 24 52029224475 ps
T1092 /workspace/coverage/default/52.uart_fifo_reset.2841455718 Jun 24 04:37:34 PM PDT 24 Jun 24 04:39:13 PM PDT 24 129120524812 ps
T1093 /workspace/coverage/default/4.uart_fifo_full.1046321680 Jun 24 04:35:00 PM PDT 24 Jun 24 04:35:22 PM PDT 24 34597660013 ps
T1094 /workspace/coverage/default/19.uart_loopback.734461131 Jun 24 04:35:43 PM PDT 24 Jun 24 04:35:55 PM PDT 24 12381012468 ps
T1095 /workspace/coverage/default/189.uart_fifo_reset.1335825407 Jun 24 04:38:21 PM PDT 24 Jun 24 04:40:21 PM PDT 24 97048107607 ps
T1096 /workspace/coverage/default/135.uart_fifo_reset.1162458138 Jun 24 04:37:59 PM PDT 24 Jun 24 04:39:11 PM PDT 24 41652383154 ps
T1097 /workspace/coverage/default/47.uart_rx_parity_err.2221161503 Jun 24 04:37:19 PM PDT 24 Jun 24 04:40:26 PM PDT 24 91954576930 ps
T1098 /workspace/coverage/default/249.uart_fifo_reset.3137347859 Jun 24 04:38:42 PM PDT 24 Jun 24 04:40:22 PM PDT 24 58118610505 ps
T1099 /workspace/coverage/default/3.uart_perf.621730331 Jun 24 04:35:25 PM PDT 24 Jun 24 04:43:48 PM PDT 24 16887368854 ps
T1100 /workspace/coverage/default/37.uart_fifo_full.102767716 Jun 24 04:36:45 PM PDT 24 Jun 24 04:37:18 PM PDT 24 28804864329 ps
T1101 /workspace/coverage/default/10.uart_rx_oversample.3629245725 Jun 24 04:35:13 PM PDT 24 Jun 24 04:35:34 PM PDT 24 2835954357 ps
T1102 /workspace/coverage/cover_reg_top/13.uart_tl_errors.1357038768 Jun 24 04:34:24 PM PDT 24 Jun 24 04:34:27 PM PDT 24 226625017 ps
T70 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1281284563 Jun 24 04:34:22 PM PDT 24 Jun 24 04:34:29 PM PDT 24 21820152 ps
T1103 /workspace/coverage/cover_reg_top/19.uart_intr_test.2845727963 Jun 24 04:34:39 PM PDT 24 Jun 24 04:34:40 PM PDT 24 46741411 ps
T1104 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1905917122 Jun 24 04:34:28 PM PDT 24 Jun 24 04:34:29 PM PDT 24 108630106 ps
T1105 /workspace/coverage/cover_reg_top/12.uart_intr_test.2061311538 Jun 24 04:34:22 PM PDT 24 Jun 24 04:34:25 PM PDT 24 56112027 ps
T1106 /workspace/coverage/cover_reg_top/46.uart_intr_test.1031971466 Jun 24 04:34:34 PM PDT 24 Jun 24 04:34:35 PM PDT 24 22050965 ps
T1107 /workspace/coverage/cover_reg_top/6.uart_intr_test.1160245388 Jun 24 04:34:16 PM PDT 24 Jun 24 04:34:17 PM PDT 24 80032413 ps
T59 /workspace/coverage/cover_reg_top/9.uart_csr_rw.1574141553 Jun 24 04:34:31 PM PDT 24 Jun 24 04:34:32 PM PDT 24 14077334 ps
T79 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.2751149784 Jun 24 04:34:20 PM PDT 24 Jun 24 04:34:23 PM PDT 24 148778339 ps
T71 /workspace/coverage/cover_reg_top/3.uart_csr_rw.491501824 Jun 24 04:34:16 PM PDT 24 Jun 24 04:34:18 PM PDT 24 12593216 ps
T72 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1578400764 Jun 24 04:34:20 PM PDT 24 Jun 24 04:34:24 PM PDT 24 73233338 ps
T60 /workspace/coverage/cover_reg_top/16.uart_csr_rw.57931302 Jun 24 04:34:28 PM PDT 24 Jun 24 04:34:29 PM PDT 24 15837629 ps
T1108 /workspace/coverage/cover_reg_top/5.uart_intr_test.1985177127 Jun 24 04:34:36 PM PDT 24 Jun 24 04:34:38 PM PDT 24 124686332 ps
T73 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1926545264 Jun 24 04:34:23 PM PDT 24 Jun 24 04:34:26 PM PDT 24 30454056 ps
T1109 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1316728414 Jun 24 04:34:17 PM PDT 24 Jun 24 04:34:21 PM PDT 24 258899406 ps
T1110 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1912969130 Jun 24 04:34:19 PM PDT 24 Jun 24 04:34:21 PM PDT 24 84760194 ps
T80 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.2861270912 Jun 24 04:34:18 PM PDT 24 Jun 24 04:34:21 PM PDT 24 127157153 ps
T1111 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1869255771 Jun 24 04:34:20 PM PDT 24 Jun 24 04:34:23 PM PDT 24 23399387 ps
T74 /workspace/coverage/cover_reg_top/14.uart_csr_rw.2438726543 Jun 24 04:34:27 PM PDT 24 Jun 24 04:34:28 PM PDT 24 22668593 ps
T75 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.3405651611 Jun 24 04:34:13 PM PDT 24 Jun 24 04:34:14 PM PDT 24 31486053 ps
T76 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.2797325002 Jun 24 04:34:21 PM PDT 24 Jun 24 04:34:23 PM PDT 24 55446559 ps
T1112 /workspace/coverage/cover_reg_top/44.uart_intr_test.2157701281 Jun 24 04:34:26 PM PDT 24 Jun 24 04:34:28 PM PDT 24 31182999 ps
T77 /workspace/coverage/cover_reg_top/17.uart_csr_rw.1834992035 Jun 24 04:34:28 PM PDT 24 Jun 24 04:34:29 PM PDT 24 38471139 ps
T1113 /workspace/coverage/cover_reg_top/0.uart_csr_rw.2342073832 Jun 24 04:34:17 PM PDT 24 Jun 24 04:34:19 PM PDT 24 11288813 ps
T81 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.216901460 Jun 24 04:34:22 PM PDT 24 Jun 24 04:34:26 PM PDT 24 401734079 ps
T1114 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.855636173 Jun 24 04:34:25 PM PDT 24 Jun 24 04:34:26 PM PDT 24 123448479 ps
T1115 /workspace/coverage/cover_reg_top/1.uart_csr_rw.2776129610 Jun 24 04:34:17 PM PDT 24 Jun 24 04:34:19 PM PDT 24 80711463 ps
T61 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1315499227 Jun 24 04:34:15 PM PDT 24 Jun 24 04:34:16 PM PDT 24 13191143 ps
T1116 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3417700421 Jun 24 04:34:16 PM PDT 24 Jun 24 04:34:18 PM PDT 24 76044197 ps
T1117 /workspace/coverage/cover_reg_top/2.uart_tl_errors.936049938 Jun 24 04:34:15 PM PDT 24 Jun 24 04:34:17 PM PDT 24 79774877 ps
T62 /workspace/coverage/cover_reg_top/18.uart_csr_rw.2302465375 Jun 24 04:34:42 PM PDT 24 Jun 24 04:34:44 PM PDT 24 17421425 ps
T127 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1166059208 Jun 24 04:34:49 PM PDT 24 Jun 24 04:34:52 PM PDT 24 92299906 ps
T1118 /workspace/coverage/cover_reg_top/14.uart_intr_test.493347123 Jun 24 04:35:07 PM PDT 24 Jun 24 04:35:09 PM PDT 24 44472033 ps
T1119 /workspace/coverage/cover_reg_top/17.uart_tl_errors.3618531925 Jun 24 04:34:28 PM PDT 24 Jun 24 04:34:30 PM PDT 24 47791052 ps
T1120 /workspace/coverage/cover_reg_top/18.uart_tl_errors.3745381335 Jun 24 04:34:40 PM PDT 24 Jun 24 04:34:43 PM PDT 24 585000684 ps
T1121 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.932492401 Jun 24 04:34:16 PM PDT 24 Jun 24 04:34:20 PM PDT 24 266695307 ps
T63 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3529589984 Jun 24 04:34:19 PM PDT 24 Jun 24 04:34:22 PM PDT 24 44165957 ps
T1122 /workspace/coverage/cover_reg_top/5.uart_csr_rw.1240184644 Jun 24 04:35:09 PM PDT 24 Jun 24 04:35:11 PM PDT 24 21890037 ps
T1123 /workspace/coverage/cover_reg_top/8.uart_csr_rw.3170744552 Jun 24 04:34:26 PM PDT 24 Jun 24 04:34:27 PM PDT 24 14741659 ps
T1124 /workspace/coverage/cover_reg_top/40.uart_intr_test.3599858935 Jun 24 04:35:10 PM PDT 24 Jun 24 04:35:12 PM PDT 24 25040299 ps
T128 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1710865854 Jun 24 04:34:52 PM PDT 24 Jun 24 04:34:54 PM PDT 24 82291105 ps
T1125 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2361918438 Jun 24 04:35:15 PM PDT 24 Jun 24 04:35:18 PM PDT 24 164882775 ps
T1126 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.79516995 Jun 24 04:34:29 PM PDT 24 Jun 24 04:34:30 PM PDT 24 111421514 ps
T1127 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.18720299 Jun 24 04:34:21 PM PDT 24 Jun 24 04:34:24 PM PDT 24 48260697 ps
T1128 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2728089708 Jun 24 04:34:19 PM PDT 24 Jun 24 04:34:21 PM PDT 24 43730959 ps
T1129 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.740899291 Jun 24 04:34:28 PM PDT 24 Jun 24 04:34:30 PM PDT 24 57780114 ps
T1130 /workspace/coverage/cover_reg_top/5.uart_tl_errors.2125561018 Jun 24 04:34:18 PM PDT 24 Jun 24 04:34:21 PM PDT 24 93949985 ps
T1131 /workspace/coverage/cover_reg_top/6.uart_tl_errors.515873037 Jun 24 04:34:30 PM PDT 24 Jun 24 04:34:33 PM PDT 24 231684907 ps
T1132 /workspace/coverage/cover_reg_top/23.uart_intr_test.2592019559 Jun 24 04:34:28 PM PDT 24 Jun 24 04:34:30 PM PDT 24 10850350 ps
T1133 /workspace/coverage/cover_reg_top/0.uart_tl_errors.537603114 Jun 24 04:34:21 PM PDT 24 Jun 24 04:34:24 PM PDT 24 47748671 ps
T1134 /workspace/coverage/cover_reg_top/33.uart_intr_test.2851645414 Jun 24 04:34:36 PM PDT 24 Jun 24 04:34:37 PM PDT 24 16461544 ps
T1135 /workspace/coverage/cover_reg_top/21.uart_intr_test.3796057451 Jun 24 04:34:37 PM PDT 24 Jun 24 04:34:39 PM PDT 24 55816046 ps
T1136 /workspace/coverage/cover_reg_top/31.uart_intr_test.2693870862 Jun 24 04:34:33 PM PDT 24 Jun 24 04:34:34 PM PDT 24 20860838 ps
T1137 /workspace/coverage/cover_reg_top/12.uart_tl_errors.4288981147 Jun 24 04:34:23 PM PDT 24 Jun 24 04:34:26 PM PDT 24 333778159 ps
T1138 /workspace/coverage/cover_reg_top/45.uart_intr_test.3580596696 Jun 24 04:34:27 PM PDT 24 Jun 24 04:34:28 PM PDT 24 12911616 ps
T1139 /workspace/coverage/cover_reg_top/11.uart_csr_rw.2209348540 Jun 24 04:34:32 PM PDT 24 Jun 24 04:34:33 PM PDT 24 15329720 ps
T1140 /workspace/coverage/cover_reg_top/47.uart_intr_test.28967123 Jun 24 04:35:11 PM PDT 24 Jun 24 04:35:13 PM PDT 24 49620563 ps
T1141 /workspace/coverage/cover_reg_top/42.uart_intr_test.450380880 Jun 24 04:34:28 PM PDT 24 Jun 24 04:34:30 PM PDT 24 21018810 ps
T1142 /workspace/coverage/cover_reg_top/17.uart_intr_test.2607451929 Jun 24 04:34:27 PM PDT 24 Jun 24 04:34:28 PM PDT 24 21110836 ps
T1143 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2381847364 Jun 24 04:34:15 PM PDT 24 Jun 24 04:34:17 PM PDT 24 85915958 ps
T1144 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.1225711115 Jun 24 04:34:20 PM PDT 24 Jun 24 04:34:24 PM PDT 24 51706916 ps
T1145 /workspace/coverage/cover_reg_top/19.uart_csr_rw.1874066420 Jun 24 04:34:43 PM PDT 24 Jun 24 04:34:45 PM PDT 24 11165871 ps
T1146 /workspace/coverage/cover_reg_top/39.uart_intr_test.2163291367 Jun 24 04:34:34 PM PDT 24 Jun 24 04:34:35 PM PDT 24 29849054 ps
T1147 /workspace/coverage/cover_reg_top/16.uart_tl_errors.463548571 Jun 24 04:34:28 PM PDT 24 Jun 24 04:34:31 PM PDT 24 286736289 ps
T1148 /workspace/coverage/cover_reg_top/8.uart_intr_test.1257032682 Jun 24 04:34:33 PM PDT 24 Jun 24 04:34:34 PM PDT 24 23071542 ps
T1149 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1809011800 Jun 24 04:34:28 PM PDT 24 Jun 24 04:34:30 PM PDT 24 109647678 ps
T1150 /workspace/coverage/cover_reg_top/11.uart_tl_errors.2557131206 Jun 24 04:34:42 PM PDT 24 Jun 24 04:34:44 PM PDT 24 90622590 ps
T129 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.4186999258 Jun 24 04:34:21 PM PDT 24 Jun 24 04:34:24 PM PDT 24 91212260 ps
T1151 /workspace/coverage/cover_reg_top/26.uart_intr_test.3562585560 Jun 24 04:34:35 PM PDT 24 Jun 24 04:34:36 PM PDT 24 18016413 ps
T1152 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1048586227 Jun 24 04:34:21 PM PDT 24 Jun 24 04:34:24 PM PDT 24 18345121 ps
T1153 /workspace/coverage/cover_reg_top/11.uart_intr_test.2609023283 Jun 24 04:34:25 PM PDT 24 Jun 24 04:34:26 PM PDT 24 51776461 ps
T1154 /workspace/coverage/cover_reg_top/7.uart_tl_errors.201474792 Jun 24 04:34:16 PM PDT 24 Jun 24 04:34:19 PM PDT 24 224771463 ps
T1155 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.2824520813 Jun 24 04:34:34 PM PDT 24 Jun 24 04:34:36 PM PDT 24 246327622 ps
T1156 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2720074998 Jun 24 04:34:43 PM PDT 24 Jun 24 04:34:45 PM PDT 24 98617967 ps
T1157 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3700414444 Jun 24 04:35:00 PM PDT 24 Jun 24 04:35:02 PM PDT 24 19565979 ps
T1158 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1431837113 Jun 24 04:34:18 PM PDT 24 Jun 24 04:34:20 PM PDT 24 15801194 ps
T1159 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1294644275 Jun 24 04:34:39 PM PDT 24 Jun 24 04:34:40 PM PDT 24 16587110 ps
T1160 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3930739502 Jun 24 04:34:19 PM PDT 24 Jun 24 04:34:22 PM PDT 24 29966516 ps
T1161 /workspace/coverage/cover_reg_top/30.uart_intr_test.608637050 Jun 24 04:34:42 PM PDT 24 Jun 24 04:34:44 PM PDT 24 12603065 ps
T1162 /workspace/coverage/cover_reg_top/3.uart_tl_errors.4240341658 Jun 24 04:34:14 PM PDT 24 Jun 24 04:34:17 PM PDT 24 94885465 ps
T64 /workspace/coverage/cover_reg_top/4.uart_csr_rw.4089646113 Jun 24 04:34:17 PM PDT 24 Jun 24 04:34:19 PM PDT 24 28185292 ps
T87 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.1885177217 Jun 24 04:34:22 PM PDT 24 Jun 24 04:34:25 PM PDT 24 93984399 ps
T1163 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.2756800052 Jun 24 04:34:14 PM PDT 24 Jun 24 04:34:16 PM PDT 24 20276499 ps
T67 /workspace/coverage/cover_reg_top/12.uart_csr_rw.1478473442 Jun 24 04:34:26 PM PDT 24 Jun 24 04:34:28 PM PDT 24 14546251 ps
T1164 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3102930676 Jun 24 04:34:25 PM PDT 24 Jun 24 04:34:27 PM PDT 24 16819093 ps
T1165 /workspace/coverage/cover_reg_top/19.uart_tl_errors.919955875 Jun 24 04:34:36 PM PDT 24 Jun 24 04:34:38 PM PDT 24 336384683 ps
T1166 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.30540565 Jun 24 04:34:33 PM PDT 24 Jun 24 04:34:35 PM PDT 24 735131001 ps
T82 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3021937012 Jun 24 04:34:38 PM PDT 24 Jun 24 04:34:40 PM PDT 24 1189378743 ps
T1167 /workspace/coverage/cover_reg_top/10.uart_csr_rw.256966936 Jun 24 04:34:36 PM PDT 24 Jun 24 04:34:38 PM PDT 24 15080738 ps
T1168 /workspace/coverage/cover_reg_top/7.uart_csr_rw.1521968033 Jun 24 04:34:19 PM PDT 24 Jun 24 04:34:21 PM PDT 24 20083520 ps
T1169 /workspace/coverage/cover_reg_top/49.uart_intr_test.1529165097 Jun 24 04:34:49 PM PDT 24 Jun 24 04:34:51 PM PDT 24 54213717 ps
T1170 /workspace/coverage/cover_reg_top/6.uart_csr_rw.2957123049 Jun 24 04:34:22 PM PDT 24 Jun 24 04:34:24 PM PDT 24 11745944 ps
T1171 /workspace/coverage/cover_reg_top/35.uart_intr_test.587180266 Jun 24 04:34:33 PM PDT 24 Jun 24 04:34:34 PM PDT 24 26908557 ps
T1172 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.2160578966 Jun 24 04:34:13 PM PDT 24 Jun 24 04:34:14 PM PDT 24 46852427 ps
T1173 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1543804820 Jun 24 04:34:35 PM PDT 24 Jun 24 04:34:37 PM PDT 24 90988615 ps
T83 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.2760375501 Jun 24 04:34:25 PM PDT 24 Jun 24 04:34:26 PM PDT 24 67027320 ps
T1174 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.2369763916 Jun 24 04:34:18 PM PDT 24 Jun 24 04:34:21 PM PDT 24 65671843 ps
T1175 /workspace/coverage/cover_reg_top/10.uart_tl_errors.512850077 Jun 24 04:34:34 PM PDT 24 Jun 24 04:34:36 PM PDT 24 89140513 ps
T1176 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.1440176056 Jun 24 04:35:04 PM PDT 24 Jun 24 04:35:06 PM PDT 24 18652487 ps
T1177 /workspace/coverage/cover_reg_top/25.uart_intr_test.2753527970 Jun 24 04:34:35 PM PDT 24 Jun 24 04:34:37 PM PDT 24 71175926 ps
T1178 /workspace/coverage/cover_reg_top/29.uart_intr_test.3181833694 Jun 24 04:34:37 PM PDT 24 Jun 24 04:34:38 PM PDT 24 13587027 ps
T84 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.2223653818 Jun 24 04:34:38 PM PDT 24 Jun 24 04:34:39 PM PDT 24 81291538 ps
T1179 /workspace/coverage/cover_reg_top/13.uart_csr_rw.884506709 Jun 24 04:34:27 PM PDT 24 Jun 24 04:34:29 PM PDT 24 89012250 ps
T1180 /workspace/coverage/cover_reg_top/24.uart_intr_test.1144519786 Jun 24 04:34:44 PM PDT 24 Jun 24 04:34:46 PM PDT 24 16062036 ps
T1181 /workspace/coverage/cover_reg_top/43.uart_intr_test.4069787914 Jun 24 04:34:49 PM PDT 24 Jun 24 04:34:51 PM PDT 24 28427963 ps
T1182 /workspace/coverage/cover_reg_top/34.uart_intr_test.2782488395 Jun 24 04:34:31 PM PDT 24 Jun 24 04:34:33 PM PDT 24 12369961 ps
T1183 /workspace/coverage/cover_reg_top/32.uart_intr_test.2044654175 Jun 24 04:34:26 PM PDT 24 Jun 24 04:34:28 PM PDT 24 44431272 ps
T1184 /workspace/coverage/cover_reg_top/16.uart_intr_test.2805923969 Jun 24 04:34:25 PM PDT 24 Jun 24 04:34:26 PM PDT 24 11177729 ps
T85 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.3222747146 Jun 24 04:34:16 PM PDT 24 Jun 24 04:34:19 PM PDT 24 856892080 ps
T1185 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.144127571 Jun 24 04:34:21 PM PDT 24 Jun 24 04:34:24 PM PDT 24 46778065 ps
T1186 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.4244934415 Jun 24 04:34:24 PM PDT 24 Jun 24 04:34:26 PM PDT 24 60782198 ps
T1187 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.4227300130 Jun 24 04:34:15 PM PDT 24 Jun 24 04:34:16 PM PDT 24 34071035 ps
T1188 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.4201862327 Jun 24 04:34:25 PM PDT 24 Jun 24 04:34:27 PM PDT 24 83332211 ps
T1189 /workspace/coverage/cover_reg_top/18.uart_intr_test.509297693 Jun 24 04:34:26 PM PDT 24 Jun 24 04:34:27 PM PDT 24 18391821 ps
T1190 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2950728885 Jun 24 04:34:14 PM PDT 24 Jun 24 04:34:15 PM PDT 24 45925267 ps
T1191 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.3397618083 Jun 24 04:34:54 PM PDT 24 Jun 24 04:34:57 PM PDT 24 28010308 ps
T1192 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.282905536 Jun 24 04:34:22 PM PDT 24 Jun 24 04:34:26 PM PDT 24 221386848 ps
T1193 /workspace/coverage/cover_reg_top/10.uart_intr_test.2701456304 Jun 24 04:34:26 PM PDT 24 Jun 24 04:34:27 PM PDT 24 85484113 ps
T1194 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3882110489 Jun 24 04:34:29 PM PDT 24 Jun 24 04:34:32 PM PDT 24 67604161 ps
T1195 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1880052649 Jun 24 04:34:40 PM PDT 24 Jun 24 04:34:41 PM PDT 24 15902247 ps
T1196 /workspace/coverage/cover_reg_top/1.uart_tl_errors.926054558 Jun 24 04:34:24 PM PDT 24 Jun 24 04:34:27 PM PDT 24 230270459 ps
T65 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1808042575 Jun 24 04:34:45 PM PDT 24 Jun 24 04:34:47 PM PDT 24 120131687 ps
T1197 /workspace/coverage/cover_reg_top/13.uart_intr_test.2471864103 Jun 24 04:34:22 PM PDT 24 Jun 24 04:34:24 PM PDT 24 31934992 ps
T1198 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.653279306 Jun 24 04:34:22 PM PDT 24 Jun 24 04:34:24 PM PDT 24 15687969 ps
T1199 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1680161319 Jun 24 04:34:28 PM PDT 24 Jun 24 04:34:30 PM PDT 24 41304176 ps
T1200 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.1944452866 Jun 24 04:34:58 PM PDT 24 Jun 24 04:35:02 PM PDT 24 1031768167 ps
T1201 /workspace/coverage/cover_reg_top/20.uart_intr_test.3040048460 Jun 24 04:34:32 PM PDT 24 Jun 24 04:34:33 PM PDT 24 53776679 ps
T1202 /workspace/coverage/cover_reg_top/9.uart_intr_test.3026507326 Jun 24 04:34:20 PM PDT 24 Jun 24 04:34:23 PM PDT 24 14173085 ps
T1203 /workspace/coverage/cover_reg_top/1.uart_intr_test.4043458576 Jun 24 04:34:16 PM PDT 24 Jun 24 04:34:18 PM PDT 24 26404865 ps
T1204 /workspace/coverage/cover_reg_top/22.uart_intr_test.2354165953 Jun 24 04:34:42 PM PDT 24 Jun 24 04:34:43 PM PDT 24 44731713 ps
T1205 /workspace/coverage/cover_reg_top/38.uart_intr_test.3184712860 Jun 24 04:34:38 PM PDT 24 Jun 24 04:34:39 PM PDT 24 15846534 ps
T1206 /workspace/coverage/cover_reg_top/15.uart_intr_test.3391524479 Jun 24 04:34:22 PM PDT 24 Jun 24 04:34:25 PM PDT 24 17191871 ps
T1207 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1925297578 Jun 24 04:34:57 PM PDT 24 Jun 24 04:35:02 PM PDT 24 698674177 ps
T66 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.2549401137 Jun 24 04:34:15 PM PDT 24 Jun 24 04:34:18 PM PDT 24 109143273 ps
T1208 /workspace/coverage/cover_reg_top/15.uart_tl_errors.110128069 Jun 24 04:34:21 PM PDT 24 Jun 24 04:34:25 PM PDT 24 1250744594 ps
T1209 /workspace/coverage/cover_reg_top/2.uart_intr_test.1163280136 Jun 24 04:34:21 PM PDT 24 Jun 24 04:34:24 PM PDT 24 17173766 ps
T1210 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2865168220 Jun 24 04:35:23 PM PDT 24 Jun 24 04:35:24 PM PDT 24 52542998 ps
T1211 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1471582845 Jun 24 04:34:24 PM PDT 24 Jun 24 04:34:26 PM PDT 24 81897027 ps
T1212 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1187556713 Jun 24 04:34:42 PM PDT 24 Jun 24 04:34:44 PM PDT 24 57688385 ps
T1213 /workspace/coverage/cover_reg_top/4.uart_intr_test.3314898737 Jun 24 04:34:36 PM PDT 24 Jun 24 04:34:38 PM PDT 24 13836337 ps
T1214 /workspace/coverage/cover_reg_top/2.uart_csr_rw.1699433668 Jun 24 04:34:16 PM PDT 24 Jun 24 04:34:17 PM PDT 24 63335622 ps
T1215 /workspace/coverage/cover_reg_top/3.uart_intr_test.3135981849 Jun 24 04:34:17 PM PDT 24 Jun 24 04:34:19 PM PDT 24 17127498 ps
T1216 /workspace/coverage/cover_reg_top/0.uart_intr_test.1222500761 Jun 24 04:34:22 PM PDT 24 Jun 24 04:34:25 PM PDT 24 22512181 ps
T1217 /workspace/coverage/cover_reg_top/48.uart_intr_test.3911567204 Jun 24 04:34:38 PM PDT 24 Jun 24 04:34:39 PM PDT 24 52069285 ps
T68 /workspace/coverage/cover_reg_top/15.uart_csr_rw.4206597857 Jun 24 04:34:57 PM PDT 24 Jun 24 04:35:00 PM PDT 24 88376288 ps
T1218 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.3757251079 Jun 24 04:34:23 PM PDT 24 Jun 24 04:34:26 PM PDT 24 23838204 ps
T1219 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2293223579 Jun 24 04:34:25 PM PDT 24 Jun 24 04:34:27 PM PDT 24 33256061 ps
T1220 /workspace/coverage/cover_reg_top/4.uart_tl_errors.876398723 Jun 24 04:34:16 PM PDT 24 Jun 24 04:34:19 PM PDT 24 401524482 ps
T1221 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2150846469 Jun 24 04:35:08 PM PDT 24 Jun 24 04:35:10 PM PDT 24 23680456 ps
T1222 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.1947365381 Jun 24 04:34:13 PM PDT 24 Jun 24 04:34:15 PM PDT 24 50236551 ps
T1223 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1433136629 Jun 24 04:34:21 PM PDT 24 Jun 24 04:34:24 PM PDT 24 295626409 ps
T1224 /workspace/coverage/cover_reg_top/36.uart_intr_test.765602876 Jun 24 04:35:10 PM PDT 24 Jun 24 04:35:12 PM PDT 24 12110209 ps
T1225 /workspace/coverage/cover_reg_top/14.uart_tl_errors.2845417406 Jun 24 04:34:57 PM PDT 24 Jun 24 04:35:00 PM PDT 24 41820669 ps
T1226 /workspace/coverage/cover_reg_top/41.uart_intr_test.262634268 Jun 24 04:34:50 PM PDT 24 Jun 24 04:34:52 PM PDT 24 35042456 ps
T1227 /workspace/coverage/cover_reg_top/9.uart_tl_errors.1970895804 Jun 24 04:34:28 PM PDT 24 Jun 24 04:34:31 PM PDT 24 1460823425 ps
T1228 /workspace/coverage/cover_reg_top/27.uart_intr_test.3702235802 Jun 24 04:34:33 PM PDT 24 Jun 24 04:34:34 PM PDT 24 13182380 ps
T1229 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3529076953 Jun 24 04:34:35 PM PDT 24 Jun 24 04:34:36 PM PDT 24 29805798 ps
T1230 /workspace/coverage/cover_reg_top/28.uart_intr_test.150854764 Jun 24 04:34:34 PM PDT 24 Jun 24 04:34:35 PM PDT 24 22392789 ps
T1231 /workspace/coverage/cover_reg_top/7.uart_intr_test.3357072773 Jun 24 04:34:22 PM PDT 24 Jun 24 04:34:24 PM PDT 24 25335921 ps
T1232 /workspace/coverage/cover_reg_top/37.uart_intr_test.2265837956 Jun 24 04:34:26 PM PDT 24 Jun 24 04:34:27 PM PDT 24 14868343 ps
T69 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.1768988997 Jun 24 04:34:15 PM PDT 24 Jun 24 04:34:16 PM PDT 24 16148462 ps
T86 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.327340913 Jun 24 04:34:15 PM PDT 24 Jun 24 04:34:17 PM PDT 24 555903772 ps
T1233 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.4072087777 Jun 24 04:34:28 PM PDT 24 Jun 24 04:34:30 PM PDT 24 87601870 ps
T1234 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3453080309 Jun 24 04:34:19 PM PDT 24 Jun 24 04:34:21 PM PDT 24 12690523 ps
T1235 /workspace/coverage/cover_reg_top/8.uart_tl_errors.2018252233 Jun 24 04:34:26 PM PDT 24 Jun 24 04:34:29 PM PDT 24 33437088 ps

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.3315348076
Short name T4
Test name
Test status
Simulation time 86464393521 ps
CPU time 702.25 seconds
Started Jun 24 04:37:36 PM PDT 24
Finished Jun 24 04:50:16 PM PDT 24
Peak memory 217372 kb
Host smart-92978250-a100-4fc9-b6f3-4df0bbe25e97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315348076 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.3315348076
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.2454778983
Short name T16
Test name
Test status
Simulation time 167402651454 ps
CPU time 567.11 seconds
Started Jun 24 04:37:14 PM PDT 24
Finished Jun 24 04:47:20 PM PDT 24
Peak memory 217068 kb
Host smart-bbd9423e-1b88-4fb4-bd82-f0a65f151659
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454778983 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.2454778983
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_stress_all.1606399960
Short name T107
Test name
Test status
Simulation time 170663281989 ps
CPU time 658.41 seconds
Started Jun 24 04:36:02 PM PDT 24
Finished Jun 24 04:47:20 PM PDT 24
Peak memory 200940 kb
Host smart-acab8c48-4371-40a9-ad3c-8b2f99f19bd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606399960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.1606399960
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.3558635150
Short name T31
Test name
Test status
Simulation time 84407852760 ps
CPU time 441.06 seconds
Started Jun 24 04:36:40 PM PDT 24
Finished Jun 24 04:44:19 PM PDT 24
Peak memory 216976 kb
Host smart-fdde86b6-aff1-4158-a225-3d23caef6b8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558635150 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.3558635150
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.2640231212
Short name T150
Test name
Test status
Simulation time 215751447188 ps
CPU time 868.02 seconds
Started Jun 24 04:35:45 PM PDT 24
Finished Jun 24 04:50:15 PM PDT 24
Peak memory 212704 kb
Host smart-03448bc5-e3b5-4d75-9566-9b5dead4e6d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640231212 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.2640231212
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_stress_all.1127988658
Short name T254
Test name
Test status
Simulation time 25386962058 ps
CPU time 312.42 seconds
Started Jun 24 04:36:09 PM PDT 24
Finished Jun 24 04:41:42 PM PDT 24
Peak memory 200464 kb
Host smart-f463f1c1-2225-4db5-9f09-1301b62f0267
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127988658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.1127988658
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.619210196
Short name T43
Test name
Test status
Simulation time 264317085603 ps
CPU time 1266.49 seconds
Started Jun 24 04:36:09 PM PDT 24
Finished Jun 24 04:57:36 PM PDT 24
Peak memory 233144 kb
Host smart-acb8679b-e721-4c58-842d-9595ede8e32e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619210196 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.619210196
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_stress_all.3317540313
Short name T138
Test name
Test status
Simulation time 182410095193 ps
CPU time 137.57 seconds
Started Jun 24 04:37:08 PM PDT 24
Finished Jun 24 04:39:54 PM PDT 24
Peak memory 200552 kb
Host smart-85b4e8e1-4601-42aa-ae26-239b2f22d21c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317540313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.3317540313
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.3597431316
Short name T102
Test name
Test status
Simulation time 459990535302 ps
CPU time 1288.67 seconds
Started Jun 24 04:36:46 PM PDT 24
Finished Jun 24 04:58:32 PM PDT 24
Peak memory 225176 kb
Host smart-bfce9a15-4c50-4a94-a717-93aceb978a5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597431316 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.3597431316
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_stress_all.2159519540
Short name T15
Test name
Test status
Simulation time 317229632042 ps
CPU time 74.63 seconds
Started Jun 24 04:36:01 PM PDT 24
Finished Jun 24 04:37:36 PM PDT 24
Peak memory 200468 kb
Host smart-03ee98d5-868a-49df-b659-ca1742a0919d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159519540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.2159519540
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_sec_cm.2125081881
Short name T28
Test name
Test status
Simulation time 69230845 ps
CPU time 0.88 seconds
Started Jun 24 04:35:15 PM PDT 24
Finished Jun 24 04:35:18 PM PDT 24
Peak memory 219272 kb
Host smart-14e52331-718b-42ce-ac45-879b5948922e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125081881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.2125081881
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/11.uart_alert_test.3901839939
Short name T108
Test name
Test status
Simulation time 15493089 ps
CPU time 0.58 seconds
Started Jun 24 04:35:19 PM PDT 24
Finished Jun 24 04:35:21 PM PDT 24
Peak memory 195920 kb
Host smart-2a8bff81-950e-4cc3-b830-78439056abd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901839939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.3901839939
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.3298234445
Short name T39
Test name
Test status
Simulation time 47630796852 ps
CPU time 271.88 seconds
Started Jun 24 04:35:02 PM PDT 24
Finished Jun 24 04:39:35 PM PDT 24
Peak memory 200432 kb
Host smart-0e7fef5a-841d-46cb-8600-056065902773
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3298234445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.3298234445
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.1088154575
Short name T139
Test name
Test status
Simulation time 472095778998 ps
CPU time 51.05 seconds
Started Jun 24 04:38:13 PM PDT 24
Finished Jun 24 04:40:07 PM PDT 24
Peak memory 200504 kb
Host smart-267a4603-6736-4834-b1b2-c9349efe04c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088154575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.1088154575
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_stress_all.2985233721
Short name T269
Test name
Test status
Simulation time 171719466205 ps
CPU time 1146.88 seconds
Started Jun 24 04:35:19 PM PDT 24
Finished Jun 24 04:54:27 PM PDT 24
Peak memory 200448 kb
Host smart-b07148ef-4060-4494-acd3-552267500aa1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985233721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.2985233721
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.2615780348
Short name T11
Test name
Test status
Simulation time 26586338200 ps
CPU time 25.25 seconds
Started Jun 24 04:35:21 PM PDT 24
Finished Jun 24 04:35:47 PM PDT 24
Peak memory 200580 kb
Host smart-a4858229-4b66-42b0-a088-0a5872c05ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615780348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.2615780348
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.4205510201
Short name T100
Test name
Test status
Simulation time 213568358056 ps
CPU time 809.01 seconds
Started Jun 24 04:37:41 PM PDT 24
Finished Jun 24 04:52:08 PM PDT 24
Peak memory 216980 kb
Host smart-43fdba54-7bb9-4d7d-afed-44045eb9fb71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205510201 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.4205510201
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.1917590445
Short name T5
Test name
Test status
Simulation time 81363123542 ps
CPU time 270.47 seconds
Started Jun 24 04:37:48 PM PDT 24
Finished Jun 24 04:43:20 PM PDT 24
Peak memory 200560 kb
Host smart-240adfac-14a5-4ae3-a57d-41771fe22d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917590445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.1917590445
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_fifo_full.3288516302
Short name T163
Test name
Test status
Simulation time 97635381408 ps
CPU time 202.88 seconds
Started Jun 24 04:35:59 PM PDT 24
Finished Jun 24 04:39:43 PM PDT 24
Peak memory 200464 kb
Host smart-1f7e7817-ffdb-4215-b11b-68d708d6ceb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288516302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.3288516302
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_stress_all.2136954241
Short name T125
Test name
Test status
Simulation time 151576919968 ps
CPU time 296.32 seconds
Started Jun 24 04:37:07 PM PDT 24
Finished Jun 24 04:42:33 PM PDT 24
Peak memory 200520 kb
Host smart-d81db4f9-c160-48cf-82d5-302ccd1df9d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136954241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.2136954241
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.2751149784
Short name T79
Test name
Test status
Simulation time 148778339 ps
CPU time 1.44 seconds
Started Jun 24 04:34:20 PM PDT 24
Finished Jun 24 04:34:23 PM PDT 24
Peak memory 198884 kb
Host smart-0469fd18-73f2-40bb-b051-5304157b8988
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751149784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.2751149784
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.57931302
Short name T60
Test name
Test status
Simulation time 15837629 ps
CPU time 0.61 seconds
Started Jun 24 04:34:28 PM PDT 24
Finished Jun 24 04:34:29 PM PDT 24
Peak memory 195244 kb
Host smart-2c499bf7-dfa1-4afd-8b9a-bd00d0798642
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57931302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.57931302
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.1833275246
Short name T137
Test name
Test status
Simulation time 131657103609 ps
CPU time 20.72 seconds
Started Jun 24 04:38:06 PM PDT 24
Finished Jun 24 04:39:33 PM PDT 24
Peak memory 200472 kb
Host smart-3ac8f613-1d68-444e-b214-888d9b21703f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833275246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.1833275246
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.1559103495
Short name T165
Test name
Test status
Simulation time 286275419221 ps
CPU time 253.94 seconds
Started Jun 24 04:37:57 PM PDT 24
Finished Jun 24 04:43:15 PM PDT 24
Peak memory 216976 kb
Host smart-45bf583d-f76a-401f-b91a-249528cad130
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559103495 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.1559103495
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.3361292209
Short name T101
Test name
Test status
Simulation time 263706789772 ps
CPU time 731.06 seconds
Started Jun 24 04:35:35 PM PDT 24
Finished Jun 24 04:47:47 PM PDT 24
Peak memory 217384 kb
Host smart-8933c68f-e982-41ff-8dce-b0323e3586c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361292209 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.3361292209
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_stress_all.3634195318
Short name T116
Test name
Test status
Simulation time 239178782829 ps
CPU time 917.48 seconds
Started Jun 24 04:36:42 PM PDT 24
Finished Jun 24 04:52:18 PM PDT 24
Peak memory 200572 kb
Host smart-976dcbab-5b53-44d4-936b-dafca9cdd7bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634195318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.3634195318
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_fifo_full.54824486
Short name T132
Test name
Test status
Simulation time 63572193510 ps
CPU time 98.23 seconds
Started Jun 24 04:36:48 PM PDT 24
Finished Jun 24 04:38:43 PM PDT 24
Peak memory 200544 kb
Host smart-951c6c39-7621-4692-9579-d353729e3da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54824486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.54824486
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.2318813173
Short name T194
Test name
Test status
Simulation time 88000054704 ps
CPU time 152.39 seconds
Started Jun 24 04:36:04 PM PDT 24
Finished Jun 24 04:38:58 PM PDT 24
Peak memory 200572 kb
Host smart-492df01a-d87b-47d2-ac45-ad03933c2a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318813173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.2318813173
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.3280570457
Short name T255
Test name
Test status
Simulation time 113823789461 ps
CPU time 106.97 seconds
Started Jun 24 04:35:58 PM PDT 24
Finished Jun 24 04:38:05 PM PDT 24
Peak memory 200252 kb
Host smart-7d408acb-befe-4cf4-be65-cc0023ac0955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280570457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.3280570457
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.3222747146
Short name T85
Test name
Test status
Simulation time 856892080 ps
CPU time 1.36 seconds
Started Jun 24 04:34:16 PM PDT 24
Finished Jun 24 04:34:19 PM PDT 24
Peak memory 199192 kb
Host smart-402d3753-0528-4d64-9c3f-fc5089522b68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222747146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.3222747146
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.3534079739
Short name T140
Test name
Test status
Simulation time 25111277189 ps
CPU time 42.67 seconds
Started Jun 24 04:36:50 PM PDT 24
Finished Jun 24 04:37:53 PM PDT 24
Peak memory 200652 kb
Host smart-39cd82b6-62d0-4415-a098-79399142a153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534079739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.3534079739
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.3155369097
Short name T50
Test name
Test status
Simulation time 80312328806 ps
CPU time 28.49 seconds
Started Jun 24 04:38:00 PM PDT 24
Finished Jun 24 04:39:34 PM PDT 24
Peak memory 200544 kb
Host smart-68d94472-dea8-4de5-b382-8bab5e6cf767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155369097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.3155369097
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.2278833015
Short name T14
Test name
Test status
Simulation time 87506327017 ps
CPU time 734.79 seconds
Started Jun 24 04:35:37 PM PDT 24
Finished Jun 24 04:47:53 PM PDT 24
Peak memory 216980 kb
Host smart-125ee6af-7815-425c-8c61-2588b349453c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278833015 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.2278833015
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.3673799390
Short name T208
Test name
Test status
Simulation time 193715077908 ps
CPU time 19.13 seconds
Started Jun 24 04:38:39 PM PDT 24
Finished Jun 24 04:40:02 PM PDT 24
Peak memory 200588 kb
Host smart-cf42c87f-1c6d-4ff6-aea1-4019d462711e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673799390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.3673799390
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.2070094798
Short name T157
Test name
Test status
Simulation time 191455932238 ps
CPU time 1177.97 seconds
Started Jun 24 04:35:09 PM PDT 24
Finished Jun 24 04:54:48 PM PDT 24
Peak memory 217028 kb
Host smart-549aec34-3b59-4ca8-a9c1-65ccf0c8c6ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070094798 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.2070094798
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.475779449
Short name T170
Test name
Test status
Simulation time 172925238368 ps
CPU time 129.54 seconds
Started Jun 24 04:38:22 PM PDT 24
Finished Jun 24 04:41:36 PM PDT 24
Peak memory 200572 kb
Host smart-53f90528-fb3c-44f4-97ed-89a71f08abf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475779449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.475779449
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.4227615364
Short name T54
Test name
Test status
Simulation time 356506883860 ps
CPU time 358.19 seconds
Started Jun 24 04:37:43 PM PDT 24
Finished Jun 24 04:44:43 PM PDT 24
Peak memory 216976 kb
Host smart-a182db0e-6d06-44ae-9231-48b3f497d30b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227615364 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.4227615364
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.105117476
Short name T180
Test name
Test status
Simulation time 92479297853 ps
CPU time 285.01 seconds
Started Jun 24 04:35:19 PM PDT 24
Finished Jun 24 04:40:05 PM PDT 24
Peak memory 217000 kb
Host smart-58cc1a3e-3bc8-4a75-a34f-02d5c2ba11f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105117476 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.105117476
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.1885177217
Short name T87
Test name
Test status
Simulation time 93984399 ps
CPU time 0.99 seconds
Started Jun 24 04:34:22 PM PDT 24
Finished Jun 24 04:34:25 PM PDT 24
Peak memory 198768 kb
Host smart-2561651e-4d47-4f25-bfa4-3d9cb0778f2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885177217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.1885177217
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.4203256046
Short name T160
Test name
Test status
Simulation time 76345885698 ps
CPU time 19.32 seconds
Started Jun 24 04:38:00 PM PDT 24
Finished Jun 24 04:39:26 PM PDT 24
Peak memory 200544 kb
Host smart-7ac4290a-3176-402a-bf26-9836da4133b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203256046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.4203256046
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.1452192445
Short name T213
Test name
Test status
Simulation time 100306816466 ps
CPU time 98.18 seconds
Started Jun 24 04:34:58 PM PDT 24
Finished Jun 24 04:36:38 PM PDT 24
Peak memory 200436 kb
Host smart-aa83d0b5-fada-4401-a3ec-cb3df3987cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452192445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.1452192445
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.2661267343
Short name T597
Test name
Test status
Simulation time 168295199137 ps
CPU time 139.31 seconds
Started Jun 24 04:38:47 PM PDT 24
Finished Jun 24 04:42:07 PM PDT 24
Peak memory 200500 kb
Host smart-fb2070ba-a9f6-4939-bf34-945a98db7e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661267343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.2661267343
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.3566810367
Short name T33
Test name
Test status
Simulation time 38179617940 ps
CPU time 242.81 seconds
Started Jun 24 04:37:18 PM PDT 24
Finished Jun 24 04:42:03 PM PDT 24
Peak memory 216208 kb
Host smart-5444b675-85bc-4beb-8765-207224bcd630
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566810367 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.3566810367
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.37088349
Short name T174
Test name
Test status
Simulation time 76123382482 ps
CPU time 985.15 seconds
Started Jun 24 04:37:43 PM PDT 24
Finished Jun 24 04:55:04 PM PDT 24
Peak memory 216960 kb
Host smart-86b7c374-5b0f-4faa-afd5-b46a0de4aabb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37088349 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.37088349
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.1098791571
Short name T199
Test name
Test status
Simulation time 37558389013 ps
CPU time 15.8 seconds
Started Jun 24 04:38:00 PM PDT 24
Finished Jun 24 04:39:22 PM PDT 24
Peak memory 200536 kb
Host smart-0170e54e-6e8c-479a-9575-0f992bdbc700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098791571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.1098791571
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.328591062
Short name T179
Test name
Test status
Simulation time 95586592542 ps
CPU time 171.8 seconds
Started Jun 24 04:38:07 PM PDT 24
Finished Jun 24 04:42:04 PM PDT 24
Peak memory 200544 kb
Host smart-e070864d-6226-4a81-8999-5113deb711fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328591062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.328591062
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_fifo_full.3764270054
Short name T339
Test name
Test status
Simulation time 230278867004 ps
CPU time 166.02 seconds
Started Jun 24 04:36:31 PM PDT 24
Finished Jun 24 04:39:34 PM PDT 24
Peak memory 200524 kb
Host smart-81823970-7571-4e4f-9bec-cf33beefd21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764270054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.3764270054
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.1679381745
Short name T699
Test name
Test status
Simulation time 80519044567 ps
CPU time 121.71 seconds
Started Jun 24 04:37:47 PM PDT 24
Finished Jun 24 04:40:48 PM PDT 24
Peak memory 200568 kb
Host smart-2d38fe5a-1833-465e-b1cc-fca98997f324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679381745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.1679381745
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.791985664
Short name T247
Test name
Test status
Simulation time 17122754451 ps
CPU time 12.85 seconds
Started Jun 24 04:38:02 PM PDT 24
Finished Jun 24 04:39:20 PM PDT 24
Peak memory 200508 kb
Host smart-1e4ff32f-2e1c-401d-ae65-5bf4548dfa9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791985664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.791985664
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.4253224791
Short name T37
Test name
Test status
Simulation time 19093203381 ps
CPU time 29.55 seconds
Started Jun 24 04:38:05 PM PDT 24
Finished Jun 24 04:39:42 PM PDT 24
Peak memory 200572 kb
Host smart-b755cc09-910b-4d85-b981-ccbf79dd6620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253224791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.4253224791
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.1551737578
Short name T171
Test name
Test status
Simulation time 50583768255 ps
CPU time 29.55 seconds
Started Jun 24 04:38:08 PM PDT 24
Finished Jun 24 04:39:42 PM PDT 24
Peak memory 200292 kb
Host smart-2a614651-915e-49aa-9a06-bb2608ab8659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551737578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.1551737578
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.3017556244
Short name T461
Test name
Test status
Simulation time 190246961247 ps
CPU time 163.08 seconds
Started Jun 24 04:38:14 PM PDT 24
Finished Jun 24 04:42:01 PM PDT 24
Peak memory 200464 kb
Host smart-4c592939-0079-4900-b8af-1c8d66dbfea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017556244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.3017556244
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.4056582763
Short name T187
Test name
Test status
Simulation time 153659283480 ps
CPU time 26.29 seconds
Started Jun 24 04:38:20 PM PDT 24
Finished Jun 24 04:39:51 PM PDT 24
Peak memory 200552 kb
Host smart-88bfadb9-a976-4188-a19b-a1c1330ad563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056582763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.4056582763
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.1572961267
Short name T548
Test name
Test status
Simulation time 294583752447 ps
CPU time 713.79 seconds
Started Jun 24 04:36:35 PM PDT 24
Finished Jun 24 04:48:46 PM PDT 24
Peak memory 216940 kb
Host smart-6b4e7125-2bf9-46e5-8b35-b2113469aa62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572961267 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.1572961267
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_perf.68889256
Short name T252
Test name
Test status
Simulation time 21154615042 ps
CPU time 1181.27 seconds
Started Jun 24 04:37:32 PM PDT 24
Finished Jun 24 04:58:07 PM PDT 24
Peak memory 200560 kb
Host smart-6dbce009-72db-440d-88fd-777a33ffe429
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=68889256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.68889256
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.3491903658
Short name T2
Test name
Test status
Simulation time 20978041687 ps
CPU time 22.73 seconds
Started Jun 24 04:37:48 PM PDT 24
Finished Jun 24 04:39:09 PM PDT 24
Peak memory 200520 kb
Host smart-2e8ea4fd-5b49-4ce7-87d5-a53c066e21d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491903658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.3491903658
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.131009437
Short name T162
Test name
Test status
Simulation time 42820223293 ps
CPU time 41.46 seconds
Started Jun 24 04:37:56 PM PDT 24
Finished Jun 24 04:39:38 PM PDT 24
Peak memory 200548 kb
Host smart-247e6006-a064-4964-9251-43c39882e3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131009437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.131009437
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.772322261
Short name T224
Test name
Test status
Simulation time 143085864262 ps
CPU time 264.36 seconds
Started Jun 24 04:37:55 PM PDT 24
Finished Jun 24 04:43:21 PM PDT 24
Peak memory 200468 kb
Host smart-32278393-1af6-4d5d-9e99-0ea50f8311e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772322261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.772322261
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_loopback.1608457404
Short name T333
Test name
Test status
Simulation time 2208406822 ps
CPU time 2.67 seconds
Started Jun 24 04:35:19 PM PDT 24
Finished Jun 24 04:35:23 PM PDT 24
Peak memory 197664 kb
Host smart-d32e9e9d-f7bf-44b6-8a07-d72a95ac3b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608457404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.1608457404
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.3105216542
Short name T183
Test name
Test status
Simulation time 41745202509 ps
CPU time 18.91 seconds
Started Jun 24 04:37:59 PM PDT 24
Finished Jun 24 04:39:21 PM PDT 24
Peak memory 200460 kb
Host smart-f97cae31-ceeb-4701-826d-e4f1f5ccb60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105216542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.3105216542
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_tx_rx.2477922930
Short name T588
Test name
Test status
Simulation time 56022557873 ps
CPU time 97.43 seconds
Started Jun 24 04:35:26 PM PDT 24
Finished Jun 24 04:37:04 PM PDT 24
Peak memory 200520 kb
Host smart-69f43e72-3bf0-47b6-987c-41da15584b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477922930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.2477922930
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.2969963510
Short name T231
Test name
Test status
Simulation time 118459857198 ps
CPU time 554.42 seconds
Started Jun 24 04:35:41 PM PDT 24
Finished Jun 24 04:44:57 PM PDT 24
Peak memory 216984 kb
Host smart-ede07690-a622-462b-a007-1facb22cfa51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969963510 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.2969963510
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.589956037
Short name T238
Test name
Test status
Simulation time 17504456800 ps
CPU time 7.14 seconds
Started Jun 24 04:38:12 PM PDT 24
Finished Jun 24 04:39:23 PM PDT 24
Peak memory 200564 kb
Host smart-1b8f05db-4106-42f6-b245-66bd4f89091c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589956037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.589956037
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.1536858799
Short name T249
Test name
Test status
Simulation time 56423493866 ps
CPU time 8.57 seconds
Started Jun 24 04:38:12 PM PDT 24
Finished Jun 24 04:39:24 PM PDT 24
Peak memory 200620 kb
Host smart-b971f464-12bf-44cd-972c-b4a7adf0b5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536858799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.1536858799
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.471966301
Short name T220
Test name
Test status
Simulation time 37957054528 ps
CPU time 16.18 seconds
Started Jun 24 04:38:21 PM PDT 24
Finished Jun 24 04:39:41 PM PDT 24
Peak memory 200576 kb
Host smart-689d94a2-bc42-4633-a8a0-d584acdd9009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471966301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.471966301
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.1600030050
Short name T246
Test name
Test status
Simulation time 191237422954 ps
CPU time 148.09 seconds
Started Jun 24 04:38:15 PM PDT 24
Finished Jun 24 04:41:47 PM PDT 24
Peak memory 200484 kb
Host smart-8b6c81b1-a370-45f2-a1d1-ce74aeddb54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600030050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.1600030050
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.763264331
Short name T998
Test name
Test status
Simulation time 110346302096 ps
CPU time 42.69 seconds
Started Jun 24 04:38:14 PM PDT 24
Finished Jun 24 04:40:01 PM PDT 24
Peak memory 200548 kb
Host smart-99ee9616-c454-4e5e-b3a2-7e35998814fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763264331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.763264331
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_stress_all.4117626536
Short name T239
Test name
Test status
Simulation time 131691170852 ps
CPU time 63.5 seconds
Started Jun 24 04:35:49 PM PDT 24
Finished Jun 24 04:36:59 PM PDT 24
Peak memory 200412 kb
Host smart-fa1ce5b7-da3a-427e-9def-082a3f7397fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117626536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.4117626536
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.2039788957
Short name T242
Test name
Test status
Simulation time 45631398388 ps
CPU time 20.12 seconds
Started Jun 24 04:38:30 PM PDT 24
Finished Jun 24 04:39:53 PM PDT 24
Peak memory 200480 kb
Host smart-1f6cc1f7-6888-465c-b311-9c7c2bae639c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039788957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.2039788957
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.2921994516
Short name T331
Test name
Test status
Simulation time 52932641391 ps
CPU time 479.04 seconds
Started Jun 24 04:35:56 PM PDT 24
Finished Jun 24 04:44:15 PM PDT 24
Peak memory 217068 kb
Host smart-368fbc29-eb68-4caf-9a57-66eb398cbcf4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921994516 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.2921994516
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.328757447
Short name T240
Test name
Test status
Simulation time 113583147061 ps
CPU time 208.37 seconds
Started Jun 24 04:36:00 PM PDT 24
Finished Jun 24 04:39:49 PM PDT 24
Peak memory 200480 kb
Host smart-208fe19c-c6ae-4b5e-be56-b5890b9fafe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328757447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.328757447
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.464202351
Short name T189
Test name
Test status
Simulation time 21519982151 ps
CPU time 10.65 seconds
Started Jun 24 04:38:40 PM PDT 24
Finished Jun 24 04:39:54 PM PDT 24
Peak memory 200624 kb
Host smart-45fb0b6e-169b-460c-9b25-bf6807cbb7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464202351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.464202351
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.2763809772
Short name T650
Test name
Test status
Simulation time 34761766736 ps
CPU time 48.93 seconds
Started Jun 24 04:38:51 PM PDT 24
Finished Jun 24 04:40:40 PM PDT 24
Peak memory 200484 kb
Host smart-ffeb7c88-c58c-4c87-a08f-79204ea9adbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763809772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.2763809772
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.2815078962
Short name T173
Test name
Test status
Simulation time 48738962062 ps
CPU time 14.76 seconds
Started Jun 24 04:35:00 PM PDT 24
Finished Jun 24 04:35:17 PM PDT 24
Peak memory 200544 kb
Host smart-63e6baf0-8f5d-44ea-8dfd-44a54955b41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815078962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.2815078962
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.3770664733
Short name T90
Test name
Test status
Simulation time 24583019704 ps
CPU time 35.01 seconds
Started Jun 24 04:35:28 PM PDT 24
Finished Jun 24 04:36:04 PM PDT 24
Peak memory 200524 kb
Host smart-b4d3b582-b45e-488d-ad50-b79f1a2c3619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770664733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.3770664733
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.2634033209
Short name T248
Test name
Test status
Simulation time 84492495302 ps
CPU time 86.8 seconds
Started Jun 24 04:37:45 PM PDT 24
Finished Jun 24 04:40:13 PM PDT 24
Peak memory 200524 kb
Host smart-d3204c5c-dafa-46a4-a91e-61c1f601a93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634033209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.2634033209
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1315499227
Short name T61
Test name
Test status
Simulation time 13191143 ps
CPU time 0.62 seconds
Started Jun 24 04:34:15 PM PDT 24
Finished Jun 24 04:34:16 PM PDT 24
Peak memory 194600 kb
Host smart-bec54983-7826-4f53-ae19-9d8659f34404
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315499227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.1315499227
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.282905536
Short name T1192
Test name
Test status
Simulation time 221386848 ps
CPU time 2.34 seconds
Started Jun 24 04:34:22 PM PDT 24
Finished Jun 24 04:34:26 PM PDT 24
Peak memory 196700 kb
Host smart-c6681eec-850d-496b-91a0-bb5e05c8d550
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282905536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.282905536
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.2369763916
Short name T1174
Test name
Test status
Simulation time 65671843 ps
CPU time 0.59 seconds
Started Jun 24 04:34:18 PM PDT 24
Finished Jun 24 04:34:21 PM PDT 24
Peak memory 195184 kb
Host smart-8c1c122d-3c27-401e-83ab-9681d1b17762
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369763916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.2369763916
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1431837113
Short name T1158
Test name
Test status
Simulation time 15801194 ps
CPU time 0.76 seconds
Started Jun 24 04:34:18 PM PDT 24
Finished Jun 24 04:34:20 PM PDT 24
Peak memory 198644 kb
Host smart-8cc503ac-96dd-4aec-bc0b-1fe2f1cf4b24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431837113 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.1431837113
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.2342073832
Short name T1113
Test name
Test status
Simulation time 11288813 ps
CPU time 0.63 seconds
Started Jun 24 04:34:17 PM PDT 24
Finished Jun 24 04:34:19 PM PDT 24
Peak memory 194976 kb
Host smart-f9173f23-3fde-41d5-8ead-76e27bcb662c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342073832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.2342073832
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.1222500761
Short name T1216
Test name
Test status
Simulation time 22512181 ps
CPU time 0.59 seconds
Started Jun 24 04:34:22 PM PDT 24
Finished Jun 24 04:34:25 PM PDT 24
Peak memory 193924 kb
Host smart-b423360d-1ad5-4f9d-87fe-56ab1c3d13bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222500761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.1222500761
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1281284563
Short name T70
Test name
Test status
Simulation time 21820152 ps
CPU time 0.62 seconds
Started Jun 24 04:34:22 PM PDT 24
Finished Jun 24 04:34:29 PM PDT 24
Peak memory 195452 kb
Host smart-be525dac-55b9-4ae5-baec-c56974a199f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281284563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.1281284563
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.537603114
Short name T1133
Test name
Test status
Simulation time 47748671 ps
CPU time 1.28 seconds
Started Jun 24 04:34:21 PM PDT 24
Finished Jun 24 04:34:24 PM PDT 24
Peak memory 199776 kb
Host smart-664f1870-0a42-45ed-90e6-f94eff33f70c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537603114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.537603114
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.1768988997
Short name T69
Test name
Test status
Simulation time 16148462 ps
CPU time 0.73 seconds
Started Jun 24 04:34:15 PM PDT 24
Finished Jun 24 04:34:16 PM PDT 24
Peak memory 196080 kb
Host smart-12262344-034b-47ae-a890-b4b1212e26dd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768988997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.1768988997
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.932492401
Short name T1121
Test name
Test status
Simulation time 266695307 ps
CPU time 2.75 seconds
Started Jun 24 04:34:16 PM PDT 24
Finished Jun 24 04:34:20 PM PDT 24
Peak memory 197788 kb
Host smart-e5bf9d2c-6eb4-4f58-aca7-4c7c8dff92d8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932492401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.932492401
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3453080309
Short name T1234
Test name
Test status
Simulation time 12690523 ps
CPU time 0.62 seconds
Started Jun 24 04:34:19 PM PDT 24
Finished Jun 24 04:34:21 PM PDT 24
Peak memory 195172 kb
Host smart-3e90a0f3-8582-4231-8dcb-aa1c1635f2fb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453080309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.3453080309
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2950728885
Short name T1190
Test name
Test status
Simulation time 45925267 ps
CPU time 0.83 seconds
Started Jun 24 04:34:14 PM PDT 24
Finished Jun 24 04:34:15 PM PDT 24
Peak memory 199456 kb
Host smart-dafaed19-d092-4e6d-979d-42faff54f63c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950728885 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.2950728885
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.2776129610
Short name T1115
Test name
Test status
Simulation time 80711463 ps
CPU time 0.65 seconds
Started Jun 24 04:34:17 PM PDT 24
Finished Jun 24 04:34:19 PM PDT 24
Peak memory 194652 kb
Host smart-ae3448d3-9096-47c1-b0c7-4fea9baf7394
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776129610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.2776129610
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.4043458576
Short name T1203
Test name
Test status
Simulation time 26404865 ps
CPU time 0.63 seconds
Started Jun 24 04:34:16 PM PDT 24
Finished Jun 24 04:34:18 PM PDT 24
Peak memory 194016 kb
Host smart-022a607b-092a-4952-935c-0a8077ed312a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043458576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.4043458576
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.4244934415
Short name T1186
Test name
Test status
Simulation time 60782198 ps
CPU time 0.72 seconds
Started Jun 24 04:34:24 PM PDT 24
Finished Jun 24 04:34:26 PM PDT 24
Peak memory 196852 kb
Host smart-6a144b3f-04ff-4be4-9ee7-d6c7ac57ca02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244934415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.4244934415
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.926054558
Short name T1196
Test name
Test status
Simulation time 230270459 ps
CPU time 2.23 seconds
Started Jun 24 04:34:24 PM PDT 24
Finished Jun 24 04:34:27 PM PDT 24
Peak memory 199520 kb
Host smart-5b020450-b5ce-4ff3-a2db-cf6ce9264879
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926054558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.926054558
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.1947365381
Short name T1222
Test name
Test status
Simulation time 50236551 ps
CPU time 1.03 seconds
Started Jun 24 04:34:13 PM PDT 24
Finished Jun 24 04:34:15 PM PDT 24
Peak memory 198832 kb
Host smart-61f4e1f8-2d18-4c03-b65d-d7c7baa29e9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947365381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.1947365381
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1905917122
Short name T1104
Test name
Test status
Simulation time 108630106 ps
CPU time 0.87 seconds
Started Jun 24 04:34:28 PM PDT 24
Finished Jun 24 04:34:29 PM PDT 24
Peak memory 199508 kb
Host smart-ec33f74b-bdd7-417b-98bb-b5fa021faf49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905917122 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.1905917122
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.256966936
Short name T1167
Test name
Test status
Simulation time 15080738 ps
CPU time 0.62 seconds
Started Jun 24 04:34:36 PM PDT 24
Finished Jun 24 04:34:38 PM PDT 24
Peak memory 195252 kb
Host smart-b690e719-7fd1-4e37-ac82-26b58c76fb3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256966936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.256966936
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.2701456304
Short name T1193
Test name
Test status
Simulation time 85484113 ps
CPU time 0.63 seconds
Started Jun 24 04:34:26 PM PDT 24
Finished Jun 24 04:34:27 PM PDT 24
Peak memory 193536 kb
Host smart-bfa581ca-19f8-45d0-baae-60c617091d81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701456304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.2701456304
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1471582845
Short name T1211
Test name
Test status
Simulation time 81897027 ps
CPU time 0.76 seconds
Started Jun 24 04:34:24 PM PDT 24
Finished Jun 24 04:34:26 PM PDT 24
Peak memory 195060 kb
Host smart-88902114-5d80-46c0-b328-e4784237cd89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471582845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.1471582845
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.512850077
Short name T1175
Test name
Test status
Simulation time 89140513 ps
CPU time 1.76 seconds
Started Jun 24 04:34:34 PM PDT 24
Finished Jun 24 04:34:36 PM PDT 24
Peak memory 199800 kb
Host smart-c38d6245-c43e-4b32-80ca-0b74f18b6af5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512850077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.512850077
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.4186999258
Short name T129
Test name
Test status
Simulation time 91212260 ps
CPU time 1.46 seconds
Started Jun 24 04:34:21 PM PDT 24
Finished Jun 24 04:34:24 PM PDT 24
Peak memory 199312 kb
Host smart-2568ac34-21d3-4eb9-aa82-cef3f28c940d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186999258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.4186999258
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1869255771
Short name T1111
Test name
Test status
Simulation time 23399387 ps
CPU time 1.06 seconds
Started Jun 24 04:34:20 PM PDT 24
Finished Jun 24 04:34:23 PM PDT 24
Peak memory 199680 kb
Host smart-b7e5cba5-5ada-4de1-a668-ba7e0e0e9d9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869255771 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.1869255771
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.2209348540
Short name T1139
Test name
Test status
Simulation time 15329720 ps
CPU time 0.61 seconds
Started Jun 24 04:34:32 PM PDT 24
Finished Jun 24 04:34:33 PM PDT 24
Peak memory 195316 kb
Host smart-7f1cdd39-e49f-44bb-a7bf-27fbb4673aca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209348540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.2209348540
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.2609023283
Short name T1153
Test name
Test status
Simulation time 51776461 ps
CPU time 0.66 seconds
Started Jun 24 04:34:25 PM PDT 24
Finished Jun 24 04:34:26 PM PDT 24
Peak memory 193604 kb
Host smart-ecee2940-d9fd-4a15-bac7-e7cf7e9a4394
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609023283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.2609023283
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1048586227
Short name T1152
Test name
Test status
Simulation time 18345121 ps
CPU time 0.78 seconds
Started Jun 24 04:34:21 PM PDT 24
Finished Jun 24 04:34:24 PM PDT 24
Peak memory 196884 kb
Host smart-6165c7ac-07d1-4f31-8ddf-ab5015909c61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048586227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.1048586227
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.2557131206
Short name T1150
Test name
Test status
Simulation time 90622590 ps
CPU time 1.1 seconds
Started Jun 24 04:34:42 PM PDT 24
Finished Jun 24 04:34:44 PM PDT 24
Peak memory 199676 kb
Host smart-1edb626b-3fa1-47c4-abe7-66853376f1e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557131206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.2557131206
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3021937012
Short name T82
Test name
Test status
Simulation time 1189378743 ps
CPU time 1.36 seconds
Started Jun 24 04:34:38 PM PDT 24
Finished Jun 24 04:34:40 PM PDT 24
Peak memory 199216 kb
Host smart-5b15b042-3048-4b01-8abe-2abdecd97656
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021937012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.3021937012
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3529076953
Short name T1229
Test name
Test status
Simulation time 29805798 ps
CPU time 0.84 seconds
Started Jun 24 04:34:35 PM PDT 24
Finished Jun 24 04:34:36 PM PDT 24
Peak memory 199672 kb
Host smart-d9d30180-cd21-49c2-96af-f96502921258
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529076953 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.3529076953
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.1478473442
Short name T67
Test name
Test status
Simulation time 14546251 ps
CPU time 0.63 seconds
Started Jun 24 04:34:26 PM PDT 24
Finished Jun 24 04:34:28 PM PDT 24
Peak memory 195400 kb
Host smart-7e2a9c3e-dd9a-4adc-a44c-58a3d6d4a128
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478473442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.1478473442
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.2061311538
Short name T1105
Test name
Test status
Simulation time 56112027 ps
CPU time 0.56 seconds
Started Jun 24 04:34:22 PM PDT 24
Finished Jun 24 04:34:25 PM PDT 24
Peak memory 194196 kb
Host smart-248c3b04-d8c5-4e53-84fd-5e37ad7cc5ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061311538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.2061311538
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.144127571
Short name T1185
Test name
Test status
Simulation time 46778065 ps
CPU time 0.76 seconds
Started Jun 24 04:34:21 PM PDT 24
Finished Jun 24 04:34:24 PM PDT 24
Peak memory 194640 kb
Host smart-96274f41-e595-4711-bdf5-f16a983a1bcf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144127571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_csr
_outstanding.144127571
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.4288981147
Short name T1137
Test name
Test status
Simulation time 333778159 ps
CPU time 1.24 seconds
Started Jun 24 04:34:23 PM PDT 24
Finished Jun 24 04:34:26 PM PDT 24
Peak memory 199156 kb
Host smart-18c56b32-754e-4a2d-800e-6e3a8886d595
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288981147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.4288981147
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.216901460
Short name T81
Test name
Test status
Simulation time 401734079 ps
CPU time 1.41 seconds
Started Jun 24 04:34:22 PM PDT 24
Finished Jun 24 04:34:26 PM PDT 24
Peak memory 199080 kb
Host smart-77db2b22-6ac0-4370-9d28-f89e10a10d22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216901460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.216901460
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1809011800
Short name T1149
Test name
Test status
Simulation time 109647678 ps
CPU time 1.61 seconds
Started Jun 24 04:34:28 PM PDT 24
Finished Jun 24 04:34:30 PM PDT 24
Peak memory 199800 kb
Host smart-0f23ec63-cc35-4157-80b6-50867e78280c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809011800 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.1809011800
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.884506709
Short name T1179
Test name
Test status
Simulation time 89012250 ps
CPU time 0.59 seconds
Started Jun 24 04:34:27 PM PDT 24
Finished Jun 24 04:34:29 PM PDT 24
Peak memory 195200 kb
Host smart-5717dadd-61d7-4480-af56-6d4473972aac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884506709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.884506709
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.2471864103
Short name T1197
Test name
Test status
Simulation time 31934992 ps
CPU time 0.56 seconds
Started Jun 24 04:34:22 PM PDT 24
Finished Jun 24 04:34:24 PM PDT 24
Peak memory 194248 kb
Host smart-b6f33030-1aa4-434a-94e7-62b2246571fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471864103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.2471864103
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.2797325002
Short name T76
Test name
Test status
Simulation time 55446559 ps
CPU time 0.8 seconds
Started Jun 24 04:34:21 PM PDT 24
Finished Jun 24 04:34:23 PM PDT 24
Peak memory 196968 kb
Host smart-284126ad-5986-4ccc-b9b7-4b5c72c8ed4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797325002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.2797325002
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.1357038768
Short name T1102
Test name
Test status
Simulation time 226625017 ps
CPU time 1.54 seconds
Started Jun 24 04:34:24 PM PDT 24
Finished Jun 24 04:34:27 PM PDT 24
Peak memory 199640 kb
Host smart-1694fb5b-6475-4710-bf28-5accceb5b9c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357038768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.1357038768
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.2824520813
Short name T1155
Test name
Test status
Simulation time 246327622 ps
CPU time 1.29 seconds
Started Jun 24 04:34:34 PM PDT 24
Finished Jun 24 04:34:36 PM PDT 24
Peak memory 199064 kb
Host smart-36d6b4f2-5250-4773-8ba7-840b4c339e50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824520813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.2824520813
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3930739502
Short name T1160
Test name
Test status
Simulation time 29966516 ps
CPU time 1.3 seconds
Started Jun 24 04:34:19 PM PDT 24
Finished Jun 24 04:34:22 PM PDT 24
Peak memory 199816 kb
Host smart-0a9b185d-d3ae-46dd-8800-a216dc564f2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930739502 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.3930739502
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.2438726543
Short name T74
Test name
Test status
Simulation time 22668593 ps
CPU time 0.58 seconds
Started Jun 24 04:34:27 PM PDT 24
Finished Jun 24 04:34:28 PM PDT 24
Peak memory 195108 kb
Host smart-ff36dbce-ef51-4fb8-9845-ea294db0de9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438726543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.2438726543
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.493347123
Short name T1118
Test name
Test status
Simulation time 44472033 ps
CPU time 0.55 seconds
Started Jun 24 04:35:07 PM PDT 24
Finished Jun 24 04:35:09 PM PDT 24
Peak memory 194200 kb
Host smart-97b8dd4f-62bc-46ec-ad1c-56471ef2f6fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493347123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.493347123
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.4201862327
Short name T1188
Test name
Test status
Simulation time 83332211 ps
CPU time 0.79 seconds
Started Jun 24 04:34:25 PM PDT 24
Finished Jun 24 04:34:27 PM PDT 24
Peak memory 197248 kb
Host smart-366b6e88-ac97-4dc3-b3c8-ae64fdc237f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201862327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.4201862327
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.2845417406
Short name T1225
Test name
Test status
Simulation time 41820669 ps
CPU time 1.08 seconds
Started Jun 24 04:34:57 PM PDT 24
Finished Jun 24 04:35:00 PM PDT 24
Peak memory 199692 kb
Host smart-a6ac9834-b94c-46b3-868b-a3205e5c122c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845417406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.2845417406
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.2223653818
Short name T84
Test name
Test status
Simulation time 81291538 ps
CPU time 1.03 seconds
Started Jun 24 04:34:38 PM PDT 24
Finished Jun 24 04:34:39 PM PDT 24
Peak memory 198580 kb
Host smart-3403d347-f36c-4ea4-a246-6a6e1641e5ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223653818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.2223653818
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1543804820
Short name T1173
Test name
Test status
Simulation time 90988615 ps
CPU time 1.25 seconds
Started Jun 24 04:34:35 PM PDT 24
Finished Jun 24 04:34:37 PM PDT 24
Peak memory 199828 kb
Host smart-87814386-549b-4ff6-ad74-c7ed017d82e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543804820 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.1543804820
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.4206597857
Short name T68
Test name
Test status
Simulation time 88376288 ps
CPU time 0.67 seconds
Started Jun 24 04:34:57 PM PDT 24
Finished Jun 24 04:35:00 PM PDT 24
Peak memory 195464 kb
Host smart-607896a3-dc68-4aa4-a1d8-5fffe9a1508b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206597857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.4206597857
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.3391524479
Short name T1206
Test name
Test status
Simulation time 17191871 ps
CPU time 0.57 seconds
Started Jun 24 04:34:22 PM PDT 24
Finished Jun 24 04:34:25 PM PDT 24
Peak memory 194184 kb
Host smart-8bb0747a-c06f-4728-a5e3-463aff723189
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391524479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.3391524479
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.3757251079
Short name T1218
Test name
Test status
Simulation time 23838204 ps
CPU time 0.75 seconds
Started Jun 24 04:34:23 PM PDT 24
Finished Jun 24 04:34:26 PM PDT 24
Peak memory 195028 kb
Host smart-6fb47d5f-c113-47ab-bfc6-8c02ad568090
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757251079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.3757251079
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.110128069
Short name T1208
Test name
Test status
Simulation time 1250744594 ps
CPU time 2.22 seconds
Started Jun 24 04:34:21 PM PDT 24
Finished Jun 24 04:34:25 PM PDT 24
Peak memory 198952 kb
Host smart-79f91aa0-0696-4581-a27b-351a58ca22cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110128069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.110128069
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1433136629
Short name T1223
Test name
Test status
Simulation time 295626409 ps
CPU time 1.35 seconds
Started Jun 24 04:34:21 PM PDT 24
Finished Jun 24 04:34:24 PM PDT 24
Peak memory 199144 kb
Host smart-ef66d7ab-8f47-4aaa-8da3-6b8f311938f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433136629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.1433136629
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.4072087777
Short name T1233
Test name
Test status
Simulation time 87601870 ps
CPU time 0.78 seconds
Started Jun 24 04:34:28 PM PDT 24
Finished Jun 24 04:34:30 PM PDT 24
Peak memory 199712 kb
Host smart-90d834fc-3a22-4932-aaa3-d839a3f221d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072087777 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.4072087777
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.2805923969
Short name T1184
Test name
Test status
Simulation time 11177729 ps
CPU time 0.63 seconds
Started Jun 24 04:34:25 PM PDT 24
Finished Jun 24 04:34:26 PM PDT 24
Peak memory 194100 kb
Host smart-1d42a4af-3c7f-414d-b863-549b3586038c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805923969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.2805923969
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.79516995
Short name T1126
Test name
Test status
Simulation time 111421514 ps
CPU time 0.78 seconds
Started Jun 24 04:34:29 PM PDT 24
Finished Jun 24 04:34:30 PM PDT 24
Peak memory 196016 kb
Host smart-c650d577-6d65-4732-958b-5e23a2bfed4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79516995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_csr_
outstanding.79516995
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.463548571
Short name T1147
Test name
Test status
Simulation time 286736289 ps
CPU time 1.55 seconds
Started Jun 24 04:34:28 PM PDT 24
Finished Jun 24 04:34:31 PM PDT 24
Peak memory 199812 kb
Host smart-e8a75a95-fdd3-491d-9b3b-be25b7ed0ad4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463548571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.463548571
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.740899291
Short name T1129
Test name
Test status
Simulation time 57780114 ps
CPU time 0.67 seconds
Started Jun 24 04:34:28 PM PDT 24
Finished Jun 24 04:34:30 PM PDT 24
Peak memory 197784 kb
Host smart-22ed91f8-208b-4368-824a-4ee8208070ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740899291 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.740899291
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.1834992035
Short name T77
Test name
Test status
Simulation time 38471139 ps
CPU time 0.58 seconds
Started Jun 24 04:34:28 PM PDT 24
Finished Jun 24 04:34:29 PM PDT 24
Peak memory 195236 kb
Host smart-eb947991-1a39-42fa-99c2-f4585ae475c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834992035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.1834992035
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.2607451929
Short name T1142
Test name
Test status
Simulation time 21110836 ps
CPU time 0.57 seconds
Started Jun 24 04:34:27 PM PDT 24
Finished Jun 24 04:34:28 PM PDT 24
Peak memory 194180 kb
Host smart-3213a6c6-8042-49ed-ae65-92999acc3d03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607451929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.2607451929
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.855636173
Short name T1114
Test name
Test status
Simulation time 123448479 ps
CPU time 0.65 seconds
Started Jun 24 04:34:25 PM PDT 24
Finished Jun 24 04:34:26 PM PDT 24
Peak memory 195256 kb
Host smart-13706c07-db00-493e-a5ed-13154e555705
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855636173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr
_outstanding.855636173
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.3618531925
Short name T1119
Test name
Test status
Simulation time 47791052 ps
CPU time 1.25 seconds
Started Jun 24 04:34:28 PM PDT 24
Finished Jun 24 04:34:30 PM PDT 24
Peak memory 199868 kb
Host smart-d3d98dc1-1299-4f68-9abc-c970e63a60d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618531925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.3618531925
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3882110489
Short name T1194
Test name
Test status
Simulation time 67604161 ps
CPU time 1.26 seconds
Started Jun 24 04:34:29 PM PDT 24
Finished Jun 24 04:34:32 PM PDT 24
Peak memory 199092 kb
Host smart-237f645f-e9fb-4395-9975-d3b1ae096244
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882110489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.3882110489
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1187556713
Short name T1212
Test name
Test status
Simulation time 57688385 ps
CPU time 0.8 seconds
Started Jun 24 04:34:42 PM PDT 24
Finished Jun 24 04:34:44 PM PDT 24
Peak memory 199672 kb
Host smart-5a9bc446-0ba7-4d67-8f2f-4e6f9057b8c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187556713 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.1187556713
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.2302465375
Short name T62
Test name
Test status
Simulation time 17421425 ps
CPU time 0.64 seconds
Started Jun 24 04:34:42 PM PDT 24
Finished Jun 24 04:34:44 PM PDT 24
Peak memory 195480 kb
Host smart-e5260f62-8a1d-4a53-b044-dd8aaf71ea36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302465375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.2302465375
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.509297693
Short name T1189
Test name
Test status
Simulation time 18391821 ps
CPU time 0.61 seconds
Started Jun 24 04:34:26 PM PDT 24
Finished Jun 24 04:34:27 PM PDT 24
Peak memory 194168 kb
Host smart-33a4eb3f-024b-4a71-9406-fc26ab60ef69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509297693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.509297693
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2720074998
Short name T1156
Test name
Test status
Simulation time 98617967 ps
CPU time 0.76 seconds
Started Jun 24 04:34:43 PM PDT 24
Finished Jun 24 04:34:45 PM PDT 24
Peak memory 195888 kb
Host smart-f51017e0-30b1-42eb-abd4-4a3fd435c57f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720074998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.2720074998
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.3745381335
Short name T1120
Test name
Test status
Simulation time 585000684 ps
CPU time 1.22 seconds
Started Jun 24 04:34:40 PM PDT 24
Finished Jun 24 04:34:43 PM PDT 24
Peak memory 199816 kb
Host smart-6ca7748a-d826-449c-ae52-702a2af4252c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745381335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.3745381335
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1166059208
Short name T127
Test name
Test status
Simulation time 92299906 ps
CPU time 0.98 seconds
Started Jun 24 04:34:49 PM PDT 24
Finished Jun 24 04:34:52 PM PDT 24
Peak memory 198816 kb
Host smart-8a316829-1b47-4a9b-9945-c5d0e3535929
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166059208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.1166059208
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2865168220
Short name T1210
Test name
Test status
Simulation time 52542998 ps
CPU time 0.82 seconds
Started Jun 24 04:35:23 PM PDT 24
Finished Jun 24 04:35:24 PM PDT 24
Peak memory 199692 kb
Host smart-9ac32d74-19a7-4cf3-9b4a-d2292163f918
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865168220 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.2865168220
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.1874066420
Short name T1145
Test name
Test status
Simulation time 11165871 ps
CPU time 0.56 seconds
Started Jun 24 04:34:43 PM PDT 24
Finished Jun 24 04:34:45 PM PDT 24
Peak memory 195200 kb
Host smart-8b69eec4-885a-4cbf-9ef4-0f8cac9650d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874066420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.1874066420
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.2845727963
Short name T1103
Test name
Test status
Simulation time 46741411 ps
CPU time 0.58 seconds
Started Jun 24 04:34:39 PM PDT 24
Finished Jun 24 04:34:40 PM PDT 24
Peak memory 194248 kb
Host smart-4dda11b6-e9ab-482f-b60d-ea1a128fea32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845727963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.2845727963
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1880052649
Short name T1195
Test name
Test status
Simulation time 15902247 ps
CPU time 0.63 seconds
Started Jun 24 04:34:40 PM PDT 24
Finished Jun 24 04:34:41 PM PDT 24
Peak memory 195464 kb
Host smart-a168a622-b8f8-40d3-827b-8719bbcac1df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880052649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.1880052649
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.919955875
Short name T1165
Test name
Test status
Simulation time 336384683 ps
CPU time 1.9 seconds
Started Jun 24 04:34:36 PM PDT 24
Finished Jun 24 04:34:38 PM PDT 24
Peak memory 199868 kb
Host smart-ad8ba17f-f127-481c-91b8-8eeea7880b87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919955875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.919955875
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2361918438
Short name T1125
Test name
Test status
Simulation time 164882775 ps
CPU time 0.93 seconds
Started Jun 24 04:35:15 PM PDT 24
Finished Jun 24 04:35:18 PM PDT 24
Peak memory 198756 kb
Host smart-d031803d-2bff-4578-95f9-2bbcd2b3f1ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361918438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.2361918438
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.653279306
Short name T1198
Test name
Test status
Simulation time 15687969 ps
CPU time 0.69 seconds
Started Jun 24 04:34:22 PM PDT 24
Finished Jun 24 04:34:24 PM PDT 24
Peak memory 194984 kb
Host smart-f1bfe268-f8b8-4201-921c-ed902c0e2cb3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653279306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.653279306
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1316728414
Short name T1109
Test name
Test status
Simulation time 258899406 ps
CPU time 2.61 seconds
Started Jun 24 04:34:17 PM PDT 24
Finished Jun 24 04:34:21 PM PDT 24
Peak memory 197680 kb
Host smart-3068df4b-bd08-4aca-8da9-1e81aea0ccd4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316728414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.1316728414
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3529589984
Short name T63
Test name
Test status
Simulation time 44165957 ps
CPU time 0.64 seconds
Started Jun 24 04:34:19 PM PDT 24
Finished Jun 24 04:34:22 PM PDT 24
Peak memory 194556 kb
Host smart-5d6ed627-45b6-4462-b33d-2bd05674418a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529589984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.3529589984
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.2756800052
Short name T1163
Test name
Test status
Simulation time 20276499 ps
CPU time 1.07 seconds
Started Jun 24 04:34:14 PM PDT 24
Finished Jun 24 04:34:16 PM PDT 24
Peak memory 199696 kb
Host smart-5fac81b0-10c4-4e2c-8f9a-a935a480f73f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756800052 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.2756800052
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.1699433668
Short name T1214
Test name
Test status
Simulation time 63335622 ps
CPU time 0.65 seconds
Started Jun 24 04:34:16 PM PDT 24
Finished Jun 24 04:34:17 PM PDT 24
Peak memory 195200 kb
Host smart-ef2f71e7-25b4-48e3-85a8-d561791bafb2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699433668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.1699433668
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.1163280136
Short name T1209
Test name
Test status
Simulation time 17173766 ps
CPU time 0.61 seconds
Started Jun 24 04:34:21 PM PDT 24
Finished Jun 24 04:34:24 PM PDT 24
Peak memory 193596 kb
Host smart-8824414c-08de-4bb6-9911-7d33ec7a5b67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163280136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.1163280136
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.4227300130
Short name T1187
Test name
Test status
Simulation time 34071035 ps
CPU time 0.76 seconds
Started Jun 24 04:34:15 PM PDT 24
Finished Jun 24 04:34:16 PM PDT 24
Peak memory 196692 kb
Host smart-cfb427f5-fad8-4001-9a9d-720e7068a1b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227300130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.4227300130
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.936049938
Short name T1117
Test name
Test status
Simulation time 79774877 ps
CPU time 1.62 seconds
Started Jun 24 04:34:15 PM PDT 24
Finished Jun 24 04:34:17 PM PDT 24
Peak memory 199804 kb
Host smart-a6616811-9026-4eea-a9fa-0d511c7a0311
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936049938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.936049938
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.2861270912
Short name T80
Test name
Test status
Simulation time 127157153 ps
CPU time 1.04 seconds
Started Jun 24 04:34:18 PM PDT 24
Finished Jun 24 04:34:21 PM PDT 24
Peak memory 198076 kb
Host smart-597481fc-5eb8-4638-8d98-a064e7e463ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861270912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.2861270912
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.3040048460
Short name T1201
Test name
Test status
Simulation time 53776679 ps
CPU time 0.57 seconds
Started Jun 24 04:34:32 PM PDT 24
Finished Jun 24 04:34:33 PM PDT 24
Peak memory 193536 kb
Host smart-be2e75ab-4649-4a57-9628-ce516f58a525
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040048460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.3040048460
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.3796057451
Short name T1135
Test name
Test status
Simulation time 55816046 ps
CPU time 0.64 seconds
Started Jun 24 04:34:37 PM PDT 24
Finished Jun 24 04:34:39 PM PDT 24
Peak memory 193600 kb
Host smart-ff599f33-9ab0-4701-82e2-a8c013160f26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796057451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.3796057451
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.2354165953
Short name T1204
Test name
Test status
Simulation time 44731713 ps
CPU time 0.58 seconds
Started Jun 24 04:34:42 PM PDT 24
Finished Jun 24 04:34:43 PM PDT 24
Peak memory 194180 kb
Host smart-06619355-cea4-427b-bf90-b02a003ce6ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354165953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.2354165953
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.2592019559
Short name T1132
Test name
Test status
Simulation time 10850350 ps
CPU time 0.57 seconds
Started Jun 24 04:34:28 PM PDT 24
Finished Jun 24 04:34:30 PM PDT 24
Peak memory 194192 kb
Host smart-4c6de7fc-635a-4432-ad06-62736569220e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592019559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.2592019559
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.1144519786
Short name T1180
Test name
Test status
Simulation time 16062036 ps
CPU time 0.59 seconds
Started Jun 24 04:34:44 PM PDT 24
Finished Jun 24 04:34:46 PM PDT 24
Peak memory 194188 kb
Host smart-f544bbd5-97ae-4abe-bed3-dab116905fe7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144519786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.1144519786
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.2753527970
Short name T1177
Test name
Test status
Simulation time 71175926 ps
CPU time 0.61 seconds
Started Jun 24 04:34:35 PM PDT 24
Finished Jun 24 04:34:37 PM PDT 24
Peak memory 194264 kb
Host smart-5a0a9229-0a7e-4d62-91c5-ffd5e1e21d6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753527970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.2753527970
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.3562585560
Short name T1151
Test name
Test status
Simulation time 18016413 ps
CPU time 0.61 seconds
Started Jun 24 04:34:35 PM PDT 24
Finished Jun 24 04:34:36 PM PDT 24
Peak memory 194264 kb
Host smart-f9f2db70-caf8-4250-a176-5b6cb033749f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562585560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.3562585560
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.3702235802
Short name T1228
Test name
Test status
Simulation time 13182380 ps
CPU time 0.62 seconds
Started Jun 24 04:34:33 PM PDT 24
Finished Jun 24 04:34:34 PM PDT 24
Peak memory 193520 kb
Host smart-2f332f09-6457-4a32-92dc-101af58681f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702235802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.3702235802
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.150854764
Short name T1230
Test name
Test status
Simulation time 22392789 ps
CPU time 0.59 seconds
Started Jun 24 04:34:34 PM PDT 24
Finished Jun 24 04:34:35 PM PDT 24
Peak memory 194192 kb
Host smart-54f3b940-87df-4ecd-b255-31baf105760a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150854764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.150854764
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.3181833694
Short name T1178
Test name
Test status
Simulation time 13587027 ps
CPU time 0.58 seconds
Started Jun 24 04:34:37 PM PDT 24
Finished Jun 24 04:34:38 PM PDT 24
Peak memory 194200 kb
Host smart-3e096d74-01ac-4c24-a3ee-b141991aa5f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181833694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.3181833694
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1808042575
Short name T65
Test name
Test status
Simulation time 120131687 ps
CPU time 0.78 seconds
Started Jun 24 04:34:45 PM PDT 24
Finished Jun 24 04:34:47 PM PDT 24
Peak memory 196124 kb
Host smart-3607c882-a96b-4684-ba63-06def117da57
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808042575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.1808042575
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.2549401137
Short name T66
Test name
Test status
Simulation time 109143273 ps
CPU time 2.21 seconds
Started Jun 24 04:34:15 PM PDT 24
Finished Jun 24 04:34:18 PM PDT 24
Peak memory 197164 kb
Host smart-79a399c8-5494-4b7d-bb9f-99c2bb9fdc8d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549401137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.2549401137
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.1944452866
Short name T1200
Test name
Test status
Simulation time 1031768167 ps
CPU time 2.23 seconds
Started Jun 24 04:34:58 PM PDT 24
Finished Jun 24 04:35:02 PM PDT 24
Peak memory 195220 kb
Host smart-9b8c4cfa-411f-4f60-8ee5-2c3f1e438ce5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944452866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.1944452866
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3417700421
Short name T1116
Test name
Test status
Simulation time 76044197 ps
CPU time 1.03 seconds
Started Jun 24 04:34:16 PM PDT 24
Finished Jun 24 04:34:18 PM PDT 24
Peak memory 199688 kb
Host smart-2d514dab-936c-47cc-ac32-62f156f829b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417700421 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.3417700421
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.491501824
Short name T71
Test name
Test status
Simulation time 12593216 ps
CPU time 0.72 seconds
Started Jun 24 04:34:16 PM PDT 24
Finished Jun 24 04:34:18 PM PDT 24
Peak memory 194564 kb
Host smart-48f9afd7-0990-4ce0-b383-a1f356108d6b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491501824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.491501824
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.3135981849
Short name T1215
Test name
Test status
Simulation time 17127498 ps
CPU time 0.62 seconds
Started Jun 24 04:34:17 PM PDT 24
Finished Jun 24 04:34:19 PM PDT 24
Peak memory 193972 kb
Host smart-db389db3-7429-44a7-ba6c-4c8e906609c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135981849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.3135981849
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.1440176056
Short name T1176
Test name
Test status
Simulation time 18652487 ps
CPU time 0.67 seconds
Started Jun 24 04:35:04 PM PDT 24
Finished Jun 24 04:35:06 PM PDT 24
Peak memory 194520 kb
Host smart-b34cb99f-b1f0-40c1-b959-28ccbbce639c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440176056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.1440176056
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.4240341658
Short name T1162
Test name
Test status
Simulation time 94885465 ps
CPU time 1.98 seconds
Started Jun 24 04:34:14 PM PDT 24
Finished Jun 24 04:34:17 PM PDT 24
Peak memory 199176 kb
Host smart-d4fc4a40-f1dd-443f-9ab0-10b6bef33e27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240341658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.4240341658
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.327340913
Short name T86
Test name
Test status
Simulation time 555903772 ps
CPU time 0.98 seconds
Started Jun 24 04:34:15 PM PDT 24
Finished Jun 24 04:34:17 PM PDT 24
Peak memory 197796 kb
Host smart-0ab36a8e-c1ca-4d9d-8268-8a6dd7d2cac1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327340913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.327340913
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.608637050
Short name T1161
Test name
Test status
Simulation time 12603065 ps
CPU time 0.56 seconds
Started Jun 24 04:34:42 PM PDT 24
Finished Jun 24 04:34:44 PM PDT 24
Peak memory 193936 kb
Host smart-b0ae596c-28b7-41b9-8fc4-1e802fcde20b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608637050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.608637050
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.2693870862
Short name T1136
Test name
Test status
Simulation time 20860838 ps
CPU time 0.57 seconds
Started Jun 24 04:34:33 PM PDT 24
Finished Jun 24 04:34:34 PM PDT 24
Peak memory 194248 kb
Host smart-a0926cea-3cb1-4eaa-92a9-8a07c7ba9a3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693870862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.2693870862
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.2044654175
Short name T1183
Test name
Test status
Simulation time 44431272 ps
CPU time 0.58 seconds
Started Jun 24 04:34:26 PM PDT 24
Finished Jun 24 04:34:28 PM PDT 24
Peak memory 194260 kb
Host smart-95f44ada-5b66-43ec-9996-c23eb44f42e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044654175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.2044654175
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.2851645414
Short name T1134
Test name
Test status
Simulation time 16461544 ps
CPU time 0.59 seconds
Started Jun 24 04:34:36 PM PDT 24
Finished Jun 24 04:34:37 PM PDT 24
Peak memory 194284 kb
Host smart-f1cbffcd-bf7d-4a0b-b02f-edfdf7212ab7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851645414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.2851645414
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.2782488395
Short name T1182
Test name
Test status
Simulation time 12369961 ps
CPU time 0.58 seconds
Started Jun 24 04:34:31 PM PDT 24
Finished Jun 24 04:34:33 PM PDT 24
Peak memory 194264 kb
Host smart-e9bee3dd-04b5-46f3-9058-86653c75b88f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782488395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.2782488395
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.587180266
Short name T1171
Test name
Test status
Simulation time 26908557 ps
CPU time 0.58 seconds
Started Jun 24 04:34:33 PM PDT 24
Finished Jun 24 04:34:34 PM PDT 24
Peak memory 194100 kb
Host smart-6c0fbad7-153c-4d8d-8882-337ec790c777
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587180266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.587180266
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.765602876
Short name T1224
Test name
Test status
Simulation time 12110209 ps
CPU time 0.56 seconds
Started Jun 24 04:35:10 PM PDT 24
Finished Jun 24 04:35:12 PM PDT 24
Peak memory 194160 kb
Host smart-a33f6dc9-7731-4a3e-8b55-966af7c8bae8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765602876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.765602876
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.2265837956
Short name T1232
Test name
Test status
Simulation time 14868343 ps
CPU time 0.59 seconds
Started Jun 24 04:34:26 PM PDT 24
Finished Jun 24 04:34:27 PM PDT 24
Peak memory 194136 kb
Host smart-e433e9bb-ebe7-44e3-b7d3-acb679c2fe59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265837956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.2265837956
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.3184712860
Short name T1205
Test name
Test status
Simulation time 15846534 ps
CPU time 0.58 seconds
Started Jun 24 04:34:38 PM PDT 24
Finished Jun 24 04:34:39 PM PDT 24
Peak memory 194140 kb
Host smart-f19a3d71-2c3e-4756-9178-ee9815e1e4aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184712860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.3184712860
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.2163291367
Short name T1146
Test name
Test status
Simulation time 29849054 ps
CPU time 0.59 seconds
Started Jun 24 04:34:34 PM PDT 24
Finished Jun 24 04:34:35 PM PDT 24
Peak memory 194100 kb
Host smart-3d3a5b1d-c83d-4178-9ab2-eab7b6d4d2c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163291367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.2163291367
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.2160578966
Short name T1172
Test name
Test status
Simulation time 46852427 ps
CPU time 0.7 seconds
Started Jun 24 04:34:13 PM PDT 24
Finished Jun 24 04:34:14 PM PDT 24
Peak memory 195620 kb
Host smart-16513936-faab-46bb-8f5d-6a632b198392
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160578966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.2160578966
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1925297578
Short name T1207
Test name
Test status
Simulation time 698674177 ps
CPU time 2.43 seconds
Started Jun 24 04:34:57 PM PDT 24
Finished Jun 24 04:35:02 PM PDT 24
Peak memory 197532 kb
Host smart-dc1da30c-57c6-45da-8d14-09cf9d982d51
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925297578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.1925297578
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2150846469
Short name T1221
Test name
Test status
Simulation time 23680456 ps
CPU time 0.58 seconds
Started Jun 24 04:35:08 PM PDT 24
Finished Jun 24 04:35:10 PM PDT 24
Peak memory 195220 kb
Host smart-e5f3a4e1-b859-4092-b748-722fdc68d024
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150846469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.2150846469
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.18720299
Short name T1127
Test name
Test status
Simulation time 48260697 ps
CPU time 0.65 seconds
Started Jun 24 04:34:21 PM PDT 24
Finished Jun 24 04:34:24 PM PDT 24
Peak memory 197160 kb
Host smart-3751aba8-04da-4994-af37-2b6be67f7073
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18720299 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.18720299
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.4089646113
Short name T64
Test name
Test status
Simulation time 28185292 ps
CPU time 0.6 seconds
Started Jun 24 04:34:17 PM PDT 24
Finished Jun 24 04:34:19 PM PDT 24
Peak memory 195216 kb
Host smart-31bb03d8-bf17-415c-a755-a5daf3d48015
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089646113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.4089646113
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.3314898737
Short name T1213
Test name
Test status
Simulation time 13836337 ps
CPU time 0.64 seconds
Started Jun 24 04:34:36 PM PDT 24
Finished Jun 24 04:34:38 PM PDT 24
Peak memory 194172 kb
Host smart-4b7b5b6e-a352-44b9-9655-e1e99d146122
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314898737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.3314898737
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.3405651611
Short name T75
Test name
Test status
Simulation time 31486053 ps
CPU time 0.81 seconds
Started Jun 24 04:34:13 PM PDT 24
Finished Jun 24 04:34:14 PM PDT 24
Peak memory 195488 kb
Host smart-66d63abf-1a99-4bdb-8f92-44c4cd8e2807
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405651611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.3405651611
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.876398723
Short name T1220
Test name
Test status
Simulation time 401524482 ps
CPU time 2.16 seconds
Started Jun 24 04:34:16 PM PDT 24
Finished Jun 24 04:34:19 PM PDT 24
Peak memory 199156 kb
Host smart-9ba0ad46-1e7d-45f6-82f5-3cb4c7bb65f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876398723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.876398723
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2728089708
Short name T1128
Test name
Test status
Simulation time 43730959 ps
CPU time 0.92 seconds
Started Jun 24 04:34:19 PM PDT 24
Finished Jun 24 04:34:21 PM PDT 24
Peak memory 198536 kb
Host smart-b0216ce7-6ecb-4cd7-913e-128ea28502be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728089708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.2728089708
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.3599858935
Short name T1124
Test name
Test status
Simulation time 25040299 ps
CPU time 0.59 seconds
Started Jun 24 04:35:10 PM PDT 24
Finished Jun 24 04:35:12 PM PDT 24
Peak memory 194200 kb
Host smart-1c139258-c8b4-407b-ae45-454b14cb95f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599858935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.3599858935
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.262634268
Short name T1226
Test name
Test status
Simulation time 35042456 ps
CPU time 0.55 seconds
Started Jun 24 04:34:50 PM PDT 24
Finished Jun 24 04:34:52 PM PDT 24
Peak memory 194192 kb
Host smart-0b0fc945-1688-4202-a36f-af98703a5b16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262634268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.262634268
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.450380880
Short name T1141
Test name
Test status
Simulation time 21018810 ps
CPU time 0.63 seconds
Started Jun 24 04:34:28 PM PDT 24
Finished Jun 24 04:34:30 PM PDT 24
Peak memory 193532 kb
Host smart-7ee681bb-d85d-4733-8ab3-524710a55978
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450380880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.450380880
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.4069787914
Short name T1181
Test name
Test status
Simulation time 28427963 ps
CPU time 0.57 seconds
Started Jun 24 04:34:49 PM PDT 24
Finished Jun 24 04:34:51 PM PDT 24
Peak memory 194180 kb
Host smart-8a241086-ee3e-488b-a791-522837d73707
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069787914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.4069787914
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.2157701281
Short name T1112
Test name
Test status
Simulation time 31182999 ps
CPU time 0.58 seconds
Started Jun 24 04:34:26 PM PDT 24
Finished Jun 24 04:34:28 PM PDT 24
Peak memory 194196 kb
Host smart-8dec0dc4-2c4a-47e1-b854-0f529e721e83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157701281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.2157701281
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.3580596696
Short name T1138
Test name
Test status
Simulation time 12911616 ps
CPU time 0.53 seconds
Started Jun 24 04:34:27 PM PDT 24
Finished Jun 24 04:34:28 PM PDT 24
Peak memory 194220 kb
Host smart-9d7fe5cb-b7b3-4b76-a797-0bf1945cbe8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580596696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.3580596696
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.1031971466
Short name T1106
Test name
Test status
Simulation time 22050965 ps
CPU time 0.57 seconds
Started Jun 24 04:34:34 PM PDT 24
Finished Jun 24 04:34:35 PM PDT 24
Peak memory 194264 kb
Host smart-6ae9b58d-9a8f-4a99-9aba-df2b6d719b85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031971466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.1031971466
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.28967123
Short name T1140
Test name
Test status
Simulation time 49620563 ps
CPU time 0.58 seconds
Started Jun 24 04:35:11 PM PDT 24
Finished Jun 24 04:35:13 PM PDT 24
Peak memory 194196 kb
Host smart-12aee7d2-d7a2-48e4-9bce-564aaba59c62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28967123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.28967123
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.3911567204
Short name T1217
Test name
Test status
Simulation time 52069285 ps
CPU time 0.58 seconds
Started Jun 24 04:34:38 PM PDT 24
Finished Jun 24 04:34:39 PM PDT 24
Peak memory 194100 kb
Host smart-6fae85c0-b2dc-402f-b5bf-51bd72bfcfb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911567204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.3911567204
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.1529165097
Short name T1169
Test name
Test status
Simulation time 54213717 ps
CPU time 0.55 seconds
Started Jun 24 04:34:49 PM PDT 24
Finished Jun 24 04:34:51 PM PDT 24
Peak memory 194264 kb
Host smart-e81577a7-d09d-49b4-b9be-293c9afd7e38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529165097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.1529165097
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3102930676
Short name T1164
Test name
Test status
Simulation time 16819093 ps
CPU time 0.82 seconds
Started Jun 24 04:34:25 PM PDT 24
Finished Jun 24 04:34:27 PM PDT 24
Peak memory 199628 kb
Host smart-68a0f633-6291-4aea-89bb-edbba02e2c70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102930676 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.3102930676
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.1240184644
Short name T1122
Test name
Test status
Simulation time 21890037 ps
CPU time 0.57 seconds
Started Jun 24 04:35:09 PM PDT 24
Finished Jun 24 04:35:11 PM PDT 24
Peak memory 195216 kb
Host smart-41431769-0699-4bc4-ae5f-26f661b7656c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240184644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.1240184644
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.1985177127
Short name T1108
Test name
Test status
Simulation time 124686332 ps
CPU time 0.58 seconds
Started Jun 24 04:34:36 PM PDT 24
Finished Jun 24 04:34:38 PM PDT 24
Peak memory 194232 kb
Host smart-3d818eae-b4e1-46f1-b18a-e0ddbcf33383
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985177127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.1985177127
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2293223579
Short name T1219
Test name
Test status
Simulation time 33256061 ps
CPU time 0.76 seconds
Started Jun 24 04:34:25 PM PDT 24
Finished Jun 24 04:34:27 PM PDT 24
Peak memory 196448 kb
Host smart-f8f2f8dd-cedb-4830-816b-7213e6ac8777
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293223579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.2293223579
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.2125561018
Short name T1130
Test name
Test status
Simulation time 93949985 ps
CPU time 1.34 seconds
Started Jun 24 04:34:18 PM PDT 24
Finished Jun 24 04:34:21 PM PDT 24
Peak memory 199132 kb
Host smart-80488997-6d85-4679-be28-eb96c9b213b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125561018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.2125561018
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1912969130
Short name T1110
Test name
Test status
Simulation time 84760194 ps
CPU time 0.84 seconds
Started Jun 24 04:34:19 PM PDT 24
Finished Jun 24 04:34:21 PM PDT 24
Peak memory 199576 kb
Host smart-8c53d8b2-7ec3-4e86-b696-5f35996a05ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912969130 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.1912969130
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.2957123049
Short name T1170
Test name
Test status
Simulation time 11745944 ps
CPU time 0.58 seconds
Started Jun 24 04:34:22 PM PDT 24
Finished Jun 24 04:34:24 PM PDT 24
Peak memory 195168 kb
Host smart-4c919dcd-05e9-4875-9fc5-f0c7a4931ad5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957123049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.2957123049
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.1160245388
Short name T1107
Test name
Test status
Simulation time 80032413 ps
CPU time 0.6 seconds
Started Jun 24 04:34:16 PM PDT 24
Finished Jun 24 04:34:17 PM PDT 24
Peak memory 194028 kb
Host smart-068a0079-5cf9-4faf-9772-b78905a405f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160245388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.1160245388
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.3397618083
Short name T1191
Test name
Test status
Simulation time 28010308 ps
CPU time 0.74 seconds
Started Jun 24 04:34:54 PM PDT 24
Finished Jun 24 04:34:57 PM PDT 24
Peak memory 197764 kb
Host smart-13bbc760-10a4-4e4d-b2ce-fc145d2bf9e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397618083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.3397618083
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.515873037
Short name T1131
Test name
Test status
Simulation time 231684907 ps
CPU time 2.25 seconds
Started Jun 24 04:34:30 PM PDT 24
Finished Jun 24 04:34:33 PM PDT 24
Peak memory 199116 kb
Host smart-1929bd2e-44ca-42b4-be08-a843d4d19f6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515873037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.515873037
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.1225711115
Short name T1144
Test name
Test status
Simulation time 51706916 ps
CPU time 1.04 seconds
Started Jun 24 04:34:20 PM PDT 24
Finished Jun 24 04:34:24 PM PDT 24
Peak memory 198632 kb
Host smart-9607d87e-cfe0-411e-b44b-cf3daa65371e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225711115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.1225711115
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2381847364
Short name T1143
Test name
Test status
Simulation time 85915958 ps
CPU time 1.05 seconds
Started Jun 24 04:34:15 PM PDT 24
Finished Jun 24 04:34:17 PM PDT 24
Peak memory 199624 kb
Host smart-39fd826b-08d1-44da-92eb-91afcbb9f866
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381847364 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.2381847364
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.1521968033
Short name T1168
Test name
Test status
Simulation time 20083520 ps
CPU time 0.61 seconds
Started Jun 24 04:34:19 PM PDT 24
Finished Jun 24 04:34:21 PM PDT 24
Peak memory 195164 kb
Host smart-301e041e-1cca-43b4-956d-cca5e4a1a392
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521968033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.1521968033
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.3357072773
Short name T1231
Test name
Test status
Simulation time 25335921 ps
CPU time 0.61 seconds
Started Jun 24 04:34:22 PM PDT 24
Finished Jun 24 04:34:24 PM PDT 24
Peak memory 194012 kb
Host smart-7cf2661a-c53c-4955-895e-6c51b81fb5e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357072773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.3357072773
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1578400764
Short name T72
Test name
Test status
Simulation time 73233338 ps
CPU time 0.71 seconds
Started Jun 24 04:34:20 PM PDT 24
Finished Jun 24 04:34:24 PM PDT 24
Peak memory 195040 kb
Host smart-52831ff3-f73b-44a4-b5d4-4316950d6b48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578400764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.1578400764
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.201474792
Short name T1154
Test name
Test status
Simulation time 224771463 ps
CPU time 1.44 seconds
Started Jun 24 04:34:16 PM PDT 24
Finished Jun 24 04:34:19 PM PDT 24
Peak memory 199848 kb
Host smart-e4f5ad4e-8251-4699-8b09-e3b2acbf1429
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201474792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.201474792
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1710865854
Short name T128
Test name
Test status
Simulation time 82291105 ps
CPU time 1.31 seconds
Started Jun 24 04:34:52 PM PDT 24
Finished Jun 24 04:34:54 PM PDT 24
Peak memory 198988 kb
Host smart-a33795e2-c6b5-4ee6-b8b5-17c8b3b48557
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710865854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.1710865854
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3700414444
Short name T1157
Test name
Test status
Simulation time 19565979 ps
CPU time 0.68 seconds
Started Jun 24 04:35:00 PM PDT 24
Finished Jun 24 04:35:02 PM PDT 24
Peak memory 197472 kb
Host smart-7b06a3df-0722-4f04-8a77-1cb39ba1b8bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700414444 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.3700414444
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.3170744552
Short name T1123
Test name
Test status
Simulation time 14741659 ps
CPU time 0.62 seconds
Started Jun 24 04:34:26 PM PDT 24
Finished Jun 24 04:34:27 PM PDT 24
Peak memory 195612 kb
Host smart-c34f6136-be2d-4870-b2e4-32c653fd8aad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170744552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.3170744552
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.1257032682
Short name T1148
Test name
Test status
Simulation time 23071542 ps
CPU time 0.62 seconds
Started Jun 24 04:34:33 PM PDT 24
Finished Jun 24 04:34:34 PM PDT 24
Peak memory 194168 kb
Host smart-11c27065-d03d-4498-b079-e40d8ff0262b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257032682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.1257032682
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1294644275
Short name T1159
Test name
Test status
Simulation time 16587110 ps
CPU time 0.73 seconds
Started Jun 24 04:34:39 PM PDT 24
Finished Jun 24 04:34:40 PM PDT 24
Peak memory 195512 kb
Host smart-13f2405b-95f3-44f0-91a1-dfbadc2e7f99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294644275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.1294644275
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.2018252233
Short name T1235
Test name
Test status
Simulation time 33437088 ps
CPU time 1.61 seconds
Started Jun 24 04:34:26 PM PDT 24
Finished Jun 24 04:34:29 PM PDT 24
Peak memory 199836 kb
Host smart-c638491b-37b8-4425-a293-b01e701f9f59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018252233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.2018252233
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.30540565
Short name T1166
Test name
Test status
Simulation time 735131001 ps
CPU time 0.96 seconds
Started Jun 24 04:34:33 PM PDT 24
Finished Jun 24 04:34:35 PM PDT 24
Peak memory 198840 kb
Host smart-a5238b47-fd38-4e88-be1b-11b820a3e0e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30540565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.30540565
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1680161319
Short name T1199
Test name
Test status
Simulation time 41304176 ps
CPU time 0.71 seconds
Started Jun 24 04:34:28 PM PDT 24
Finished Jun 24 04:34:30 PM PDT 24
Peak memory 198336 kb
Host smart-46647ed9-a386-4ec5-9968-4eba2dc5a61d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680161319 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.1680161319
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.1574141553
Short name T59
Test name
Test status
Simulation time 14077334 ps
CPU time 0.59 seconds
Started Jun 24 04:34:31 PM PDT 24
Finished Jun 24 04:34:32 PM PDT 24
Peak memory 195196 kb
Host smart-1f1a1553-8366-41c1-b340-aa02136dc169
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574141553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.1574141553
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.3026507326
Short name T1202
Test name
Test status
Simulation time 14173085 ps
CPU time 0.56 seconds
Started Jun 24 04:34:20 PM PDT 24
Finished Jun 24 04:34:23 PM PDT 24
Peak memory 194220 kb
Host smart-c76239ec-e391-44f9-95f1-7522dca341cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026507326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.3026507326
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1926545264
Short name T73
Test name
Test status
Simulation time 30454056 ps
CPU time 0.75 seconds
Started Jun 24 04:34:23 PM PDT 24
Finished Jun 24 04:34:26 PM PDT 24
Peak memory 197568 kb
Host smart-73f98201-4428-417b-bd97-0dd3bd827b2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926545264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.1926545264
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.1970895804
Short name T1227
Test name
Test status
Simulation time 1460823425 ps
CPU time 2.18 seconds
Started Jun 24 04:34:28 PM PDT 24
Finished Jun 24 04:34:31 PM PDT 24
Peak memory 199804 kb
Host smart-52c01ba0-301f-4e4f-98e9-b3d89447e923
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970895804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.1970895804
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.2760375501
Short name T83
Test name
Test status
Simulation time 67027320 ps
CPU time 0.98 seconds
Started Jun 24 04:34:25 PM PDT 24
Finished Jun 24 04:34:26 PM PDT 24
Peak memory 198996 kb
Host smart-388bfd28-28c4-4eb8-9725-c74822e8351f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760375501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.2760375501
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.2699803478
Short name T968
Test name
Test status
Simulation time 12901040 ps
CPU time 0.57 seconds
Started Jun 24 04:35:00 PM PDT 24
Finished Jun 24 04:35:03 PM PDT 24
Peak memory 194832 kb
Host smart-176e51f5-12f3-41cd-889e-ab32875cc7b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699803478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2699803478
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.2387899290
Short name T263
Test name
Test status
Simulation time 50514008137 ps
CPU time 22.9 seconds
Started Jun 24 04:35:04 PM PDT 24
Finished Jun 24 04:35:28 PM PDT 24
Peak memory 200464 kb
Host smart-22ebdb55-8d98-4460-8e07-426dd550fddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387899290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.2387899290
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.1268382462
Short name T715
Test name
Test status
Simulation time 61671649552 ps
CPU time 50.23 seconds
Started Jun 24 04:35:00 PM PDT 24
Finished Jun 24 04:35:52 PM PDT 24
Peak memory 200408 kb
Host smart-04a60644-6bce-4f9a-b67e-46c24262b67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268382462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.1268382462
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.997788823
Short name T202
Test name
Test status
Simulation time 37787030010 ps
CPU time 81.93 seconds
Started Jun 24 04:34:57 PM PDT 24
Finished Jun 24 04:36:21 PM PDT 24
Peak memory 200460 kb
Host smart-aebde990-2f87-42b4-a5e7-528c46d066f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997788823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.997788823
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.1448250746
Short name T466
Test name
Test status
Simulation time 53155734238 ps
CPU time 53.53 seconds
Started Jun 24 04:35:13 PM PDT 24
Finished Jun 24 04:36:08 PM PDT 24
Peak memory 200416 kb
Host smart-706684b0-22ee-4821-b90f-7e179687e560
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448250746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.1448250746
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.2901800634
Short name T399
Test name
Test status
Simulation time 138022741321 ps
CPU time 297.88 seconds
Started Jun 24 04:34:57 PM PDT 24
Finished Jun 24 04:39:57 PM PDT 24
Peak memory 200440 kb
Host smart-bfaf920b-c75b-42da-aed6-00cb25ccef0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2901800634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.2901800634
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.3433162910
Short name T457
Test name
Test status
Simulation time 52901187 ps
CPU time 0.75 seconds
Started Jun 24 04:34:57 PM PDT 24
Finished Jun 24 04:35:00 PM PDT 24
Peak memory 196344 kb
Host smart-a6303843-df16-4417-b05e-4f3bef54e75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433162910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.3433162910
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.3374134391
Short name T475
Test name
Test status
Simulation time 11570822061 ps
CPU time 21.88 seconds
Started Jun 24 04:35:20 PM PDT 24
Finished Jun 24 04:35:43 PM PDT 24
Peak memory 200576 kb
Host smart-58a47a9c-691c-4607-b703-e31e216969aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374134391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.3374134391
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.1521556058
Short name T967
Test name
Test status
Simulation time 36972133387 ps
CPU time 150.53 seconds
Started Jun 24 04:34:59 PM PDT 24
Finished Jun 24 04:37:32 PM PDT 24
Peak memory 200472 kb
Host smart-0a421387-50a9-4c3f-a98d-9f796a6880fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1521556058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.1521556058
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.1143613501
Short name T13
Test name
Test status
Simulation time 3792360132 ps
CPU time 7.65 seconds
Started Jun 24 04:34:54 PM PDT 24
Finished Jun 24 04:35:03 PM PDT 24
Peak memory 199496 kb
Host smart-2123a213-a824-42f8-b688-f7f92d7b60df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1143613501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.1143613501
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.942227355
Short name T962
Test name
Test status
Simulation time 53391967571 ps
CPU time 81.41 seconds
Started Jun 24 04:34:59 PM PDT 24
Finished Jun 24 04:36:22 PM PDT 24
Peak memory 200464 kb
Host smart-2b3104ce-b60a-48d0-8493-9b018ced4e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942227355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.942227355
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.3904048039
Short name T538
Test name
Test status
Simulation time 71499105716 ps
CPU time 100.83 seconds
Started Jun 24 04:34:55 PM PDT 24
Finished Jun 24 04:36:38 PM PDT 24
Peak memory 196664 kb
Host smart-ab1e7870-f9c5-4930-a92e-a6ce2e730288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904048039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.3904048039
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.559682353
Short name T410
Test name
Test status
Simulation time 529990111 ps
CPU time 1.44 seconds
Started Jun 24 04:34:54 PM PDT 24
Finished Jun 24 04:34:58 PM PDT 24
Peak memory 200144 kb
Host smart-7268598b-1d15-4c0d-8794-17e5bed18feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559682353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.559682353
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.1839312842
Short name T172
Test name
Test status
Simulation time 232829304083 ps
CPU time 244.94 seconds
Started Jun 24 04:35:00 PM PDT 24
Finished Jun 24 04:39:07 PM PDT 24
Peak memory 200444 kb
Host smart-75ccec3e-c7f8-4df2-b8c7-9154fbd37cea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839312842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.1839312842
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.604761992
Short name T533
Test name
Test status
Simulation time 25374970323 ps
CPU time 274.38 seconds
Started Jun 24 04:34:59 PM PDT 24
Finished Jun 24 04:39:35 PM PDT 24
Peak memory 208776 kb
Host smart-115fe794-4f1e-43c7-a0a6-2dbeb50cb8b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604761992 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.604761992
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.2316718874
Short name T346
Test name
Test status
Simulation time 667268433 ps
CPU time 2.4 seconds
Started Jun 24 04:34:55 PM PDT 24
Finished Jun 24 04:35:00 PM PDT 24
Peak memory 199032 kb
Host smart-fe9cff3e-0544-4c39-b015-840caa9aa7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316718874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.2316718874
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.2441355733
Short name T756
Test name
Test status
Simulation time 71022730709 ps
CPU time 33.62 seconds
Started Jun 24 04:35:14 PM PDT 24
Finished Jun 24 04:35:49 PM PDT 24
Peak memory 200564 kb
Host smart-d89ab9ad-6434-4774-a51c-df9bd0e6fcb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441355733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.2441355733
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.2558069463
Short name T483
Test name
Test status
Simulation time 11303088 ps
CPU time 0.57 seconds
Started Jun 24 04:34:59 PM PDT 24
Finished Jun 24 04:35:02 PM PDT 24
Peak memory 195792 kb
Host smart-f4dce185-31c1-402f-ba5a-e74c77c5fa3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558069463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.2558069463
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.1929352050
Short name T438
Test name
Test status
Simulation time 37695731871 ps
CPU time 18.35 seconds
Started Jun 24 04:34:57 PM PDT 24
Finished Jun 24 04:35:17 PM PDT 24
Peak memory 200628 kb
Host smart-5b420319-505a-49ce-9f0d-5b150c9f5b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929352050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.1929352050
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.176247728
Short name T820
Test name
Test status
Simulation time 29572569788 ps
CPU time 56.41 seconds
Started Jun 24 04:34:59 PM PDT 24
Finished Jun 24 04:35:57 PM PDT 24
Peak memory 200464 kb
Host smart-15de497a-6c65-442e-86a7-25d643df08ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176247728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.176247728
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_intr.3793471396
Short name T516
Test name
Test status
Simulation time 184937482988 ps
CPU time 69.66 seconds
Started Jun 24 04:34:54 PM PDT 24
Finished Jun 24 04:36:06 PM PDT 24
Peak memory 196944 kb
Host smart-b30f015d-6e08-4343-a687-1f5b115222c1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793471396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.3793471396
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.3928676481
Short name T401
Test name
Test status
Simulation time 115602302050 ps
CPU time 570.4 seconds
Started Jun 24 04:35:16 PM PDT 24
Finished Jun 24 04:44:49 PM PDT 24
Peak memory 200468 kb
Host smart-8a9b7934-02af-40c8-a4c9-16827366b4b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3928676481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.3928676481
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.1342956607
Short name T1024
Test name
Test status
Simulation time 5956859064 ps
CPU time 2.58 seconds
Started Jun 24 04:35:18 PM PDT 24
Finished Jun 24 04:35:22 PM PDT 24
Peak memory 200108 kb
Host smart-9d20f371-f925-460e-b0f0-04dcf0a098da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342956607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.1342956607
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_perf.1732884905
Short name T42
Test name
Test status
Simulation time 12799564572 ps
CPU time 188.24 seconds
Started Jun 24 04:34:58 PM PDT 24
Finished Jun 24 04:38:08 PM PDT 24
Peak memory 200444 kb
Host smart-0191c46a-bd0f-4e55-9f81-9d89e0a2fa08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1732884905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.1732884905
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.179171623
Short name T21
Test name
Test status
Simulation time 4782576785 ps
CPU time 3.22 seconds
Started Jun 24 04:35:00 PM PDT 24
Finished Jun 24 04:35:05 PM PDT 24
Peak memory 199796 kb
Host smart-6cf65c0c-4fc8-4a67-8e05-cfb836cfd3cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=179171623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.179171623
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.107202091
Short name T524
Test name
Test status
Simulation time 33954776400 ps
CPU time 48.63 seconds
Started Jun 24 04:35:10 PM PDT 24
Finished Jun 24 04:36:00 PM PDT 24
Peak memory 200484 kb
Host smart-150cff42-7fcf-4b23-91cd-c4020d407adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107202091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.107202091
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.2379457903
Short name T898
Test name
Test status
Simulation time 5760570518 ps
CPU time 2.85 seconds
Started Jun 24 04:35:25 PM PDT 24
Finished Jun 24 04:35:29 PM PDT 24
Peak memory 196656 kb
Host smart-0937b4a1-307f-4ac5-94af-1fb4747cf22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379457903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.2379457903
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.4184984028
Short name T26
Test name
Test status
Simulation time 113934310 ps
CPU time 0.77 seconds
Started Jun 24 04:35:12 PM PDT 24
Finished Jun 24 04:35:14 PM PDT 24
Peak memory 218920 kb
Host smart-3658298f-2729-4355-8381-c18d7316184c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184984028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.4184984028
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.1042304115
Short name T1082
Test name
Test status
Simulation time 6068707641 ps
CPU time 12.89 seconds
Started Jun 24 04:34:57 PM PDT 24
Finished Jun 24 04:35:12 PM PDT 24
Peak memory 200596 kb
Host smart-7998eab7-993b-4c13-8817-9a7844e31b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042304115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.1042304115
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.1245341464
Short name T530
Test name
Test status
Simulation time 8952269730 ps
CPU time 10.84 seconds
Started Jun 24 04:35:09 PM PDT 24
Finished Jun 24 04:35:21 PM PDT 24
Peak memory 200200 kb
Host smart-5a299a50-fb66-4a3c-9408-2d00ba009b36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245341464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.1245341464
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.3827499880
Short name T838
Test name
Test status
Simulation time 24776476951 ps
CPU time 286.68 seconds
Started Jun 24 04:34:55 PM PDT 24
Finished Jun 24 04:39:44 PM PDT 24
Peak memory 216948 kb
Host smart-ee7082af-21a4-4855-9f89-71e16ad10c55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827499880 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.3827499880
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.3050624326
Short name T985
Test name
Test status
Simulation time 8429266598 ps
CPU time 5.75 seconds
Started Jun 24 04:35:16 PM PDT 24
Finished Jun 24 04:35:24 PM PDT 24
Peak memory 200428 kb
Host smart-038d0df0-bd1b-4731-aefc-409f8f47383a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050624326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.3050624326
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.1525447192
Short name T507
Test name
Test status
Simulation time 46668108017 ps
CPU time 41.75 seconds
Started Jun 24 04:35:06 PM PDT 24
Finished Jun 24 04:35:54 PM PDT 24
Peak memory 200468 kb
Host smart-61e6a9cb-92e1-46f7-be1e-0f52b1bff10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525447192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.1525447192
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.826171311
Short name T598
Test name
Test status
Simulation time 33167733 ps
CPU time 0.53 seconds
Started Jun 24 04:35:30 PM PDT 24
Finished Jun 24 04:35:32 PM PDT 24
Peak memory 195412 kb
Host smart-aa4486a3-eb74-45fe-8a86-4eaa1a12774c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826171311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.826171311
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.28182667
Short name T887
Test name
Test status
Simulation time 98117795824 ps
CPU time 26.72 seconds
Started Jun 24 04:35:39 PM PDT 24
Finished Jun 24 04:36:07 PM PDT 24
Peak memory 200492 kb
Host smart-302d0238-8dab-4c72-aa92-0bb3fdd21bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28182667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.28182667
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.3094835835
Short name T525
Test name
Test status
Simulation time 28304141006 ps
CPU time 44.89 seconds
Started Jun 24 04:35:37 PM PDT 24
Finished Jun 24 04:36:23 PM PDT 24
Peak memory 200528 kb
Host smart-6e3f6531-c6b9-4cb3-ba4e-0b9bc9253e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094835835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.3094835835
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.520282694
Short name T167
Test name
Test status
Simulation time 41899936416 ps
CPU time 21.68 seconds
Started Jun 24 04:35:21 PM PDT 24
Finished Jun 24 04:35:44 PM PDT 24
Peak memory 200548 kb
Host smart-0620db31-da1d-49a0-84b5-afad1c2ba5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520282694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.520282694
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.3502543184
Short name T426
Test name
Test status
Simulation time 620568651986 ps
CPU time 233.54 seconds
Started Jun 24 04:35:14 PM PDT 24
Finished Jun 24 04:39:10 PM PDT 24
Peak memory 199100 kb
Host smart-af1f1cac-6102-4d9a-829a-7546fa9fd423
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502543184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.3502543184
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.4167773019
Short name T373
Test name
Test status
Simulation time 104616002280 ps
CPU time 305.9 seconds
Started Jun 24 04:35:24 PM PDT 24
Finished Jun 24 04:40:31 PM PDT 24
Peak memory 200512 kb
Host smart-29aa4a29-3a1d-432f-8431-42fafe1c98af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4167773019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.4167773019
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.278450482
Short name T389
Test name
Test status
Simulation time 505578697 ps
CPU time 0.89 seconds
Started Jun 24 04:35:18 PM PDT 24
Finished Jun 24 04:35:21 PM PDT 24
Peak memory 197700 kb
Host smart-077fa2b9-c317-41ce-be2e-fdf0caa863b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278450482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.278450482
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_perf.2893579924
Short name T613
Test name
Test status
Simulation time 14036581330 ps
CPU time 192.78 seconds
Started Jun 24 04:35:34 PM PDT 24
Finished Jun 24 04:38:48 PM PDT 24
Peak memory 200472 kb
Host smart-93642e42-c585-483d-a6a5-e1f4963e8add
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2893579924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.2893579924
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.3629245725
Short name T1101
Test name
Test status
Simulation time 2835954357 ps
CPU time 18.81 seconds
Started Jun 24 04:35:13 PM PDT 24
Finished Jun 24 04:35:34 PM PDT 24
Peak memory 199680 kb
Host smart-b52723da-c01b-4e50-bc42-63dfa45d171a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3629245725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.3629245725
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.462376360
Short name T939
Test name
Test status
Simulation time 76133193805 ps
CPU time 118.77 seconds
Started Jun 24 04:35:34 PM PDT 24
Finished Jun 24 04:37:34 PM PDT 24
Peak memory 200532 kb
Host smart-cdb6613d-2f30-4522-9c00-e8df3f4f0e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462376360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.462376360
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.3257129815
Short name T10
Test name
Test status
Simulation time 69605515064 ps
CPU time 22.22 seconds
Started Jun 24 04:35:29 PM PDT 24
Finished Jun 24 04:35:52 PM PDT 24
Peak memory 196492 kb
Host smart-88d0ced3-35aa-430c-9384-f1f574e026db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257129815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.3257129815
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.3395929008
Short name T3
Test name
Test status
Simulation time 5740670322 ps
CPU time 17.79 seconds
Started Jun 24 04:35:24 PM PDT 24
Finished Jun 24 04:35:43 PM PDT 24
Peak memory 200500 kb
Host smart-98fd42aa-d8dc-487b-8520-afd3e7ad6bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395929008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.3395929008
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.3661343792
Short name T907
Test name
Test status
Simulation time 173785932022 ps
CPU time 292.8 seconds
Started Jun 24 04:35:25 PM PDT 24
Finished Jun 24 04:40:19 PM PDT 24
Peak memory 200500 kb
Host smart-13f7b69c-040f-4bc8-b430-c12242b20bf1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661343792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.3661343792
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.1389493732
Short name T532
Test name
Test status
Simulation time 121544305793 ps
CPU time 453.41 seconds
Started Jun 24 04:35:19 PM PDT 24
Finished Jun 24 04:42:54 PM PDT 24
Peak memory 216976 kb
Host smart-e7a997b3-0700-4fdd-8b9e-80eb681a54b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389493732 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.1389493732
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.4226691871
Short name T484
Test name
Test status
Simulation time 809667875 ps
CPU time 6.18 seconds
Started Jun 24 04:35:25 PM PDT 24
Finished Jun 24 04:35:32 PM PDT 24
Peak memory 200264 kb
Host smart-d4f5ff6e-ff11-45ea-a61a-3506dc422985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226691871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.4226691871
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.1637762081
Short name T463
Test name
Test status
Simulation time 36902979670 ps
CPU time 77.92 seconds
Started Jun 24 04:35:19 PM PDT 24
Finished Jun 24 04:36:38 PM PDT 24
Peak memory 200528 kb
Host smart-30820e7f-0307-4931-8b35-fa05618970e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637762081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.1637762081
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.314992159
Short name T250
Test name
Test status
Simulation time 20905783910 ps
CPU time 26.24 seconds
Started Jun 24 04:37:57 PM PDT 24
Finished Jun 24 04:39:28 PM PDT 24
Peak memory 200388 kb
Host smart-cb8c126c-3c7b-415b-a11a-a5e1ae63b122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314992159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.314992159
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.1518797604
Short name T135
Test name
Test status
Simulation time 85019166999 ps
CPU time 134.71 seconds
Started Jun 24 04:37:57 PM PDT 24
Finished Jun 24 04:41:16 PM PDT 24
Peak memory 200420 kb
Host smart-4d32747a-78b5-49bf-a301-d1c4f9be3f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518797604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.1518797604
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.2225992498
Short name T571
Test name
Test status
Simulation time 63112712735 ps
CPU time 34.04 seconds
Started Jun 24 04:37:54 PM PDT 24
Finished Jun 24 04:39:31 PM PDT 24
Peak memory 200620 kb
Host smart-1027fabd-dfcd-456e-a00b-fbf5b9419a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225992498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.2225992498
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.736735253
Short name T485
Test name
Test status
Simulation time 48348545704 ps
CPU time 21.64 seconds
Started Jun 24 04:37:52 PM PDT 24
Finished Jun 24 04:39:18 PM PDT 24
Peak memory 200484 kb
Host smart-13a08417-2a1e-4688-87fd-ea6c3bdd2591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736735253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.736735253
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.669351584
Short name T561
Test name
Test status
Simulation time 112377456420 ps
CPU time 50.56 seconds
Started Jun 24 04:37:55 PM PDT 24
Finished Jun 24 04:39:47 PM PDT 24
Peak memory 200528 kb
Host smart-1a18ac88-01f4-4d68-8a7f-9c96c4814dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669351584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.669351584
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.222113685
Short name T1068
Test name
Test status
Simulation time 69374452898 ps
CPU time 99.13 seconds
Started Jun 24 04:37:56 PM PDT 24
Finished Jun 24 04:40:40 PM PDT 24
Peak memory 200524 kb
Host smart-0915bfde-cb30-489c-b631-21a78fb85c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222113685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.222113685
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.2539083323
Short name T134
Test name
Test status
Simulation time 37742907297 ps
CPU time 27.32 seconds
Started Jun 24 04:37:52 PM PDT 24
Finished Jun 24 04:39:24 PM PDT 24
Peak memory 200408 kb
Host smart-7c7d4f6e-4f27-43a1-aa5f-22f761424c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539083323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.2539083323
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.177628020
Short name T578
Test name
Test status
Simulation time 122647183037 ps
CPU time 53.17 seconds
Started Jun 24 04:37:53 PM PDT 24
Finished Jun 24 04:39:50 PM PDT 24
Peak memory 200452 kb
Host smart-33131ef0-5f23-49f8-a14b-5529ddc15cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177628020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.177628020
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_fifo_full.2904119991
Short name T1067
Test name
Test status
Simulation time 36443842728 ps
CPU time 14.62 seconds
Started Jun 24 04:35:24 PM PDT 24
Finished Jun 24 04:35:39 PM PDT 24
Peak memory 200536 kb
Host smart-99e3e378-0e2a-43fa-8ae9-c19ee31fbbe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904119991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.2904119991
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.340377010
Short name T972
Test name
Test status
Simulation time 140224905928 ps
CPU time 56.61 seconds
Started Jun 24 04:35:29 PM PDT 24
Finished Jun 24 04:36:26 PM PDT 24
Peak memory 200312 kb
Host smart-918404f9-7ebd-4edf-ab95-03ed980facb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340377010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.340377010
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.2738335785
Short name T152
Test name
Test status
Simulation time 54470835178 ps
CPU time 83.74 seconds
Started Jun 24 04:35:20 PM PDT 24
Finished Jun 24 04:36:45 PM PDT 24
Peak memory 200532 kb
Host smart-ec9d7ce7-40ed-4e27-8657-b1911c6c1191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738335785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.2738335785
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.3708635147
Short name T19
Test name
Test status
Simulation time 49559354086 ps
CPU time 40.05 seconds
Started Jun 24 04:35:31 PM PDT 24
Finished Jun 24 04:36:11 PM PDT 24
Peak memory 200412 kb
Host smart-bbd5ed04-450f-469e-8bfc-e919fcc8965c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708635147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.3708635147
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.1237746074
Short name T503
Test name
Test status
Simulation time 135771739994 ps
CPU time 656.16 seconds
Started Jun 24 04:35:19 PM PDT 24
Finished Jun 24 04:46:17 PM PDT 24
Peak memory 200876 kb
Host smart-6e842225-4e35-4258-bb30-73c42a6751dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1237746074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.1237746074
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_perf.951877987
Short name T819
Test name
Test status
Simulation time 4835418407 ps
CPU time 107.53 seconds
Started Jun 24 04:35:22 PM PDT 24
Finished Jun 24 04:37:10 PM PDT 24
Peak memory 200464 kb
Host smart-00d2be15-571d-4c87-8947-e590ece8974a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=951877987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.951877987
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.3643441570
Short name T864
Test name
Test status
Simulation time 2716651355 ps
CPU time 4.08 seconds
Started Jun 24 04:35:24 PM PDT 24
Finished Jun 24 04:35:28 PM PDT 24
Peak memory 199704 kb
Host smart-249625f0-8e91-4339-8ae7-575e39572879
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3643441570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.3643441570
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.2722035623
Short name T541
Test name
Test status
Simulation time 235907462304 ps
CPU time 119.13 seconds
Started Jun 24 04:35:26 PM PDT 24
Finished Jun 24 04:37:26 PM PDT 24
Peak memory 200508 kb
Host smart-5d12b72a-d04e-4886-9d13-4aabd4e53b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722035623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.2722035623
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.1554020058
Short name T259
Test name
Test status
Simulation time 3199654930 ps
CPU time 1.07 seconds
Started Jun 24 04:35:20 PM PDT 24
Finished Jun 24 04:35:23 PM PDT 24
Peak memory 196396 kb
Host smart-1820233f-8e2f-4193-bdf6-af1985f4a3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554020058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.1554020058
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.4016997394
Short name T290
Test name
Test status
Simulation time 5315982648 ps
CPU time 19.78 seconds
Started Jun 24 04:35:37 PM PDT 24
Finished Jun 24 04:35:58 PM PDT 24
Peak memory 200268 kb
Host smart-cd267b6a-209f-4e11-b8f6-98a7f3c6c75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016997394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.4016997394
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.3845455745
Short name T97
Test name
Test status
Simulation time 160011383907 ps
CPU time 884.4 seconds
Started Jun 24 04:35:34 PM PDT 24
Finished Jun 24 04:50:20 PM PDT 24
Peak memory 200488 kb
Host smart-d727b432-3285-4d8d-83f3-4d3778edca33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845455745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.3845455745
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.291168809
Short name T791
Test name
Test status
Simulation time 87222952182 ps
CPU time 1020.76 seconds
Started Jun 24 04:35:23 PM PDT 24
Finished Jun 24 04:52:25 PM PDT 24
Peak memory 216888 kb
Host smart-97705833-2b8b-4324-a267-fdc595e3a3f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291168809 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.291168809
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.63413972
Short name T994
Test name
Test status
Simulation time 12847135875 ps
CPU time 21.03 seconds
Started Jun 24 04:35:32 PM PDT 24
Finished Jun 24 04:35:54 PM PDT 24
Peak memory 200488 kb
Host smart-6a40d130-ad47-4b08-8e41-36e078a9f28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63413972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.63413972
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.2456851420
Short name T681
Test name
Test status
Simulation time 15991578735 ps
CPU time 28.52 seconds
Started Jun 24 04:35:23 PM PDT 24
Finished Jun 24 04:35:52 PM PDT 24
Peak memory 200552 kb
Host smart-22fb542c-11e1-4b12-9a66-9527dbb15280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456851420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.2456851420
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.4055666768
Short name T867
Test name
Test status
Simulation time 60136227905 ps
CPU time 89.3 seconds
Started Jun 24 04:37:58 PM PDT 24
Finished Jun 24 04:40:31 PM PDT 24
Peak memory 200512 kb
Host smart-a65f9fb6-9533-42fd-8f5e-a037a763d37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055666768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.4055666768
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.615512208
Short name T430
Test name
Test status
Simulation time 28572357778 ps
CPU time 40.87 seconds
Started Jun 24 04:37:53 PM PDT 24
Finished Jun 24 04:39:38 PM PDT 24
Peak memory 200488 kb
Host smart-16b93077-408c-4c76-9030-29581fc9dae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615512208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.615512208
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.3719727425
Short name T724
Test name
Test status
Simulation time 49154842410 ps
CPU time 46.71 seconds
Started Jun 24 04:37:55 PM PDT 24
Finished Jun 24 04:39:43 PM PDT 24
Peak memory 200580 kb
Host smart-94adf7f7-b86a-418c-b590-d74343ae1633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719727425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.3719727425
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.1017738448
Short name T623
Test name
Test status
Simulation time 114848221597 ps
CPU time 194.44 seconds
Started Jun 24 04:37:58 PM PDT 24
Finished Jun 24 04:42:16 PM PDT 24
Peak memory 200512 kb
Host smart-12dd2049-faa2-469c-8532-b509d8ce72b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017738448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.1017738448
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.3362795489
Short name T261
Test name
Test status
Simulation time 52701163275 ps
CPU time 76.27 seconds
Started Jun 24 04:37:54 PM PDT 24
Finished Jun 24 04:40:13 PM PDT 24
Peak memory 200580 kb
Host smart-ca6a00aa-86ea-456e-b8be-415d647cdbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362795489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.3362795489
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.1903918988
Short name T631
Test name
Test status
Simulation time 41122351957 ps
CPU time 35.04 seconds
Started Jun 24 04:37:54 PM PDT 24
Finished Jun 24 04:39:32 PM PDT 24
Peak memory 200544 kb
Host smart-d651ce6b-4857-48c1-8220-c6ae83d1c95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903918988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.1903918988
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.3113064139
Short name T297
Test name
Test status
Simulation time 40023572143 ps
CPU time 33.4 seconds
Started Jun 24 04:37:55 PM PDT 24
Finished Jun 24 04:39:30 PM PDT 24
Peak memory 200520 kb
Host smart-8a72e3b0-3859-4358-aa99-fe54bd297467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113064139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.3113064139
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.331217271
Short name T258
Test name
Test status
Simulation time 24715437131 ps
CPU time 34.9 seconds
Started Jun 24 04:37:53 PM PDT 24
Finished Jun 24 04:39:31 PM PDT 24
Peak memory 200488 kb
Host smart-17d10619-09c8-48b3-a5d7-f76151c83127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331217271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.331217271
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.442425327
Short name T456
Test name
Test status
Simulation time 11156563 ps
CPU time 0.54 seconds
Started Jun 24 04:35:32 PM PDT 24
Finished Jun 24 04:35:33 PM PDT 24
Peak memory 194884 kb
Host smart-f28905e1-5040-4dc0-8743-2a8fc59cbf5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442425327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.442425327
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.2520993307
Short name T1070
Test name
Test status
Simulation time 125441635841 ps
CPU time 181.24 seconds
Started Jun 24 04:35:40 PM PDT 24
Finished Jun 24 04:38:42 PM PDT 24
Peak memory 200560 kb
Host smart-ba83c848-bab9-43ad-a0b4-bd376c6e5ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520993307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.2520993307
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.2475155239
Short name T276
Test name
Test status
Simulation time 63009720297 ps
CPU time 113.6 seconds
Started Jun 24 04:35:28 PM PDT 24
Finished Jun 24 04:37:23 PM PDT 24
Peak memory 200452 kb
Host smart-edd1cbe3-50e3-485b-80b5-94793dc92267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475155239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.2475155239
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.1984131009
Short name T782
Test name
Test status
Simulation time 5817353330 ps
CPU time 7.07 seconds
Started Jun 24 04:35:37 PM PDT 24
Finished Jun 24 04:35:45 PM PDT 24
Peak memory 200444 kb
Host smart-d275c627-f0a9-4a91-a71d-2f278fc1a5f9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984131009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.1984131009
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.1505828688
Short name T768
Test name
Test status
Simulation time 169493155547 ps
CPU time 226.35 seconds
Started Jun 24 04:35:31 PM PDT 24
Finished Jun 24 04:39:19 PM PDT 24
Peak memory 200512 kb
Host smart-db409e12-0fc9-4c5f-992a-d3d057ad0130
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1505828688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.1505828688
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.2557945229
Short name T400
Test name
Test status
Simulation time 5370851745 ps
CPU time 3.56 seconds
Started Jun 24 04:35:38 PM PDT 24
Finished Jun 24 04:35:42 PM PDT 24
Peak memory 200488 kb
Host smart-584916df-ea82-46c6-996c-ef21c784e80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557945229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.2557945229
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_perf.911681900
Short name T861
Test name
Test status
Simulation time 10246986854 ps
CPU time 446.04 seconds
Started Jun 24 04:35:36 PM PDT 24
Finished Jun 24 04:43:02 PM PDT 24
Peak memory 200472 kb
Host smart-92e4476c-f8ee-4de7-b74a-60bc48bdf3e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=911681900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.911681900
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.3590511202
Short name T902
Test name
Test status
Simulation time 2833150254 ps
CPU time 5.42 seconds
Started Jun 24 04:35:19 PM PDT 24
Finished Jun 24 04:35:26 PM PDT 24
Peak memory 198668 kb
Host smart-2f6d0f16-bd96-4f01-baeb-c2f527d56e96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3590511202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.3590511202
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.3119698317
Short name T554
Test name
Test status
Simulation time 140121256824 ps
CPU time 222.63 seconds
Started Jun 24 04:35:34 PM PDT 24
Finished Jun 24 04:39:18 PM PDT 24
Peak memory 200520 kb
Host smart-4524dc30-3b80-493d-a7d0-550ede6214ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119698317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.3119698317
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.1691272906
Short name T877
Test name
Test status
Simulation time 4297449229 ps
CPU time 2.81 seconds
Started Jun 24 04:35:19 PM PDT 24
Finished Jun 24 04:35:23 PM PDT 24
Peak memory 196660 kb
Host smart-3fd2c59f-44bc-47bb-8f88-ccee22e75cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691272906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.1691272906
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.1037296363
Short name T744
Test name
Test status
Simulation time 256315561 ps
CPU time 1.19 seconds
Started Jun 24 04:35:22 PM PDT 24
Finished Jun 24 04:35:24 PM PDT 24
Peak memory 198876 kb
Host smart-617bae96-a947-4a0e-9e05-ef0505d61679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037296363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.1037296363
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.968834328
Short name T674
Test name
Test status
Simulation time 215163735412 ps
CPU time 103.04 seconds
Started Jun 24 04:35:38 PM PDT 24
Finished Jun 24 04:37:22 PM PDT 24
Peak memory 200504 kb
Host smart-33a04c8a-27fa-4e6c-9c4f-59666d5e59cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968834328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.968834328
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.3057495396
Short name T35
Test name
Test status
Simulation time 19788607839 ps
CPU time 644.4 seconds
Started Jun 24 04:35:26 PM PDT 24
Finished Jun 24 04:46:11 PM PDT 24
Peak memory 216236 kb
Host smart-8641f53a-8345-49a6-a78f-ee41d902279e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057495396 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.3057495396
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.186318015
Short name T41
Test name
Test status
Simulation time 1842575338 ps
CPU time 1.5 seconds
Started Jun 24 04:35:34 PM PDT 24
Finished Jun 24 04:35:36 PM PDT 24
Peak memory 197960 kb
Host smart-31496728-29ba-4554-8bd5-59f0dee5d723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186318015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.186318015
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.1191502014
Short name T439
Test name
Test status
Simulation time 42383589782 ps
CPU time 13.9 seconds
Started Jun 24 04:35:40 PM PDT 24
Finished Jun 24 04:35:55 PM PDT 24
Peak memory 197808 kb
Host smart-45a78f46-202f-4d39-9586-db20e13801d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191502014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.1191502014
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.1317209056
Short name T679
Test name
Test status
Simulation time 43850358750 ps
CPU time 78.61 seconds
Started Jun 24 04:38:00 PM PDT 24
Finished Jun 24 04:40:24 PM PDT 24
Peak memory 200576 kb
Host smart-bebdca4b-9490-4cda-8de6-e5f0349e61f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317209056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.1317209056
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.2712804432
Short name T149
Test name
Test status
Simulation time 115911847812 ps
CPU time 94.38 seconds
Started Jun 24 04:38:02 PM PDT 24
Finished Jun 24 04:40:42 PM PDT 24
Peak memory 200844 kb
Host smart-0207160b-3644-4536-ad2d-efbe133e3f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712804432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.2712804432
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.2176908924
Short name T214
Test name
Test status
Simulation time 21440546795 ps
CPU time 42.06 seconds
Started Jun 24 04:38:01 PM PDT 24
Finished Jun 24 04:39:49 PM PDT 24
Peak memory 200464 kb
Host smart-031621e9-8ed0-4a6c-b0d4-7a61e108778d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176908924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.2176908924
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.3703624933
Short name T225
Test name
Test status
Simulation time 60580369735 ps
CPU time 100.76 seconds
Started Jun 24 04:38:02 PM PDT 24
Finished Jun 24 04:40:48 PM PDT 24
Peak memory 200356 kb
Host smart-6992a8b4-981e-46bd-90c6-4e84339b778e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703624933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.3703624933
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.1591509595
Short name T388
Test name
Test status
Simulation time 43493957810 ps
CPU time 17.24 seconds
Started Jun 24 04:38:02 PM PDT 24
Finished Jun 24 04:39:25 PM PDT 24
Peak memory 200464 kb
Host smart-59c1b53a-3247-45ee-a405-750b3be85244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591509595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.1591509595
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.1531350023
Short name T409
Test name
Test status
Simulation time 57283086069 ps
CPU time 21.88 seconds
Started Jun 24 04:38:02 PM PDT 24
Finished Jun 24 04:39:29 PM PDT 24
Peak memory 200512 kb
Host smart-638a31b7-a5bf-4cd2-be66-42c4ddb98a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531350023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.1531350023
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.3799927566
Short name T207
Test name
Test status
Simulation time 56706489434 ps
CPU time 44.69 seconds
Started Jun 24 04:37:59 PM PDT 24
Finished Jun 24 04:39:47 PM PDT 24
Peak memory 200620 kb
Host smart-79f3a711-58b9-4551-817e-030061464eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799927566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.3799927566
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.426071394
Short name T589
Test name
Test status
Simulation time 15140220 ps
CPU time 0.57 seconds
Started Jun 24 04:35:29 PM PDT 24
Finished Jun 24 04:35:30 PM PDT 24
Peak memory 196152 kb
Host smart-c249a238-f14e-4188-8f78-1b064a556402
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426071394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.426071394
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.2147903877
Short name T975
Test name
Test status
Simulation time 185094222092 ps
CPU time 221.04 seconds
Started Jun 24 04:35:32 PM PDT 24
Finished Jun 24 04:39:14 PM PDT 24
Peak memory 200524 kb
Host smart-7a792ca1-c69f-4586-8fa4-a373a46ed0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147903877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.2147903877
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.2163867968
Short name T948
Test name
Test status
Simulation time 13776450974 ps
CPU time 24.94 seconds
Started Jun 24 04:35:37 PM PDT 24
Finished Jun 24 04:36:03 PM PDT 24
Peak memory 200368 kb
Host smart-37138460-469b-4f7e-a9dd-f1b98db0b26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163867968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.2163867968
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.1924664430
Short name T614
Test name
Test status
Simulation time 79925499431 ps
CPU time 270.69 seconds
Started Jun 24 04:35:25 PM PDT 24
Finished Jun 24 04:39:56 PM PDT 24
Peak memory 200536 kb
Host smart-dddf8d68-6b0f-49b6-9f9d-1fc5759460da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924664430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.1924664430
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.522419783
Short name T502
Test name
Test status
Simulation time 54406006222 ps
CPU time 28.73 seconds
Started Jun 24 04:35:24 PM PDT 24
Finished Jun 24 04:35:53 PM PDT 24
Peak memory 200504 kb
Host smart-87089074-7411-4cbd-9cda-23da34323360
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522419783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.522419783
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.3932297722
Short name T712
Test name
Test status
Simulation time 195016958824 ps
CPU time 364.37 seconds
Started Jun 24 04:35:29 PM PDT 24
Finished Jun 24 04:41:34 PM PDT 24
Peak memory 200412 kb
Host smart-14e28cd2-22a6-4a77-a5c8-700d8f0e9e48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3932297722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.3932297722
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.354156283
Short name T1071
Test name
Test status
Simulation time 7884991681 ps
CPU time 8.95 seconds
Started Jun 24 04:35:37 PM PDT 24
Finished Jun 24 04:35:47 PM PDT 24
Peak memory 199220 kb
Host smart-2a6a3816-b231-4efe-9919-4499a0c3f13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354156283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.354156283
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.3018918731
Short name T377
Test name
Test status
Simulation time 32237500897 ps
CPU time 13.22 seconds
Started Jun 24 04:35:38 PM PDT 24
Finished Jun 24 04:35:52 PM PDT 24
Peak memory 200500 kb
Host smart-edfbcd81-6899-45ee-8c87-5dd4e6761d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018918731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.3018918731
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.236487916
Short name T1029
Test name
Test status
Simulation time 19373756995 ps
CPU time 1024.64 seconds
Started Jun 24 04:35:27 PM PDT 24
Finished Jun 24 04:52:32 PM PDT 24
Peak memory 200500 kb
Host smart-35034ae2-1d51-4061-bf5a-500121a349f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=236487916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.236487916
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.2168334404
Short name T446
Test name
Test status
Simulation time 7568859492 ps
CPU time 68.09 seconds
Started Jun 24 04:35:33 PM PDT 24
Finished Jun 24 04:36:42 PM PDT 24
Peak memory 198916 kb
Host smart-395f0342-9a9d-4bf0-a477-7a0eaaf4f8d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2168334404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.2168334404
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.3717778115
Short name T960
Test name
Test status
Simulation time 186790649615 ps
CPU time 140.97 seconds
Started Jun 24 04:35:36 PM PDT 24
Finished Jun 24 04:37:58 PM PDT 24
Peak memory 200452 kb
Host smart-62e70aef-51a7-40ea-852f-d6fc80c5915e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717778115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.3717778115
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.1223251465
Short name T522
Test name
Test status
Simulation time 6033324599 ps
CPU time 3.04 seconds
Started Jun 24 04:35:37 PM PDT 24
Finished Jun 24 04:35:41 PM PDT 24
Peak memory 196412 kb
Host smart-9a9de94d-6380-44b0-96ac-1d774422595f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223251465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.1223251465
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.1632767665
Short name T391
Test name
Test status
Simulation time 6327019725 ps
CPU time 9.73 seconds
Started Jun 24 04:35:33 PM PDT 24
Finished Jun 24 04:35:44 PM PDT 24
Peak memory 199952 kb
Host smart-7e8cb4f0-8602-433c-a546-92df9ef00eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632767665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.1632767665
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.1726724918
Short name T203
Test name
Test status
Simulation time 389163434590 ps
CPU time 621.71 seconds
Started Jun 24 04:35:35 PM PDT 24
Finished Jun 24 04:45:57 PM PDT 24
Peak memory 200468 kb
Host smart-e82c5b1d-f8dc-4d7a-8a18-98e1b0ffb524
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726724918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.1726724918
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.3145608812
Short name T953
Test name
Test status
Simulation time 6625166518 ps
CPU time 19.31 seconds
Started Jun 24 04:35:36 PM PDT 24
Finished Jun 24 04:35:56 PM PDT 24
Peak memory 200260 kb
Host smart-9e25d901-9548-41b4-b9c6-3775df7adb69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145608812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.3145608812
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.148666685
Short name T289
Test name
Test status
Simulation time 27973904474 ps
CPU time 34.68 seconds
Started Jun 24 04:38:00 PM PDT 24
Finished Jun 24 04:39:37 PM PDT 24
Peak memory 200608 kb
Host smart-f4f8e923-289d-4ead-b4da-0847f7b95962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148666685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.148666685
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.3908704454
Short name T983
Test name
Test status
Simulation time 333358104645 ps
CPU time 38.81 seconds
Started Jun 24 04:38:01 PM PDT 24
Finished Jun 24 04:39:46 PM PDT 24
Peak memory 200464 kb
Host smart-e8538eca-3f1c-41a3-8915-45c55e4fe9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908704454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.3908704454
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.898429852
Short name T794
Test name
Test status
Simulation time 75856766788 ps
CPU time 14.22 seconds
Started Jun 24 04:38:02 PM PDT 24
Finished Jun 24 04:39:22 PM PDT 24
Peak memory 200472 kb
Host smart-470ba050-8f9d-47de-a805-38437d7a20f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898429852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.898429852
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.3321209192
Short name T476
Test name
Test status
Simulation time 104311159247 ps
CPU time 90.58 seconds
Started Jun 24 04:37:59 PM PDT 24
Finished Jun 24 04:40:33 PM PDT 24
Peak memory 200572 kb
Host smart-aee2133c-4fce-4062-8110-b7882b0d82dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321209192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.3321209192
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.751935713
Short name T955
Test name
Test status
Simulation time 45244098586 ps
CPU time 103.44 seconds
Started Jun 24 04:38:02 PM PDT 24
Finished Jun 24 04:40:51 PM PDT 24
Peak memory 200468 kb
Host smart-c4502ef5-623f-4e44-be30-f29693b38ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751935713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.751935713
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.1162458138
Short name T1096
Test name
Test status
Simulation time 41652383154 ps
CPU time 7.86 seconds
Started Jun 24 04:37:59 PM PDT 24
Finished Jun 24 04:39:11 PM PDT 24
Peak memory 200480 kb
Host smart-730208b6-b56a-4acb-b925-9b4c1840bef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162458138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.1162458138
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.1319559837
Short name T747
Test name
Test status
Simulation time 57207709288 ps
CPU time 15.65 seconds
Started Jun 24 04:38:02 PM PDT 24
Finished Jun 24 04:39:23 PM PDT 24
Peak memory 200456 kb
Host smart-6aef9fab-9742-4a3d-ae46-cb4aba4898fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319559837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.1319559837
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.1354034075
Short name T1045
Test name
Test status
Simulation time 10420804774 ps
CPU time 17.1 seconds
Started Jun 24 04:38:00 PM PDT 24
Finished Jun 24 04:39:23 PM PDT 24
Peak memory 200520 kb
Host smart-99a61ef2-1398-476c-94a3-07b8f1d07e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354034075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.1354034075
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.1740592876
Short name T778
Test name
Test status
Simulation time 85169559003 ps
CPU time 33.39 seconds
Started Jun 24 04:38:01 PM PDT 24
Finished Jun 24 04:39:40 PM PDT 24
Peak memory 200592 kb
Host smart-614892e6-2a58-4cbe-b23c-d7a76b46d904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740592876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.1740592876
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.2777254591
Short name T738
Test name
Test status
Simulation time 113477851 ps
CPU time 0.53 seconds
Started Jun 24 04:35:33 PM PDT 24
Finished Jun 24 04:35:34 PM PDT 24
Peak memory 195884 kb
Host smart-2c7cb9e2-cf01-48f4-8751-6da5c5254694
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777254591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.2777254591
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.823950721
Short name T751
Test name
Test status
Simulation time 41419990164 ps
CPU time 58.95 seconds
Started Jun 24 04:35:36 PM PDT 24
Finished Jun 24 04:36:36 PM PDT 24
Peak memory 200552 kb
Host smart-0f944b45-1561-4d53-857c-e7b60d56867b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823950721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.823950721
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.421670154
Short name T557
Test name
Test status
Simulation time 56031907993 ps
CPU time 23.08 seconds
Started Jun 24 04:35:25 PM PDT 24
Finished Jun 24 04:35:48 PM PDT 24
Peak memory 200472 kb
Host smart-05b3c34f-3f7d-44f9-9262-c8a959d3af39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421670154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.421670154
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.2232664152
Short name T634
Test name
Test status
Simulation time 99690044613 ps
CPU time 133.21 seconds
Started Jun 24 04:35:36 PM PDT 24
Finished Jun 24 04:37:50 PM PDT 24
Peak memory 200448 kb
Host smart-30f9d224-8fe8-485e-ab5d-e81543327492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232664152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.2232664152
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.2349827435
Short name T585
Test name
Test status
Simulation time 52737265796 ps
CPU time 21.36 seconds
Started Jun 24 04:35:32 PM PDT 24
Finished Jun 24 04:35:54 PM PDT 24
Peak memory 199584 kb
Host smart-bba1139c-5cd5-4c0a-9cb2-0df54e21d2e7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349827435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.2349827435
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.3844229815
Short name T947
Test name
Test status
Simulation time 323698360319 ps
CPU time 388.23 seconds
Started Jun 24 04:35:47 PM PDT 24
Finished Jun 24 04:42:19 PM PDT 24
Peak memory 200464 kb
Host smart-ebdeab8e-dba4-4832-9220-8ab2252d6dbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3844229815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.3844229815
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.183333279
Short name T868
Test name
Test status
Simulation time 5155542551 ps
CPU time 1.75 seconds
Started Jun 24 04:35:36 PM PDT 24
Finished Jun 24 04:35:39 PM PDT 24
Peak memory 198044 kb
Host smart-6837dc92-7abe-44e5-a01d-2ef8ee6e5ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183333279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.183333279
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_perf.2660174719
Short name T262
Test name
Test status
Simulation time 12311613775 ps
CPU time 620.32 seconds
Started Jun 24 04:35:36 PM PDT 24
Finished Jun 24 04:45:57 PM PDT 24
Peak memory 200496 kb
Host smart-a467dfff-50c5-4591-851f-b988014be474
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2660174719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.2660174719
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.1635360470
Short name T355
Test name
Test status
Simulation time 6895225061 ps
CPU time 16.7 seconds
Started Jun 24 04:35:34 PM PDT 24
Finished Jun 24 04:35:52 PM PDT 24
Peak memory 199820 kb
Host smart-eae3aa27-dca4-465c-a5cd-e637444bcbd5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1635360470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.1635360470
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.1793802316
Short name T434
Test name
Test status
Simulation time 53547964720 ps
CPU time 43.57 seconds
Started Jun 24 04:35:51 PM PDT 24
Finished Jun 24 04:36:47 PM PDT 24
Peak memory 200488 kb
Host smart-473d65d6-3e44-4b5a-973b-6130aaabe049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793802316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.1793802316
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.2172068955
Short name T574
Test name
Test status
Simulation time 2472052593 ps
CPU time 4.21 seconds
Started Jun 24 04:35:31 PM PDT 24
Finished Jun 24 04:35:36 PM PDT 24
Peak memory 197052 kb
Host smart-9b146246-c37c-47b1-a51e-466c4cbff629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172068955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.2172068955
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.4090146132
Short name T293
Test name
Test status
Simulation time 611567059 ps
CPU time 2.21 seconds
Started Jun 24 04:35:38 PM PDT 24
Finished Jun 24 04:35:41 PM PDT 24
Peak memory 198752 kb
Host smart-aa616249-4d41-40e8-a4ee-4b463fb0c704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090146132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.4090146132
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.3732646592
Short name T18
Test name
Test status
Simulation time 1963955754 ps
CPU time 2.82 seconds
Started Jun 24 04:35:36 PM PDT 24
Finished Jun 24 04:35:39 PM PDT 24
Peak memory 199040 kb
Host smart-9ebcec96-80cb-433b-aeb2-c4c95c118eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732646592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.3732646592
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.945360921
Short name T988
Test name
Test status
Simulation time 25653484510 ps
CPU time 21.94 seconds
Started Jun 24 04:35:36 PM PDT 24
Finished Jun 24 04:35:59 PM PDT 24
Peak memory 200628 kb
Host smart-a0e7e588-0d4e-4898-8962-1462ec00beaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945360921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.945360921
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.2788226889
Short name T627
Test name
Test status
Simulation time 161752199021 ps
CPU time 31 seconds
Started Jun 24 04:37:59 PM PDT 24
Finished Jun 24 04:39:33 PM PDT 24
Peak memory 200544 kb
Host smart-8085318f-d1be-485d-ad9e-4cbeb8d7c342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788226889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.2788226889
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.1236395123
Short name T825
Test name
Test status
Simulation time 126167883979 ps
CPU time 198.66 seconds
Started Jun 24 04:37:59 PM PDT 24
Finished Jun 24 04:42:21 PM PDT 24
Peak memory 200468 kb
Host smart-b0443c2e-045b-4ea0-b655-cd68168e09ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236395123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.1236395123
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.3980500893
Short name T657
Test name
Test status
Simulation time 190235732803 ps
CPU time 261.67 seconds
Started Jun 24 04:38:05 PM PDT 24
Finished Jun 24 04:43:34 PM PDT 24
Peak memory 200604 kb
Host smart-9861b64a-2e7d-4441-9afe-24124a8e71db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980500893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.3980500893
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.616626818
Short name T1012
Test name
Test status
Simulation time 23271786327 ps
CPU time 36.35 seconds
Started Jun 24 04:38:06 PM PDT 24
Finished Jun 24 04:39:49 PM PDT 24
Peak memory 200572 kb
Host smart-fe008766-fde9-4a5e-b059-92a252e93124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616626818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.616626818
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.547620162
Short name T436
Test name
Test status
Simulation time 16654727713 ps
CPU time 47.46 seconds
Started Jun 24 04:38:04 PM PDT 24
Finished Jun 24 04:39:59 PM PDT 24
Peak memory 200532 kb
Host smart-bcbed617-f61c-42d9-a64f-0a64f4336fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547620162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.547620162
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.1479155689
Short name T912
Test name
Test status
Simulation time 84148920103 ps
CPU time 53.26 seconds
Started Jun 24 04:38:06 PM PDT 24
Finished Jun 24 04:40:06 PM PDT 24
Peak memory 200484 kb
Host smart-3ca3a168-575f-4ec9-aa2f-8bc604dfe174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479155689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.1479155689
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.3105857577
Short name T890
Test name
Test status
Simulation time 102430995968 ps
CPU time 23.61 seconds
Started Jun 24 04:38:07 PM PDT 24
Finished Jun 24 04:39:36 PM PDT 24
Peak memory 200444 kb
Host smart-5432ac1f-ac7a-47c7-a7f8-402301653dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105857577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.3105857577
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.2046660049
Short name T635
Test name
Test status
Simulation time 39929142070 ps
CPU time 32.86 seconds
Started Jun 24 04:38:05 PM PDT 24
Finished Jun 24 04:39:45 PM PDT 24
Peak memory 200492 kb
Host smart-e12102bb-822d-44eb-a969-d95d02fe5d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046660049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.2046660049
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.2316266622
Short name T24
Test name
Test status
Simulation time 15932423 ps
CPU time 0.55 seconds
Started Jun 24 04:35:42 PM PDT 24
Finished Jun 24 04:35:44 PM PDT 24
Peak memory 195960 kb
Host smart-332246fc-18f3-472e-8cc1-fca125aa0965
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316266622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.2316266622
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.3424688816
Short name T813
Test name
Test status
Simulation time 69782504744 ps
CPU time 95.54 seconds
Started Jun 24 04:35:40 PM PDT 24
Finished Jun 24 04:37:16 PM PDT 24
Peak memory 200456 kb
Host smart-af4d7af4-4565-426d-a782-35ce63c5c8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424688816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.3424688816
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.3392383325
Short name T926
Test name
Test status
Simulation time 73677807534 ps
CPU time 40.33 seconds
Started Jun 24 04:35:46 PM PDT 24
Finished Jun 24 04:36:30 PM PDT 24
Peak memory 200520 kb
Host smart-22bcc945-dea8-4b14-bf00-f703122406fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392383325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.3392383325
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.1133565109
Short name T759
Test name
Test status
Simulation time 19262453390 ps
CPU time 13.22 seconds
Started Jun 24 04:35:43 PM PDT 24
Finished Jun 24 04:35:58 PM PDT 24
Peak memory 200464 kb
Host smart-597d747d-a0b1-429f-9dab-bacef2d2d804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133565109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.1133565109
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.3952607717
Short name T767
Test name
Test status
Simulation time 22933633903 ps
CPU time 29.7 seconds
Started Jun 24 04:35:42 PM PDT 24
Finished Jun 24 04:36:13 PM PDT 24
Peak memory 198672 kb
Host smart-ece72f1d-696a-4bf5-a4ab-ab13a0ed12e3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952607717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.3952607717
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.1967585782
Short name T365
Test name
Test status
Simulation time 214389536197 ps
CPU time 1469.23 seconds
Started Jun 24 04:35:34 PM PDT 24
Finished Jun 24 05:00:05 PM PDT 24
Peak memory 200560 kb
Host smart-66d58d8a-5f48-4d3b-b8ba-146659beca78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1967585782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.1967585782
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.53256949
Short name T636
Test name
Test status
Simulation time 4797671012 ps
CPU time 9.03 seconds
Started Jun 24 04:35:47 PM PDT 24
Finished Jun 24 04:36:01 PM PDT 24
Peak memory 198472 kb
Host smart-33075d43-ead5-49fb-9911-f9fa44e178b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53256949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.53256949
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_perf.95280375
Short name T450
Test name
Test status
Simulation time 10292425187 ps
CPU time 163.88 seconds
Started Jun 24 04:35:41 PM PDT 24
Finished Jun 24 04:38:26 PM PDT 24
Peak memory 200504 kb
Host smart-251cc92c-c36f-4d88-ba8c-e39eed74d690
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=95280375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.95280375
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.1214068949
Short name T376
Test name
Test status
Simulation time 4825863122 ps
CPU time 5.41 seconds
Started Jun 24 04:35:47 PM PDT 24
Finished Jun 24 04:35:56 PM PDT 24
Peak memory 199408 kb
Host smart-fc71e52c-7483-4acc-ba7e-62b048e8c5dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1214068949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.1214068949
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.790750363
Short name T739
Test name
Test status
Simulation time 219393714548 ps
CPU time 294.98 seconds
Started Jun 24 04:35:35 PM PDT 24
Finished Jun 24 04:40:31 PM PDT 24
Peak memory 200576 kb
Host smart-78b67fcf-0ab6-4617-a7d4-0866f1665e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790750363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.790750363
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.1921451739
Short name T773
Test name
Test status
Simulation time 4301990994 ps
CPU time 7.74 seconds
Started Jun 24 04:35:51 PM PDT 24
Finished Jun 24 04:36:11 PM PDT 24
Peak memory 196792 kb
Host smart-8e5a1825-d1f6-4779-847d-e280fa8dae34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921451739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.1921451739
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.84202908
Short name T809
Test name
Test status
Simulation time 5523989277 ps
CPU time 8.39 seconds
Started Jun 24 04:35:42 PM PDT 24
Finished Jun 24 04:35:51 PM PDT 24
Peak memory 200276 kb
Host smart-acd80d0c-8708-45aa-a79c-60e095396708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84202908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.84202908
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.3501523334
Short name T789
Test name
Test status
Simulation time 6809849515 ps
CPU time 15.13 seconds
Started Jun 24 04:35:38 PM PDT 24
Finished Jun 24 04:35:54 PM PDT 24
Peak memory 199628 kb
Host smart-42dff8bc-e580-442e-bcfc-006d2f7c996a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501523334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.3501523334
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.517970191
Short name T950
Test name
Test status
Simulation time 14656979241 ps
CPU time 13.86 seconds
Started Jun 24 04:35:32 PM PDT 24
Finished Jun 24 04:35:47 PM PDT 24
Peak memory 200576 kb
Host smart-bac43e60-5578-475f-bc95-df3453dbc50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517970191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.517970191
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.1637001925
Short name T177
Test name
Test status
Simulation time 38179855979 ps
CPU time 17.6 seconds
Started Jun 24 04:38:05 PM PDT 24
Finished Jun 24 04:39:30 PM PDT 24
Peak memory 200540 kb
Host smart-95333090-0785-4e08-b6b2-3b00a4f91573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637001925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.1637001925
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.1160000121
Short name T209
Test name
Test status
Simulation time 45483572662 ps
CPU time 12.06 seconds
Started Jun 24 04:38:08 PM PDT 24
Finished Jun 24 04:39:24 PM PDT 24
Peak memory 200524 kb
Host smart-aa936b79-db84-4ddf-a4cc-6bf52d2de9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160000121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.1160000121
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.1772642541
Short name T633
Test name
Test status
Simulation time 42165380266 ps
CPU time 18.99 seconds
Started Jun 24 04:38:11 PM PDT 24
Finished Jun 24 04:39:34 PM PDT 24
Peak memory 200488 kb
Host smart-de2f877b-ed34-44c7-80d9-73284b2d5d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772642541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.1772642541
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.300835640
Short name T803
Test name
Test status
Simulation time 178041582983 ps
CPU time 270.88 seconds
Started Jun 24 04:38:06 PM PDT 24
Finished Jun 24 04:43:43 PM PDT 24
Peak memory 200468 kb
Host smart-a99d4a64-2025-4184-9c3e-f2fd81a95da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300835640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.300835640
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.2692879281
Short name T1078
Test name
Test status
Simulation time 130494912151 ps
CPU time 25.94 seconds
Started Jun 24 04:38:07 PM PDT 24
Finished Jun 24 04:39:38 PM PDT 24
Peak memory 200540 kb
Host smart-a2136670-7d1a-4823-8c99-70424a0a72db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692879281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.2692879281
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.2887022186
Short name T192
Test name
Test status
Simulation time 49524968467 ps
CPU time 75.23 seconds
Started Jun 24 04:38:05 PM PDT 24
Finished Jun 24 04:40:27 PM PDT 24
Peak memory 200488 kb
Host smart-aff7f76f-8f71-4ab1-b3f0-7190eaaa224b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887022186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.2887022186
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.3655208946
Short name T872
Test name
Test status
Simulation time 112391621768 ps
CPU time 193.24 seconds
Started Jun 24 04:38:09 PM PDT 24
Finished Jun 24 04:42:27 PM PDT 24
Peak memory 200580 kb
Host smart-902ac1e4-649c-45a2-8175-4aa027ac1301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655208946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.3655208946
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.87792749
Short name T745
Test name
Test status
Simulation time 18679402548 ps
CPU time 33.41 seconds
Started Jun 24 04:38:11 PM PDT 24
Finished Jun 24 04:39:49 PM PDT 24
Peak memory 200552 kb
Host smart-0bbddc72-93b9-472c-89b7-11b7279bf15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87792749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.87792749
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.1480290132
Short name T494
Test name
Test status
Simulation time 46904573 ps
CPU time 0.56 seconds
Started Jun 24 04:35:34 PM PDT 24
Finished Jun 24 04:35:35 PM PDT 24
Peak memory 195864 kb
Host smart-bc1a3b79-7576-4b25-b5dc-a31e92ab2019
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480290132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.1480290132
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.2103921214
Short name T645
Test name
Test status
Simulation time 35013012596 ps
CPU time 58.03 seconds
Started Jun 24 04:35:37 PM PDT 24
Finished Jun 24 04:36:36 PM PDT 24
Peak memory 200560 kb
Host smart-580a864b-bde5-40ec-94c6-57f823a3b3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103921214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.2103921214
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.907722305
Short name T260
Test name
Test status
Simulation time 86139266761 ps
CPU time 124.38 seconds
Started Jun 24 04:35:34 PM PDT 24
Finished Jun 24 04:37:39 PM PDT 24
Peak memory 200620 kb
Host smart-fa53476a-c7ea-49a7-8470-82ed604fc9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907722305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.907722305
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.426334140
Short name T685
Test name
Test status
Simulation time 106571186009 ps
CPU time 40.56 seconds
Started Jun 24 04:35:32 PM PDT 24
Finished Jun 24 04:36:14 PM PDT 24
Peak memory 200000 kb
Host smart-cfba404f-4fac-41b7-8fd5-1981bb8c0269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426334140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.426334140
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.2744624403
Short name T431
Test name
Test status
Simulation time 11975586120 ps
CPU time 7.62 seconds
Started Jun 24 04:35:35 PM PDT 24
Finished Jun 24 04:35:44 PM PDT 24
Peak memory 200168 kb
Host smart-06634876-df2c-4c53-9c61-5f0dfd8c52bd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744624403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.2744624403
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.2713198987
Short name T567
Test name
Test status
Simulation time 123744507373 ps
CPU time 1109.96 seconds
Started Jun 24 04:35:34 PM PDT 24
Finished Jun 24 04:54:05 PM PDT 24
Peak memory 200592 kb
Host smart-b51ab868-a144-479c-9965-91aa14bed3e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2713198987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.2713198987
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.3162174351
Short name T857
Test name
Test status
Simulation time 2647520503 ps
CPU time 1.74 seconds
Started Jun 24 04:35:41 PM PDT 24
Finished Jun 24 04:35:43 PM PDT 24
Peak memory 196316 kb
Host smart-47de9f76-4218-41db-b750-5f2db37bc316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162174351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.3162174351
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.3422968564
Short name T1041
Test name
Test status
Simulation time 5657363346 ps
CPU time 9.82 seconds
Started Jun 24 04:35:39 PM PDT 24
Finished Jun 24 04:35:49 PM PDT 24
Peak memory 198184 kb
Host smart-77f78610-3c13-4c26-8dab-5b52d39dc360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422968564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.3422968564
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.643914577
Short name T496
Test name
Test status
Simulation time 4844265065 ps
CPU time 273.79 seconds
Started Jun 24 04:35:39 PM PDT 24
Finished Jun 24 04:40:14 PM PDT 24
Peak memory 200504 kb
Host smart-37eb290d-e597-4467-8243-31f29b62bf47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=643914577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.643914577
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.566193421
Short name T343
Test name
Test status
Simulation time 1407293266 ps
CPU time 1.76 seconds
Started Jun 24 04:35:48 PM PDT 24
Finished Jun 24 04:35:55 PM PDT 24
Peak memory 198604 kb
Host smart-ebd5c1f1-27dd-43d6-b675-10d6ce38f0b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=566193421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.566193421
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.3720192716
Short name T626
Test name
Test status
Simulation time 129971750490 ps
CPU time 194.72 seconds
Started Jun 24 04:35:47 PM PDT 24
Finished Jun 24 04:39:05 PM PDT 24
Peak memory 200464 kb
Host smart-953db397-1ffe-4999-a5ce-1d6f8c05f3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720192716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.3720192716
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.807069067
Short name T353
Test name
Test status
Simulation time 5679731448 ps
CPU time 9.47 seconds
Started Jun 24 04:35:46 PM PDT 24
Finished Jun 24 04:35:59 PM PDT 24
Peak memory 196772 kb
Host smart-d182a98c-107d-476e-9481-fdbc9ea25888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807069067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.807069067
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.1450948680
Short name T7
Test name
Test status
Simulation time 5377949272 ps
CPU time 8.05 seconds
Started Jun 24 04:35:31 PM PDT 24
Finished Jun 24 04:35:40 PM PDT 24
Peak memory 200248 kb
Host smart-045470d3-6c4e-4855-8c19-41d5bced036b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450948680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.1450948680
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.1722774497
Short name T821
Test name
Test status
Simulation time 149873926788 ps
CPU time 52.56 seconds
Started Jun 24 04:35:38 PM PDT 24
Finished Jun 24 04:36:31 PM PDT 24
Peak memory 200504 kb
Host smart-a5eb1cd8-1400-4b51-b01d-54c10e66b3bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722774497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.1722774497
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.3312269660
Short name T444
Test name
Test status
Simulation time 65147495808 ps
CPU time 874.11 seconds
Started Jun 24 04:35:43 PM PDT 24
Finished Jun 24 04:50:18 PM PDT 24
Peak memory 217108 kb
Host smart-f879b554-8a36-44de-99c6-6be1ec99894c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312269660 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.3312269660
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.198465989
Short name T523
Test name
Test status
Simulation time 701036080 ps
CPU time 2.19 seconds
Started Jun 24 04:35:47 PM PDT 24
Finished Jun 24 04:35:53 PM PDT 24
Peak memory 199296 kb
Host smart-2d4addff-5531-40b4-b5dd-69ff0a72345a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198465989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.198465989
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.3869098747
Short name T469
Test name
Test status
Simulation time 51450358250 ps
CPU time 35.2 seconds
Started Jun 24 04:35:38 PM PDT 24
Finished Jun 24 04:36:14 PM PDT 24
Peak memory 200216 kb
Host smart-48a37319-2893-4ce4-b673-1e49c00b70f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869098747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.3869098747
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.798560791
Short name T656
Test name
Test status
Simulation time 128811713501 ps
CPU time 112.05 seconds
Started Jun 24 04:38:06 PM PDT 24
Finished Jun 24 04:41:04 PM PDT 24
Peak memory 200460 kb
Host smart-4c5ba022-f7d6-44b8-bb09-5eb778f7f5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798560791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.798560791
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.1317862277
Short name T924
Test name
Test status
Simulation time 139918589562 ps
CPU time 107.13 seconds
Started Jun 24 04:38:13 PM PDT 24
Finished Jun 24 04:41:05 PM PDT 24
Peak memory 200520 kb
Host smart-b3b0d64f-1d74-4756-af1b-fb8ee88421d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317862277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.1317862277
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.3577474577
Short name T680
Test name
Test status
Simulation time 43095899290 ps
CPU time 18.61 seconds
Started Jun 24 04:38:13 PM PDT 24
Finished Jun 24 04:39:36 PM PDT 24
Peak memory 200368 kb
Host smart-037befaf-10db-4b60-b58f-a115f03da029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577474577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.3577474577
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.1069034092
Short name T218
Test name
Test status
Simulation time 105109044569 ps
CPU time 150.42 seconds
Started Jun 24 04:38:15 PM PDT 24
Finished Jun 24 04:41:49 PM PDT 24
Peak memory 200516 kb
Host smart-8b6e368f-c8e5-48fe-af39-ff28291c9f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069034092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.1069034092
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.2231711169
Short name T335
Test name
Test status
Simulation time 39489475280 ps
CPU time 11.51 seconds
Started Jun 24 04:38:13 PM PDT 24
Finished Jun 24 04:39:30 PM PDT 24
Peak memory 200512 kb
Host smart-e1ed6c2a-9ec6-48ab-9f8d-6a7dffa75e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231711169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.2231711169
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.1966635124
Short name T742
Test name
Test status
Simulation time 418753573758 ps
CPU time 58.66 seconds
Started Jun 24 04:38:15 PM PDT 24
Finished Jun 24 04:40:17 PM PDT 24
Peak memory 200516 kb
Host smart-f9bdc4b6-55b4-44f0-bf66-a74a1c084425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966635124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.1966635124
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.399841884
Short name T734
Test name
Test status
Simulation time 44677987777 ps
CPU time 68.04 seconds
Started Jun 24 04:38:13 PM PDT 24
Finished Jun 24 04:40:26 PM PDT 24
Peak memory 200576 kb
Host smart-cf5e2fc0-f122-4a6b-aee2-f0ac4a5f066e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399841884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.399841884
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.1216401012
Short name T413
Test name
Test status
Simulation time 32039100248 ps
CPU time 13.51 seconds
Started Jun 24 04:38:13 PM PDT 24
Finished Jun 24 04:39:31 PM PDT 24
Peak memory 200252 kb
Host smart-55842e0f-9127-447a-8d49-797f8c140eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216401012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.1216401012
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.941470672
Short name T151
Test name
Test status
Simulation time 60571587839 ps
CPU time 19.89 seconds
Started Jun 24 04:38:12 PM PDT 24
Finished Jun 24 04:39:35 PM PDT 24
Peak memory 200272 kb
Host smart-b8487747-bab9-49dd-9ff1-15356492e852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941470672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.941470672
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.1814829435
Short name T584
Test name
Test status
Simulation time 17419335 ps
CPU time 0.57 seconds
Started Jun 24 04:35:44 PM PDT 24
Finished Jun 24 04:35:46 PM PDT 24
Peak memory 195864 kb
Host smart-e8dd0856-b90a-41e7-b1fb-5afd4eccddc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814829435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.1814829435
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.230484701
Short name T147
Test name
Test status
Simulation time 123704028545 ps
CPU time 63.92 seconds
Started Jun 24 04:35:47 PM PDT 24
Finished Jun 24 04:36:55 PM PDT 24
Peak memory 200536 kb
Host smart-c157841f-5830-4742-80c4-c02c3c19e5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230484701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.230484701
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.3208824566
Short name T544
Test name
Test status
Simulation time 18354257383 ps
CPU time 14.52 seconds
Started Jun 24 04:35:36 PM PDT 24
Finished Jun 24 04:35:51 PM PDT 24
Peak memory 200460 kb
Host smart-d6aa6655-10d3-46d4-ab59-d3129be6bdf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208824566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.3208824566
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.2282826980
Short name T831
Test name
Test status
Simulation time 141023177094 ps
CPU time 63.61 seconds
Started Jun 24 04:35:34 PM PDT 24
Finished Jun 24 04:36:39 PM PDT 24
Peak memory 200620 kb
Host smart-de759532-91ef-4173-8a01-34fc7d18295f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282826980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.2282826980
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.3192323949
Short name T121
Test name
Test status
Simulation time 50834826076 ps
CPU time 87.87 seconds
Started Jun 24 04:35:36 PM PDT 24
Finished Jun 24 04:37:04 PM PDT 24
Peak memory 200508 kb
Host smart-9d146330-1c4b-48eb-82ac-706722b6e1dc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192323949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.3192323949
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.4252779235
Short name T267
Test name
Test status
Simulation time 142837081289 ps
CPU time 381.76 seconds
Started Jun 24 04:35:47 PM PDT 24
Finished Jun 24 04:42:13 PM PDT 24
Peak memory 200448 kb
Host smart-a26aecc7-69d6-4f7a-b5f8-c8c3ce0725a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4252779235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.4252779235
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.1589530993
Short name T596
Test name
Test status
Simulation time 10479942975 ps
CPU time 4.07 seconds
Started Jun 24 04:35:45 PM PDT 24
Finished Jun 24 04:35:51 PM PDT 24
Peak memory 200420 kb
Host smart-d4b61418-8068-4f26-b0b8-3c5754fbcca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589530993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.1589530993
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_perf.1914102860
Short name T915
Test name
Test status
Simulation time 26575013049 ps
CPU time 1482.41 seconds
Started Jun 24 04:35:46 PM PDT 24
Finished Jun 24 05:00:32 PM PDT 24
Peak memory 200496 kb
Host smart-18c9a039-0150-4a90-8830-092db61b71b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1914102860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.1914102860
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.651924339
Short name T951
Test name
Test status
Simulation time 6080920400 ps
CPU time 23.97 seconds
Started Jun 24 04:35:34 PM PDT 24
Finished Jun 24 04:35:59 PM PDT 24
Peak memory 200456 kb
Host smart-15d0ad2b-841a-40ec-b544-669dfcc19ae9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=651924339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.651924339
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.103136202
Short name T758
Test name
Test status
Simulation time 106733354800 ps
CPU time 172.44 seconds
Started Jun 24 04:35:44 PM PDT 24
Finished Jun 24 04:38:39 PM PDT 24
Peak memory 200516 kb
Host smart-64e0d7f9-b20c-4d96-9302-420d1a0d8cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103136202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.103136202
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.1393938543
Short name T814
Test name
Test status
Simulation time 3183346757 ps
CPU time 3.07 seconds
Started Jun 24 04:35:37 PM PDT 24
Finished Jun 24 04:35:41 PM PDT 24
Peak memory 196800 kb
Host smart-f985fb8c-f260-479a-aaa3-463d10ef665d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393938543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.1393938543
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.2453236067
Short name T639
Test name
Test status
Simulation time 6168070530 ps
CPU time 17.33 seconds
Started Jun 24 04:35:33 PM PDT 24
Finished Jun 24 04:35:51 PM PDT 24
Peak memory 200492 kb
Host smart-37f4e80b-c192-434f-b125-2756ae7464ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453236067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.2453236067
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.3248304976
Short name T126
Test name
Test status
Simulation time 47096566362 ps
CPU time 532.64 seconds
Started Jun 24 04:35:44 PM PDT 24
Finished Jun 24 04:44:39 PM PDT 24
Peak memory 216980 kb
Host smart-0741e6af-e45f-49b8-9daa-1e8460f0afec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248304976 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.3248304976
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.2631827806
Short name T1005
Test name
Test status
Simulation time 6778499457 ps
CPU time 9.27 seconds
Started Jun 24 04:35:48 PM PDT 24
Finished Jun 24 04:36:01 PM PDT 24
Peak memory 200404 kb
Host smart-8c402667-d3f1-4a7f-aadd-ce631d8b4285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631827806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.2631827806
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.109834758
Short name T964
Test name
Test status
Simulation time 22069086455 ps
CPU time 27.81 seconds
Started Jun 24 04:35:34 PM PDT 24
Finished Jun 24 04:36:03 PM PDT 24
Peak memory 200468 kb
Host smart-6b6f287e-644f-42e9-96fe-408afb2a8a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109834758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.109834758
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.663169259
Short name T526
Test name
Test status
Simulation time 14460363771 ps
CPU time 24.55 seconds
Started Jun 24 04:38:14 PM PDT 24
Finished Jun 24 04:39:43 PM PDT 24
Peak memory 200544 kb
Host smart-aaea36ee-6404-424c-8c9a-017b61bdeb4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663169259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.663169259
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.2397269397
Short name T822
Test name
Test status
Simulation time 23907774499 ps
CPU time 18.32 seconds
Started Jun 24 04:38:11 PM PDT 24
Finished Jun 24 04:39:34 PM PDT 24
Peak memory 200524 kb
Host smart-52535a34-7e6a-40d7-8434-cbddfc396ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397269397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.2397269397
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.3929944021
Short name T735
Test name
Test status
Simulation time 78544071336 ps
CPU time 21.68 seconds
Started Jun 24 04:38:14 PM PDT 24
Finished Jun 24 04:39:40 PM PDT 24
Peak memory 200544 kb
Host smart-ed272eba-1349-418a-b155-2131ea8b6fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929944021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.3929944021
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.3495767574
Short name T234
Test name
Test status
Simulation time 122434999987 ps
CPU time 15.36 seconds
Started Jun 24 04:38:12 PM PDT 24
Finished Jun 24 04:39:31 PM PDT 24
Peak memory 200668 kb
Host smart-a9cee02e-a237-4d85-9350-f566954813c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495767574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.3495767574
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.1628581622
Short name T661
Test name
Test status
Simulation time 60567784438 ps
CPU time 88.69 seconds
Started Jun 24 04:38:12 PM PDT 24
Finished Jun 24 04:40:44 PM PDT 24
Peak memory 200464 kb
Host smart-e456e054-041d-4b49-9d69-88820a5889b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628581622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.1628581622
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.207232553
Short name T539
Test name
Test status
Simulation time 45090546045 ps
CPU time 15.46 seconds
Started Jun 24 04:38:12 PM PDT 24
Finished Jun 24 04:39:31 PM PDT 24
Peak memory 200608 kb
Host smart-080b0b70-573f-4949-8334-789760320332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207232553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.207232553
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.209278868
Short name T637
Test name
Test status
Simulation time 32161216 ps
CPU time 0.57 seconds
Started Jun 24 04:35:49 PM PDT 24
Finished Jun 24 04:35:56 PM PDT 24
Peak memory 195944 kb
Host smart-8dfd3279-481b-4ee9-8205-6262f0482101
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209278868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.209278868
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.1278139081
Short name T480
Test name
Test status
Simulation time 39973980122 ps
CPU time 64.67 seconds
Started Jun 24 04:35:44 PM PDT 24
Finished Jun 24 04:36:51 PM PDT 24
Peak memory 200544 kb
Host smart-13e56bca-f283-4478-9d75-850ef093701e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278139081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.1278139081
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.371391715
Short name T879
Test name
Test status
Simulation time 19050457121 ps
CPU time 30.99 seconds
Started Jun 24 04:35:43 PM PDT 24
Finished Jun 24 04:36:16 PM PDT 24
Peak memory 200168 kb
Host smart-a1408cb5-3746-4bd9-9529-39cc1a4eb1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371391715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.371391715
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.349248330
Short name T977
Test name
Test status
Simulation time 220236259228 ps
CPU time 165.63 seconds
Started Jun 24 04:35:46 PM PDT 24
Finished Jun 24 04:38:35 PM PDT 24
Peak memory 200576 kb
Host smart-caa98ca9-37b2-413a-bf03-7054a419d120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349248330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.349248330
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.2801258037
Short name T765
Test name
Test status
Simulation time 54474689517 ps
CPU time 25.47 seconds
Started Jun 24 04:35:40 PM PDT 24
Finished Jun 24 04:36:05 PM PDT 24
Peak memory 200508 kb
Host smart-5e7ee331-fe59-443e-9466-a914e7424c5e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801258037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.2801258037
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.4208969990
Short name T783
Test name
Test status
Simulation time 102674260794 ps
CPU time 349.58 seconds
Started Jun 24 04:35:43 PM PDT 24
Finished Jun 24 04:41:35 PM PDT 24
Peak memory 200548 kb
Host smart-c7e61e8f-144e-4cfd-9331-bfdffe03babb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4208969990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.4208969990
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.2087285758
Short name T625
Test name
Test status
Simulation time 10020525138 ps
CPU time 2.75 seconds
Started Jun 24 04:35:42 PM PDT 24
Finished Jun 24 04:35:52 PM PDT 24
Peak memory 199112 kb
Host smart-ee9baa17-62f2-482b-969c-b5fcf9fc553c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087285758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.2087285758
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_perf.803466444
Short name T1089
Test name
Test status
Simulation time 3905859079 ps
CPU time 106.66 seconds
Started Jun 24 04:35:42 PM PDT 24
Finished Jun 24 04:37:30 PM PDT 24
Peak memory 200600 kb
Host smart-eb42a8ca-e093-4f13-9c6b-35e5b673eda9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=803466444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.803466444
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.4080233945
Short name T933
Test name
Test status
Simulation time 3585960093 ps
CPU time 6.57 seconds
Started Jun 24 04:35:43 PM PDT 24
Finished Jun 24 04:35:50 PM PDT 24
Peak memory 198568 kb
Host smart-7a09c667-6703-4e8f-9a76-c55abd0980b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4080233945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.4080233945
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.2298868360
Short name T587
Test name
Test status
Simulation time 14241427220 ps
CPU time 17.58 seconds
Started Jun 24 04:35:48 PM PDT 24
Finished Jun 24 04:36:11 PM PDT 24
Peak memory 200460 kb
Host smart-a05b2585-65fe-4efd-b3ea-aace3385489c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298868360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.2298868360
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.2209596883
Short name T312
Test name
Test status
Simulation time 32122671604 ps
CPU time 10.1 seconds
Started Jun 24 04:35:44 PM PDT 24
Finished Jun 24 04:35:55 PM PDT 24
Peak memory 196572 kb
Host smart-f8bbbc22-60a4-40d3-92fb-e4b0f71f231d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209596883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.2209596883
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.4174568123
Short name T969
Test name
Test status
Simulation time 938697382 ps
CPU time 2.33 seconds
Started Jun 24 04:35:47 PM PDT 24
Finished Jun 24 04:35:53 PM PDT 24
Peak memory 199364 kb
Host smart-f391a4e3-7808-4643-bec8-73256afa2362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174568123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.4174568123
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.659504878
Short name T815
Test name
Test status
Simulation time 132905180138 ps
CPU time 187.35 seconds
Started Jun 24 04:35:41 PM PDT 24
Finished Jun 24 04:38:49 PM PDT 24
Peak memory 200504 kb
Host smart-a2bdef2f-a40b-4885-a839-ed2f0326216b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659504878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.659504878
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.3648187855
Short name T17
Test name
Test status
Simulation time 1910630717 ps
CPU time 2.57 seconds
Started Jun 24 04:35:39 PM PDT 24
Finished Jun 24 04:35:42 PM PDT 24
Peak memory 200440 kb
Host smart-4f4693aa-3ccb-4cc9-bcc0-06132ad67cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648187855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.3648187855
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.2869122854
Short name T909
Test name
Test status
Simulation time 68187597388 ps
CPU time 138.46 seconds
Started Jun 24 04:35:43 PM PDT 24
Finished Jun 24 04:38:03 PM PDT 24
Peak memory 200552 kb
Host smart-ef4d4277-e315-43f6-8778-4df4afb0d765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869122854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.2869122854
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.2014163933
Short name T552
Test name
Test status
Simulation time 143215889049 ps
CPU time 76.91 seconds
Started Jun 24 04:38:11 PM PDT 24
Finished Jun 24 04:40:32 PM PDT 24
Peak memory 200636 kb
Host smart-ebb40f28-b926-4991-adba-5b0d6ab1e3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014163933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.2014163933
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.3363274401
Short name T802
Test name
Test status
Simulation time 25673862550 ps
CPU time 36.43 seconds
Started Jun 24 04:38:14 PM PDT 24
Finished Jun 24 04:39:55 PM PDT 24
Peak memory 200548 kb
Host smart-ab097470-dd09-437b-b8ce-48aa9e30112a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363274401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.3363274401
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.678815366
Short name T205
Test name
Test status
Simulation time 31756309475 ps
CPU time 46.82 seconds
Started Jun 24 04:38:20 PM PDT 24
Finished Jun 24 04:40:10 PM PDT 24
Peak memory 200512 kb
Host smart-b8f9bb34-276e-4ec0-b429-835bb055dac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678815366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.678815366
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.1640283257
Short name T340
Test name
Test status
Simulation time 32013030474 ps
CPU time 52.48 seconds
Started Jun 24 04:38:22 PM PDT 24
Finished Jun 24 04:40:18 PM PDT 24
Peak memory 200468 kb
Host smart-1f32f68a-8584-4bd0-8b5a-5a57541096c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640283257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.1640283257
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.1992984054
Short name T232
Test name
Test status
Simulation time 21878241592 ps
CPU time 40 seconds
Started Jun 24 04:38:22 PM PDT 24
Finished Jun 24 04:40:06 PM PDT 24
Peak memory 200544 kb
Host smart-a77e39b9-afbf-4320-8a0b-14206c8d1f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992984054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.1992984054
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.1662331061
Short name T479
Test name
Test status
Simulation time 58510759866 ps
CPU time 40.09 seconds
Started Jun 24 04:38:21 PM PDT 24
Finished Jun 24 04:40:05 PM PDT 24
Peak memory 200852 kb
Host smart-669770fd-2b2d-41e3-a995-8311c11953a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662331061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.1662331061
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.1158342809
Short name T1007
Test name
Test status
Simulation time 216024406981 ps
CPU time 29.62 seconds
Started Jun 24 04:38:20 PM PDT 24
Finished Jun 24 04:39:53 PM PDT 24
Peak memory 200932 kb
Host smart-4a6150da-be94-4c29-9865-8cd113f5aa83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158342809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.1158342809
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.1335825407
Short name T1095
Test name
Test status
Simulation time 97048107607 ps
CPU time 55.56 seconds
Started Jun 24 04:38:21 PM PDT 24
Finished Jun 24 04:40:21 PM PDT 24
Peak memory 200512 kb
Host smart-be837cc3-6df9-4975-8633-41090d32cfe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335825407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.1335825407
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.1000462738
Short name T920
Test name
Test status
Simulation time 22446478 ps
CPU time 0.56 seconds
Started Jun 24 04:35:42 PM PDT 24
Finished Jun 24 04:35:43 PM PDT 24
Peak memory 195900 kb
Host smart-b829eee6-8711-480b-b4a4-ccad2e8b3f22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000462738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.1000462738
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.2638079753
Short name T943
Test name
Test status
Simulation time 48838550345 ps
CPU time 31.31 seconds
Started Jun 24 04:35:39 PM PDT 24
Finished Jun 24 04:36:11 PM PDT 24
Peak memory 200548 kb
Host smart-b607656a-da52-4690-be41-53d44fbb66a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638079753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.2638079753
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.754659373
Short name T707
Test name
Test status
Simulation time 127750169111 ps
CPU time 62.02 seconds
Started Jun 24 04:35:48 PM PDT 24
Finished Jun 24 04:36:54 PM PDT 24
Peak memory 200112 kb
Host smart-90c3cb04-aa5b-47a0-95ed-de233ec3b3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754659373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.754659373
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.2057373524
Short name T490
Test name
Test status
Simulation time 59622835886 ps
CPU time 23.7 seconds
Started Jun 24 04:35:42 PM PDT 24
Finished Jun 24 04:36:06 PM PDT 24
Peak memory 200540 kb
Host smart-b83616f2-84c5-4285-8df0-442dce17303d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057373524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.2057373524
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.1900713607
Short name T646
Test name
Test status
Simulation time 18731935577 ps
CPU time 32.67 seconds
Started Jun 24 04:35:47 PM PDT 24
Finished Jun 24 04:36:23 PM PDT 24
Peak memory 197516 kb
Host smart-598de37a-650b-406a-8e4b-30b3591da731
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900713607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.1900713607
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.1248022035
Short name T683
Test name
Test status
Simulation time 88019180787 ps
CPU time 807.48 seconds
Started Jun 24 04:35:49 PM PDT 24
Finished Jun 24 04:49:23 PM PDT 24
Peak memory 200508 kb
Host smart-c2a507ba-76a4-47da-ae05-9f703da9efb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1248022035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.1248022035
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.734461131
Short name T1094
Test name
Test status
Simulation time 12381012468 ps
CPU time 11.06 seconds
Started Jun 24 04:35:43 PM PDT 24
Finished Jun 24 04:35:55 PM PDT 24
Peak memory 200436 kb
Host smart-ac59b1aa-fd15-4cd0-a8bf-83a3a5ceae2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734461131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.734461131
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_perf.1137863234
Short name T989
Test name
Test status
Simulation time 18403852768 ps
CPU time 246.85 seconds
Started Jun 24 04:35:45 PM PDT 24
Finished Jun 24 04:39:54 PM PDT 24
Peak memory 200500 kb
Host smart-f5d20a24-25f4-46b8-883a-d06dd380cf47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1137863234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.1137863234
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.1558496684
Short name T360
Test name
Test status
Simulation time 3546304151 ps
CPU time 6.16 seconds
Started Jun 24 04:35:48 PM PDT 24
Finished Jun 24 04:35:59 PM PDT 24
Peak memory 199460 kb
Host smart-d128464f-a98e-4daf-a80a-18774a308a33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1558496684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.1558496684
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.3420082981
Short name T601
Test name
Test status
Simulation time 62293120694 ps
CPU time 24.17 seconds
Started Jun 24 04:35:41 PM PDT 24
Finished Jun 24 04:36:06 PM PDT 24
Peak memory 200240 kb
Host smart-3ab11b4c-bf5b-48fc-9277-fbe9bfbe6d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420082981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.3420082981
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.2704274634
Short name T429
Test name
Test status
Simulation time 4665749787 ps
CPU time 2.56 seconds
Started Jun 24 04:35:45 PM PDT 24
Finished Jun 24 04:35:51 PM PDT 24
Peak memory 196824 kb
Host smart-249819bb-7177-4064-aa14-f212387e0ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704274634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.2704274634
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.852504913
Short name T386
Test name
Test status
Simulation time 1071401429 ps
CPU time 1.4 seconds
Started Jun 24 04:35:47 PM PDT 24
Finished Jun 24 04:35:53 PM PDT 24
Peak memory 198900 kb
Host smart-1463974b-f044-45c6-9878-04cd615f6aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852504913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.852504913
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.286578793
Short name T117
Test name
Test status
Simulation time 159149201714 ps
CPU time 271.95 seconds
Started Jun 24 04:35:43 PM PDT 24
Finished Jun 24 04:40:16 PM PDT 24
Peak memory 200536 kb
Host smart-a354cfd6-8ffb-470f-a36e-faba11b03543
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286578793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.286578793
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.1419016168
Short name T649
Test name
Test status
Simulation time 13456884933 ps
CPU time 21.28 seconds
Started Jun 24 04:35:46 PM PDT 24
Finished Jun 24 04:36:10 PM PDT 24
Peak memory 200208 kb
Host smart-61586dc9-0b75-46a3-a873-6b14328f9e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419016168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.1419016168
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.1636957149
Short name T896
Test name
Test status
Simulation time 108836732343 ps
CPU time 55.32 seconds
Started Jun 24 04:35:36 PM PDT 24
Finished Jun 24 04:36:33 PM PDT 24
Peak memory 200492 kb
Host smart-e7556635-a063-4754-b8f5-68aee6dc68ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636957149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.1636957149
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.3413802575
Short name T229
Test name
Test status
Simulation time 16086973741 ps
CPU time 18.38 seconds
Started Jun 24 04:38:30 PM PDT 24
Finished Jun 24 04:39:52 PM PDT 24
Peak memory 200432 kb
Host smart-c802d5ba-a9a6-440e-a7e2-22a6e7fba701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413802575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.3413802575
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.1850196928
Short name T757
Test name
Test status
Simulation time 27769660438 ps
CPU time 43.44 seconds
Started Jun 24 04:38:21 PM PDT 24
Finished Jun 24 04:40:09 PM PDT 24
Peak memory 200440 kb
Host smart-5d9f0c54-c697-4e3b-ae7c-f6cc8f634be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850196928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.1850196928
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.1407162841
Short name T284
Test name
Test status
Simulation time 48225010634 ps
CPU time 69.03 seconds
Started Jun 24 04:38:20 PM PDT 24
Finished Jun 24 04:40:34 PM PDT 24
Peak memory 200464 kb
Host smart-4bff4ec7-a600-4f22-8340-166032fcaba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407162841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.1407162841
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.2331255909
Short name T577
Test name
Test status
Simulation time 13848919513 ps
CPU time 20.39 seconds
Started Jun 24 04:38:30 PM PDT 24
Finished Jun 24 04:39:54 PM PDT 24
Peak memory 200248 kb
Host smart-7b08d709-e4cd-4cb5-a3a0-f52617d989bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331255909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.2331255909
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.1258065303
Short name T420
Test name
Test status
Simulation time 67694581734 ps
CPU time 46.14 seconds
Started Jun 24 04:38:21 PM PDT 24
Finished Jun 24 04:40:11 PM PDT 24
Peak memory 200544 kb
Host smart-87fa910c-764c-4b44-b5c9-c3de3a2b5f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258065303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.1258065303
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.3206202386
Short name T779
Test name
Test status
Simulation time 86136100092 ps
CPU time 27.65 seconds
Started Jun 24 04:38:30 PM PDT 24
Finished Jun 24 04:40:01 PM PDT 24
Peak memory 200244 kb
Host smart-0d32162b-a841-4580-9a0e-0f1e4c9cd609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206202386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.3206202386
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.842539991
Short name T265
Test name
Test status
Simulation time 96987504803 ps
CPU time 104.81 seconds
Started Jun 24 04:38:24 PM PDT 24
Finished Jun 24 04:41:14 PM PDT 24
Peak memory 200488 kb
Host smart-250f7431-9ba4-45f6-adcd-6f7b0d61cff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842539991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.842539991
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.1952623988
Short name T415
Test name
Test status
Simulation time 12874578469 ps
CPU time 6.63 seconds
Started Jun 24 04:38:30 PM PDT 24
Finished Jun 24 04:39:40 PM PDT 24
Peak memory 200524 kb
Host smart-b0515cbe-2edc-474d-b75e-cc93e22eccba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952623988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.1952623988
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.578385845
Short name T25
Test name
Test status
Simulation time 38207399 ps
CPU time 0.57 seconds
Started Jun 24 04:35:01 PM PDT 24
Finished Jun 24 04:35:03 PM PDT 24
Peak memory 195856 kb
Host smart-9e8bc1ec-8842-4c46-81c4-fa9bc735bab1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578385845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.578385845
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.3350101535
Short name T460
Test name
Test status
Simulation time 119195187120 ps
CPU time 15.84 seconds
Started Jun 24 04:35:01 PM PDT 24
Finished Jun 24 04:35:19 PM PDT 24
Peak memory 200580 kb
Host smart-ed2dd4f6-9b45-4ff9-9780-5fd68322fce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350101535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.3350101535
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.2390367079
Short name T307
Test name
Test status
Simulation time 126546774729 ps
CPU time 14.92 seconds
Started Jun 24 04:35:26 PM PDT 24
Finished Jun 24 04:35:41 PM PDT 24
Peak memory 200308 kb
Host smart-fbddc977-d750-4512-ab42-169568769edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390367079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.2390367079
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.3698594234
Short name T1085
Test name
Test status
Simulation time 161302603937 ps
CPU time 56.18 seconds
Started Jun 24 04:35:13 PM PDT 24
Finished Jun 24 04:36:11 PM PDT 24
Peak memory 200488 kb
Host smart-3f60544e-c9ee-4a74-b963-2382267910f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698594234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.3698594234
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.1677972330
Short name T958
Test name
Test status
Simulation time 52921020067 ps
CPU time 26.18 seconds
Started Jun 24 04:35:03 PM PDT 24
Finished Jun 24 04:35:30 PM PDT 24
Peak memory 200484 kb
Host smart-1f65a729-cc10-4363-8d85-640056b1b0a2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677972330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.1677972330
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_loopback.3042154979
Short name T653
Test name
Test status
Simulation time 4489863785 ps
CPU time 8.58 seconds
Started Jun 24 04:35:03 PM PDT 24
Finished Jun 24 04:35:13 PM PDT 24
Peak memory 200252 kb
Host smart-7f674a62-8fd3-4cb1-bf20-5b2ebd7a8381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042154979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.3042154979
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_perf.2484208004
Short name T817
Test name
Test status
Simulation time 19580091319 ps
CPU time 1013.92 seconds
Started Jun 24 04:34:58 PM PDT 24
Finished Jun 24 04:51:54 PM PDT 24
Peak memory 200444 kb
Host smart-05079825-a5d4-4b88-abdc-2e959bbb2caf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2484208004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.2484208004
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.900750370
Short name T428
Test name
Test status
Simulation time 3293588762 ps
CPU time 25.39 seconds
Started Jun 24 04:35:15 PM PDT 24
Finished Jun 24 04:35:43 PM PDT 24
Peak memory 199040 kb
Host smart-e507ea6a-6eca-4ca5-bf6a-76841198cb14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=900750370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.900750370
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.1262149709
Short name T323
Test name
Test status
Simulation time 158307211092 ps
CPU time 29 seconds
Started Jun 24 04:35:16 PM PDT 24
Finished Jun 24 04:35:47 PM PDT 24
Peak memory 200604 kb
Host smart-923cb925-4f7e-4575-80a4-8edfa83dcd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262149709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.1262149709
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.3639005067
Short name T109
Test name
Test status
Simulation time 1772556195 ps
CPU time 2.11 seconds
Started Jun 24 04:35:02 PM PDT 24
Finished Jun 24 04:35:06 PM PDT 24
Peak memory 196192 kb
Host smart-d5086a54-ebf9-4414-a99f-ad129f5509e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639005067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.3639005067
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.1095308271
Short name T89
Test name
Test status
Simulation time 233349485 ps
CPU time 0.85 seconds
Started Jun 24 04:35:09 PM PDT 24
Finished Jun 24 04:35:11 PM PDT 24
Peak memory 219032 kb
Host smart-5effaf5f-43a4-4111-8a8f-6fc483449235
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095308271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.1095308271
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.939795894
Short name T448
Test name
Test status
Simulation time 865860604 ps
CPU time 1.75 seconds
Started Jun 24 04:35:14 PM PDT 24
Finished Jun 24 04:35:18 PM PDT 24
Peak memory 200360 kb
Host smart-465734a5-5fe7-4bf1-9481-d3b9a1335a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939795894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.939795894
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.2557903627
Short name T856
Test name
Test status
Simulation time 525846604534 ps
CPU time 641.28 seconds
Started Jun 24 04:35:06 PM PDT 24
Finished Jun 24 04:45:48 PM PDT 24
Peak memory 200480 kb
Host smart-cfc1067a-2982-4675-bf9d-127d149bb059
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557903627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.2557903627
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.3532434118
Short name T971
Test name
Test status
Simulation time 996277964 ps
CPU time 2.63 seconds
Started Jun 24 04:35:08 PM PDT 24
Finished Jun 24 04:35:12 PM PDT 24
Peak memory 198860 kb
Host smart-e7309dc6-066c-4e52-81b1-d1f88f48ec43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532434118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.3532434118
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.387293414
Short name T383
Test name
Test status
Simulation time 24776439983 ps
CPU time 17.23 seconds
Started Jun 24 04:35:26 PM PDT 24
Finished Jun 24 04:35:44 PM PDT 24
Peak memory 199240 kb
Host smart-38ba6f92-e186-46ca-bfb9-851ae091d385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387293414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.387293414
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.541772978
Short name T687
Test name
Test status
Simulation time 163379107 ps
CPU time 0.6 seconds
Started Jun 24 04:35:44 PM PDT 24
Finished Jun 24 04:35:46 PM PDT 24
Peak memory 195864 kb
Host smart-9ef06e30-f5bb-47b2-80b1-8c6dde25dad2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541772978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.541772978
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.1732119439
Short name T264
Test name
Test status
Simulation time 127008822201 ps
CPU time 134.98 seconds
Started Jun 24 04:35:45 PM PDT 24
Finished Jun 24 04:38:02 PM PDT 24
Peak memory 200432 kb
Host smart-4ccdb935-c04c-4c4d-93ee-1ee4c0f627ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732119439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.1732119439
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.2839408851
Short name T565
Test name
Test status
Simulation time 37533680080 ps
CPU time 72.97 seconds
Started Jun 24 04:35:46 PM PDT 24
Finished Jun 24 04:37:02 PM PDT 24
Peak memory 200500 kb
Host smart-a9e64507-bb6a-465b-8b11-b57914b72133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839408851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.2839408851
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.2015673015
Short name T515
Test name
Test status
Simulation time 178611814932 ps
CPU time 386.46 seconds
Started Jun 24 04:35:44 PM PDT 24
Finished Jun 24 04:42:12 PM PDT 24
Peak memory 200512 kb
Host smart-1f5d3487-423c-4dec-b1e0-c02cb4789c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015673015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.2015673015
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.3676783804
Short name T721
Test name
Test status
Simulation time 10189225792 ps
CPU time 10.14 seconds
Started Jun 24 04:35:48 PM PDT 24
Finished Jun 24 04:36:02 PM PDT 24
Peak memory 200448 kb
Host smart-49a6c57a-785b-4083-ab35-40c055a97f57
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676783804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.3676783804
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.3252890047
Short name T546
Test name
Test status
Simulation time 183291004540 ps
CPU time 180.42 seconds
Started Jun 24 04:35:41 PM PDT 24
Finished Jun 24 04:38:42 PM PDT 24
Peak memory 200488 kb
Host smart-c3d654ac-da79-419e-b15c-7d752eec9e3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3252890047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.3252890047
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.1741491867
Short name T986
Test name
Test status
Simulation time 8763911367 ps
CPU time 10.54 seconds
Started Jun 24 04:35:40 PM PDT 24
Finished Jun 24 04:35:52 PM PDT 24
Peak memory 200500 kb
Host smart-7c18fc28-5ddc-49b6-b55a-84f9cd44b0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741491867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.1741491867
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_perf.2014140944
Short name T766
Test name
Test status
Simulation time 13005455259 ps
CPU time 196.09 seconds
Started Jun 24 04:35:42 PM PDT 24
Finished Jun 24 04:38:59 PM PDT 24
Peak memory 200504 kb
Host smart-14c847fd-0d95-4202-b501-75fbb37e7e62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2014140944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.2014140944
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.1956451434
Short name T880
Test name
Test status
Simulation time 6264814776 ps
CPU time 62.59 seconds
Started Jun 24 04:35:40 PM PDT 24
Finished Jun 24 04:36:44 PM PDT 24
Peak memory 198852 kb
Host smart-726943db-efe1-4811-bfdc-3ae4c5288102
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1956451434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.1956451434
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.1510353157
Short name T1086
Test name
Test status
Simulation time 9739190952 ps
CPU time 10.5 seconds
Started Jun 24 04:35:45 PM PDT 24
Finished Jun 24 04:35:59 PM PDT 24
Peak memory 200524 kb
Host smart-a0a738d7-893e-4518-9f12-b2fd9b873574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510353157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.1510353157
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.3977999638
Short name T703
Test name
Test status
Simulation time 4313518650 ps
CPU time 6.83 seconds
Started Jun 24 04:35:49 PM PDT 24
Finished Jun 24 04:36:02 PM PDT 24
Peak memory 197136 kb
Host smart-f8953411-745b-4308-b896-4f866f17fc55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977999638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.3977999638
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.1167857331
Short name T993
Test name
Test status
Simulation time 281267676 ps
CPU time 1 seconds
Started Jun 24 04:35:46 PM PDT 24
Finished Jun 24 04:35:50 PM PDT 24
Peak memory 199088 kb
Host smart-8997ecfa-8b25-4f6d-b622-916a4cc1cef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167857331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.1167857331
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.1070144730
Short name T540
Test name
Test status
Simulation time 22641853034 ps
CPU time 136.02 seconds
Started Jun 24 04:35:44 PM PDT 24
Finished Jun 24 04:38:02 PM PDT 24
Peak memory 216868 kb
Host smart-97eeefd0-26c5-48c3-b8a5-2a60908aa1c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070144730 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.1070144730
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.3359716413
Short name T317
Test name
Test status
Simulation time 1417672098 ps
CPU time 2.85 seconds
Started Jun 24 04:35:41 PM PDT 24
Finished Jun 24 04:35:45 PM PDT 24
Peak memory 199440 kb
Host smart-b5761c22-970c-4f3a-bce6-40ca4ae46132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359716413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.3359716413
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.2285412941
Short name T1001
Test name
Test status
Simulation time 71230017016 ps
CPU time 127.65 seconds
Started Jun 24 04:35:48 PM PDT 24
Finished Jun 24 04:38:01 PM PDT 24
Peak memory 200464 kb
Host smart-aa83723e-364d-4d37-99a5-55912326c0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285412941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.2285412941
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.4212349683
Short name T433
Test name
Test status
Simulation time 18646292860 ps
CPU time 17.21 seconds
Started Jun 24 04:38:23 PM PDT 24
Finished Jun 24 04:39:46 PM PDT 24
Peak memory 200612 kb
Host smart-942944e9-b444-4883-a4c5-1be4cf38d742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212349683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.4212349683
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.105786897
Short name T701
Test name
Test status
Simulation time 219111353333 ps
CPU time 44.84 seconds
Started Jun 24 04:38:21 PM PDT 24
Finished Jun 24 04:40:10 PM PDT 24
Peak memory 200460 kb
Host smart-d12df596-9a43-4b70-9bee-4b8de680e57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105786897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.105786897
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.2678473244
Short name T790
Test name
Test status
Simulation time 136365029699 ps
CPU time 421.56 seconds
Started Jun 24 04:38:24 PM PDT 24
Finished Jun 24 04:46:30 PM PDT 24
Peak memory 200576 kb
Host smart-7c4cc791-710b-40fc-acb8-1773f2a637c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678473244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.2678473244
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.2005011583
Short name T1018
Test name
Test status
Simulation time 25366295614 ps
CPU time 43.03 seconds
Started Jun 24 04:38:20 PM PDT 24
Finished Jun 24 04:40:08 PM PDT 24
Peak memory 200460 kb
Host smart-5d1832fb-4988-4a34-954f-00db6698dd33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005011583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.2005011583
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.2543542439
Short name T542
Test name
Test status
Simulation time 76610543869 ps
CPU time 106.65 seconds
Started Jun 24 04:38:19 PM PDT 24
Finished Jun 24 04:41:10 PM PDT 24
Peak memory 200512 kb
Host smart-71991b80-1b4b-484c-a700-d5aef270ddc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543542439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.2543542439
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.808345109
Short name T607
Test name
Test status
Simulation time 8671265659 ps
CPU time 13.85 seconds
Started Jun 24 04:38:19 PM PDT 24
Finished Jun 24 04:39:37 PM PDT 24
Peak memory 200296 kb
Host smart-eaa9e631-6603-4b2e-9ce9-951228ccfef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808345109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.808345109
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.3929267712
Short name T641
Test name
Test status
Simulation time 47110492279 ps
CPU time 104.5 seconds
Started Jun 24 04:38:20 PM PDT 24
Finished Jun 24 04:41:09 PM PDT 24
Peak memory 200520 kb
Host smart-6839c0a2-da56-44dd-ad12-8741120fed19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929267712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.3929267712
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.1447819114
Short name T644
Test name
Test status
Simulation time 21209785952 ps
CPU time 34.79 seconds
Started Jun 24 04:38:21 PM PDT 24
Finished Jun 24 04:40:00 PM PDT 24
Peak memory 200400 kb
Host smart-1814be99-91e4-4d14-8917-920d88d2e1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447819114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.1447819114
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.3811330137
Short name T427
Test name
Test status
Simulation time 74069321122 ps
CPU time 37.54 seconds
Started Jun 24 04:38:23 PM PDT 24
Finished Jun 24 04:40:04 PM PDT 24
Peak memory 200488 kb
Host smart-8ac5d37d-2163-4f6d-8024-6a6e08b76ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811330137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.3811330137
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.280905578
Short name T357
Test name
Test status
Simulation time 47629870 ps
CPU time 0.6 seconds
Started Jun 24 04:35:47 PM PDT 24
Finished Jun 24 04:35:52 PM PDT 24
Peak memory 195812 kb
Host smart-51573ccb-2d71-45cc-98ef-6463e055c86b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280905578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.280905578
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.3145882978
Short name T394
Test name
Test status
Simulation time 101044135360 ps
CPU time 161.99 seconds
Started Jun 24 04:35:44 PM PDT 24
Finished Jun 24 04:38:28 PM PDT 24
Peak memory 200544 kb
Host smart-fa84c997-4e1a-406b-a503-602e1faae998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145882978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.3145882978
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.630941501
Short name T797
Test name
Test status
Simulation time 12491530044 ps
CPU time 19.87 seconds
Started Jun 24 04:36:00 PM PDT 24
Finished Jun 24 04:36:41 PM PDT 24
Peak memory 200284 kb
Host smart-5bc215cb-bf46-478d-9794-a5eb92eb4753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630941501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.630941501
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.2522185871
Short name T145
Test name
Test status
Simulation time 27150892110 ps
CPU time 14.77 seconds
Started Jun 24 04:35:49 PM PDT 24
Finished Jun 24 04:36:10 PM PDT 24
Peak memory 199132 kb
Host smart-adbf5249-4cda-4102-bceb-a2c74cd71b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522185871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.2522185871
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.2560013833
Short name T326
Test name
Test status
Simulation time 354284559958 ps
CPU time 543.06 seconds
Started Jun 24 04:35:56 PM PDT 24
Finished Jun 24 04:45:19 PM PDT 24
Peak memory 198724 kb
Host smart-1c018185-1b33-49a9-ae87-9cde08265c1a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560013833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.2560013833
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.407804958
Short name T1066
Test name
Test status
Simulation time 206046552918 ps
CPU time 970.88 seconds
Started Jun 24 04:35:50 PM PDT 24
Finished Jun 24 04:52:11 PM PDT 24
Peak memory 200468 kb
Host smart-af461a76-6ea2-4eb5-a78d-b1ca7e6eb4cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=407804958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.407804958
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.4068854089
Short name T381
Test name
Test status
Simulation time 4547825944 ps
CPU time 4.75 seconds
Started Jun 24 04:36:00 PM PDT 24
Finished Jun 24 04:36:25 PM PDT 24
Peak memory 196800 kb
Host smart-a0f7a900-ed71-46d3-9eeb-c442997ee780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068854089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.4068854089
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_perf.3818013838
Short name T694
Test name
Test status
Simulation time 15662137737 ps
CPU time 441.69 seconds
Started Jun 24 04:35:53 PM PDT 24
Finished Jun 24 04:43:30 PM PDT 24
Peak memory 200500 kb
Host smart-7a989e19-7111-4e14-99e7-a754a2d7e4bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3818013838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.3818013838
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.177037404
Short name T468
Test name
Test status
Simulation time 4094237284 ps
CPU time 27.44 seconds
Started Jun 24 04:35:52 PM PDT 24
Finished Jun 24 04:36:35 PM PDT 24
Peak memory 198892 kb
Host smart-5f0bdc44-584e-4276-8edf-221c0ec022e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=177037404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.177037404
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.1644196168
Short name T696
Test name
Test status
Simulation time 93341346967 ps
CPU time 152.89 seconds
Started Jun 24 04:35:49 PM PDT 24
Finished Jun 24 04:38:29 PM PDT 24
Peak memory 200872 kb
Host smart-ad1c092b-3029-465d-84d1-ae7e73c7ad25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644196168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.1644196168
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.3314217736
Short name T497
Test name
Test status
Simulation time 585002781 ps
CPU time 1.59 seconds
Started Jun 24 04:35:49 PM PDT 24
Finished Jun 24 04:35:57 PM PDT 24
Peak memory 196020 kb
Host smart-161bd493-d3a7-4aba-88bd-6cecd5433859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314217736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.3314217736
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.1472798750
Short name T279
Test name
Test status
Simulation time 11573140527 ps
CPU time 24.88 seconds
Started Jun 24 04:35:41 PM PDT 24
Finished Jun 24 04:36:06 PM PDT 24
Peak memory 200432 kb
Host smart-4b2a61f8-43d6-48c8-b32b-6786a44493c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472798750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.1472798750
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.2526199169
Short name T616
Test name
Test status
Simulation time 171219045989 ps
CPU time 149.61 seconds
Started Jun 24 04:35:55 PM PDT 24
Finished Jun 24 04:38:44 PM PDT 24
Peak memory 200604 kb
Host smart-d8a2cc75-7fdc-4dcd-a59c-ed7489cf77bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526199169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.2526199169
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.2706113032
Short name T615
Test name
Test status
Simulation time 16669503466 ps
CPU time 140.59 seconds
Started Jun 24 04:35:47 PM PDT 24
Finished Jun 24 04:38:12 PM PDT 24
Peak memory 212528 kb
Host smart-7878fa74-0872-48a8-b303-1dcdf325407a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706113032 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.2706113032
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.2899916480
Short name T722
Test name
Test status
Simulation time 6636566996 ps
CPU time 7.28 seconds
Started Jun 24 04:35:49 PM PDT 24
Finished Jun 24 04:36:04 PM PDT 24
Peak memory 200492 kb
Host smart-8f931b01-7bb5-4611-9894-13f90c4e1fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899916480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.2899916480
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.2514043681
Short name T521
Test name
Test status
Simulation time 158108188049 ps
CPU time 71.51 seconds
Started Jun 24 04:35:48 PM PDT 24
Finished Jun 24 04:37:04 PM PDT 24
Peak memory 200532 kb
Host smart-6526d4cd-6881-4912-8ef3-bda1ab4fe098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514043681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.2514043681
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.2122670062
Short name T1079
Test name
Test status
Simulation time 167722156225 ps
CPU time 100.25 seconds
Started Jun 24 04:38:21 PM PDT 24
Finished Jun 24 04:41:06 PM PDT 24
Peak memory 200560 kb
Host smart-ff50171c-0a52-4f0d-b61d-8fc986282e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122670062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.2122670062
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.1554949107
Short name T719
Test name
Test status
Simulation time 58286604545 ps
CPU time 62.88 seconds
Started Jun 24 04:38:20 PM PDT 24
Finished Jun 24 04:40:28 PM PDT 24
Peak memory 200640 kb
Host smart-02b97125-5343-4937-91b3-93d49448d6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554949107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.1554949107
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.3627669083
Short name T1063
Test name
Test status
Simulation time 82911936781 ps
CPU time 207.07 seconds
Started Jun 24 04:38:21 PM PDT 24
Finished Jun 24 04:42:53 PM PDT 24
Peak memory 200540 kb
Host smart-95ca5a53-6cf1-4dff-ac6b-1d8faae93e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627669083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.3627669083
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.981613874
Short name T198
Test name
Test status
Simulation time 201065239043 ps
CPU time 157.86 seconds
Started Jun 24 04:38:25 PM PDT 24
Finished Jun 24 04:42:08 PM PDT 24
Peak memory 200924 kb
Host smart-06033e5a-5955-469f-99f4-5ad3886a047d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981613874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.981613874
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.2899535654
Short name T511
Test name
Test status
Simulation time 13485051887 ps
CPU time 22.1 seconds
Started Jun 24 04:38:25 PM PDT 24
Finished Jun 24 04:39:52 PM PDT 24
Peak memory 200068 kb
Host smart-8b47b5c0-3fc2-49d1-b51d-38fc7d9e9894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899535654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.2899535654
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.2297677902
Short name T217
Test name
Test status
Simulation time 35606308251 ps
CPU time 71.24 seconds
Started Jun 24 04:38:25 PM PDT 24
Finished Jun 24 04:40:41 PM PDT 24
Peak memory 200412 kb
Host smart-53e3c464-c49c-4a1f-9f5e-7d1cc01f0951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297677902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.2297677902
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.2838073443
Short name T257
Test name
Test status
Simulation time 117241605975 ps
CPU time 15.93 seconds
Started Jun 24 04:38:26 PM PDT 24
Finished Jun 24 04:39:46 PM PDT 24
Peak memory 200464 kb
Host smart-5e221e7f-5445-405b-bb52-15d721d48a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838073443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.2838073443
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.2930912961
Short name T131
Test name
Test status
Simulation time 35580066708 ps
CPU time 60.56 seconds
Started Jun 24 04:38:24 PM PDT 24
Finished Jun 24 04:40:30 PM PDT 24
Peak memory 200604 kb
Host smart-d50f6e2f-dbec-47e7-b1e2-d8a8253a531b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930912961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.2930912961
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.3122254550
Short name T144
Test name
Test status
Simulation time 47061984352 ps
CPU time 71.69 seconds
Started Jun 24 04:38:25 PM PDT 24
Finished Jun 24 04:40:41 PM PDT 24
Peak memory 200472 kb
Host smart-879fc33c-5e73-412c-9c5c-cbed2070ff2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122254550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.3122254550
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.773530515
Short name T830
Test name
Test status
Simulation time 43238008503 ps
CPU time 86.67 seconds
Started Jun 24 04:38:25 PM PDT 24
Finished Jun 24 04:40:56 PM PDT 24
Peak memory 200488 kb
Host smart-f48cf7b5-3e77-4b34-8f0a-ac5ff2df12aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773530515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.773530515
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.3054252148
Short name T375
Test name
Test status
Simulation time 61136075 ps
CPU time 0.58 seconds
Started Jun 24 04:35:50 PM PDT 24
Finished Jun 24 04:36:01 PM PDT 24
Peak memory 196288 kb
Host smart-b7dd3a33-174b-4cc9-bd33-5916d0a2093f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054252148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.3054252148
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.4117239173
Short name T672
Test name
Test status
Simulation time 101518135778 ps
CPU time 41.24 seconds
Started Jun 24 04:35:50 PM PDT 24
Finished Jun 24 04:36:41 PM PDT 24
Peak memory 200520 kb
Host smart-f4f8d62a-ef6f-4353-abed-7d97f7c4796d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117239173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.4117239173
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.3194227009
Short name T318
Test name
Test status
Simulation time 51438602511 ps
CPU time 43.32 seconds
Started Jun 24 04:35:55 PM PDT 24
Finished Jun 24 04:36:57 PM PDT 24
Peak memory 200240 kb
Host smart-0714b7b5-917d-4dad-affe-f9418362b66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194227009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.3194227009
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.620201861
Short name T586
Test name
Test status
Simulation time 40461144847 ps
CPU time 80.34 seconds
Started Jun 24 04:35:54 PM PDT 24
Finished Jun 24 04:37:33 PM PDT 24
Peak memory 200564 kb
Host smart-7c4ad2bb-135e-4c30-8e6e-ea4d626b135f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620201861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.620201861
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.2791679779
Short name T367
Test name
Test status
Simulation time 69331339208 ps
CPU time 28.14 seconds
Started Jun 24 04:35:53 PM PDT 24
Finished Jun 24 04:36:37 PM PDT 24
Peak memory 199564 kb
Host smart-ce0e487c-e5ad-46de-b9a7-014d370a816d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791679779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.2791679779
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.985303196
Short name T843
Test name
Test status
Simulation time 86119902841 ps
CPU time 618.55 seconds
Started Jun 24 04:35:52 PM PDT 24
Finished Jun 24 04:46:26 PM PDT 24
Peak memory 200468 kb
Host smart-573005a6-2885-4463-8c02-10b7da85d6b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=985303196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.985303196
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.1548892087
Short name T704
Test name
Test status
Simulation time 1894427537 ps
CPU time 1.42 seconds
Started Jun 24 04:35:49 PM PDT 24
Finished Jun 24 04:35:59 PM PDT 24
Peak memory 196456 kb
Host smart-bb48b45b-5450-4bfd-8596-82ce288ca6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548892087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.1548892087
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_perf.2327590330
Short name T315
Test name
Test status
Simulation time 9310974384 ps
CPU time 192.15 seconds
Started Jun 24 04:35:48 PM PDT 24
Finished Jun 24 04:39:06 PM PDT 24
Peak memory 200436 kb
Host smart-02a3f867-0792-41d2-8218-687665cd8a15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2327590330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.2327590330
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.1574634080
Short name T987
Test name
Test status
Simulation time 2427361740 ps
CPU time 16.62 seconds
Started Jun 24 04:35:45 PM PDT 24
Finished Jun 24 04:36:05 PM PDT 24
Peak memory 198868 kb
Host smart-72292d31-3c78-4a7f-9390-178ee2bcd123
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1574634080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.1574634080
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.1953405352
Short name T836
Test name
Test status
Simulation time 159506743978 ps
CPU time 236.21 seconds
Started Jun 24 04:35:56 PM PDT 24
Finished Jun 24 04:40:12 PM PDT 24
Peak memory 200568 kb
Host smart-8ed29871-866a-477e-b691-aba82ed6070c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953405352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.1953405352
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.2864721071
Short name T666
Test name
Test status
Simulation time 3040020903 ps
CPU time 5.52 seconds
Started Jun 24 04:35:57 PM PDT 24
Finished Jun 24 04:36:22 PM PDT 24
Peak memory 196372 kb
Host smart-3e8bd7f6-8f1b-4d6a-a14f-eda55de872e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864721071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.2864721071
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.1408343
Short name T1008
Test name
Test status
Simulation time 10571100788 ps
CPU time 29.3 seconds
Started Jun 24 04:35:48 PM PDT 24
Finished Jun 24 04:36:24 PM PDT 24
Peak memory 200116 kb
Host smart-14982fa7-b4b2-4e7d-8cc1-c1deef218578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.1408343
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.2233521996
Short name T529
Test name
Test status
Simulation time 123905097047 ps
CPU time 456.82 seconds
Started Jun 24 04:35:49 PM PDT 24
Finished Jun 24 04:43:35 PM PDT 24
Peak memory 211412 kb
Host smart-1d8187fc-4648-43e2-bcbf-45dc256478ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233521996 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.2233521996
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.3543286028
Short name T835
Test name
Test status
Simulation time 757474793 ps
CPU time 3.53 seconds
Started Jun 24 04:35:50 PM PDT 24
Finished Jun 24 04:36:02 PM PDT 24
Peak memory 199064 kb
Host smart-cd485d2d-4c6c-4060-9c6f-4ad5770bcc53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543286028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.3543286028
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.459141642
Short name T684
Test name
Test status
Simulation time 43393933085 ps
CPU time 7.35 seconds
Started Jun 24 04:35:53 PM PDT 24
Finished Jun 24 04:36:16 PM PDT 24
Peak memory 200624 kb
Host smart-33c39556-fda9-489f-95cd-b1afa8e26ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459141642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.459141642
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.3580261296
Short name T946
Test name
Test status
Simulation time 93400027973 ps
CPU time 41.41 seconds
Started Jun 24 04:38:26 PM PDT 24
Finished Jun 24 04:40:11 PM PDT 24
Peak memory 200500 kb
Host smart-8a8e0ac9-df6b-42ba-8f6c-a6671fe7a013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580261296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.3580261296
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.1071294054
Short name T723
Test name
Test status
Simulation time 65417125583 ps
CPU time 137.92 seconds
Started Jun 24 04:38:30 PM PDT 24
Finished Jun 24 04:41:51 PM PDT 24
Peak memory 200436 kb
Host smart-7e2e0774-b366-4a51-bb59-8539c7250dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071294054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.1071294054
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.374944784
Short name T45
Test name
Test status
Simulation time 199919187160 ps
CPU time 321.36 seconds
Started Jun 24 04:38:25 PM PDT 24
Finished Jun 24 04:44:51 PM PDT 24
Peak memory 200540 kb
Host smart-6ab39d73-ba90-463a-b68c-3c3e77023a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374944784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.374944784
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.1479906618
Short name T195
Test name
Test status
Simulation time 84072191497 ps
CPU time 33.21 seconds
Started Jun 24 04:38:25 PM PDT 24
Finished Jun 24 04:40:03 PM PDT 24
Peak memory 200492 kb
Host smart-a6492e5a-f16b-4dda-b3e2-1ffe2c49855f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479906618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.1479906618
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.3352412723
Short name T495
Test name
Test status
Simulation time 60316309214 ps
CPU time 25.18 seconds
Started Jun 24 04:38:26 PM PDT 24
Finished Jun 24 04:39:55 PM PDT 24
Peak memory 200540 kb
Host smart-90ee21df-df29-467e-9480-348b11bc7713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352412723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.3352412723
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.159278782
Short name T1074
Test name
Test status
Simulation time 169296241492 ps
CPU time 683.46 seconds
Started Jun 24 04:38:26 PM PDT 24
Finished Jun 24 04:50:53 PM PDT 24
Peak memory 200548 kb
Host smart-32509de4-e413-4755-bb98-334dc5c4adaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159278782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.159278782
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.1645307325
Short name T599
Test name
Test status
Simulation time 31665158501 ps
CPU time 79.74 seconds
Started Jun 24 04:38:27 PM PDT 24
Finished Jun 24 04:40:50 PM PDT 24
Peak memory 200932 kb
Host smart-427a8877-2ede-4557-83c1-d28945463b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645307325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.1645307325
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.2381975728
Short name T944
Test name
Test status
Simulation time 68122871429 ps
CPU time 32.52 seconds
Started Jun 24 04:38:24 PM PDT 24
Finished Jun 24 04:40:02 PM PDT 24
Peak memory 200636 kb
Host smart-93294176-23e0-4cc7-b400-4a5d4f33d19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381975728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.2381975728
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.2916835224
Short name T161
Test name
Test status
Simulation time 189751880940 ps
CPU time 34.65 seconds
Started Jun 24 04:38:25 PM PDT 24
Finished Jun 24 04:40:04 PM PDT 24
Peak memory 200540 kb
Host smart-6a8e8df3-61b8-4711-816c-fa451a0fc152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916835224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.2916835224
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.3378822458
Short name T957
Test name
Test status
Simulation time 9627304641 ps
CPU time 4.18 seconds
Started Jun 24 04:38:30 PM PDT 24
Finished Jun 24 04:39:38 PM PDT 24
Peak memory 199328 kb
Host smart-cc7dfa77-4c8b-402a-a0a4-982756d86564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378822458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.3378822458
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.1474562183
Short name T378
Test name
Test status
Simulation time 171120525 ps
CPU time 0.55 seconds
Started Jun 24 04:35:54 PM PDT 24
Finished Jun 24 04:36:11 PM PDT 24
Peak memory 195924 kb
Host smart-d9672511-befd-4fe2-b1df-4d976806488c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474562183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.1474562183
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.49088447
Short name T576
Test name
Test status
Simulation time 87184172065 ps
CPU time 126.27 seconds
Started Jun 24 04:35:50 PM PDT 24
Finished Jun 24 04:38:06 PM PDT 24
Peak memory 199096 kb
Host smart-21599498-e772-4dda-9528-78409168d6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49088447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.49088447
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.3684195185
Short name T244
Test name
Test status
Simulation time 67011270389 ps
CPU time 173.63 seconds
Started Jun 24 04:35:54 PM PDT 24
Finished Jun 24 04:39:04 PM PDT 24
Peak memory 200524 kb
Host smart-a0ed9a71-b668-40db-89b3-a85299b7c2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684195185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.3684195185
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.1939217509
Short name T118
Test name
Test status
Simulation time 20852167291 ps
CPU time 35.37 seconds
Started Jun 24 04:35:57 PM PDT 24
Finished Jun 24 04:36:53 PM PDT 24
Peak memory 200448 kb
Host smart-df544f8a-76a0-42ca-94ac-3567845f0c9c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939217509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.1939217509
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.1824952547
Short name T302
Test name
Test status
Simulation time 94614669476 ps
CPU time 116.66 seconds
Started Jun 24 04:35:56 PM PDT 24
Finished Jun 24 04:38:11 PM PDT 24
Peak memory 200516 kb
Host smart-a9af9afa-20d0-46ca-8625-0d3c8171b109
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1824952547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.1824952547
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.1670478147
Short name T441
Test name
Test status
Simulation time 6524684159 ps
CPU time 3.23 seconds
Started Jun 24 04:35:48 PM PDT 24
Finished Jun 24 04:35:56 PM PDT 24
Peak memory 199216 kb
Host smart-39276202-3e9f-4564-9823-efe63b2813aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670478147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.1670478147
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_perf.219512726
Short name T608
Test name
Test status
Simulation time 9319978995 ps
CPU time 404.8 seconds
Started Jun 24 04:35:58 PM PDT 24
Finished Jun 24 04:43:03 PM PDT 24
Peak memory 200540 kb
Host smart-c7b73386-3511-49d6-9001-49339a756427
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=219512726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.219512726
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.2719835011
Short name T111
Test name
Test status
Simulation time 4947846346 ps
CPU time 32.02 seconds
Started Jun 24 04:35:54 PM PDT 24
Finished Jun 24 04:36:44 PM PDT 24
Peak memory 198704 kb
Host smart-12b8effa-82f4-4224-aa5b-d57029637006
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2719835011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.2719835011
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.1369186092
Short name T91
Test name
Test status
Simulation time 79121299836 ps
CPU time 161.3 seconds
Started Jun 24 04:35:59 PM PDT 24
Finished Jun 24 04:39:02 PM PDT 24
Peak memory 200564 kb
Host smart-12ef9fdf-b8ad-4772-bb9c-704abd234163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369186092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.1369186092
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.1773657519
Short name T604
Test name
Test status
Simulation time 629921007 ps
CPU time 1.63 seconds
Started Jun 24 04:35:48 PM PDT 24
Finished Jun 24 04:35:55 PM PDT 24
Peak memory 196564 kb
Host smart-02b200b9-db3d-4790-9078-cbddddbdd34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773657519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.1773657519
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.1676542815
Short name T301
Test name
Test status
Simulation time 932036861 ps
CPU time 3.61 seconds
Started Jun 24 04:35:52 PM PDT 24
Finished Jun 24 04:36:08 PM PDT 24
Peak memory 198952 kb
Host smart-c9e3663a-5df7-4030-8876-38b1ca92b455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676542815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.1676542815
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.279567422
Short name T49
Test name
Test status
Simulation time 100128280088 ps
CPU time 1170.18 seconds
Started Jun 24 04:36:01 PM PDT 24
Finished Jun 24 04:55:52 PM PDT 24
Peak memory 217040 kb
Host smart-178c3738-927c-4d48-bb24-fe180771591d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279567422 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.279567422
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.2064376165
Short name T910
Test name
Test status
Simulation time 1895487427 ps
CPU time 2.08 seconds
Started Jun 24 04:35:54 PM PDT 24
Finished Jun 24 04:36:12 PM PDT 24
Peak memory 199252 kb
Host smart-84f29054-d586-439d-8da5-9dcd35e6b1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064376165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.2064376165
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.2184079060
Short name T558
Test name
Test status
Simulation time 27146300127 ps
CPU time 12.48 seconds
Started Jun 24 04:35:48 PM PDT 24
Finished Jun 24 04:36:07 PM PDT 24
Peak memory 200652 kb
Host smart-56eef5fe-3c55-4cc8-912f-1c2bb2a0bea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184079060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.2184079060
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.2887171200
Short name T770
Test name
Test status
Simulation time 21232406192 ps
CPU time 10.45 seconds
Started Jun 24 04:38:26 PM PDT 24
Finished Jun 24 04:39:40 PM PDT 24
Peak memory 200532 kb
Host smart-5cb7648e-fbfe-4133-bf24-60506910d12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887171200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.2887171200
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.1288429115
Short name T236
Test name
Test status
Simulation time 25210405760 ps
CPU time 11.28 seconds
Started Jun 24 04:38:25 PM PDT 24
Finished Jun 24 04:39:41 PM PDT 24
Peak memory 200480 kb
Host smart-5e22c304-9a94-48d6-a0df-53fa45bf1795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288429115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.1288429115
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.1024081369
Short name T1030
Test name
Test status
Simulation time 148979606882 ps
CPU time 63.18 seconds
Started Jun 24 04:38:30 PM PDT 24
Finished Jun 24 04:40:37 PM PDT 24
Peak memory 199128 kb
Host smart-06498df1-b7b8-477b-a2d3-9748d3644767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024081369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.1024081369
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.827134673
Short name T677
Test name
Test status
Simulation time 66388093729 ps
CPU time 32.18 seconds
Started Jun 24 04:38:26 PM PDT 24
Finished Jun 24 04:40:02 PM PDT 24
Peak memory 200528 kb
Host smart-fc76b197-fe4d-421c-8626-ea8317fe33cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827134673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.827134673
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.404037976
Short name T876
Test name
Test status
Simulation time 35180559098 ps
CPU time 57.33 seconds
Started Jun 24 04:38:25 PM PDT 24
Finished Jun 24 04:40:27 PM PDT 24
Peak memory 200552 kb
Host smart-26ce6835-0e51-4ec5-85bb-1ec4be44b437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404037976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.404037976
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.79358703
Short name T206
Test name
Test status
Simulation time 162652558198 ps
CPU time 265.47 seconds
Started Jun 24 04:38:27 PM PDT 24
Finished Jun 24 04:43:55 PM PDT 24
Peak memory 200564 kb
Host smart-e3520137-d5c4-4050-8dd8-8f8059f5e04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79358703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.79358703
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.3083701002
Short name T801
Test name
Test status
Simulation time 20734339575 ps
CPU time 34.66 seconds
Started Jun 24 04:38:29 PM PDT 24
Finished Jun 24 04:40:07 PM PDT 24
Peak memory 200568 kb
Host smart-89f4fffd-167c-47f4-9368-bead97dbaf28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083701002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.3083701002
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.137082372
Short name T143
Test name
Test status
Simulation time 46805190032 ps
CPU time 86.02 seconds
Started Jun 24 04:38:33 PM PDT 24
Finished Jun 24 04:41:00 PM PDT 24
Peak memory 200552 kb
Host smart-d649b0e8-6e63-4ffb-b9b6-74ce5c132c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137082372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.137082372
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.2377557709
Short name T1061
Test name
Test status
Simulation time 326411713065 ps
CPU time 323.12 seconds
Started Jun 24 04:38:37 PM PDT 24
Finished Jun 24 04:45:01 PM PDT 24
Peak memory 200636 kb
Host smart-88622d5d-37ac-423c-a668-1d55bb7122ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377557709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.2377557709
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.2871293420
Short name T1091
Test name
Test status
Simulation time 52029224475 ps
CPU time 76.27 seconds
Started Jun 24 04:38:34 PM PDT 24
Finished Jun 24 04:40:53 PM PDT 24
Peak memory 200620 kb
Host smart-8bcd0e46-b171-4201-84f4-bd09e73cc7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871293420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.2871293420
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.3230819446
Short name T347
Test name
Test status
Simulation time 13465531 ps
CPU time 0.57 seconds
Started Jun 24 04:35:55 PM PDT 24
Finished Jun 24 04:36:14 PM PDT 24
Peak memory 195864 kb
Host smart-5f0b8143-7f47-4a1b-83ba-9bb1490cbb8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230819446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.3230819446
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.2651938633
Short name T1040
Test name
Test status
Simulation time 41495941478 ps
CPU time 61.19 seconds
Started Jun 24 04:35:58 PM PDT 24
Finished Jun 24 04:37:20 PM PDT 24
Peak memory 200524 kb
Host smart-64501474-f268-48c6-8066-b9bc98911975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651938633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.2651938633
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_intr.2756073595
Short name T356
Test name
Test status
Simulation time 9109445842 ps
CPU time 5.5 seconds
Started Jun 24 04:35:55 PM PDT 24
Finished Jun 24 04:36:19 PM PDT 24
Peak memory 200460 kb
Host smart-ad1485f4-2954-4dd4-9e5c-2ed311fe3e95
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756073595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.2756073595
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.1873640892
Short name T311
Test name
Test status
Simulation time 86577695562 ps
CPU time 138.81 seconds
Started Jun 24 04:35:54 PM PDT 24
Finished Jun 24 04:38:31 PM PDT 24
Peak memory 200532 kb
Host smart-e5fe41c0-a904-4323-b1b3-0bd038aff5d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1873640892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.1873640892
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.24796227
Short name T796
Test name
Test status
Simulation time 8135154833 ps
CPU time 4.5 seconds
Started Jun 24 04:36:01 PM PDT 24
Finished Jun 24 04:36:26 PM PDT 24
Peak memory 199292 kb
Host smart-785c3eb4-a486-423e-b105-3d9fa74560c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24796227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.24796227
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.2483366071
Short name T980
Test name
Test status
Simulation time 27995549211 ps
CPU time 11.63 seconds
Started Jun 24 04:35:58 PM PDT 24
Finished Jun 24 04:36:29 PM PDT 24
Peak memory 199548 kb
Host smart-3ce949fd-3b82-4c50-9c5a-93b8ce8fb4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483366071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.2483366071
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.3201278467
Short name T863
Test name
Test status
Simulation time 10834672766 ps
CPU time 173.23 seconds
Started Jun 24 04:36:01 PM PDT 24
Finished Jun 24 04:39:15 PM PDT 24
Peak memory 200428 kb
Host smart-175cbd39-90d6-41b9-8cda-3c72f0841133
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3201278467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.3201278467
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.2647760504
Short name T40
Test name
Test status
Simulation time 2934012339 ps
CPU time 18.09 seconds
Started Jun 24 04:36:05 PM PDT 24
Finished Jun 24 04:36:45 PM PDT 24
Peak memory 199448 kb
Host smart-86c6ef6a-5faa-45e4-b078-4d4bcb17072b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2647760504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.2647760504
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.965723693
Short name T395
Test name
Test status
Simulation time 135808219593 ps
CPU time 24.6 seconds
Started Jun 24 04:35:58 PM PDT 24
Finished Jun 24 04:36:43 PM PDT 24
Peak memory 200512 kb
Host smart-1626b83c-b9f4-49a9-a125-a99893d0e40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965723693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.965723693
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.2286492054
Short name T560
Test name
Test status
Simulation time 34108546631 ps
CPU time 45.72 seconds
Started Jun 24 04:35:59 PM PDT 24
Finished Jun 24 04:37:04 PM PDT 24
Peak memory 196608 kb
Host smart-3a1406db-77cf-4a2f-97f3-8f786821201e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286492054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.2286492054
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.2520906251
Short name T1009
Test name
Test status
Simulation time 125344231 ps
CPU time 0.97 seconds
Started Jun 24 04:36:00 PM PDT 24
Finished Jun 24 04:36:22 PM PDT 24
Peak memory 198792 kb
Host smart-4a2a0b9c-732f-48b4-924f-445f5be8df6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520906251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.2520906251
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.247371880
Short name T505
Test name
Test status
Simulation time 6745694606 ps
CPU time 22.29 seconds
Started Jun 24 04:35:56 PM PDT 24
Finished Jun 24 04:36:38 PM PDT 24
Peak memory 200208 kb
Host smart-c272c25f-8f4b-482b-8297-5e892b199be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247371880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.247371880
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.1731842963
Short name T309
Test name
Test status
Simulation time 91373743744 ps
CPU time 27.82 seconds
Started Jun 24 04:36:01 PM PDT 24
Finished Jun 24 04:36:50 PM PDT 24
Peak memory 200516 kb
Host smart-4592cb06-f644-45e1-b83d-3302ada2e9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731842963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.1731842963
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.2296309215
Short name T228
Test name
Test status
Simulation time 26488470464 ps
CPU time 22.43 seconds
Started Jun 24 04:38:32 PM PDT 24
Finished Jun 24 04:39:56 PM PDT 24
Peak memory 200448 kb
Host smart-3296ef14-5e9e-4803-9493-2d5b89ea87a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296309215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.2296309215
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.2836852797
Short name T928
Test name
Test status
Simulation time 65104561420 ps
CPU time 88.96 seconds
Started Jun 24 04:38:33 PM PDT 24
Finished Jun 24 04:41:05 PM PDT 24
Peak memory 200412 kb
Host smart-d59cd538-f047-4975-836f-05995ca4aa50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836852797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.2836852797
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.1332920587
Short name T1057
Test name
Test status
Simulation time 144318475338 ps
CPU time 258.86 seconds
Started Jun 24 04:38:34 PM PDT 24
Finished Jun 24 04:43:56 PM PDT 24
Peak memory 200596 kb
Host smart-ecba7754-8a59-457d-bc4c-652b82be59e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332920587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.1332920587
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.3191078331
Short name T304
Test name
Test status
Simulation time 93789244028 ps
CPU time 32.29 seconds
Started Jun 24 04:38:32 PM PDT 24
Finished Jun 24 04:40:06 PM PDT 24
Peak memory 200524 kb
Host smart-578f4459-d10e-44ca-b4c5-ae21e4833e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191078331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.3191078331
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.3188481892
Short name T215
Test name
Test status
Simulation time 76282369578 ps
CPU time 135.06 seconds
Started Jun 24 04:38:34 PM PDT 24
Finished Jun 24 04:41:52 PM PDT 24
Peak memory 200532 kb
Host smart-e9f0a500-6eb5-400f-bcf9-8e857ae8ee6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188481892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.3188481892
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.3521309374
Short name T853
Test name
Test status
Simulation time 48532568873 ps
CPU time 24.38 seconds
Started Jun 24 04:38:33 PM PDT 24
Finished Jun 24 04:40:01 PM PDT 24
Peak memory 200604 kb
Host smart-b176750a-fd82-449b-9917-caf434e1ba56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521309374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.3521309374
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.2520504498
Short name T695
Test name
Test status
Simulation time 24040465224 ps
CPU time 47.93 seconds
Started Jun 24 04:38:41 PM PDT 24
Finished Jun 24 04:40:32 PM PDT 24
Peak memory 200524 kb
Host smart-7ae6e2bf-6f87-49ff-9f5e-e479b62c6bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520504498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.2520504498
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.3307760554
Short name T219
Test name
Test status
Simulation time 11901317356 ps
CPU time 31.64 seconds
Started Jun 24 04:38:40 PM PDT 24
Finished Jun 24 04:40:15 PM PDT 24
Peak memory 200484 kb
Host smart-54b74840-1597-4ac0-8a84-c7b7ecd49d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307760554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.3307760554
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.2130854440
Short name T870
Test name
Test status
Simulation time 228768756341 ps
CPU time 82.64 seconds
Started Jun 24 04:38:42 PM PDT 24
Finished Jun 24 04:41:07 PM PDT 24
Peak memory 200520 kb
Host smart-9b513ceb-baa5-4c72-be6b-7f52ac7ffa6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130854440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.2130854440
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.3137347859
Short name T1098
Test name
Test status
Simulation time 58118610505 ps
CPU time 37.95 seconds
Started Jun 24 04:38:42 PM PDT 24
Finished Jun 24 04:40:22 PM PDT 24
Peak memory 200456 kb
Host smart-e80cd336-3400-4d0b-b8d4-d66f71f2d300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137347859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.3137347859
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.2715724973
Short name T1053
Test name
Test status
Simulation time 23028966 ps
CPU time 0.57 seconds
Started Jun 24 04:36:02 PM PDT 24
Finished Jun 24 04:36:24 PM PDT 24
Peak memory 195524 kb
Host smart-b872db0c-fe9b-40b2-b0ce-dc176cc504e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715724973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.2715724973
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.4135762436
Short name T141
Test name
Test status
Simulation time 135473693774 ps
CPU time 22.99 seconds
Started Jun 24 04:36:01 PM PDT 24
Finished Jun 24 04:36:45 PM PDT 24
Peak memory 200872 kb
Host smart-9bdfb706-87db-428d-bcc9-046b891901f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135762436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.4135762436
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.1802035496
Short name T186
Test name
Test status
Simulation time 240287105018 ps
CPU time 120.44 seconds
Started Jun 24 04:35:59 PM PDT 24
Finished Jun 24 04:38:19 PM PDT 24
Peak memory 200460 kb
Host smart-ca1b93eb-1a65-497e-81ee-fbadc4348086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802035496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.1802035496
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_intr.3427667039
Short name T981
Test name
Test status
Simulation time 11900365215 ps
CPU time 21.13 seconds
Started Jun 24 04:36:02 PM PDT 24
Finished Jun 24 04:36:43 PM PDT 24
Peak memory 200604 kb
Host smart-57f6ee79-54a6-49df-bc47-f48bcebbb613
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427667039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.3427667039
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.2873287082
Short name T1037
Test name
Test status
Simulation time 138010163327 ps
CPU time 498.74 seconds
Started Jun 24 04:35:58 PM PDT 24
Finished Jun 24 04:44:36 PM PDT 24
Peak memory 200528 kb
Host smart-f2d0f0cc-82b2-47ad-ac98-8a9a4c9ab8f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2873287082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.2873287082
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.2402447914
Short name T811
Test name
Test status
Simulation time 3551835768 ps
CPU time 7.03 seconds
Started Jun 24 04:35:55 PM PDT 24
Finished Jun 24 04:36:21 PM PDT 24
Peak memory 199580 kb
Host smart-91604f58-82e7-4aa1-9396-c99ab11b93c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402447914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.2402447914
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_perf.1536693918
Short name T689
Test name
Test status
Simulation time 505382951 ps
CPU time 6.9 seconds
Started Jun 24 04:35:54 PM PDT 24
Finished Jun 24 04:36:17 PM PDT 24
Peak memory 200536 kb
Host smart-5124b58d-8fa0-4114-aaa0-4dbc33ded632
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1536693918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.1536693918
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.753035668
Short name T828
Test name
Test status
Simulation time 6848538915 ps
CPU time 59.21 seconds
Started Jun 24 04:35:54 PM PDT 24
Finished Jun 24 04:37:12 PM PDT 24
Peak memory 199588 kb
Host smart-a6ad40e2-e829-4497-a5e0-dce8bf5e5b6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=753035668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.753035668
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.4027656850
Short name T917
Test name
Test status
Simulation time 86295490581 ps
CPU time 145.81 seconds
Started Jun 24 04:35:59 PM PDT 24
Finished Jun 24 04:38:46 PM PDT 24
Peak memory 200460 kb
Host smart-e88cad95-b2ff-4c9b-a129-098e24d06eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027656850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.4027656850
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.229783177
Short name T390
Test name
Test status
Simulation time 654707935 ps
CPU time 1.16 seconds
Started Jun 24 04:36:00 PM PDT 24
Finished Jun 24 04:36:23 PM PDT 24
Peak memory 195920 kb
Host smart-df9c2955-c81d-42ae-9a83-ab8dc79bc091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229783177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.229783177
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.759459568
Short name T1042
Test name
Test status
Simulation time 265355234 ps
CPU time 1.07 seconds
Started Jun 24 04:35:59 PM PDT 24
Finished Jun 24 04:36:20 PM PDT 24
Peak memory 198992 kb
Host smart-9e0d23bc-ca17-482c-a8c2-f061a6ffc60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759459568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.759459568
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.1153137180
Short name T1013
Test name
Test status
Simulation time 74255200989 ps
CPU time 1205.95 seconds
Started Jun 24 04:36:03 PM PDT 24
Finished Jun 24 04:56:30 PM PDT 24
Peak memory 217076 kb
Host smart-6c9d7722-d86b-4f8b-a172-a4b18b0ecca5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153137180 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.1153137180
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.3835798217
Short name T535
Test name
Test status
Simulation time 1045159080 ps
CPU time 1.65 seconds
Started Jun 24 04:36:03 PM PDT 24
Finished Jun 24 04:36:27 PM PDT 24
Peak memory 199312 kb
Host smart-2bc47252-df14-44b0-b204-54842595f54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835798217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.3835798217
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.3980356576
Short name T1014
Test name
Test status
Simulation time 612805136 ps
CPU time 1.62 seconds
Started Jun 24 04:35:57 PM PDT 24
Finished Jun 24 04:36:17 PM PDT 24
Peak memory 197688 kb
Host smart-ab239078-5f7a-4c98-9b62-bb0a36d2e0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980356576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.3980356576
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.2353109130
Short name T893
Test name
Test status
Simulation time 146319745269 ps
CPU time 128.35 seconds
Started Jun 24 04:38:40 PM PDT 24
Finished Jun 24 04:41:51 PM PDT 24
Peak memory 200464 kb
Host smart-04c5229a-7a8e-4a15-b35d-51e02d15003a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353109130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.2353109130
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.1229086673
Short name T481
Test name
Test status
Simulation time 22499690345 ps
CPU time 51.65 seconds
Started Jun 24 04:38:42 PM PDT 24
Finished Jun 24 04:40:36 PM PDT 24
Peak memory 200532 kb
Host smart-f8a451b7-14c3-4e59-b6b9-ae4d3a328367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229086673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.1229086673
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.2752724332
Short name T775
Test name
Test status
Simulation time 189878975409 ps
CPU time 21.61 seconds
Started Jun 24 04:38:43 PM PDT 24
Finished Jun 24 04:40:06 PM PDT 24
Peak memory 200544 kb
Host smart-f07e1f8c-6ea4-4740-94f7-514db861cf49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752724332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.2752724332
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.2665429103
Short name T749
Test name
Test status
Simulation time 47269551722 ps
CPU time 82.35 seconds
Started Jun 24 04:38:40 PM PDT 24
Finished Jun 24 04:41:05 PM PDT 24
Peak memory 200544 kb
Host smart-8893b112-5e6a-4bbd-b91d-3503510a0707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665429103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.2665429103
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.1225175375
Short name T223
Test name
Test status
Simulation time 81970828782 ps
CPU time 122.83 seconds
Started Jun 24 04:38:42 PM PDT 24
Finished Jun 24 04:41:47 PM PDT 24
Peak memory 200500 kb
Host smart-6daabd1a-2eff-4886-90cf-f11923cad167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225175375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.1225175375
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.3153877145
Short name T869
Test name
Test status
Simulation time 117050613621 ps
CPU time 193.96 seconds
Started Jun 24 04:38:41 PM PDT 24
Finished Jun 24 04:42:57 PM PDT 24
Peak memory 200588 kb
Host smart-568d55d3-c10f-447e-a915-e71de1363e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153877145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.3153877145
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.3082362873
Short name T931
Test name
Test status
Simulation time 18423867279 ps
CPU time 30.55 seconds
Started Jun 24 04:38:41 PM PDT 24
Finished Jun 24 04:40:14 PM PDT 24
Peak memory 200464 kb
Host smart-f1b772b1-6d22-4c0e-bb99-84e3c97ff1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082362873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.3082362873
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.1190891477
Short name T78
Test name
Test status
Simulation time 109721265132 ps
CPU time 148.19 seconds
Started Jun 24 04:38:40 PM PDT 24
Finished Jun 24 04:42:11 PM PDT 24
Peak memory 200480 kb
Host smart-8a666977-373d-4792-90ae-d1b8ad256aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190891477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.1190891477
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.998779277
Short name T885
Test name
Test status
Simulation time 46368684273 ps
CPU time 36.09 seconds
Started Jun 24 04:38:42 PM PDT 24
Finished Jun 24 04:40:20 PM PDT 24
Peak memory 200440 kb
Host smart-1895463c-f1e8-4d0d-ad75-0e1f76f35d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998779277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.998779277
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.1026586992
Short name T423
Test name
Test status
Simulation time 42349169 ps
CPU time 0.54 seconds
Started Jun 24 04:36:02 PM PDT 24
Finished Jun 24 04:36:22 PM PDT 24
Peak memory 195960 kb
Host smart-5d9959e1-08d2-4508-be7b-92241f59f0ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026586992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.1026586992
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.1007645149
Short name T298
Test name
Test status
Simulation time 43591125218 ps
CPU time 37.92 seconds
Started Jun 24 04:36:05 PM PDT 24
Finished Jun 24 04:37:03 PM PDT 24
Peak memory 200516 kb
Host smart-1f31fece-abcc-4e7b-80b1-f10f0277e5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007645149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.1007645149
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.3618862223
Short name T777
Test name
Test status
Simulation time 21797169299 ps
CPU time 29.53 seconds
Started Jun 24 04:36:02 PM PDT 24
Finished Jun 24 04:36:51 PM PDT 24
Peak memory 200272 kb
Host smart-3347e5c6-35e6-428f-b499-9ed0ad5cd523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618862223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.3618862223
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.1998671305
Short name T36
Test name
Test status
Simulation time 20369758244 ps
CPU time 11.46 seconds
Started Jun 24 04:36:06 PM PDT 24
Finished Jun 24 04:36:39 PM PDT 24
Peak memory 200576 kb
Host smart-d71700bd-3531-4e07-bca8-16061b61af41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998671305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.1998671305
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.2887393502
Short name T268
Test name
Test status
Simulation time 31107439882 ps
CPU time 10.69 seconds
Started Jun 24 04:36:04 PM PDT 24
Finished Jun 24 04:36:36 PM PDT 24
Peak memory 199648 kb
Host smart-07ad1d4d-5543-42d8-a74c-c5d307af7860
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887393502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.2887393502
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.1365218617
Short name T603
Test name
Test status
Simulation time 143708387081 ps
CPU time 1093.65 seconds
Started Jun 24 04:36:05 PM PDT 24
Finished Jun 24 04:54:41 PM PDT 24
Peak memory 200512 kb
Host smart-f659518d-9a99-45ad-bb1f-665b0305f924
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1365218617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.1365218617
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.3712738615
Short name T342
Test name
Test status
Simulation time 1772808913 ps
CPU time 2.72 seconds
Started Jun 24 04:36:02 PM PDT 24
Finished Jun 24 04:36:26 PM PDT 24
Peak memory 198608 kb
Host smart-242724ad-c036-4a22-bfd5-d8b1c191acc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712738615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.3712738615
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_perf.4020634233
Short name T925
Test name
Test status
Simulation time 11229164228 ps
CPU time 137.02 seconds
Started Jun 24 04:36:04 PM PDT 24
Finished Jun 24 04:38:42 PM PDT 24
Peak memory 200412 kb
Host smart-6a441ded-bc08-4ae7-a818-964727e66aab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4020634233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.4020634233
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.3709665424
Short name T605
Test name
Test status
Simulation time 2528366898 ps
CPU time 8.02 seconds
Started Jun 24 04:36:01 PM PDT 24
Finished Jun 24 04:36:30 PM PDT 24
Peak memory 199732 kb
Host smart-d688d89f-96f4-4077-9518-d60c4bb43ca7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3709665424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.3709665424
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.1701303616
Short name T181
Test name
Test status
Simulation time 178088701854 ps
CPU time 75.13 seconds
Started Jun 24 04:36:00 PM PDT 24
Finished Jun 24 04:37:37 PM PDT 24
Peak memory 200536 kb
Host smart-11f2e4ba-7721-40c1-b02b-3af40f52781c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701303616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.1701303616
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.583448301
Short name T322
Test name
Test status
Simulation time 39367399096 ps
CPU time 32.49 seconds
Started Jun 24 04:36:03 PM PDT 24
Finished Jun 24 04:36:56 PM PDT 24
Peak memory 196836 kb
Host smart-23e4d0ee-c603-44a9-9645-4aee1d278d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583448301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.583448301
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.1911494974
Short name T295
Test name
Test status
Simulation time 278341009 ps
CPU time 1.03 seconds
Started Jun 24 04:36:02 PM PDT 24
Finished Jun 24 04:36:24 PM PDT 24
Peak memory 199252 kb
Host smart-40cf3213-aaa8-40e2-ba82-a5525d77da13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911494974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.1911494974
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.4249218747
Short name T443
Test name
Test status
Simulation time 1581317556 ps
CPU time 4.08 seconds
Started Jun 24 04:36:06 PM PDT 24
Finished Jun 24 04:36:32 PM PDT 24
Peak memory 199264 kb
Host smart-343f6663-c745-4acf-8511-8291ce78c003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249218747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.4249218747
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.1733452566
Short name T851
Test name
Test status
Simulation time 15582091398 ps
CPU time 23.66 seconds
Started Jun 24 04:36:02 PM PDT 24
Finished Jun 24 04:36:46 PM PDT 24
Peak memory 200532 kb
Host smart-ef4101ed-ea9f-431f-b52d-eabe7eed9ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733452566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.1733452566
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.1920103185
Short name T908
Test name
Test status
Simulation time 74058644494 ps
CPU time 181.36 seconds
Started Jun 24 04:38:42 PM PDT 24
Finished Jun 24 04:42:45 PM PDT 24
Peak memory 200756 kb
Host smart-51f9efe2-c55f-4abc-8b08-1fc0d393a8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920103185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.1920103185
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.3667019369
Short name T211
Test name
Test status
Simulation time 22371465358 ps
CPU time 18.51 seconds
Started Jun 24 04:38:41 PM PDT 24
Finished Jun 24 04:40:02 PM PDT 24
Peak memory 200464 kb
Host smart-462513e9-6631-4caf-86ce-4aafb5f9b4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667019369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.3667019369
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.220202343
Short name T537
Test name
Test status
Simulation time 36989072982 ps
CPU time 20.9 seconds
Started Jun 24 04:38:41 PM PDT 24
Finished Jun 24 04:40:04 PM PDT 24
Peak memory 200484 kb
Host smart-1838240b-2e71-472f-930e-dd1545efd7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220202343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.220202343
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.3400747480
Short name T752
Test name
Test status
Simulation time 16422156623 ps
CPU time 27.11 seconds
Started Jun 24 04:38:41 PM PDT 24
Finished Jun 24 04:40:11 PM PDT 24
Peak memory 200560 kb
Host smart-178d35e3-f0d3-4c95-9a22-ab1eba8b03ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400747480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.3400747480
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.279149973
Short name T940
Test name
Test status
Simulation time 16576478127 ps
CPU time 25.08 seconds
Started Jun 24 04:38:41 PM PDT 24
Finished Jun 24 04:40:08 PM PDT 24
Peak memory 200456 kb
Host smart-50cf0920-bb3c-40af-9564-7de73e797a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279149973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.279149973
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.3550692811
Short name T153
Test name
Test status
Simulation time 19122559193 ps
CPU time 29.55 seconds
Started Jun 24 04:38:40 PM PDT 24
Finished Jun 24 04:40:12 PM PDT 24
Peak memory 200444 kb
Host smart-ea165873-0774-4460-94ea-8832bf452408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550692811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.3550692811
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.2659449423
Short name T168
Test name
Test status
Simulation time 78561190472 ps
CPU time 70.66 seconds
Started Jun 24 04:38:42 PM PDT 24
Finished Jun 24 04:40:55 PM PDT 24
Peak memory 200524 kb
Host smart-363080e3-eb92-449f-9480-8dae720b9dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659449423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.2659449423
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.3361700493
Short name T1015
Test name
Test status
Simulation time 99045880689 ps
CPU time 80.58 seconds
Started Jun 24 04:38:40 PM PDT 24
Finished Jun 24 04:41:04 PM PDT 24
Peak memory 200584 kb
Host smart-7483dc16-bc4b-482e-b1a7-1113d37bf857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361700493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.3361700493
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.3026791099
Short name T834
Test name
Test status
Simulation time 92938757109 ps
CPU time 35.15 seconds
Started Jun 24 04:38:41 PM PDT 24
Finished Jun 24 04:40:18 PM PDT 24
Peak memory 200524 kb
Host smart-2c476e44-70ad-4b37-8f58-8e056c043122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026791099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.3026791099
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.4224528691
Short name T897
Test name
Test status
Simulation time 17354103 ps
CPU time 0.56 seconds
Started Jun 24 04:36:05 PM PDT 24
Finished Jun 24 04:36:26 PM PDT 24
Peak memory 195332 kb
Host smart-6bbf0be3-a72c-4111-b307-478b7be6aaf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224528691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.4224528691
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.4218441891
Short name T629
Test name
Test status
Simulation time 165751374134 ps
CPU time 222.33 seconds
Started Jun 24 04:36:07 PM PDT 24
Finished Jun 24 04:40:10 PM PDT 24
Peak memory 200548 kb
Host smart-756fd337-4835-4fe6-beb0-197cd7ae6dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218441891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.4218441891
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.3510902929
Short name T922
Test name
Test status
Simulation time 53576339067 ps
CPU time 78.03 seconds
Started Jun 24 04:36:06 PM PDT 24
Finished Jun 24 04:37:46 PM PDT 24
Peak memory 200344 kb
Host smart-a91c374d-e769-439e-b54b-9d4ba1b52db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510902929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.3510902929
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.2611478789
Short name T827
Test name
Test status
Simulation time 12795729772 ps
CPU time 21.62 seconds
Started Jun 24 04:36:04 PM PDT 24
Finished Jun 24 04:36:47 PM PDT 24
Peak memory 200620 kb
Host smart-505e4ffe-ab57-40a3-b304-9ad94e07cbc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611478789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.2611478789
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.1816458521
Short name T848
Test name
Test status
Simulation time 222680381492 ps
CPU time 249.43 seconds
Started Jun 24 04:36:02 PM PDT 24
Finished Jun 24 04:40:31 PM PDT 24
Peak memory 199908 kb
Host smart-89c3818e-e7d7-47e2-a087-58fbe9c407d7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816458521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.1816458521
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.230507512
Short name T266
Test name
Test status
Simulation time 64285277474 ps
CPU time 542.56 seconds
Started Jun 24 04:36:08 PM PDT 24
Finished Jun 24 04:45:31 PM PDT 24
Peak memory 200416 kb
Host smart-76e835b7-4f5d-401b-a721-b08ad675c8d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=230507512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.230507512
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.1008536263
Short name T418
Test name
Test status
Simulation time 6086724932 ps
CPU time 4.29 seconds
Started Jun 24 04:36:06 PM PDT 24
Finished Jun 24 04:36:32 PM PDT 24
Peak memory 200420 kb
Host smart-00d07045-6380-4582-bc72-bdf551066d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008536263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.1008536263
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_perf.2250425668
Short name T741
Test name
Test status
Simulation time 19519297121 ps
CPU time 240.72 seconds
Started Jun 24 04:36:06 PM PDT 24
Finished Jun 24 04:40:28 PM PDT 24
Peak memory 200500 kb
Host smart-87352d40-af3b-4944-9a00-0443cbfa0634
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2250425668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.2250425668
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.210847944
Short name T841
Test name
Test status
Simulation time 6694947035 ps
CPU time 10.83 seconds
Started Jun 24 04:36:01 PM PDT 24
Finished Jun 24 04:36:33 PM PDT 24
Peak memory 199348 kb
Host smart-b0af5508-d818-467e-9ddc-19d00c50fc3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=210847944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.210847944
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.3422260318
Short name T182
Test name
Test status
Simulation time 12854193881 ps
CPU time 22.43 seconds
Started Jun 24 04:36:05 PM PDT 24
Finished Jun 24 04:36:49 PM PDT 24
Peak memory 200320 kb
Host smart-de2e853f-a656-43e8-a913-4378b4fdff84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422260318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.3422260318
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.2002316992
Short name T888
Test name
Test status
Simulation time 2939567927 ps
CPU time 5.05 seconds
Started Jun 24 04:36:03 PM PDT 24
Finished Jun 24 04:36:29 PM PDT 24
Peak memory 196372 kb
Host smart-082520b8-2595-4e5a-aac6-6ed0b4a738ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002316992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.2002316992
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.2748875990
Short name T932
Test name
Test status
Simulation time 5679973489 ps
CPU time 10.63 seconds
Started Jun 24 04:36:03 PM PDT 24
Finished Jun 24 04:36:34 PM PDT 24
Peak memory 200268 kb
Host smart-6a07a201-ad42-4efc-9ab2-e4916e1b383e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748875990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.2748875990
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.1481967987
Short name T892
Test name
Test status
Simulation time 55301404067 ps
CPU time 107.51 seconds
Started Jun 24 04:35:59 PM PDT 24
Finished Jun 24 04:38:06 PM PDT 24
Peak memory 200444 kb
Host smart-dcc56f43-31bc-47c0-b0a6-9c128f53278f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481967987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.1481967987
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.3045154858
Short name T1058
Test name
Test status
Simulation time 269312724651 ps
CPU time 418.54 seconds
Started Jun 24 04:36:04 PM PDT 24
Finished Jun 24 04:43:24 PM PDT 24
Peak memory 216976 kb
Host smart-8efc1455-f285-4c3d-b932-cd4f99f3eb22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045154858 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.3045154858
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.2854435942
Short name T842
Test name
Test status
Simulation time 629317960 ps
CPU time 2.33 seconds
Started Jun 24 04:36:03 PM PDT 24
Finished Jun 24 04:36:26 PM PDT 24
Peak memory 199524 kb
Host smart-764bbb18-a5c9-4306-a203-d625529404ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854435942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.2854435942
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.2947700605
Short name T459
Test name
Test status
Simulation time 25552373936 ps
CPU time 39.85 seconds
Started Jun 24 04:36:05 PM PDT 24
Finished Jun 24 04:37:07 PM PDT 24
Peak memory 200468 kb
Host smart-55d948dd-938a-43e7-ba17-3c59c1c4faad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947700605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.2947700605
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.2648861488
Short name T979
Test name
Test status
Simulation time 50020615206 ps
CPU time 17.53 seconds
Started Jun 24 04:38:39 PM PDT 24
Finished Jun 24 04:40:00 PM PDT 24
Peak memory 200544 kb
Host smart-860e2764-5a25-46b1-9748-02e833ed2b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648861488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.2648861488
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.1350879948
Short name T854
Test name
Test status
Simulation time 21543425673 ps
CPU time 34.55 seconds
Started Jun 24 04:38:41 PM PDT 24
Finished Jun 24 04:40:18 PM PDT 24
Peak memory 200524 kb
Host smart-ae15ac9f-088e-4154-9874-5f5eb4bc624b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350879948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.1350879948
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.3921472452
Short name T1021
Test name
Test status
Simulation time 175773035920 ps
CPU time 267.15 seconds
Started Jun 24 04:38:42 PM PDT 24
Finished Jun 24 04:44:11 PM PDT 24
Peak memory 200580 kb
Host smart-985cb56c-ec40-4e73-9fbc-bd5fbbfe79fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921472452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.3921472452
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.2412150397
Short name T188
Test name
Test status
Simulation time 47261496810 ps
CPU time 27.93 seconds
Started Jun 24 04:38:50 PM PDT 24
Finished Jun 24 04:40:19 PM PDT 24
Peak memory 200572 kb
Host smart-0c45f5e2-27bb-4211-9b3a-5d130f0943dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412150397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.2412150397
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.1570651707
Short name T233
Test name
Test status
Simulation time 50262767111 ps
CPU time 39.42 seconds
Started Jun 24 04:38:47 PM PDT 24
Finished Jun 24 04:40:28 PM PDT 24
Peak memory 200420 kb
Host smart-43f55095-7c81-45c2-9edf-ffb6dc347e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570651707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.1570651707
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.3694587048
Short name T337
Test name
Test status
Simulation time 71961430333 ps
CPU time 140.8 seconds
Started Jun 24 04:38:48 PM PDT 24
Finished Jun 24 04:42:09 PM PDT 24
Peak memory 200604 kb
Host smart-7ecf1d66-0164-47ec-9257-b03a756a8327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694587048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.3694587048
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.3555889020
Short name T878
Test name
Test status
Simulation time 82306472130 ps
CPU time 74.24 seconds
Started Jun 24 04:38:49 PM PDT 24
Finished Jun 24 04:41:03 PM PDT 24
Peak memory 200532 kb
Host smart-213b222d-0826-4487-beca-7324d4a7eaf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555889020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.3555889020
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.1791142296
Short name T130
Test name
Test status
Simulation time 131119847206 ps
CPU time 47.05 seconds
Started Jun 24 04:38:46 PM PDT 24
Finished Jun 24 04:40:35 PM PDT 24
Peak memory 200444 kb
Host smart-8a4d2053-95f2-40a6-8c38-067a3ca7b230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791142296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.1791142296
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.2278091568
Short name T733
Test name
Test status
Simulation time 42558490 ps
CPU time 0.55 seconds
Started Jun 24 04:36:10 PM PDT 24
Finished Jun 24 04:36:30 PM PDT 24
Peak memory 196264 kb
Host smart-eab713fa-b118-4d57-9e55-a40ff6190f2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278091568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.2278091568
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.1252927312
Short name T8
Test name
Test status
Simulation time 99768712807 ps
CPU time 38.03 seconds
Started Jun 24 04:36:11 PM PDT 24
Finished Jun 24 04:37:09 PM PDT 24
Peak memory 200520 kb
Host smart-48f6bf6f-dd37-4282-8ba7-94cf4f09fd65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252927312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.1252927312
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.2663464139
Short name T176
Test name
Test status
Simulation time 155390077384 ps
CPU time 59.89 seconds
Started Jun 24 04:36:01 PM PDT 24
Finished Jun 24 04:37:22 PM PDT 24
Peak memory 200604 kb
Host smart-275d9735-346b-4572-b604-71d3e089ce2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663464139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.2663464139
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.2486335707
Short name T1073
Test name
Test status
Simulation time 115545287967 ps
CPU time 50.23 seconds
Started Jun 24 04:36:00 PM PDT 24
Finished Jun 24 04:37:11 PM PDT 24
Peak memory 200488 kb
Host smart-cf692b8d-46b1-489b-83a5-6cd9e5e9ff59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486335707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.2486335707
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.1318290493
Short name T945
Test name
Test status
Simulation time 4508514141 ps
CPU time 5.08 seconds
Started Jun 24 04:36:07 PM PDT 24
Finished Jun 24 04:36:33 PM PDT 24
Peak memory 200488 kb
Host smart-4fafa904-5c17-4ff5-9c26-1b7f6e3444a9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318290493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.1318290493
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.653798651
Short name T1002
Test name
Test status
Simulation time 182078133499 ps
CPU time 314.51 seconds
Started Jun 24 04:36:07 PM PDT 24
Finished Jun 24 04:41:43 PM PDT 24
Peak memory 200528 kb
Host smart-8b95f961-25ce-4d6e-8d19-43a005752607
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=653798651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.653798651
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.1819541657
Short name T403
Test name
Test status
Simulation time 5351600752 ps
CPU time 9.58 seconds
Started Jun 24 04:36:01 PM PDT 24
Finished Jun 24 04:36:31 PM PDT 24
Peak memory 199128 kb
Host smart-ad8b5a38-2009-4fd9-bfbc-dfa0907c9bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819541657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.1819541657
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_perf.2803004749
Short name T816
Test name
Test status
Simulation time 11388096937 ps
CPU time 624.35 seconds
Started Jun 24 04:36:01 PM PDT 24
Finished Jun 24 04:46:46 PM PDT 24
Peak memory 200844 kb
Host smart-8e09c475-fd17-4be6-b5d7-8002d8515443
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2803004749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.2803004749
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.4048157482
Short name T911
Test name
Test status
Simulation time 6325634273 ps
CPU time 3.31 seconds
Started Jun 24 04:36:06 PM PDT 24
Finished Jun 24 04:36:31 PM PDT 24
Peak memory 199884 kb
Host smart-80eeae60-70dc-451f-b2d6-a29d2f364fb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4048157482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.4048157482
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.3851411210
Short name T559
Test name
Test status
Simulation time 41186134976 ps
CPU time 35.84 seconds
Started Jun 24 04:36:05 PM PDT 24
Finished Jun 24 04:37:04 PM PDT 24
Peak memory 200524 kb
Host smart-e744c29d-7ac1-493d-8cc5-f690b467b655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851411210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.3851411210
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.263130410
Short name T844
Test name
Test status
Simulation time 2625582897 ps
CPU time 1.82 seconds
Started Jun 24 04:36:00 PM PDT 24
Finished Jun 24 04:36:22 PM PDT 24
Peak memory 196216 kb
Host smart-a8444d45-e95e-454b-8812-812e7be3c1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263130410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.263130410
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.2490549393
Short name T411
Test name
Test status
Simulation time 503190531 ps
CPU time 1.21 seconds
Started Jun 24 04:36:02 PM PDT 24
Finished Jun 24 04:36:23 PM PDT 24
Peak memory 199200 kb
Host smart-fc009fda-70be-4d9d-bf70-fc72f454bb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490549393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.2490549393
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.2526392835
Short name T156
Test name
Test status
Simulation time 44405306504 ps
CPU time 20.97 seconds
Started Jun 24 04:36:05 PM PDT 24
Finished Jun 24 04:36:49 PM PDT 24
Peak memory 200584 kb
Host smart-7d5c678c-42d5-4084-b9fd-7c67422f3b12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526392835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.2526392835
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.3748737462
Short name T57
Test name
Test status
Simulation time 26870457173 ps
CPU time 222.75 seconds
Started Jun 24 04:36:08 PM PDT 24
Finished Jun 24 04:40:11 PM PDT 24
Peak memory 216528 kb
Host smart-1d971f4f-ce02-465c-913d-afcd362e86a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748737462 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.3748737462
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.1209448233
Short name T425
Test name
Test status
Simulation time 570973512 ps
CPU time 1.52 seconds
Started Jun 24 04:36:03 PM PDT 24
Finished Jun 24 04:36:27 PM PDT 24
Peak memory 199304 kb
Host smart-83dee1ae-4e2e-4b28-ad25-8249285d7c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209448233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.1209448233
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.4055788715
Short name T328
Test name
Test status
Simulation time 11082038084 ps
CPU time 9.19 seconds
Started Jun 24 04:36:06 PM PDT 24
Finished Jun 24 04:36:37 PM PDT 24
Peak memory 197556 kb
Host smart-c1d1630f-b4af-4987-86c1-a9e38f1b00d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055788715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.4055788715
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.1531703476
Short name T934
Test name
Test status
Simulation time 38190577861 ps
CPU time 26.94 seconds
Started Jun 24 04:38:46 PM PDT 24
Finished Jun 24 04:40:15 PM PDT 24
Peak memory 200492 kb
Host smart-6a9a4b86-be99-479b-9827-860fc90196ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531703476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.1531703476
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.1515640849
Short name T190
Test name
Test status
Simulation time 80241237504 ps
CPU time 106.48 seconds
Started Jun 24 04:38:49 PM PDT 24
Finished Jun 24 04:41:36 PM PDT 24
Peak memory 200532 kb
Host smart-21adeb41-2571-4a0c-b814-4f2b139951fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515640849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.1515640849
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.2170705674
Short name T1055
Test name
Test status
Simulation time 22575340019 ps
CPU time 43.08 seconds
Started Jun 24 04:38:48 PM PDT 24
Finished Jun 24 04:40:32 PM PDT 24
Peak memory 200544 kb
Host smart-2d4201f2-d057-4769-b38f-6fab17f0036f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170705674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.2170705674
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.495007551
Short name T709
Test name
Test status
Simulation time 286892560474 ps
CPU time 543.76 seconds
Started Jun 24 04:38:47 PM PDT 24
Finished Jun 24 04:48:52 PM PDT 24
Peak memory 200488 kb
Host smart-eb19b579-deb4-435c-9ddb-285b24c6cd08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495007551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.495007551
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.2332224256
Short name T740
Test name
Test status
Simulation time 103263136444 ps
CPU time 50.81 seconds
Started Jun 24 04:38:48 PM PDT 24
Finished Jun 24 04:40:39 PM PDT 24
Peak memory 200484 kb
Host smart-367f0fc1-5312-4c2c-b373-3a17fae1fe71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332224256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.2332224256
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.198250696
Short name T204
Test name
Test status
Simulation time 49687571762 ps
CPU time 79.69 seconds
Started Jun 24 04:38:47 PM PDT 24
Finished Jun 24 04:41:08 PM PDT 24
Peak memory 200556 kb
Host smart-e8b09781-f245-4564-99f3-8839c3a2cad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198250696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.198250696
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.1792786929
Short name T692
Test name
Test status
Simulation time 58018476376 ps
CPU time 94.67 seconds
Started Jun 24 04:38:50 PM PDT 24
Finished Jun 24 04:41:25 PM PDT 24
Peak memory 200500 kb
Host smart-210febcf-cb44-4598-86d8-8dda31083dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792786929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.1792786929
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.1654445151
Short name T478
Test name
Test status
Simulation time 38780271869 ps
CPU time 56.67 seconds
Started Jun 24 04:38:47 PM PDT 24
Finished Jun 24 04:40:45 PM PDT 24
Peak memory 200448 kb
Host smart-9fb3dd0a-6ec6-4c96-b30f-b1912bc1d876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654445151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.1654445151
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.20550510
Short name T930
Test name
Test status
Simulation time 18753148039 ps
CPU time 15.81 seconds
Started Jun 24 04:38:46 PM PDT 24
Finished Jun 24 04:40:04 PM PDT 24
Peak memory 199872 kb
Host smart-d27202b3-f1d9-4b44-ba8f-a699408355d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20550510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.20550510
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.2729554465
Short name T517
Test name
Test status
Simulation time 25990592 ps
CPU time 0.56 seconds
Started Jun 24 04:36:07 PM PDT 24
Finished Jun 24 04:36:29 PM PDT 24
Peak memory 195856 kb
Host smart-9df23e20-a13e-4918-9c82-84dde29f4753
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729554465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.2729554465
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.3922642845
Short name T1043
Test name
Test status
Simulation time 135415080558 ps
CPU time 69.65 seconds
Started Jun 24 04:36:07 PM PDT 24
Finished Jun 24 04:37:37 PM PDT 24
Peak memory 200576 kb
Host smart-273acee2-f8f9-4b20-9a49-5abc29e1cbed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922642845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.3922642845
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.2512852849
Short name T424
Test name
Test status
Simulation time 58072786576 ps
CPU time 28.65 seconds
Started Jun 24 04:36:07 PM PDT 24
Finished Jun 24 04:36:57 PM PDT 24
Peak memory 200536 kb
Host smart-4c5f5d48-fc52-461c-a1fd-d6f108a1d549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512852849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.2512852849
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.2272598149
Short name T193
Test name
Test status
Simulation time 113462519600 ps
CPU time 41.99 seconds
Started Jun 24 04:36:03 PM PDT 24
Finished Jun 24 04:37:06 PM PDT 24
Peak memory 200528 kb
Host smart-5b224cf2-4bac-4caf-bdb9-624b7546cf8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272598149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.2272598149
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.503920752
Short name T736
Test name
Test status
Simulation time 47140855684 ps
CPU time 17.78 seconds
Started Jun 24 04:36:10 PM PDT 24
Finished Jun 24 04:36:49 PM PDT 24
Peak memory 200500 kb
Host smart-684ce5e7-c6b1-4fac-a337-81e7e6fd15ad
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503920752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.503920752
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.3988863133
Short name T992
Test name
Test status
Simulation time 41899379566 ps
CPU time 403.51 seconds
Started Jun 24 04:36:08 PM PDT 24
Finished Jun 24 04:43:12 PM PDT 24
Peak memory 200476 kb
Host smart-c7633acd-e962-4cef-905c-912c8b69e599
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3988863133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.3988863133
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.1568263653
Short name T1031
Test name
Test status
Simulation time 3500585267 ps
CPU time 6.26 seconds
Started Jun 24 04:36:13 PM PDT 24
Finished Jun 24 04:36:39 PM PDT 24
Peak memory 200128 kb
Host smart-22ea2ed1-77c7-4a23-9752-a96302157677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568263653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.1568263653
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_perf.29807755
Short name T416
Test name
Test status
Simulation time 3025821384 ps
CPU time 34.9 seconds
Started Jun 24 04:36:06 PM PDT 24
Finished Jun 24 04:37:03 PM PDT 24
Peak memory 200492 kb
Host smart-03ed6df5-05ae-4119-98dd-52cf83980a98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=29807755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.29807755
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.2729132430
Short name T393
Test name
Test status
Simulation time 2543723467 ps
CPU time 9.1 seconds
Started Jun 24 04:36:01 PM PDT 24
Finished Jun 24 04:36:31 PM PDT 24
Peak memory 199528 kb
Host smart-cdc9d095-cb80-483d-8100-40045e08713b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2729132430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.2729132430
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.3178837940
Short name T823
Test name
Test status
Simulation time 37170387538 ps
CPU time 60.94 seconds
Started Jun 24 04:36:11 PM PDT 24
Finished Jun 24 04:37:32 PM PDT 24
Peak memory 200524 kb
Host smart-bc5510f7-fca2-4d9e-8d83-bbe87abfed7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178837940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.3178837940
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.4081063466
Short name T489
Test name
Test status
Simulation time 1673433266 ps
CPU time 3.52 seconds
Started Jun 24 04:36:09 PM PDT 24
Finished Jun 24 04:36:33 PM PDT 24
Peak memory 196004 kb
Host smart-2d5664d5-28cd-47ac-bf99-f83328554ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081063466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.4081063466
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.176878589
Short name T98
Test name
Test status
Simulation time 543151905 ps
CPU time 1.43 seconds
Started Jun 24 04:36:01 PM PDT 24
Finished Jun 24 04:36:23 PM PDT 24
Peak memory 198988 kb
Host smart-81c8e383-7f0d-4f33-a2b1-a068a3e4485b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176878589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.176878589
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.988024381
Short name T292
Test name
Test status
Simulation time 5258697814 ps
CPU time 2.09 seconds
Started Jun 24 04:36:07 PM PDT 24
Finished Jun 24 04:36:31 PM PDT 24
Peak memory 199048 kb
Host smart-6d38d88d-16bb-4742-80bb-cb065c02f2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988024381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.988024381
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.3263020982
Short name T422
Test name
Test status
Simulation time 121504004395 ps
CPU time 86.31 seconds
Started Jun 24 04:36:02 PM PDT 24
Finished Jun 24 04:37:50 PM PDT 24
Peak memory 200612 kb
Host smart-4690527c-33bb-45c6-8ace-989757371000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263020982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.3263020982
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.1669369647
Short name T338
Test name
Test status
Simulation time 76435129278 ps
CPU time 55.84 seconds
Started Jun 24 04:38:47 PM PDT 24
Finished Jun 24 04:40:44 PM PDT 24
Peak memory 200636 kb
Host smart-46b86453-d72c-4611-adfa-596831b91dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669369647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.1669369647
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.3200073227
Short name T941
Test name
Test status
Simulation time 112797232275 ps
CPU time 338.41 seconds
Started Jun 24 04:38:48 PM PDT 24
Finished Jun 24 04:45:27 PM PDT 24
Peak memory 200572 kb
Host smart-ff16228b-5903-40f2-b4cd-fe85e49239e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200073227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.3200073227
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.2084514453
Short name T807
Test name
Test status
Simulation time 143091234661 ps
CPU time 47.25 seconds
Started Jun 24 04:38:46 PM PDT 24
Finished Jun 24 04:40:35 PM PDT 24
Peak memory 200568 kb
Host smart-d108ac42-44fa-496e-b314-dc742fb4ea25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084514453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.2084514453
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.2157146695
Short name T991
Test name
Test status
Simulation time 91067327022 ps
CPU time 36.74 seconds
Started Jun 24 04:38:52 PM PDT 24
Finished Jun 24 04:40:28 PM PDT 24
Peak memory 200460 kb
Host smart-96df792a-c89f-484b-806b-83e2c374f142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157146695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.2157146695
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.48767352
Short name T191
Test name
Test status
Simulation time 185243963037 ps
CPU time 43.55 seconds
Started Jun 24 04:38:53 PM PDT 24
Finished Jun 24 04:40:34 PM PDT 24
Peak memory 200516 kb
Host smart-e49a7243-ebcb-4600-b694-8c93056ab004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48767352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.48767352
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.2527500889
Short name T164
Test name
Test status
Simulation time 55281558576 ps
CPU time 88.9 seconds
Started Jun 24 04:38:54 PM PDT 24
Finished Jun 24 04:41:20 PM PDT 24
Peak memory 200480 kb
Host smart-9174fb8d-f4bc-4b82-8bd8-ba078aea6ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527500889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.2527500889
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.3654128661
Short name T717
Test name
Test status
Simulation time 221551519154 ps
CPU time 176.18 seconds
Started Jun 24 04:38:54 PM PDT 24
Finished Jun 24 04:42:47 PM PDT 24
Peak memory 200536 kb
Host smart-7e37f625-f501-4432-be3b-f0ed933ac06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654128661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.3654128661
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.1250719527
Short name T221
Test name
Test status
Simulation time 51230239791 ps
CPU time 43.32 seconds
Started Jun 24 04:38:55 PM PDT 24
Finished Jun 24 04:40:34 PM PDT 24
Peak memory 200784 kb
Host smart-5a743ea3-98a4-4bea-8c36-aeaec55cb9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250719527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.1250719527
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.1351540455
Short name T313
Test name
Test status
Simulation time 65751849699 ps
CPU time 108.8 seconds
Started Jun 24 04:38:53 PM PDT 24
Finished Jun 24 04:41:40 PM PDT 24
Peak memory 200484 kb
Host smart-15049ab6-68ea-4aef-9f85-e1e3e3593208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351540455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.1351540455
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.14224657
Short name T241
Test name
Test status
Simulation time 55122330674 ps
CPU time 12.83 seconds
Started Jun 24 04:38:54 PM PDT 24
Finished Jun 24 04:40:04 PM PDT 24
Peak memory 200192 kb
Host smart-108453b2-e64f-4102-afe9-14fc520acb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14224657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.14224657
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.1001839481
Short name T1004
Test name
Test status
Simulation time 15804604 ps
CPU time 0.57 seconds
Started Jun 24 04:35:07 PM PDT 24
Finished Jun 24 04:35:08 PM PDT 24
Peak memory 195860 kb
Host smart-48391038-1000-4dcd-91e1-87e40eaec79a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001839481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.1001839481
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.2904061441
Short name T582
Test name
Test status
Simulation time 251963560814 ps
CPU time 64.29 seconds
Started Jun 24 04:35:17 PM PDT 24
Finished Jun 24 04:36:24 PM PDT 24
Peak memory 200464 kb
Host smart-ad3cfdad-342a-4f46-8a12-65e7f8c4e060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904061441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.2904061441
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.1852666872
Short name T632
Test name
Test status
Simulation time 20224157659 ps
CPU time 8.66 seconds
Started Jun 24 04:35:06 PM PDT 24
Finished Jun 24 04:35:15 PM PDT 24
Peak memory 200464 kb
Host smart-a306603e-be1e-47f4-acac-b6285c681311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852666872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.1852666872
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.1758424150
Short name T690
Test name
Test status
Simulation time 72148919491 ps
CPU time 26.05 seconds
Started Jun 24 04:35:10 PM PDT 24
Finished Jun 24 04:35:38 PM PDT 24
Peak memory 200464 kb
Host smart-ec305438-75b4-4ba6-8c30-4283ab50b202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758424150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.1758424150
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.4158908666
Short name T974
Test name
Test status
Simulation time 22944074863 ps
CPU time 12.95 seconds
Started Jun 24 04:35:07 PM PDT 24
Finished Jun 24 04:35:21 PM PDT 24
Peak memory 200508 kb
Host smart-c403487f-5e1d-4c80-aa8d-ff3112048914
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158908666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.4158908666
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.2512231884
Short name T384
Test name
Test status
Simulation time 103750125619 ps
CPU time 199.66 seconds
Started Jun 24 04:34:59 PM PDT 24
Finished Jun 24 04:38:20 PM PDT 24
Peak memory 200444 kb
Host smart-e264b5f2-bb15-4af4-b2b2-9859bc769619
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2512231884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.2512231884
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.2652691851
Short name T849
Test name
Test status
Simulation time 9896997271 ps
CPU time 5.02 seconds
Started Jun 24 04:35:14 PM PDT 24
Finished Jun 24 04:35:22 PM PDT 24
Peak memory 200520 kb
Host smart-8c50df16-8e28-45b5-b0be-31e8fa66d091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652691851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.2652691851
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_perf.621730331
Short name T1099
Test name
Test status
Simulation time 16887368854 ps
CPU time 502.63 seconds
Started Jun 24 04:35:25 PM PDT 24
Finished Jun 24 04:43:48 PM PDT 24
Peak memory 200432 kb
Host smart-83e39791-7c9a-4743-9485-4bbff85b26f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=621730331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.621730331
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.3672121694
Short name T865
Test name
Test status
Simulation time 3897793200 ps
CPU time 30.51 seconds
Started Jun 24 04:35:08 PM PDT 24
Finished Jun 24 04:35:39 PM PDT 24
Peak memory 198416 kb
Host smart-8cd676d4-c3bb-46f6-b201-ebc1da7d6a51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3672121694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3672121694
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.2489214247
Short name T676
Test name
Test status
Simulation time 101109317021 ps
CPU time 226.93 seconds
Started Jun 24 04:35:00 PM PDT 24
Finished Jun 24 04:38:48 PM PDT 24
Peak memory 200492 kb
Host smart-f8dbd902-53c3-47e5-9876-cdeaa9453311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489214247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.2489214247
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.4209029481
Short name T296
Test name
Test status
Simulation time 4456608040 ps
CPU time 1.06 seconds
Started Jun 24 04:35:10 PM PDT 24
Finished Jun 24 04:35:12 PM PDT 24
Peak memory 196792 kb
Host smart-41b4807e-b893-4c5d-a3c3-9362e97cb7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209029481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.4209029481
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.3250754696
Short name T88
Test name
Test status
Simulation time 282459849 ps
CPU time 0.87 seconds
Started Jun 24 04:35:15 PM PDT 24
Finished Jun 24 04:35:19 PM PDT 24
Peak memory 219036 kb
Host smart-d3643c47-b733-4c3d-8ade-28c51c781c75
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250754696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.3250754696
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.1181643385
Short name T954
Test name
Test status
Simulation time 5719987546 ps
CPU time 39.5 seconds
Started Jun 24 04:35:16 PM PDT 24
Finished Jun 24 04:35:58 PM PDT 24
Peak memory 200488 kb
Host smart-b28c3994-59dc-4b91-bf22-45e9851bf794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181643385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.1181643385
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.3470400062
Short name T124
Test name
Test status
Simulation time 233537157002 ps
CPU time 1100 seconds
Started Jun 24 04:35:02 PM PDT 24
Finished Jun 24 04:53:23 PM PDT 24
Peak memory 200440 kb
Host smart-0fba78a8-2ceb-4085-84b8-ab30c8b0cf0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470400062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.3470400062
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.1146630781
Short name T453
Test name
Test status
Simulation time 966798249 ps
CPU time 3.35 seconds
Started Jun 24 04:35:26 PM PDT 24
Finished Jun 24 04:35:30 PM PDT 24
Peak memory 199252 kb
Host smart-c81940c1-e0d7-4937-9d0b-3a20a65a3bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146630781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.1146630781
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.3129379886
Short name T612
Test name
Test status
Simulation time 172251101381 ps
CPU time 121.96 seconds
Started Jun 24 04:35:09 PM PDT 24
Finished Jun 24 04:37:12 PM PDT 24
Peak memory 200572 kb
Host smart-843e6eb0-d485-4554-862a-29bacd056947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129379886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.3129379886
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.4029820888
Short name T23
Test name
Test status
Simulation time 14811319 ps
CPU time 0.56 seconds
Started Jun 24 04:36:08 PM PDT 24
Finished Jun 24 04:36:29 PM PDT 24
Peak memory 195888 kb
Host smart-0054a3db-b656-4a5e-8e36-573bb1ae8203
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029820888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.4029820888
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.2424577507
Short name T146
Test name
Test status
Simulation time 26230670074 ps
CPU time 40.13 seconds
Started Jun 24 04:36:09 PM PDT 24
Finished Jun 24 04:37:10 PM PDT 24
Peak memory 200636 kb
Host smart-fc8be73e-7e6b-40af-a56e-6c758f5797f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424577507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.2424577507
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.1448760834
Short name T555
Test name
Test status
Simulation time 187813445994 ps
CPU time 67.36 seconds
Started Jun 24 04:36:09 PM PDT 24
Finished Jun 24 04:37:37 PM PDT 24
Peak memory 200504 kb
Host smart-9e5fe645-97bb-4a9e-bc27-591278afe8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448760834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.1448760834
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.3328008482
Short name T316
Test name
Test status
Simulation time 14780897101 ps
CPU time 29.18 seconds
Started Jun 24 04:36:15 PM PDT 24
Finished Jun 24 04:37:03 PM PDT 24
Peak memory 200440 kb
Host smart-b8e81bb3-9191-467c-9891-da932dbf5454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328008482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.3328008482
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.3567595251
Short name T499
Test name
Test status
Simulation time 47119888044 ps
CPU time 15.53 seconds
Started Jun 24 04:36:10 PM PDT 24
Finished Jun 24 04:36:47 PM PDT 24
Peak memory 200540 kb
Host smart-b17d3951-bb8c-4be8-9cd6-df685fc4723c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567595251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.3567595251
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.842789844
Short name T891
Test name
Test status
Simulation time 364212009537 ps
CPU time 271.41 seconds
Started Jun 24 04:36:12 PM PDT 24
Finished Jun 24 04:41:04 PM PDT 24
Peak memory 200596 kb
Host smart-fb5a5a45-3d0a-43f6-a522-a93f6e561e7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=842789844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.842789844
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.1403107545
Short name T361
Test name
Test status
Simulation time 7863971571 ps
CPU time 14.74 seconds
Started Jun 24 04:36:12 PM PDT 24
Finished Jun 24 04:36:47 PM PDT 24
Peak memory 200172 kb
Host smart-18bc8528-9968-4c90-83be-8ba5a7134019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403107545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.1403107545
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_perf.912821969
Short name T963
Test name
Test status
Simulation time 5054021177 ps
CPU time 166.16 seconds
Started Jun 24 04:36:07 PM PDT 24
Finished Jun 24 04:39:15 PM PDT 24
Peak memory 200480 kb
Host smart-bbee3dee-222b-4465-85e1-dcb01b2eac2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=912821969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.912821969
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.3331796377
Short name T1088
Test name
Test status
Simulation time 3059209287 ps
CPU time 6.39 seconds
Started Jun 24 04:36:09 PM PDT 24
Finished Jun 24 04:36:36 PM PDT 24
Peak memory 198740 kb
Host smart-6a9fc362-6b5e-4567-a782-2465efc3fb81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3331796377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.3331796377
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.2342405876
Short name T1044
Test name
Test status
Simulation time 42678391180 ps
CPU time 18.49 seconds
Started Jun 24 04:36:11 PM PDT 24
Finished Jun 24 04:36:50 PM PDT 24
Peak memory 200524 kb
Host smart-accdc2ff-951f-4525-b0b9-404d5474b846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342405876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.2342405876
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.984759178
Short name T112
Test name
Test status
Simulation time 2510816778 ps
CPU time 1.38 seconds
Started Jun 24 04:36:07 PM PDT 24
Finished Jun 24 04:36:30 PM PDT 24
Peak memory 196288 kb
Host smart-5f3cf6b6-79a1-44c9-83b8-5995df680810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984759178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.984759178
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.2654815954
Short name T753
Test name
Test status
Simulation time 888171601 ps
CPU time 3.34 seconds
Started Jun 24 04:36:10 PM PDT 24
Finished Jun 24 04:36:33 PM PDT 24
Peak memory 198928 kb
Host smart-2a774f4b-4364-4256-ad5e-a24666fd169d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654815954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.2654815954
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.312564996
Short name T341
Test name
Test status
Simulation time 333099856590 ps
CPU time 786.4 seconds
Started Jun 24 04:36:12 PM PDT 24
Finished Jun 24 04:49:39 PM PDT 24
Peak memory 200504 kb
Host smart-4f38b187-dca9-4d73-85f7-13d4726f4d83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312564996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.312564996
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.3758646054
Short name T999
Test name
Test status
Simulation time 82640084557 ps
CPU time 546.47 seconds
Started Jun 24 04:36:15 PM PDT 24
Finished Jun 24 04:45:40 PM PDT 24
Peak memory 217368 kb
Host smart-b2704bfa-15dd-4525-b94b-063046747222
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758646054 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.3758646054
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.4078250028
Short name T314
Test name
Test status
Simulation time 3042195927 ps
CPU time 2.22 seconds
Started Jun 24 04:36:15 PM PDT 24
Finished Jun 24 04:36:37 PM PDT 24
Peak memory 199680 kb
Host smart-59416ddc-bc8c-4ffb-8d8e-39f7176a2ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078250028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.4078250028
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.331492379
Short name T487
Test name
Test status
Simulation time 66154960718 ps
CPU time 109.92 seconds
Started Jun 24 04:36:08 PM PDT 24
Finished Jun 24 04:38:19 PM PDT 24
Peak memory 200536 kb
Host smart-5896c5a3-6777-4122-b61b-fe2e0567abed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331492379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.331492379
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.1630785363
Short name T349
Test name
Test status
Simulation time 21106037 ps
CPU time 0.6 seconds
Started Jun 24 04:36:26 PM PDT 24
Finished Jun 24 04:36:45 PM PDT 24
Peak memory 195888 kb
Host smart-ffb537af-50b0-4cf6-8ae0-85b00542429b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630785363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.1630785363
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.2608942576
Short name T300
Test name
Test status
Simulation time 155980710868 ps
CPU time 305.47 seconds
Started Jun 24 04:36:29 PM PDT 24
Finished Jun 24 04:41:52 PM PDT 24
Peak memory 200584 kb
Host smart-55ec0344-f724-4b85-88ba-3434425f9b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608942576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.2608942576
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.2299476009
Short name T305
Test name
Test status
Simulation time 171743129324 ps
CPU time 122.21 seconds
Started Jun 24 04:36:24 PM PDT 24
Finished Jun 24 04:38:44 PM PDT 24
Peak memory 200436 kb
Host smart-8d576766-6004-4a50-8287-f386885764d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299476009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.2299476009
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.3074567939
Short name T718
Test name
Test status
Simulation time 120326805850 ps
CPU time 64.06 seconds
Started Jun 24 04:36:25 PM PDT 24
Finished Jun 24 04:37:46 PM PDT 24
Peak memory 200920 kb
Host smart-e4ea9d53-5e11-4a1d-9d94-6da2fbb48262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074567939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.3074567939
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.1269680841
Short name T123
Test name
Test status
Simulation time 37453960690 ps
CPU time 74.03 seconds
Started Jun 24 04:36:28 PM PDT 24
Finished Jun 24 04:37:59 PM PDT 24
Peak memory 200420 kb
Host smart-280a2bc3-5740-44ce-8d0c-4fe993809c80
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269680841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.1269680841
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.3290424460
Short name T889
Test name
Test status
Simulation time 78682159971 ps
CPU time 596.42 seconds
Started Jun 24 04:36:26 PM PDT 24
Finished Jun 24 04:46:40 PM PDT 24
Peak memory 200488 kb
Host smart-968f2e22-72b2-48dc-a992-5438d3d8a4cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3290424460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.3290424460
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.3745019893
Short name T1069
Test name
Test status
Simulation time 6553497944 ps
CPU time 12.3 seconds
Started Jun 24 04:36:25 PM PDT 24
Finished Jun 24 04:36:56 PM PDT 24
Peak memory 199088 kb
Host smart-52766b42-cb65-4733-8c62-d0f49e976705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745019893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.3745019893
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_perf.3607171846
Short name T847
Test name
Test status
Simulation time 3183389534 ps
CPU time 42.66 seconds
Started Jun 24 04:36:27 PM PDT 24
Finished Jun 24 04:37:27 PM PDT 24
Peak memory 200512 kb
Host smart-79772c55-626e-4838-9641-9db7bb6091c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3607171846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.3607171846
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.349347929
Short name T873
Test name
Test status
Simulation time 5068954961 ps
CPU time 17.52 seconds
Started Jun 24 04:36:26 PM PDT 24
Finished Jun 24 04:37:02 PM PDT 24
Peak memory 198732 kb
Host smart-59fcf9dc-a39a-4c5c-99f2-87ef8011feac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=349347929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.349347929
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.1807345295
Short name T628
Test name
Test status
Simulation time 124488200546 ps
CPU time 243.19 seconds
Started Jun 24 04:36:30 PM PDT 24
Finished Jun 24 04:40:51 PM PDT 24
Peak memory 200572 kb
Host smart-413e3e98-0e53-44aa-8bea-8ca6130463ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807345295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.1807345295
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.2435852774
Short name T978
Test name
Test status
Simulation time 3119865320 ps
CPU time 1.95 seconds
Started Jun 24 04:36:30 PM PDT 24
Finished Jun 24 04:36:50 PM PDT 24
Peak memory 196528 kb
Host smart-fb4c5a58-c86b-4469-bbda-5e3a4d690b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435852774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.2435852774
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.1370605684
Short name T700
Test name
Test status
Simulation time 510924542 ps
CPU time 1.46 seconds
Started Jun 24 04:36:09 PM PDT 24
Finished Jun 24 04:36:31 PM PDT 24
Peak memory 199484 kb
Host smart-19670309-ce63-4f46-9323-83eb4988323b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370605684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.1370605684
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.2289433716
Short name T581
Test name
Test status
Simulation time 249665908616 ps
CPU time 558.63 seconds
Started Jun 24 04:36:26 PM PDT 24
Finished Jun 24 04:46:03 PM PDT 24
Peak memory 200464 kb
Host smart-976cb22c-c128-4c10-9794-2b98f79ddb55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289433716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.2289433716
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.3648181772
Short name T771
Test name
Test status
Simulation time 1610120195 ps
CPU time 5.59 seconds
Started Jun 24 04:36:29 PM PDT 24
Finished Jun 24 04:36:52 PM PDT 24
Peak memory 198956 kb
Host smart-67f838d6-0c53-4692-af8f-0e1f7d7775ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648181772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.3648181772
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.3662751422
Short name T364
Test name
Test status
Simulation time 21379471007 ps
CPU time 8.84 seconds
Started Jun 24 04:36:11 PM PDT 24
Finished Jun 24 04:36:40 PM PDT 24
Peak memory 200500 kb
Host smart-cba1eca4-78dc-4c5b-b1e1-25a6bc6c329f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662751422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.3662751422
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.4158439895
Short name T810
Test name
Test status
Simulation time 12915553 ps
CPU time 0.62 seconds
Started Jun 24 04:36:34 PM PDT 24
Finished Jun 24 04:36:51 PM PDT 24
Peak memory 195828 kb
Host smart-ba87816a-c8d7-41ab-b781-b0d629b1ae96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158439895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.4158439895
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.1677401020
Short name T997
Test name
Test status
Simulation time 65412454418 ps
CPU time 105.61 seconds
Started Jun 24 04:36:27 PM PDT 24
Finished Jun 24 04:38:31 PM PDT 24
Peak memory 200460 kb
Host smart-6a828f6d-0869-460a-9dd5-a9e4a13e29d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677401020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.1677401020
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.4092792228
Short name T665
Test name
Test status
Simulation time 10099352504 ps
CPU time 31.03 seconds
Started Jun 24 04:36:29 PM PDT 24
Finished Jun 24 04:37:17 PM PDT 24
Peak memory 200480 kb
Host smart-b6c75775-8ecc-4532-9a5c-eca1287b21dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092792228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.4092792228
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.1144646434
Short name T737
Test name
Test status
Simulation time 82223258608 ps
CPU time 70.31 seconds
Started Jun 24 04:36:25 PM PDT 24
Finished Jun 24 04:37:54 PM PDT 24
Peak memory 200620 kb
Host smart-33b350de-a7ad-4dc7-ab52-b5d56023f437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144646434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.1144646434
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.2279856602
Short name T651
Test name
Test status
Simulation time 18338118427 ps
CPU time 7.74 seconds
Started Jun 24 04:36:27 PM PDT 24
Finished Jun 24 04:36:52 PM PDT 24
Peak memory 198296 kb
Host smart-0a3b5f5d-061b-4887-912b-f39255acf72e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279856602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.2279856602
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.2683606099
Short name T606
Test name
Test status
Simulation time 59223864829 ps
CPU time 128.76 seconds
Started Jun 24 04:36:35 PM PDT 24
Finished Jun 24 04:39:01 PM PDT 24
Peak memory 200488 kb
Host smart-48bb4296-090c-485b-87fd-ba03c20d9ee3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2683606099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.2683606099
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.3207755017
Short name T786
Test name
Test status
Simulation time 7729214025 ps
CPU time 9.5 seconds
Started Jun 24 04:36:27 PM PDT 24
Finished Jun 24 04:36:54 PM PDT 24
Peak memory 200104 kb
Host smart-191d40f1-17d6-49e5-bc12-53215a09c93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207755017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.3207755017
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_perf.4151519597
Short name T662
Test name
Test status
Simulation time 3004744736 ps
CPU time 155.18 seconds
Started Jun 24 04:36:26 PM PDT 24
Finished Jun 24 04:39:19 PM PDT 24
Peak memory 200460 kb
Host smart-064e5c7b-603e-48a2-bafa-80d57cf98f2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4151519597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.4151519597
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.1776240494
Short name T1032
Test name
Test status
Simulation time 3268335097 ps
CPU time 12.95 seconds
Started Jun 24 04:36:25 PM PDT 24
Finished Jun 24 04:36:57 PM PDT 24
Peak memory 199732 kb
Host smart-fcfdd15b-bcbc-45e7-9ee5-ed9a22a0a3ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1776240494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.1776240494
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.66676013
Short name T158
Test name
Test status
Simulation time 9097504794 ps
CPU time 13.95 seconds
Started Jun 24 04:36:28 PM PDT 24
Finished Jun 24 04:36:59 PM PDT 24
Peak memory 200552 kb
Host smart-099e8472-534e-4136-b9f2-f0da8e622ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66676013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.66676013
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.3493751190
Short name T688
Test name
Test status
Simulation time 43613088159 ps
CPU time 62.43 seconds
Started Jun 24 04:36:25 PM PDT 24
Finished Jun 24 04:37:46 PM PDT 24
Peak memory 196800 kb
Host smart-1082ad9c-dce8-403a-8385-451337eb4f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493751190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.3493751190
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.1639286478
Short name T382
Test name
Test status
Simulation time 648153566 ps
CPU time 2.54 seconds
Started Jun 24 04:36:25 PM PDT 24
Finished Jun 24 04:36:46 PM PDT 24
Peak memory 198920 kb
Host smart-4e2ec29c-ffed-4ed6-9059-477de227287c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639286478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.1639286478
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.3433414949
Short name T442
Test name
Test status
Simulation time 1299045863 ps
CPU time 1.98 seconds
Started Jun 24 04:36:28 PM PDT 24
Finished Jun 24 04:36:47 PM PDT 24
Peak memory 200140 kb
Host smart-339d9fad-ad29-4907-bc65-47200ce1b658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433414949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.3433414949
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.4026064898
Short name T536
Test name
Test status
Simulation time 36374521117 ps
CPU time 58.41 seconds
Started Jun 24 04:36:25 PM PDT 24
Finished Jun 24 04:37:41 PM PDT 24
Peak memory 200528 kb
Host smart-895471d6-c879-4c0c-9e8c-557dafdafb10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026064898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.4026064898
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.2859848333
Short name T572
Test name
Test status
Simulation time 19202348 ps
CPU time 0.57 seconds
Started Jun 24 04:36:36 PM PDT 24
Finished Jun 24 04:36:53 PM PDT 24
Peak memory 195884 kb
Host smart-3c418bbe-a9e1-4656-9cf4-acdd1e014770
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859848333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.2859848333
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.1016164631
Short name T310
Test name
Test status
Simulation time 112953526948 ps
CPU time 406.99 seconds
Started Jun 24 04:36:32 PM PDT 24
Finished Jun 24 04:43:35 PM PDT 24
Peak memory 200544 kb
Host smart-d60ab150-833c-40a5-967c-1912eb5b1692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016164631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.1016164631
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.1925244377
Short name T702
Test name
Test status
Simulation time 36695402448 ps
CPU time 59.03 seconds
Started Jun 24 04:36:37 PM PDT 24
Finished Jun 24 04:37:53 PM PDT 24
Peak memory 200604 kb
Host smart-93b31aac-9055-4b4e-9e16-d8092b386576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925244377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.1925244377
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.1582870434
Short name T564
Test name
Test status
Simulation time 46985904210 ps
CPU time 36.72 seconds
Started Jun 24 04:36:36 PM PDT 24
Finished Jun 24 04:37:31 PM PDT 24
Peak memory 200620 kb
Host smart-c05950c1-66c6-4227-99e7-f6410411a1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582870434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.1582870434
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.2927112900
Short name T840
Test name
Test status
Simulation time 46020864587 ps
CPU time 72.14 seconds
Started Jun 24 04:36:34 PM PDT 24
Finished Jun 24 04:38:03 PM PDT 24
Peak memory 200552 kb
Host smart-8832d324-4635-452d-bd5e-540bf742f817
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927112900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.2927112900
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.2126663376
Short name T569
Test name
Test status
Simulation time 232774950364 ps
CPU time 142.14 seconds
Started Jun 24 04:36:35 PM PDT 24
Finished Jun 24 04:39:14 PM PDT 24
Peak memory 200500 kb
Host smart-ba3fed14-7024-4c1f-9c27-8ddda7859a51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2126663376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.2126663376
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.3410525031
Short name T46
Test name
Test status
Simulation time 3104950154 ps
CPU time 2.56 seconds
Started Jun 24 04:36:35 PM PDT 24
Finished Jun 24 04:36:55 PM PDT 24
Peak memory 199040 kb
Host smart-4f538ae8-0793-4135-ad52-262dfa1310c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410525031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.3410525031
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_perf.864274791
Short name T686
Test name
Test status
Simulation time 8586305014 ps
CPU time 525.96 seconds
Started Jun 24 04:36:33 PM PDT 24
Finished Jun 24 04:45:37 PM PDT 24
Peak memory 200588 kb
Host smart-b8832d03-bc96-4031-bb79-ecc79fec9861
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=864274791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.864274791
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.1428461615
Short name T675
Test name
Test status
Simulation time 5750423527 ps
CPU time 25.2 seconds
Started Jun 24 04:36:37 PM PDT 24
Finished Jun 24 04:37:19 PM PDT 24
Peak memory 198764 kb
Host smart-9de83d1e-3c0e-46f5-997f-8fc733b07087
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1428461615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.1428461615
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.586922448
Short name T148
Test name
Test status
Simulation time 98204295844 ps
CPU time 114.89 seconds
Started Jun 24 04:36:37 PM PDT 24
Finished Jun 24 04:38:49 PM PDT 24
Peak memory 200448 kb
Host smart-b4e3801f-e3f6-461f-947e-73db7050c1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586922448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.586922448
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.1839967001
Short name T408
Test name
Test status
Simulation time 4512661896 ps
CPU time 2.51 seconds
Started Jun 24 04:36:34 PM PDT 24
Finished Jun 24 04:36:53 PM PDT 24
Peak memory 196640 kb
Host smart-b2551998-1b67-470d-b142-fc9badc9dec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839967001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.1839967001
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.1715142135
Short name T1059
Test name
Test status
Simulation time 100665328 ps
CPU time 0.81 seconds
Started Jun 24 04:36:33 PM PDT 24
Finished Jun 24 04:36:50 PM PDT 24
Peak memory 197684 kb
Host smart-81618024-a96d-4c75-af4c-3b483f198420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715142135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.1715142135
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.339763633
Short name T726
Test name
Test status
Simulation time 64600713191 ps
CPU time 750.16 seconds
Started Jun 24 04:36:34 PM PDT 24
Finished Jun 24 04:49:21 PM PDT 24
Peak memory 200504 kb
Host smart-02996b0d-13f6-45ae-9eff-bb3e9e50c267
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339763633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.339763633
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.1737830973
Short name T575
Test name
Test status
Simulation time 7432240715 ps
CPU time 28.51 seconds
Started Jun 24 04:36:36 PM PDT 24
Finished Jun 24 04:37:23 PM PDT 24
Peak memory 200288 kb
Host smart-60d713c6-9298-443a-9caf-7f3cbb9e1569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737830973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.1737830973
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.1092586283
Short name T965
Test name
Test status
Simulation time 15020226427 ps
CPU time 13.01 seconds
Started Jun 24 04:36:37 PM PDT 24
Finished Jun 24 04:37:09 PM PDT 24
Peak memory 200468 kb
Host smart-0ea45b4c-18e4-414d-876a-f8d427382ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092586283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.1092586283
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.744136018
Short name T663
Test name
Test status
Simulation time 12124323 ps
CPU time 0.56 seconds
Started Jun 24 04:36:35 PM PDT 24
Finished Jun 24 04:36:53 PM PDT 24
Peak memory 195960 kb
Host smart-e7bd3b7a-4fdf-4730-83c7-2257a3535a9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744136018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.744136018
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.1180123569
Short name T583
Test name
Test status
Simulation time 116160962375 ps
CPU time 72.35 seconds
Started Jun 24 04:36:33 PM PDT 24
Finished Jun 24 04:38:02 PM PDT 24
Peak memory 200524 kb
Host smart-5d6f952d-e1a4-4eee-9c03-9c252d7cc0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180123569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.1180123569
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.1997497215
Short name T708
Test name
Test status
Simulation time 14405573147 ps
CPU time 23.59 seconds
Started Jun 24 04:36:32 PM PDT 24
Finished Jun 24 04:37:12 PM PDT 24
Peak memory 200356 kb
Host smart-9f892f65-3d59-487e-b21f-70b4ab9f1ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997497215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.1997497215
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.2798199982
Short name T949
Test name
Test status
Simulation time 16060739645 ps
CPU time 4.64 seconds
Started Jun 24 04:36:35 PM PDT 24
Finished Jun 24 04:36:57 PM PDT 24
Peak memory 198940 kb
Host smart-d870fcf6-6e13-448d-a289-2d32a49c3402
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798199982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.2798199982
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.1700433381
Short name T501
Test name
Test status
Simulation time 228224810073 ps
CPU time 62.49 seconds
Started Jun 24 04:36:38 PM PDT 24
Finished Jun 24 04:37:58 PM PDT 24
Peak memory 200532 kb
Host smart-24997261-8e6e-41c6-8663-567516375329
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1700433381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.1700433381
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.445238603
Short name T380
Test name
Test status
Simulation time 4096341755 ps
CPU time 4.79 seconds
Started Jun 24 04:36:35 PM PDT 24
Finished Jun 24 04:36:57 PM PDT 24
Peak memory 199872 kb
Host smart-693f0ec8-eae2-4708-bdbd-b8984d3394b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445238603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.445238603
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_perf.686997701
Short name T984
Test name
Test status
Simulation time 7214755226 ps
CPU time 110.2 seconds
Started Jun 24 04:36:38 PM PDT 24
Finished Jun 24 04:38:46 PM PDT 24
Peak memory 200444 kb
Host smart-27881fb6-1271-4b77-a763-267441dd0ae4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=686997701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.686997701
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.47209880
Short name T369
Test name
Test status
Simulation time 1381794407 ps
CPU time 3.12 seconds
Started Jun 24 04:36:34 PM PDT 24
Finished Jun 24 04:36:55 PM PDT 24
Peak memory 198784 kb
Host smart-88087330-dd93-4998-919d-63ca16f5eba2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=47209880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.47209880
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.1380511637
Short name T970
Test name
Test status
Simulation time 165928130381 ps
CPU time 265.94 seconds
Started Jun 24 04:36:34 PM PDT 24
Finished Jun 24 04:41:17 PM PDT 24
Peak memory 200516 kb
Host smart-62d2a659-182c-4b22-b655-e8e14de17be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380511637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.1380511637
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.36714113
Short name T350
Test name
Test status
Simulation time 3725005636 ps
CPU time 1.31 seconds
Started Jun 24 04:36:35 PM PDT 24
Finished Jun 24 04:36:54 PM PDT 24
Peak memory 196576 kb
Host smart-0c084eb7-9ac4-4c05-bef2-56379297b551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36714113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.36714113
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.201471482
Short name T875
Test name
Test status
Simulation time 650643052 ps
CPU time 2.64 seconds
Started Jun 24 04:36:33 PM PDT 24
Finished Jun 24 04:36:52 PM PDT 24
Peak memory 199392 kb
Host smart-58a9dba0-a421-4d4a-919d-bffaf1846a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201471482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.201471482
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.506687115
Short name T609
Test name
Test status
Simulation time 227715438203 ps
CPU time 1973.05 seconds
Started Jun 24 04:36:35 PM PDT 24
Finished Jun 24 05:09:46 PM PDT 24
Peak memory 200524 kb
Host smart-1c87b892-3247-47ff-8e5a-1b3e7414753e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506687115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.506687115
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.2608913396
Short name T550
Test name
Test status
Simulation time 30328576734 ps
CPU time 305.27 seconds
Started Jun 24 04:36:33 PM PDT 24
Finished Jun 24 04:41:56 PM PDT 24
Peak memory 216212 kb
Host smart-39b80142-2a11-455a-a795-19e526ce0ce2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608913396 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.2608913396
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.1241644283
Short name T553
Test name
Test status
Simulation time 6462422308 ps
CPU time 10.38 seconds
Started Jun 24 04:36:32 PM PDT 24
Finished Jun 24 04:36:59 PM PDT 24
Peak memory 200420 kb
Host smart-8cc464e1-be7b-4f8a-9bc0-7e866d279865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241644283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.1241644283
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.3778397244
Short name T336
Test name
Test status
Simulation time 52981580478 ps
CPU time 106.65 seconds
Started Jun 24 04:36:34 PM PDT 24
Finished Jun 24 04:38:37 PM PDT 24
Peak memory 200568 kb
Host smart-93bbff6a-a43c-48bd-9086-31be77064f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778397244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.3778397244
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.1013213798
Short name T566
Test name
Test status
Simulation time 12281809 ps
CPU time 0.56 seconds
Started Jun 24 04:36:34 PM PDT 24
Finished Jun 24 04:36:51 PM PDT 24
Peak memory 195876 kb
Host smart-eb90fbae-65a3-4e66-afee-98f18c80db00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013213798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.1013213798
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.745584488
Short name T725
Test name
Test status
Simulation time 129676808488 ps
CPU time 182.64 seconds
Started Jun 24 04:36:36 PM PDT 24
Finished Jun 24 04:39:55 PM PDT 24
Peak memory 200516 kb
Host smart-2fdf9f73-a895-48ad-985b-8e5d3de8ec77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745584488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.745584488
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.886153038
Short name T761
Test name
Test status
Simulation time 80606705927 ps
CPU time 62.25 seconds
Started Jun 24 04:36:35 PM PDT 24
Finished Jun 24 04:37:54 PM PDT 24
Peak memory 200476 kb
Host smart-290b6972-4847-41e8-8b27-abd7d5ed9ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886153038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.886153038
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.2242855857
Short name T498
Test name
Test status
Simulation time 25314084133 ps
CPU time 57.24 seconds
Started Jun 24 04:36:36 PM PDT 24
Finished Jun 24 04:37:50 PM PDT 24
Peak memory 200612 kb
Host smart-74d49b5b-e9e5-4991-8dd6-9700ddff46bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242855857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.2242855857
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.2778346817
Short name T846
Test name
Test status
Simulation time 42839354908 ps
CPU time 18.68 seconds
Started Jun 24 04:36:31 PM PDT 24
Finished Jun 24 04:37:07 PM PDT 24
Peak memory 200184 kb
Host smart-964e24a3-a769-41f4-9ba4-f824425ed9a7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778346817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.2778346817
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.2515384370
Short name T464
Test name
Test status
Simulation time 108602496574 ps
CPU time 206.38 seconds
Started Jun 24 04:36:34 PM PDT 24
Finished Jun 24 04:40:18 PM PDT 24
Peak memory 200572 kb
Host smart-f495716a-8e00-4dc0-8fe3-3dab4279a455
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2515384370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.2515384370
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.1139125527
Short name T832
Test name
Test status
Simulation time 8024484969 ps
CPU time 14.51 seconds
Started Jun 24 04:36:33 PM PDT 24
Finished Jun 24 04:37:04 PM PDT 24
Peak memory 199264 kb
Host smart-39979294-0a50-406c-8353-6b092ca1fb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139125527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.1139125527
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_perf.1790656232
Short name T435
Test name
Test status
Simulation time 13324419740 ps
CPU time 39.84 seconds
Started Jun 24 04:36:38 PM PDT 24
Finished Jun 24 04:37:36 PM PDT 24
Peak memory 200324 kb
Host smart-edddbc56-c095-4faa-be4c-87e6f5d33a9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1790656232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.1790656232
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.1972859158
Short name T670
Test name
Test status
Simulation time 1848289489 ps
CPU time 1.61 seconds
Started Jun 24 04:36:33 PM PDT 24
Finished Jun 24 04:36:52 PM PDT 24
Peak memory 198724 kb
Host smart-ac66c06c-9ccf-411f-b8c0-3fa232b454b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1972859158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.1972859158
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.3726441459
Short name T1049
Test name
Test status
Simulation time 26788866124 ps
CPU time 40.1 seconds
Started Jun 24 04:36:36 PM PDT 24
Finished Jun 24 04:37:33 PM PDT 24
Peak memory 200488 kb
Host smart-15ab45fc-d35f-4d3b-b0dc-36c37512ec2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726441459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.3726441459
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.2170789215
Short name T858
Test name
Test status
Simulation time 3903378680 ps
CPU time 6.79 seconds
Started Jun 24 04:36:36 PM PDT 24
Finished Jun 24 04:36:59 PM PDT 24
Peak memory 196824 kb
Host smart-ee8a8d75-a774-4c9a-82fa-a2ba7e7a0298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170789215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.2170789215
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.3303852126
Short name T374
Test name
Test status
Simulation time 862438797 ps
CPU time 1.79 seconds
Started Jun 24 04:36:34 PM PDT 24
Finished Jun 24 04:36:54 PM PDT 24
Peak memory 199244 kb
Host smart-6935e6f0-4632-4aa7-8f8a-da44ab2bf680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303852126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.3303852126
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.159433299
Short name T800
Test name
Test status
Simulation time 97847026184 ps
CPU time 285.33 seconds
Started Jun 24 04:36:38 PM PDT 24
Finished Jun 24 04:41:41 PM PDT 24
Peak memory 215852 kb
Host smart-b1edfbfb-5662-4263-9032-7288e3773570
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159433299 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.159433299
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.1295648570
Short name T397
Test name
Test status
Simulation time 1353995936 ps
CPU time 1.76 seconds
Started Jun 24 04:36:33 PM PDT 24
Finished Jun 24 04:36:52 PM PDT 24
Peak memory 199896 kb
Host smart-cc9b914c-5f5b-461b-b024-9c5a0f9595f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295648570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.1295648570
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.1868961149
Short name T966
Test name
Test status
Simulation time 92681074796 ps
CPU time 47.5 seconds
Started Jun 24 04:36:36 PM PDT 24
Finished Jun 24 04:37:42 PM PDT 24
Peak memory 200612 kb
Host smart-a92365ab-2954-4ae8-87bc-ea8cdf4a8ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868961149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.1868961149
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.1655742953
Short name T899
Test name
Test status
Simulation time 39934662 ps
CPU time 0.61 seconds
Started Jun 24 04:36:40 PM PDT 24
Finished Jun 24 04:36:59 PM PDT 24
Peak memory 195532 kb
Host smart-71589755-2727-49a8-8d3b-4f8d2ef08e87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655742953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.1655742953
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.3987459576
Short name T795
Test name
Test status
Simulation time 112908628019 ps
CPU time 380.43 seconds
Started Jun 24 04:36:34 PM PDT 24
Finished Jun 24 04:43:12 PM PDT 24
Peak memory 200524 kb
Host smart-63703d83-a534-4c5d-83be-e08533f36a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987459576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.3987459576
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.1751978967
Short name T1022
Test name
Test status
Simulation time 41562744773 ps
CPU time 68 seconds
Started Jun 24 04:36:35 PM PDT 24
Finished Jun 24 04:38:00 PM PDT 24
Peak memory 200472 kb
Host smart-b1eb4cc3-e886-4b6d-b344-a38de46b0461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751978967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.1751978967
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.187673877
Short name T251
Test name
Test status
Simulation time 48786308068 ps
CPU time 22.86 seconds
Started Jun 24 04:36:37 PM PDT 24
Finished Jun 24 04:37:18 PM PDT 24
Peak memory 200528 kb
Host smart-2b72c761-6b66-43b9-8baf-a0d81ea999e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187673877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.187673877
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.2632804474
Short name T414
Test name
Test status
Simulation time 37330260160 ps
CPU time 60.12 seconds
Started Jun 24 04:36:37 PM PDT 24
Finished Jun 24 04:37:54 PM PDT 24
Peak memory 200588 kb
Host smart-670c6ecf-a0f5-4808-b1a2-c53296d957e9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632804474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.2632804474
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.40406156
Short name T806
Test name
Test status
Simulation time 210578144412 ps
CPU time 336.1 seconds
Started Jun 24 04:36:43 PM PDT 24
Finished Jun 24 04:42:37 PM PDT 24
Peak memory 200472 kb
Host smart-c31062e0-6836-41a6-89c6-fc79438a43a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=40406156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.40406156
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.1454594670
Short name T600
Test name
Test status
Simulation time 7386842266 ps
CPU time 4.32 seconds
Started Jun 24 04:36:40 PM PDT 24
Finished Jun 24 04:37:02 PM PDT 24
Peak memory 199448 kb
Host smart-2098b3d4-2831-410e-9575-d483e0e59d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454594670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.1454594670
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.2070992271
Short name T706
Test name
Test status
Simulation time 24152687658 ps
CPU time 56.08 seconds
Started Jun 24 04:36:33 PM PDT 24
Finished Jun 24 04:37:47 PM PDT 24
Peak memory 200580 kb
Host smart-3bbb6c97-ffa8-4c9e-ab53-43429de45b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070992271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.2070992271
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.3887889175
Short name T905
Test name
Test status
Simulation time 13173284379 ps
CPU time 157.14 seconds
Started Jun 24 04:36:48 PM PDT 24
Finished Jun 24 04:39:42 PM PDT 24
Peak memory 200492 kb
Host smart-b91a5a85-1a39-455b-b6fe-0d0e1dc5e8e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3887889175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.3887889175
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.1630005272
Short name T914
Test name
Test status
Simulation time 3705889380 ps
CPU time 27.14 seconds
Started Jun 24 04:36:36 PM PDT 24
Finished Jun 24 04:37:21 PM PDT 24
Peak memory 199652 kb
Host smart-0337f8ec-5269-4796-bab1-f518bfe5a735
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1630005272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.1630005272
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.3777946091
Short name T159
Test name
Test status
Simulation time 117911673729 ps
CPU time 39.67 seconds
Started Jun 24 04:36:38 PM PDT 24
Finished Jun 24 04:37:35 PM PDT 24
Peak memory 200484 kb
Host smart-07b25080-699b-4932-82f1-ddb54f2523a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777946091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.3777946091
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.3880733163
Short name T772
Test name
Test status
Simulation time 5447959500 ps
CPU time 9.37 seconds
Started Jun 24 04:36:46 PM PDT 24
Finished Jun 24 04:37:13 PM PDT 24
Peak memory 196820 kb
Host smart-50560c84-d94b-4d42-970d-20a596f3abf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880733163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.3880733163
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.78873223
Short name T923
Test name
Test status
Simulation time 6198998652 ps
CPU time 7.75 seconds
Started Jun 24 04:36:36 PM PDT 24
Finished Jun 24 04:37:02 PM PDT 24
Peak memory 200216 kb
Host smart-d853284b-9323-4a08-b541-1837945a3496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78873223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.78873223
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.1730474833
Short name T1060
Test name
Test status
Simulation time 1917814981 ps
CPU time 1.8 seconds
Started Jun 24 04:36:37 PM PDT 24
Finished Jun 24 04:36:57 PM PDT 24
Peak memory 198964 kb
Host smart-7b302bd4-0c53-4153-927f-4d0ec2dd1e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730474833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.1730474833
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.521627788
Short name T562
Test name
Test status
Simulation time 113323793191 ps
CPU time 48.95 seconds
Started Jun 24 04:36:33 PM PDT 24
Finished Jun 24 04:37:40 PM PDT 24
Peak memory 200624 kb
Host smart-47b5fe90-69ce-44f6-90c4-8b198e2a6586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521627788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.521627788
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.1929338069
Short name T531
Test name
Test status
Simulation time 51252925 ps
CPU time 0.55 seconds
Started Jun 24 04:36:39 PM PDT 24
Finished Jun 24 04:36:58 PM PDT 24
Peak memory 195860 kb
Host smart-218202d2-06e0-4519-ad4e-ba9b44cac973
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929338069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.1929338069
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.102767716
Short name T1100
Test name
Test status
Simulation time 28804864329 ps
CPU time 15.49 seconds
Started Jun 24 04:36:45 PM PDT 24
Finished Jun 24 04:37:18 PM PDT 24
Peak memory 200544 kb
Host smart-f21e0cf2-fe73-4bdc-88de-c394fc907742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102767716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.102767716
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.634560201
Short name T166
Test name
Test status
Simulation time 27343683415 ps
CPU time 49.93 seconds
Started Jun 24 04:36:38 PM PDT 24
Finished Jun 24 04:37:46 PM PDT 24
Peak memory 200548 kb
Host smart-e94c55b8-831f-4919-abc0-823293d3cae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634560201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.634560201
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.4160301623
Short name T763
Test name
Test status
Simulation time 70773249891 ps
CPU time 179.44 seconds
Started Jun 24 04:36:40 PM PDT 24
Finished Jun 24 04:39:57 PM PDT 24
Peak memory 200484 kb
Host smart-6e2c0304-dc47-4e99-b23f-a9d0350baaaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160301623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.4160301623
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.2954447784
Short name T1033
Test name
Test status
Simulation time 12208922823 ps
CPU time 16.03 seconds
Started Jun 24 04:36:45 PM PDT 24
Finished Jun 24 04:37:19 PM PDT 24
Peak memory 198032 kb
Host smart-28c0fb3d-3b7a-4599-8b62-3e978acb1446
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954447784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.2954447784
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.1207943314
Short name T713
Test name
Test status
Simulation time 207605650531 ps
CPU time 308.01 seconds
Started Jun 24 04:36:46 PM PDT 24
Finished Jun 24 04:42:11 PM PDT 24
Peak memory 200472 kb
Host smart-3a54eaf0-aa53-4d1c-993d-a9da4aaf974b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1207943314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.1207943314
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.605809563
Short name T362
Test name
Test status
Simulation time 2819369798 ps
CPU time 5.05 seconds
Started Jun 24 04:36:39 PM PDT 24
Finished Jun 24 04:37:03 PM PDT 24
Peak memory 197860 kb
Host smart-0a6857a7-96d7-4e5f-ab4a-a4afdd60ea65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605809563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.605809563
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_perf.103568117
Short name T1047
Test name
Test status
Simulation time 27331279550 ps
CPU time 344.83 seconds
Started Jun 24 04:36:37 PM PDT 24
Finished Jun 24 04:42:39 PM PDT 24
Peak memory 200444 kb
Host smart-be524992-ce41-4ca4-a1a6-e51b79debc0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=103568117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.103568117
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.2206052788
Short name T1065
Test name
Test status
Simulation time 5381801875 ps
CPU time 49.78 seconds
Started Jun 24 04:36:47 PM PDT 24
Finished Jun 24 04:37:55 PM PDT 24
Peak memory 199872 kb
Host smart-af808c8c-b61e-420e-a24c-0db763702eed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2206052788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.2206052788
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.1876812640
Short name T406
Test name
Test status
Simulation time 34242011130 ps
CPU time 42.17 seconds
Started Jun 24 04:36:46 PM PDT 24
Finished Jun 24 04:37:46 PM PDT 24
Peak memory 200576 kb
Host smart-5a318e1a-89e2-4124-ad97-5939df4a5260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876812640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.1876812640
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.2576235887
Short name T1028
Test name
Test status
Simulation time 86805969252 ps
CPU time 68.48 seconds
Started Jun 24 04:36:43 PM PDT 24
Finished Jun 24 04:38:09 PM PDT 24
Peak memory 196504 kb
Host smart-a6dc266b-c650-4c3c-93dd-81961e17d15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576235887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.2576235887
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.3452251905
Short name T527
Test name
Test status
Simulation time 456966367 ps
CPU time 1.18 seconds
Started Jun 24 04:36:38 PM PDT 24
Finished Jun 24 04:36:57 PM PDT 24
Peak memory 198932 kb
Host smart-b2b336d0-8cfa-449b-838c-996d837546d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452251905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.3452251905
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.1996670090
Short name T894
Test name
Test status
Simulation time 273970484585 ps
CPU time 268.16 seconds
Started Jun 24 04:36:45 PM PDT 24
Finished Jun 24 04:41:31 PM PDT 24
Peak memory 200524 kb
Host smart-53d83c2e-dc33-4daf-8994-3b0a3f18db51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996670090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.1996670090
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.2852726236
Short name T845
Test name
Test status
Simulation time 998754298 ps
CPU time 3.95 seconds
Started Jun 24 04:36:38 PM PDT 24
Finished Jun 24 04:37:00 PM PDT 24
Peak memory 199032 kb
Host smart-f50e1e44-b114-49e7-bcc7-2750b8aa5b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852726236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.2852726236
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.135721111
Short name T1046
Test name
Test status
Simulation time 69728825872 ps
CPU time 48.88 seconds
Started Jun 24 04:36:39 PM PDT 24
Finished Jun 24 04:37:45 PM PDT 24
Peak memory 200488 kb
Host smart-10904c4c-2731-4ccc-aa94-e53a151dcb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135721111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.135721111
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.3221204694
Short name T344
Test name
Test status
Simulation time 18234579 ps
CPU time 0.57 seconds
Started Jun 24 04:36:40 PM PDT 24
Finished Jun 24 04:36:59 PM PDT 24
Peak memory 195864 kb
Host smart-aecef04c-f7ed-4e19-9989-b991b9c6623e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221204694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.3221204694
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.4277964116
Short name T185
Test name
Test status
Simulation time 367736841627 ps
CPU time 143.37 seconds
Started Jun 24 04:36:41 PM PDT 24
Finished Jun 24 04:39:22 PM PDT 24
Peak memory 200564 kb
Host smart-18d2ed73-40b9-4604-af63-3555720efa0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277964116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.4277964116
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.2397341837
Short name T748
Test name
Test status
Simulation time 211829243954 ps
CPU time 594.89 seconds
Started Jun 24 04:36:42 PM PDT 24
Finished Jun 24 04:46:55 PM PDT 24
Peak memory 200624 kb
Host smart-ffc5b4f1-1fa1-4339-b4f6-56d50a1c9877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397341837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.2397341837
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.765953069
Short name T405
Test name
Test status
Simulation time 72737403440 ps
CPU time 64.64 seconds
Started Jun 24 04:36:45 PM PDT 24
Finished Jun 24 04:38:07 PM PDT 24
Peak memory 200548 kb
Host smart-dab32cc3-c016-477a-86d6-e9b3bfce8d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765953069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.765953069
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.313815392
Short name T329
Test name
Test status
Simulation time 212517761112 ps
CPU time 269.97 seconds
Started Jun 24 04:36:38 PM PDT 24
Finished Jun 24 04:41:26 PM PDT 24
Peak memory 197480 kb
Host smart-e8c9df34-3c69-4309-8db3-45f247840602
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313815392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.313815392
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.3389444931
Short name T272
Test name
Test status
Simulation time 348031162320 ps
CPU time 356.58 seconds
Started Jun 24 04:36:38 PM PDT 24
Finished Jun 24 04:42:52 PM PDT 24
Peak memory 200392 kb
Host smart-0a0c6dba-488d-4e5f-b390-c389202d10a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3389444931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.3389444931
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.1542062797
Short name T348
Test name
Test status
Simulation time 10178810065 ps
CPU time 12.58 seconds
Started Jun 24 04:36:43 PM PDT 24
Finished Jun 24 04:37:13 PM PDT 24
Peak memory 200484 kb
Host smart-46623c67-720f-4874-ac5a-b932bbf35713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542062797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.1542062797
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_perf.1425126097
Short name T514
Test name
Test status
Simulation time 24578803714 ps
CPU time 1319.98 seconds
Started Jun 24 04:36:43 PM PDT 24
Finished Jun 24 04:59:01 PM PDT 24
Peak memory 200640 kb
Host smart-a32db1bd-1deb-4a7f-b697-608f64debf9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1425126097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.1425126097
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.786925403
Short name T437
Test name
Test status
Simulation time 5891321098 ps
CPU time 52.83 seconds
Started Jun 24 04:36:40 PM PDT 24
Finished Jun 24 04:37:52 PM PDT 24
Peak memory 198716 kb
Host smart-763cd12f-08b0-48e2-a392-4ca2a092b093
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=786925403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.786925403
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.966796781
Short name T556
Test name
Test status
Simulation time 188948090664 ps
CPU time 59.08 seconds
Started Jun 24 04:36:38 PM PDT 24
Finished Jun 24 04:37:55 PM PDT 24
Peak memory 200100 kb
Host smart-81c01a85-23ba-46e2-b5af-fec86517d6d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966796781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.966796781
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.3507245428
Short name T452
Test name
Test status
Simulation time 38493654913 ps
CPU time 8.9 seconds
Started Jun 24 04:36:38 PM PDT 24
Finished Jun 24 04:37:05 PM PDT 24
Peak memory 196392 kb
Host smart-1ef95cc7-6171-4716-b788-9eb732e57d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507245428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.3507245428
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.239387652
Short name T52
Test name
Test status
Simulation time 557455122 ps
CPU time 1.92 seconds
Started Jun 24 04:36:40 PM PDT 24
Finished Jun 24 04:37:00 PM PDT 24
Peak memory 199376 kb
Host smart-7478f32e-e319-4981-a967-bfccaec3a499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239387652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.239387652
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.278396395
Short name T509
Test name
Test status
Simulation time 125490957861 ps
CPU time 706.02 seconds
Started Jun 24 04:36:41 PM PDT 24
Finished Jun 24 04:48:45 PM PDT 24
Peak memory 217080 kb
Host smart-b1a65edb-f375-438c-97c8-7c7e42c9f9f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278396395 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.278396395
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.949381303
Short name T392
Test name
Test status
Simulation time 6635128765 ps
CPU time 29.77 seconds
Started Jun 24 04:36:37 PM PDT 24
Finished Jun 24 04:37:25 PM PDT 24
Peak memory 200512 kb
Host smart-d73d3512-db0f-4aa8-88ba-5b8cd9e9bca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949381303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.949381303
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.2461272664
Short name T937
Test name
Test status
Simulation time 67408519062 ps
CPU time 30.33 seconds
Started Jun 24 04:36:39 PM PDT 24
Finished Jun 24 04:37:27 PM PDT 24
Peak memory 200472 kb
Host smart-bafaf8ca-155a-46f0-8c44-c9db5fa176eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461272664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.2461272664
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.3449162173
Short name T1025
Test name
Test status
Simulation time 14206037 ps
CPU time 0.59 seconds
Started Jun 24 04:36:50 PM PDT 24
Finished Jun 24 04:37:10 PM PDT 24
Peak memory 195828 kb
Host smart-8501d5e0-b222-4bd5-bd3f-a4294f7a6fb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449162173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.3449162173
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.494605118
Short name T996
Test name
Test status
Simulation time 9512565397 ps
CPU time 12.78 seconds
Started Jun 24 04:36:47 PM PDT 24
Finished Jun 24 04:37:18 PM PDT 24
Peak memory 198360 kb
Host smart-d250fb01-f9f1-458d-aa8a-567b141e0cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494605118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.494605118
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.1313566567
Short name T563
Test name
Test status
Simulation time 22807275167 ps
CPU time 36.49 seconds
Started Jun 24 04:36:42 PM PDT 24
Finished Jun 24 04:37:37 PM PDT 24
Peak memory 200628 kb
Host smart-df81a75f-92c4-4648-9e0d-4033cc844fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313566567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.1313566567
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.3186551231
Short name T1010
Test name
Test status
Simulation time 44801439092 ps
CPU time 81.42 seconds
Started Jun 24 04:36:39 PM PDT 24
Finished Jun 24 04:38:19 PM PDT 24
Peak memory 200532 kb
Host smart-925d73cc-5831-4a79-9ed9-0afe5f1f49e5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186551231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.3186551231
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.3925519073
Short name T793
Test name
Test status
Simulation time 102843466304 ps
CPU time 752.58 seconds
Started Jun 24 04:36:49 PM PDT 24
Finished Jun 24 04:49:41 PM PDT 24
Peak memory 200532 kb
Host smart-ed7e8e02-2be3-4539-af42-ff111aa77663
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3925519073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.3925519073
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.2254481507
Short name T47
Test name
Test status
Simulation time 10357908799 ps
CPU time 26.11 seconds
Started Jun 24 04:36:49 PM PDT 24
Finished Jun 24 04:37:35 PM PDT 24
Peak memory 199936 kb
Host smart-63afed60-b602-4698-962c-c54f88df219b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254481507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.2254481507
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_perf.3084013738
Short name T804
Test name
Test status
Simulation time 10188363929 ps
CPU time 114.68 seconds
Started Jun 24 04:36:49 PM PDT 24
Finished Jun 24 04:39:04 PM PDT 24
Peak memory 200440 kb
Host smart-a5164fe6-d96a-40ce-95e4-ec65fc18c783
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3084013738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.3084013738
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.3291923384
Short name T513
Test name
Test status
Simulation time 3796313851 ps
CPU time 6.6 seconds
Started Jun 24 04:36:43 PM PDT 24
Finished Jun 24 04:37:07 PM PDT 24
Peak memory 198636 kb
Host smart-028fd7fd-2337-4072-a98b-bcfe44c48c20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3291923384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.3291923384
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.973435431
Short name T458
Test name
Test status
Simulation time 138758252807 ps
CPU time 63.92 seconds
Started Jun 24 04:36:43 PM PDT 24
Finished Jun 24 04:38:04 PM PDT 24
Peak memory 200636 kb
Host smart-7748043d-b888-4ffc-ad67-a9477c7090df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973435431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.973435431
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.1715451752
Short name T520
Test name
Test status
Simulation time 1602623177 ps
CPU time 1.23 seconds
Started Jun 24 04:36:46 PM PDT 24
Finished Jun 24 04:37:05 PM PDT 24
Peak memory 196244 kb
Host smart-4b704b44-3452-484f-a806-9a38cfb5a4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715451752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.1715451752
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.3683002168
Short name T647
Test name
Test status
Simulation time 5517255251 ps
CPU time 13.35 seconds
Started Jun 24 04:36:40 PM PDT 24
Finished Jun 24 04:37:11 PM PDT 24
Peak memory 200532 kb
Host smart-d861a6a0-cad0-4350-83b5-64e3cd643356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683002168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.3683002168
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.3313178944
Short name T642
Test name
Test status
Simulation time 2345978728 ps
CPU time 2.23 seconds
Started Jun 24 04:36:45 PM PDT 24
Finished Jun 24 04:37:05 PM PDT 24
Peak memory 200336 kb
Host smart-2b857662-a324-497a-b710-adfda6a64bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313178944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.3313178944
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.2955147867
Short name T486
Test name
Test status
Simulation time 27103702559 ps
CPU time 23.11 seconds
Started Jun 24 04:36:41 PM PDT 24
Finished Jun 24 04:37:22 PM PDT 24
Peak memory 200564 kb
Host smart-79f13b71-3ffd-47ea-a84c-85cecd851788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955147867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.2955147867
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.2277296009
Short name T477
Test name
Test status
Simulation time 14606257 ps
CPU time 0.57 seconds
Started Jun 24 04:35:22 PM PDT 24
Finished Jun 24 04:35:23 PM PDT 24
Peak memory 195864 kb
Host smart-8b912b0b-9945-4d2f-8fb7-5404cee6ab4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277296009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.2277296009
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.1046321680
Short name T1093
Test name
Test status
Simulation time 34597660013 ps
CPU time 19.34 seconds
Started Jun 24 04:35:00 PM PDT 24
Finished Jun 24 04:35:22 PM PDT 24
Peak memory 200464 kb
Host smart-6c091e25-6aff-4d16-9e27-42a7c2bc70a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046321680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.1046321680
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.1874961118
Short name T114
Test name
Test status
Simulation time 133770582265 ps
CPU time 118.42 seconds
Started Jun 24 04:35:14 PM PDT 24
Finished Jun 24 04:37:15 PM PDT 24
Peak memory 200412 kb
Host smart-3c8b4ad7-cb53-4d67-89c1-4073898e3f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874961118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.1874961118
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_intr.3204802874
Short name T619
Test name
Test status
Simulation time 320186519419 ps
CPU time 85.83 seconds
Started Jun 24 04:35:08 PM PDT 24
Finished Jun 24 04:36:35 PM PDT 24
Peak memory 200404 kb
Host smart-1befb24e-49a7-46d9-92e9-0dbf8098960f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204802874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.3204802874
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.4117963019
Short name T826
Test name
Test status
Simulation time 124693183169 ps
CPU time 262.99 seconds
Started Jun 24 04:35:09 PM PDT 24
Finished Jun 24 04:39:34 PM PDT 24
Peak memory 200464 kb
Host smart-00d08925-1be6-44ef-9911-92f10dc97e1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4117963019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.4117963019
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.3115926166
Short name T358
Test name
Test status
Simulation time 5112660345 ps
CPU time 8.85 seconds
Started Jun 24 04:35:14 PM PDT 24
Finished Jun 24 04:35:25 PM PDT 24
Peak memory 200432 kb
Host smart-a9af4144-978c-43cf-8d5a-64b7ca8b8962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115926166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.3115926166
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_perf.2585646061
Short name T591
Test name
Test status
Simulation time 7167353449 ps
CPU time 381.15 seconds
Started Jun 24 04:35:06 PM PDT 24
Finished Jun 24 04:41:27 PM PDT 24
Peak memory 200520 kb
Host smart-db2bb84f-332a-4a77-a318-90630d12bcee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2585646061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.2585646061
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.1518560988
Short name T351
Test name
Test status
Simulation time 2509140472 ps
CPU time 18.8 seconds
Started Jun 24 04:35:10 PM PDT 24
Finished Jun 24 04:35:31 PM PDT 24
Peak memory 199676 kb
Host smart-b6ff0888-0c57-46ba-a0ba-bc4ba98cc0f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1518560988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.1518560988
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.1025167690
Short name T467
Test name
Test status
Simulation time 81666095549 ps
CPU time 153.25 seconds
Started Jun 24 04:35:12 PM PDT 24
Finished Jun 24 04:37:47 PM PDT 24
Peak memory 200572 kb
Host smart-822bdf85-3819-4e8e-a71b-7d3729acae19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025167690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.1025167690
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.3400713599
Short name T620
Test name
Test status
Simulation time 52503203604 ps
CPU time 21.79 seconds
Started Jun 24 04:35:19 PM PDT 24
Finished Jun 24 04:35:42 PM PDT 24
Peak memory 196620 kb
Host smart-f0fcc199-e89f-4dd2-a53c-d95a8792f380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400713599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.3400713599
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.2466890243
Short name T27
Test name
Test status
Simulation time 35474854 ps
CPU time 0.79 seconds
Started Jun 24 04:35:11 PM PDT 24
Finished Jun 24 04:35:14 PM PDT 24
Peak memory 218972 kb
Host smart-2cf9050d-a99d-4ed7-9bea-eca96fe6985c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466890243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.2466890243
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.4135894228
Short name T973
Test name
Test status
Simulation time 5723269757 ps
CPU time 5.25 seconds
Started Jun 24 04:35:02 PM PDT 24
Finished Jun 24 04:35:09 PM PDT 24
Peak memory 200432 kb
Host smart-68baf21e-3c86-4c70-bfe8-eed0a7e1790c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135894228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.4135894228
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.1279427174
Short name T716
Test name
Test status
Simulation time 187805910220 ps
CPU time 893.68 seconds
Started Jun 24 04:35:21 PM PDT 24
Finished Jun 24 04:50:16 PM PDT 24
Peak memory 200328 kb
Host smart-8d072f55-f6cf-49ec-90ef-254448816f96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279427174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.1279427174
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.4107285281
Short name T491
Test name
Test status
Simulation time 941390889 ps
CPU time 2.87 seconds
Started Jun 24 04:35:00 PM PDT 24
Finished Jun 24 04:35:05 PM PDT 24
Peak memory 200316 kb
Host smart-51c32bb2-37ce-4d54-91e4-33e872551518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107285281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.4107285281
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.3934364878
Short name T1051
Test name
Test status
Simulation time 80846254660 ps
CPU time 35.44 seconds
Started Jun 24 04:35:14 PM PDT 24
Finished Jun 24 04:35:51 PM PDT 24
Peak memory 200528 kb
Host smart-0a7296d2-b6f3-48b6-9384-4f14ae01f56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934364878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.3934364878
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.1050925871
Short name T354
Test name
Test status
Simulation time 63652919 ps
CPU time 0.57 seconds
Started Jun 24 04:36:54 PM PDT 24
Finished Jun 24 04:37:14 PM PDT 24
Peak memory 195880 kb
Host smart-2026a43a-905a-400e-b84e-35eb5d558303
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050925871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.1050925871
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.749133703
Short name T133
Test name
Test status
Simulation time 48942717273 ps
CPU time 29.77 seconds
Started Jun 24 04:36:50 PM PDT 24
Finished Jun 24 04:37:41 PM PDT 24
Peak memory 200876 kb
Host smart-bf403659-d573-4140-baea-a65a5de95d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749133703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.749133703
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.4190330434
Short name T94
Test name
Test status
Simulation time 17037737965 ps
CPU time 8.77 seconds
Started Jun 24 04:36:50 PM PDT 24
Finished Jun 24 04:37:18 PM PDT 24
Peak memory 200548 kb
Host smart-b09b6233-a484-4655-8276-3af2ef0c67e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190330434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.4190330434
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_intr.1617499944
Short name T1038
Test name
Test status
Simulation time 87154854348 ps
CPU time 76.12 seconds
Started Jun 24 04:36:53 PM PDT 24
Finished Jun 24 04:38:28 PM PDT 24
Peak memory 200400 kb
Host smart-decb4ce6-8d09-4c2b-b359-79e7b4257bb0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617499944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.1617499944
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.3867879055
Short name T760
Test name
Test status
Simulation time 87349333718 ps
CPU time 139.44 seconds
Started Jun 24 04:36:49 PM PDT 24
Finished Jun 24 04:39:26 PM PDT 24
Peak memory 200556 kb
Host smart-0457d1a5-1541-4788-aab3-893569edff1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3867879055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.3867879055
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.1819083104
Short name T901
Test name
Test status
Simulation time 1827305605 ps
CPU time 6.15 seconds
Started Jun 24 04:36:48 PM PDT 24
Finished Jun 24 04:37:13 PM PDT 24
Peak memory 198928 kb
Host smart-32912e36-40a7-4d74-9e92-c87be3c23aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819083104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.1819083104
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_perf.1023663726
Short name T274
Test name
Test status
Simulation time 16246079341 ps
CPU time 785.65 seconds
Started Jun 24 04:36:48 PM PDT 24
Finished Jun 24 04:50:12 PM PDT 24
Peak memory 200500 kb
Host smart-3595e8f6-895b-476e-b147-e974670865a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1023663726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.1023663726
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.1993949766
Short name T852
Test name
Test status
Simulation time 1907670130 ps
CPU time 7.02 seconds
Started Jun 24 04:36:48 PM PDT 24
Finished Jun 24 04:37:12 PM PDT 24
Peak memory 199268 kb
Host smart-b408ebb6-ccb0-44d3-9efa-eb0875acaf5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1993949766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.1993949766
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.1992089766
Short name T1076
Test name
Test status
Simulation time 42809367867 ps
CPU time 31.84 seconds
Started Jun 24 04:36:49 PM PDT 24
Finished Jun 24 04:37:41 PM PDT 24
Peak memory 200552 kb
Host smart-faa7745c-9988-45c4-ba7f-2a97fee49a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992089766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.1992089766
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.3334168394
Short name T1027
Test name
Test status
Simulation time 1699186591 ps
CPU time 2.12 seconds
Started Jun 24 04:36:49 PM PDT 24
Finished Jun 24 04:37:11 PM PDT 24
Peak memory 195924 kb
Host smart-5b300e94-511c-4599-b16a-b2778d7c9eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334168394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.3334168394
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.1279568880
Short name T451
Test name
Test status
Simulation time 662383832 ps
CPU time 1.41 seconds
Started Jun 24 04:36:53 PM PDT 24
Finished Jun 24 04:37:13 PM PDT 24
Peak memory 198852 kb
Host smart-63ed8642-8d10-4ccf-886e-928ef386af10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279568880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.1279568880
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.2516805788
Short name T175
Test name
Test status
Simulation time 475822144130 ps
CPU time 167.72 seconds
Started Jun 24 04:36:54 PM PDT 24
Finished Jun 24 04:40:01 PM PDT 24
Peak memory 200444 kb
Host smart-ad0810b7-b3f0-4664-b7ea-dc3a98635d12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516805788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.2516805788
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.2501666622
Short name T105
Test name
Test status
Simulation time 108939324086 ps
CPU time 308.88 seconds
Started Jun 24 04:36:53 PM PDT 24
Finished Jun 24 04:42:21 PM PDT 24
Peak memory 216984 kb
Host smart-588b022e-f5ec-4a8b-bb61-5a9d3a192bdf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501666622 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.2501666622
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.223424891
Short name T859
Test name
Test status
Simulation time 393015037 ps
CPU time 1.31 seconds
Started Jun 24 04:36:50 PM PDT 24
Finished Jun 24 04:37:10 PM PDT 24
Peak memory 197664 kb
Host smart-59844937-02e7-48fe-8eef-47cf0edf8eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223424891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.223424891
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.4267880907
Short name T1019
Test name
Test status
Simulation time 28577599497 ps
CPU time 12.57 seconds
Started Jun 24 04:36:49 PM PDT 24
Finished Jun 24 04:37:21 PM PDT 24
Peak memory 200580 kb
Host smart-7cd2707b-49c8-48e2-b701-e6da4500a2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267880907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.4267880907
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.3216114885
Short name T1020
Test name
Test status
Simulation time 40558701 ps
CPU time 0.57 seconds
Started Jun 24 04:36:53 PM PDT 24
Finished Jun 24 04:37:12 PM PDT 24
Peak memory 195920 kb
Host smart-a8f2919f-1ce9-4729-b145-012f799abbbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216114885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.3216114885
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.433102663
Short name T270
Test name
Test status
Simulation time 28766908925 ps
CPU time 12.19 seconds
Started Jun 24 04:36:54 PM PDT 24
Finished Jun 24 04:37:25 PM PDT 24
Peak memory 200544 kb
Host smart-f27c6b4e-dcae-4ee2-a42b-4db0e56184c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433102663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.433102663
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.1541055817
Short name T184
Test name
Test status
Simulation time 188909515318 ps
CPU time 27.4 seconds
Started Jun 24 04:36:57 PM PDT 24
Finished Jun 24 04:37:45 PM PDT 24
Peak memory 200484 kb
Host smart-16d349c2-d0da-4ca0-bc44-d226d48670a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541055817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.1541055817
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.3391323944
Short name T421
Test name
Test status
Simulation time 27508963108 ps
CPU time 15.21 seconds
Started Jun 24 04:36:57 PM PDT 24
Finished Jun 24 04:37:32 PM PDT 24
Peak memory 200268 kb
Host smart-4870c39a-2e43-4e58-966f-a6b7ce08c198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391323944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.3391323944
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.3416878625
Short name T500
Test name
Test status
Simulation time 10762585076 ps
CPU time 18.39 seconds
Started Jun 24 04:36:57 PM PDT 24
Finished Jun 24 04:37:36 PM PDT 24
Peak memory 200528 kb
Host smart-f1184cd9-0df8-48eb-9ee4-f4b56927672d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416878625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.3416878625
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.2671432691
Short name T1084
Test name
Test status
Simulation time 156062692643 ps
CPU time 708.47 seconds
Started Jun 24 04:36:55 PM PDT 24
Finished Jun 24 04:49:04 PM PDT 24
Peak memory 200172 kb
Host smart-422b7979-a101-4544-89e0-43594762d598
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2671432691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.2671432691
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.3399980806
Short name T22
Test name
Test status
Simulation time 5623607714 ps
CPU time 10.25 seconds
Started Jun 24 04:37:00 PM PDT 24
Finished Jun 24 04:37:32 PM PDT 24
Peak memory 199680 kb
Host smart-38db5245-02ff-49df-b76a-b1b9777f5426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399980806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.3399980806
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_perf.3921537115
Short name T621
Test name
Test status
Simulation time 14613587448 ps
CPU time 582.84 seconds
Started Jun 24 04:37:05 PM PDT 24
Finished Jun 24 04:47:16 PM PDT 24
Peak memory 200532 kb
Host smart-77cc1e52-7626-4cb3-911b-1b7a11a1ce2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3921537115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.3921537115
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.1492336384
Short name T504
Test name
Test status
Simulation time 4453131386 ps
CPU time 11.24 seconds
Started Jun 24 04:37:01 PM PDT 24
Finished Jun 24 04:37:35 PM PDT 24
Peak memory 198696 kb
Host smart-b516c77f-71eb-42e3-8a61-a591b2d054f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1492336384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.1492336384
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.3104264809
Short name T895
Test name
Test status
Simulation time 21881881004 ps
CPU time 17.85 seconds
Started Jun 24 04:36:57 PM PDT 24
Finished Jun 24 04:37:35 PM PDT 24
Peak memory 200544 kb
Host smart-b1317a8e-fb00-408f-b721-cb0eae89cf4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104264809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.3104264809
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.2797595008
Short name T648
Test name
Test status
Simulation time 2956005006 ps
CPU time 2.9 seconds
Started Jun 24 04:37:03 PM PDT 24
Finished Jun 24 04:37:30 PM PDT 24
Peak memory 196248 kb
Host smart-29843b80-2779-4dc4-b609-916a17e73289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797595008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.2797595008
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.336288784
Short name T881
Test name
Test status
Simulation time 466452779 ps
CPU time 1.3 seconds
Started Jun 24 04:36:53 PM PDT 24
Finished Jun 24 04:37:13 PM PDT 24
Peak memory 199484 kb
Host smart-83ac09ad-6fee-4339-bfbc-1297d799e727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336288784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.336288784
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.4200678214
Short name T230
Test name
Test status
Simulation time 43375732335 ps
CPU time 88.11 seconds
Started Jun 24 04:36:55 PM PDT 24
Finished Jun 24 04:38:42 PM PDT 24
Peak memory 200824 kb
Host smart-507bda6c-88a2-4c73-9e96-2e669be2be97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200678214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.4200678214
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.383872533
Short name T104
Test name
Test status
Simulation time 154634008226 ps
CPU time 355.11 seconds
Started Jun 24 04:36:54 PM PDT 24
Finished Jun 24 04:43:08 PM PDT 24
Peak memory 217008 kb
Host smart-e7c3c8ae-9553-4abf-95b8-4bf45e3ee897
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383872533 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.383872533
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.532891518
Short name T510
Test name
Test status
Simulation time 966247338 ps
CPU time 3.71 seconds
Started Jun 24 04:37:00 PM PDT 24
Finished Jun 24 04:37:25 PM PDT 24
Peak memory 198928 kb
Host smart-9e77df09-c3dd-48d8-8862-27bce152ca92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532891518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.532891518
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.2745017639
Short name T303
Test name
Test status
Simulation time 54101969673 ps
CPU time 71.72 seconds
Started Jun 24 04:37:03 PM PDT 24
Finished Jun 24 04:38:39 PM PDT 24
Peak memory 199732 kb
Host smart-7aac36b8-d41d-42c1-aee4-3e322e452241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745017639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.2745017639
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.2303872884
Short name T372
Test name
Test status
Simulation time 14548750 ps
CPU time 0.58 seconds
Started Jun 24 04:37:03 PM PDT 24
Finished Jun 24 04:37:27 PM PDT 24
Peak memory 195312 kb
Host smart-feb3ac24-163b-46fb-bb06-eea0c4dc3642
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303872884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.2303872884
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.2979716206
Short name T493
Test name
Test status
Simulation time 63081228663 ps
CPU time 92.99 seconds
Started Jun 24 04:37:00 PM PDT 24
Finished Jun 24 04:38:54 PM PDT 24
Peak memory 200464 kb
Host smart-a58cb524-828d-405d-98f4-019eccfa31b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979716206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.2979716206
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.3666926353
Short name T473
Test name
Test status
Simulation time 92414569490 ps
CPU time 148.71 seconds
Started Jun 24 04:37:03 PM PDT 24
Finished Jun 24 04:39:56 PM PDT 24
Peak memory 200208 kb
Host smart-150ea203-6aa2-43a8-8165-a2eba1a019db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666926353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.3666926353
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.974728571
Short name T237
Test name
Test status
Simulation time 138896730223 ps
CPU time 69.82 seconds
Started Jun 24 04:37:03 PM PDT 24
Finished Jun 24 04:38:37 PM PDT 24
Peak memory 199636 kb
Host smart-f8c80aa1-6d01-4283-9c38-56646794e49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974728571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.974728571
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.2037085266
Short name T402
Test name
Test status
Simulation time 48628427589 ps
CPU time 29.64 seconds
Started Jun 24 04:36:57 PM PDT 24
Finished Jun 24 04:37:46 PM PDT 24
Peak memory 200516 kb
Host smart-a0ba449a-31cf-46f2-8b1c-ea6171321eba
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037085266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.2037085266
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.4201233894
Short name T278
Test name
Test status
Simulation time 336174379277 ps
CPU time 234.72 seconds
Started Jun 24 04:37:01 PM PDT 24
Finished Jun 24 04:41:16 PM PDT 24
Peak memory 200528 kb
Host smart-fd93b626-14d9-4527-97aa-7fde80a72b87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4201233894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.4201233894
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.1286015169
Short name T368
Test name
Test status
Simulation time 3636087284 ps
CPU time 2.48 seconds
Started Jun 24 04:37:01 PM PDT 24
Finished Jun 24 04:37:24 PM PDT 24
Peak memory 198628 kb
Host smart-830eeec1-7057-4ba4-a99a-2dea81c641ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286015169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.1286015169
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_perf.3770391533
Short name T370
Test name
Test status
Simulation time 8218662903 ps
CPU time 467.1 seconds
Started Jun 24 04:37:05 PM PDT 24
Finished Jun 24 04:45:20 PM PDT 24
Peak memory 200476 kb
Host smart-34ad7b93-459f-4bc8-8d6d-17be4658405b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3770391533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.3770391533
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.3140086922
Short name T363
Test name
Test status
Simulation time 1529613632 ps
CPU time 1.44 seconds
Started Jun 24 04:36:54 PM PDT 24
Finished Jun 24 04:37:14 PM PDT 24
Peak memory 198676 kb
Host smart-e559eef6-bec6-4105-98c5-8190c9c25ee3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3140086922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.3140086922
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.901838007
Short name T492
Test name
Test status
Simulation time 94789621807 ps
CPU time 75.49 seconds
Started Jun 24 04:36:55 PM PDT 24
Finished Jun 24 04:38:31 PM PDT 24
Peak memory 200140 kb
Host smart-c7dff358-b233-4864-a2db-bd1307b4e536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901838007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.901838007
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.2507797439
Short name T519
Test name
Test status
Simulation time 50021984761 ps
CPU time 70.69 seconds
Started Jun 24 04:37:00 PM PDT 24
Finished Jun 24 04:38:32 PM PDT 24
Peak memory 196316 kb
Host smart-ac97bf11-a0b4-40e3-bbc8-8b1acf6d70c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507797439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.2507797439
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.1339472879
Short name T299
Test name
Test status
Simulation time 6086427948 ps
CPU time 13.04 seconds
Started Jun 24 04:36:56 PM PDT 24
Finished Jun 24 04:37:30 PM PDT 24
Peak memory 200444 kb
Host smart-de655748-0e7e-4b6f-b94f-9c18d9bd2adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339472879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.1339472879
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.3412231380
Short name T277
Test name
Test status
Simulation time 28408148861 ps
CPU time 170.84 seconds
Started Jun 24 04:37:03 PM PDT 24
Finished Jun 24 04:40:18 PM PDT 24
Peak memory 216084 kb
Host smart-f3186128-dbf7-42ab-b82c-3c5a58ee9b38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412231380 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.3412231380
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.3043614778
Short name T306
Test name
Test status
Simulation time 853707231 ps
CPU time 2.57 seconds
Started Jun 24 04:37:02 PM PDT 24
Finished Jun 24 04:37:27 PM PDT 24
Peak memory 199192 kb
Host smart-8c67cdd9-7470-4a93-9e86-94ef94de886d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043614778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.3043614778
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.2525028270
Short name T528
Test name
Test status
Simulation time 5159355270 ps
CPU time 8.19 seconds
Started Jun 24 04:36:55 PM PDT 24
Finished Jun 24 04:37:23 PM PDT 24
Peak memory 200460 kb
Host smart-ff2cd3db-3085-41ca-afdc-eb0f8e81c3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525028270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.2525028270
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.2039760525
Short name T1048
Test name
Test status
Simulation time 44775557 ps
CPU time 0.57 seconds
Started Jun 24 04:37:21 PM PDT 24
Finished Jun 24 04:38:05 PM PDT 24
Peak memory 195976 kb
Host smart-7d39764e-5c83-4762-bd95-5889af542f18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039760525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.2039760525
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.1249733601
Short name T471
Test name
Test status
Simulation time 91192741381 ps
CPU time 77.93 seconds
Started Jun 24 04:37:03 PM PDT 24
Finished Jun 24 04:38:45 PM PDT 24
Peak memory 200420 kb
Host smart-9f985b5d-2c00-4c46-82db-e0275b1c0f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249733601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.1249733601
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.3345331719
Short name T697
Test name
Test status
Simulation time 80262651489 ps
CPU time 106.65 seconds
Started Jun 24 04:37:02 PM PDT 24
Finished Jun 24 04:39:13 PM PDT 24
Peak memory 200544 kb
Host smart-777176d0-5594-4972-a101-ee3c98794cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345331719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.3345331719
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.1470990029
Short name T570
Test name
Test status
Simulation time 85625192056 ps
CPU time 75.68 seconds
Started Jun 24 04:37:03 PM PDT 24
Finished Jun 24 04:38:42 PM PDT 24
Peak memory 200492 kb
Host smart-9f8b8792-6651-424a-9002-5c8a32fd0924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470990029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.1470990029
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.1714458210
Short name T325
Test name
Test status
Simulation time 126057992038 ps
CPU time 190.42 seconds
Started Jun 24 04:37:03 PM PDT 24
Finished Jun 24 04:40:37 PM PDT 24
Peak memory 196488 kb
Host smart-2f7031b5-3f40-4d3b-a9b0-61b8848da363
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714458210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.1714458210
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.2484537623
Short name T253
Test name
Test status
Simulation time 68911919454 ps
CPU time 600.54 seconds
Started Jun 24 04:37:08 PM PDT 24
Finished Jun 24 04:47:37 PM PDT 24
Peak memory 200528 kb
Host smart-d26a24e3-0ff3-4404-a7bd-2d0935bfc78b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2484537623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.2484537623
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.3114668562
Short name T658
Test name
Test status
Simulation time 6619313111 ps
CPU time 5.02 seconds
Started Jun 24 04:37:07 PM PDT 24
Finished Jun 24 04:37:41 PM PDT 24
Peak memory 199100 kb
Host smart-d4586984-4400-4b2d-b306-2fea36660d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114668562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.3114668562
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_perf.1918626043
Short name T474
Test name
Test status
Simulation time 15385479685 ps
CPU time 209.04 seconds
Started Jun 24 04:37:08 PM PDT 24
Finished Jun 24 04:41:06 PM PDT 24
Peak memory 200508 kb
Host smart-926ff4c4-1e9d-4898-9387-97d4fc7d9a3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1918626043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.1918626043
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.1236605622
Short name T916
Test name
Test status
Simulation time 2447119140 ps
CPU time 4.47 seconds
Started Jun 24 04:37:00 PM PDT 24
Finished Jun 24 04:37:26 PM PDT 24
Peak memory 198540 kb
Host smart-4be57e05-d02c-4b64-b48c-2e9f65a57eb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1236605622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.1236605622
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.3857590362
Short name T746
Test name
Test status
Simulation time 116399475380 ps
CPU time 212.65 seconds
Started Jun 24 04:37:03 PM PDT 24
Finished Jun 24 04:41:00 PM PDT 24
Peak memory 200436 kb
Host smart-8ab65e45-f936-446c-b905-39e45f24f789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857590362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.3857590362
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.1547509549
Short name T285
Test name
Test status
Simulation time 686126725 ps
CPU time 0.93 seconds
Started Jun 24 04:37:00 PM PDT 24
Finished Jun 24 04:37:22 PM PDT 24
Peak memory 195976 kb
Host smart-34cdd6eb-3ad1-4a52-9027-9286d26d9082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547509549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.1547509549
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.3486174916
Short name T829
Test name
Test status
Simulation time 5829101598 ps
CPU time 17.01 seconds
Started Jun 24 04:37:01 PM PDT 24
Finished Jun 24 04:37:39 PM PDT 24
Peak memory 200444 kb
Host smart-790a7e4f-9e98-4c4d-bb05-ad12f52ef7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486174916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.3486174916
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.2689272854
Short name T1087
Test name
Test status
Simulation time 12308302770 ps
CPU time 16.04 seconds
Started Jun 24 04:36:59 PM PDT 24
Finished Jun 24 04:37:35 PM PDT 24
Peak memory 200332 kb
Host smart-9e500c73-3f32-46c2-befd-06b9415f620a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689272854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.2689272854
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.2842341622
Short name T281
Test name
Test status
Simulation time 40252067657 ps
CPU time 73.65 seconds
Started Jun 24 04:37:00 PM PDT 24
Finished Jun 24 04:38:35 PM PDT 24
Peak memory 200480 kb
Host smart-fe106789-e555-4430-8217-051033ee2bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842341622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.2842341622
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.854937770
Short name T482
Test name
Test status
Simulation time 19510240 ps
CPU time 0.61 seconds
Started Jun 24 04:37:09 PM PDT 24
Finished Jun 24 04:37:41 PM PDT 24
Peak memory 195860 kb
Host smart-014c7a89-f2e4-439e-957e-809a4116d037
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854937770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.854937770
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.3238077437
Short name T611
Test name
Test status
Simulation time 134143335971 ps
CPU time 32.21 seconds
Started Jun 24 04:37:07 PM PDT 24
Finished Jun 24 04:38:09 PM PDT 24
Peak memory 200492 kb
Host smart-e8b8909f-22d3-49e7-b652-20b54bdb246b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238077437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.3238077437
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.860720178
Short name T617
Test name
Test status
Simulation time 76519682004 ps
CPU time 40.81 seconds
Started Jun 24 04:37:06 PM PDT 24
Finished Jun 24 04:38:17 PM PDT 24
Peak memory 199180 kb
Host smart-96261e2a-b194-4f67-b0b2-67ad52e4227f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860720178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.860720178
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.3162654611
Short name T1064
Test name
Test status
Simulation time 6043569521 ps
CPU time 7.79 seconds
Started Jun 24 04:37:06 PM PDT 24
Finished Jun 24 04:37:41 PM PDT 24
Peak memory 200632 kb
Host smart-00163fbf-91e8-4269-b8fd-7b15c38d9631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162654611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.3162654611
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.3465129490
Short name T568
Test name
Test status
Simulation time 45613413172 ps
CPU time 39.87 seconds
Started Jun 24 04:37:07 PM PDT 24
Finished Jun 24 04:38:16 PM PDT 24
Peak memory 200492 kb
Host smart-edf148c7-50c4-4582-91b8-65f8d70a9c0f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465129490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.3465129490
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.291646260
Short name T1050
Test name
Test status
Simulation time 105338236700 ps
CPU time 427.71 seconds
Started Jun 24 04:37:22 PM PDT 24
Finished Jun 24 04:45:17 PM PDT 24
Peak memory 200492 kb
Host smart-382419e3-7d57-461d-9049-d107e88f41be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=291646260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.291646260
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.3187814395
Short name T359
Test name
Test status
Simulation time 10096299612 ps
CPU time 4.34 seconds
Started Jun 24 04:37:08 PM PDT 24
Finished Jun 24 04:37:41 PM PDT 24
Peak memory 200332 kb
Host smart-6623659b-23c0-4234-b884-3efdcec6d433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187814395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.3187814395
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_perf.1908459328
Short name T440
Test name
Test status
Simulation time 21272363870 ps
CPU time 900.72 seconds
Started Jun 24 04:37:09 PM PDT 24
Finished Jun 24 04:52:41 PM PDT 24
Peak memory 200448 kb
Host smart-9b573f32-cc03-4bba-ada5-461fc992e412
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1908459328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.1908459328
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.3942920505
Short name T610
Test name
Test status
Simulation time 3382843435 ps
CPU time 12.89 seconds
Started Jun 24 04:37:06 PM PDT 24
Finished Jun 24 04:37:49 PM PDT 24
Peak memory 198576 kb
Host smart-a674b0eb-2691-4c34-9df4-d52b440b96a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3942920505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.3942920505
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.3704686821
Short name T959
Test name
Test status
Simulation time 50176908390 ps
CPU time 33.43 seconds
Started Jun 24 04:37:14 PM PDT 24
Finished Jun 24 04:38:26 PM PDT 24
Peak memory 200540 kb
Host smart-0f1d1296-4641-4415-817b-3505b0ac942e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704686821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.3704686821
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.2944749179
Short name T366
Test name
Test status
Simulation time 2927223817 ps
CPU time 4.94 seconds
Started Jun 24 04:37:06 PM PDT 24
Finished Jun 24 04:37:41 PM PDT 24
Peak memory 196536 kb
Host smart-1439a79c-a924-4864-abc8-34dfca6d7e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944749179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.2944749179
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.20843373
Short name T593
Test name
Test status
Simulation time 6151135202 ps
CPU time 13.49 seconds
Started Jun 24 04:37:06 PM PDT 24
Finished Jun 24 04:37:46 PM PDT 24
Peak memory 200328 kb
Host smart-b79d0a81-3169-454f-9c6b-2439a5d20d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20843373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.20843373
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.1474105192
Short name T412
Test name
Test status
Simulation time 1134274312 ps
CPU time 2.87 seconds
Started Jun 24 04:37:06 PM PDT 24
Finished Jun 24 04:37:36 PM PDT 24
Peak memory 199052 kb
Host smart-f99fd712-aef8-41ef-baab-67c32df38ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474105192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.1474105192
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.1713618961
Short name T445
Test name
Test status
Simulation time 24597734307 ps
CPU time 35.17 seconds
Started Jun 24 04:37:07 PM PDT 24
Finished Jun 24 04:38:11 PM PDT 24
Peak memory 200548 kb
Host smart-4d7a7c06-6790-4d57-8c66-2d00338339bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713618961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.1713618961
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.2112726567
Short name T669
Test name
Test status
Simulation time 11308505 ps
CPU time 0.57 seconds
Started Jun 24 04:37:17 PM PDT 24
Finished Jun 24 04:38:01 PM PDT 24
Peak memory 195920 kb
Host smart-ef1260d9-40de-497a-865f-0cde8d808dc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112726567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.2112726567
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.2563952208
Short name T579
Test name
Test status
Simulation time 380416310521 ps
CPU time 40.2 seconds
Started Jun 24 04:37:05 PM PDT 24
Finished Jun 24 04:38:13 PM PDT 24
Peak memory 200524 kb
Host smart-bcb491c4-a5ca-4820-a3dc-d9d91e6752ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563952208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.2563952208
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.2887993879
Short name T952
Test name
Test status
Simulation time 89592726193 ps
CPU time 78.63 seconds
Started Jun 24 04:37:12 PM PDT 24
Finished Jun 24 04:39:07 PM PDT 24
Peak memory 200892 kb
Host smart-65abae99-eaad-4295-89e0-5a0be8fa6f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887993879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.2887993879
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.1520098371
Short name T982
Test name
Test status
Simulation time 29138092518 ps
CPU time 11.56 seconds
Started Jun 24 04:37:09 PM PDT 24
Finished Jun 24 04:37:52 PM PDT 24
Peak memory 200412 kb
Host smart-bdbb0c93-41a7-49a6-98c9-ea42d7b915c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520098371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.1520098371
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.3375251383
Short name T714
Test name
Test status
Simulation time 36069552213 ps
CPU time 5.36 seconds
Started Jun 24 04:37:07 PM PDT 24
Finished Jun 24 04:37:41 PM PDT 24
Peak memory 200508 kb
Host smart-468e8a0d-62f8-45a1-b46e-e7087ed3583f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375251383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.3375251383
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.2990618983
Short name T818
Test name
Test status
Simulation time 90000111136 ps
CPU time 399.3 seconds
Started Jun 24 04:37:18 PM PDT 24
Finished Jun 24 04:44:40 PM PDT 24
Peak memory 200468 kb
Host smart-17f27407-abb4-42a9-8aa2-e9cdc007c1d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2990618983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.2990618983
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.4191472114
Short name T904
Test name
Test status
Simulation time 131515734 ps
CPU time 0.87 seconds
Started Jun 24 04:37:14 PM PDT 24
Finished Jun 24 04:37:53 PM PDT 24
Peak memory 198960 kb
Host smart-5acc287e-75e0-4149-82a7-d21b50c1cb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191472114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.4191472114
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_perf.3880151661
Short name T398
Test name
Test status
Simulation time 12667972444 ps
CPU time 191.23 seconds
Started Jun 24 04:37:34 PM PDT 24
Finished Jun 24 04:41:41 PM PDT 24
Peak memory 200564 kb
Host smart-73482d4a-a04b-4dab-bb19-d78a46331859
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3880151661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.3880151661
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.258093856
Short name T38
Test name
Test status
Simulation time 4456418108 ps
CPU time 10.35 seconds
Started Jun 24 04:37:06 PM PDT 24
Finished Jun 24 04:37:43 PM PDT 24
Peak memory 199708 kb
Host smart-7c9f6e30-c989-44f4-8f53-b2779b3d1259
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=258093856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.258093856
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.1350674167
Short name T839
Test name
Test status
Simulation time 159474303128 ps
CPU time 311.51 seconds
Started Jun 24 04:37:17 PM PDT 24
Finished Jun 24 04:43:12 PM PDT 24
Peak memory 200324 kb
Host smart-f6bd8c0b-33a2-44dd-b919-ef61be4a4bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350674167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.1350674167
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.2506521080
Short name T673
Test name
Test status
Simulation time 34650173491 ps
CPU time 58.72 seconds
Started Jun 24 04:37:18 PM PDT 24
Finished Jun 24 04:38:59 PM PDT 24
Peak memory 196612 kb
Host smart-efe02601-2e09-4474-a1f9-d7469e11def6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506521080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.2506521080
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.2964266936
Short name T682
Test name
Test status
Simulation time 291337099 ps
CPU time 1.67 seconds
Started Jun 24 04:37:08 PM PDT 24
Finished Jun 24 04:37:38 PM PDT 24
Peak memory 198924 kb
Host smart-f6eed645-60ca-46b6-aa3e-07745203dc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964266936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.2964266936
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.1203984915
Short name T1011
Test name
Test status
Simulation time 335146196646 ps
CPU time 178.02 seconds
Started Jun 24 04:37:15 PM PDT 24
Finished Jun 24 04:40:54 PM PDT 24
Peak memory 200460 kb
Host smart-5d910824-7b07-4c79-b8f0-a29a7bb3d4ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203984915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.1203984915
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.113846478
Short name T784
Test name
Test status
Simulation time 1016439218 ps
CPU time 4.24 seconds
Started Jun 24 04:37:17 PM PDT 24
Finished Jun 24 04:38:05 PM PDT 24
Peak memory 200436 kb
Host smart-99a456cc-605c-4e6f-b7bf-6faef243d1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113846478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.113846478
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.3677969864
Short name T884
Test name
Test status
Simulation time 26366578059 ps
CPU time 54.76 seconds
Started Jun 24 04:37:08 PM PDT 24
Finished Jun 24 04:38:31 PM PDT 24
Peak memory 200488 kb
Host smart-a4510edc-2d86-4bf9-ac8a-a5c7ff6b17c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677969864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.3677969864
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.1508702701
Short name T942
Test name
Test status
Simulation time 14972439 ps
CPU time 0.58 seconds
Started Jun 24 04:37:17 PM PDT 24
Finished Jun 24 04:38:01 PM PDT 24
Peak memory 195864 kb
Host smart-88bd7bd6-2bf2-480c-9770-4439661ad200
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508702701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.1508702701
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.60590300
Short name T785
Test name
Test status
Simulation time 107693313124 ps
CPU time 305.27 seconds
Started Jun 24 04:37:15 PM PDT 24
Finished Jun 24 04:43:02 PM PDT 24
Peak memory 200564 kb
Host smart-76405a28-225e-4ebd-aa7f-2891201edd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60590300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.60590300
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.2797645321
Short name T508
Test name
Test status
Simulation time 17896476878 ps
CPU time 27.95 seconds
Started Jun 24 04:37:16 PM PDT 24
Finished Jun 24 04:38:25 PM PDT 24
Peak memory 200708 kb
Host smart-433fc7d6-5ca2-4cd1-8313-914b32657b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797645321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.2797645321
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.2280731531
Short name T710
Test name
Test status
Simulation time 257677246567 ps
CPU time 106.36 seconds
Started Jun 24 04:37:16 PM PDT 24
Finished Jun 24 04:39:43 PM PDT 24
Peak memory 200568 kb
Host smart-51767806-fd75-4457-aa03-4077c5e363ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280731531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.2280731531
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.3228266058
Short name T12
Test name
Test status
Simulation time 6796989026 ps
CPU time 15.39 seconds
Started Jun 24 04:37:18 PM PDT 24
Finished Jun 24 04:38:16 PM PDT 24
Peak memory 199388 kb
Host smart-521ac7cd-4b29-45d9-9b62-d0574022fb85
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228266058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.3228266058
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.3543528542
Short name T990
Test name
Test status
Simulation time 111502241860 ps
CPU time 480.92 seconds
Started Jun 24 04:37:14 PM PDT 24
Finished Jun 24 04:45:53 PM PDT 24
Peak memory 200452 kb
Host smart-9324cdf9-77b1-400c-b065-349fd1266005
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3543528542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.3543528542
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.513604149
Short name T956
Test name
Test status
Simulation time 7280240355 ps
CPU time 4.16 seconds
Started Jun 24 04:37:15 PM PDT 24
Finished Jun 24 04:38:01 PM PDT 24
Peak memory 200220 kb
Host smart-701c7919-5d46-4275-ab81-5b5984c2f1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513604149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.513604149
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_perf.2814637222
Short name T534
Test name
Test status
Simulation time 15051952516 ps
CPU time 212.24 seconds
Started Jun 24 04:37:18 PM PDT 24
Finished Jun 24 04:41:33 PM PDT 24
Peak memory 200508 kb
Host smart-616e64df-f44a-4bf6-80b9-63624009ce1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2814637222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.2814637222
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.3597060741
Short name T1035
Test name
Test status
Simulation time 2877951678 ps
CPU time 5.89 seconds
Started Jun 24 04:37:16 PM PDT 24
Finished Jun 24 04:38:03 PM PDT 24
Peak memory 198952 kb
Host smart-55366fdd-e103-4c8b-93f8-f16592c55483
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3597060741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.3597060741
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.1413106177
Short name T698
Test name
Test status
Simulation time 136887014916 ps
CPU time 357.76 seconds
Started Jun 24 04:37:16 PM PDT 24
Finished Jun 24 04:43:54 PM PDT 24
Peak memory 200464 kb
Host smart-d03e17eb-30d2-4fbc-86de-307242239b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413106177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.1413106177
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.3641340614
Short name T385
Test name
Test status
Simulation time 2166773081 ps
CPU time 1.58 seconds
Started Jun 24 04:37:18 PM PDT 24
Finished Jun 24 04:38:02 PM PDT 24
Peak memory 196244 kb
Host smart-199d1196-fff3-417e-8f2e-fb19295e6a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641340614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.3641340614
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.3452748405
Short name T1034
Test name
Test status
Simulation time 432157269 ps
CPU time 2 seconds
Started Jun 24 04:37:16 PM PDT 24
Finished Jun 24 04:37:59 PM PDT 24
Peak memory 199524 kb
Host smart-7cb82fde-e8d9-4d3b-810a-8965a6e66c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452748405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.3452748405
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.1107950292
Short name T9
Test name
Test status
Simulation time 1164511785 ps
CPU time 2.21 seconds
Started Jun 24 04:37:14 PM PDT 24
Finished Jun 24 04:37:55 PM PDT 24
Peak memory 199356 kb
Host smart-844c0084-2308-43f6-a411-a9a88644466e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107950292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.1107950292
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.1892647965
Short name T652
Test name
Test status
Simulation time 40737728554 ps
CPU time 56.62 seconds
Started Jun 24 04:37:17 PM PDT 24
Finished Jun 24 04:38:57 PM PDT 24
Peak memory 200488 kb
Host smart-c0159cb4-1c1b-4bc0-bbcf-024f1bb3d01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892647965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.1892647965
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.3477894459
Short name T1083
Test name
Test status
Simulation time 37175508 ps
CPU time 0.55 seconds
Started Jun 24 04:37:20 PM PDT 24
Finished Jun 24 04:38:05 PM PDT 24
Peak memory 195148 kb
Host smart-3c500eb0-6a5f-4e3f-b422-d5c6ab8fc52a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477894459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.3477894459
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.1758731576
Short name T286
Test name
Test status
Simulation time 13052180932 ps
CPU time 21.76 seconds
Started Jun 24 04:37:19 PM PDT 24
Finished Jun 24 04:38:26 PM PDT 24
Peak memory 200576 kb
Host smart-0cd89e47-e4cb-48a6-959c-f68e61560d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758731576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.1758731576
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.3467829715
Short name T776
Test name
Test status
Simulation time 148454254475 ps
CPU time 67.21 seconds
Started Jun 24 04:37:17 PM PDT 24
Finished Jun 24 04:39:08 PM PDT 24
Peak memory 200620 kb
Host smart-3190fdc2-3a49-49af-9994-2d4ebdf2b785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467829715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.3467829715
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.3905614372
Short name T755
Test name
Test status
Simulation time 98812667850 ps
CPU time 169.77 seconds
Started Jun 24 04:37:17 PM PDT 24
Finished Jun 24 04:40:50 PM PDT 24
Peak memory 200524 kb
Host smart-877eab59-0162-4611-bcb6-537d731c4215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905614372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.3905614372
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.1114326076
Short name T886
Test name
Test status
Simulation time 95659938210 ps
CPU time 108.54 seconds
Started Jun 24 04:37:15 PM PDT 24
Finished Jun 24 04:39:45 PM PDT 24
Peak memory 200464 kb
Host smart-eb37ea8c-111c-46dd-9381-7aff30bcd52a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114326076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.1114326076
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.1501558706
Short name T769
Test name
Test status
Simulation time 86515670963 ps
CPU time 288.4 seconds
Started Jun 24 04:37:20 PM PDT 24
Finished Jun 24 04:42:53 PM PDT 24
Peak memory 200456 kb
Host smart-39eb024b-4c8f-482c-9e13-efdbe0bfbffb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1501558706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.1501558706
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.2635062322
Short name T995
Test name
Test status
Simulation time 12553990322 ps
CPU time 14.87 seconds
Started Jun 24 04:37:20 PM PDT 24
Finished Jun 24 04:38:19 PM PDT 24
Peak memory 200492 kb
Host smart-51252aa8-34ba-494f-964a-a96a6dc2687d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635062322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.2635062322
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_perf.1085119445
Short name T432
Test name
Test status
Simulation time 15261300776 ps
CPU time 777.74 seconds
Started Jun 24 04:37:25 PM PDT 24
Finished Jun 24 04:51:11 PM PDT 24
Peak memory 200504 kb
Host smart-3253cf30-73b9-48e0-88d6-c21d6cfdeebd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1085119445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.1085119445
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.1656634827
Short name T407
Test name
Test status
Simulation time 5708663321 ps
CPU time 49.4 seconds
Started Jun 24 04:37:19 PM PDT 24
Finished Jun 24 04:38:53 PM PDT 24
Peak memory 198756 kb
Host smart-a7cf8759-ba46-42e5-a7ed-53ec01de79e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1656634827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.1656634827
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.2221161503
Short name T1097
Test name
Test status
Simulation time 91954576930 ps
CPU time 142.69 seconds
Started Jun 24 04:37:19 PM PDT 24
Finished Jun 24 04:40:26 PM PDT 24
Peak memory 200604 kb
Host smart-c9104f8e-31f7-4961-a5b5-f5ddc4ffca1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221161503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.2221161503
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.148536285
Short name T874
Test name
Test status
Simulation time 2987464295 ps
CPU time 0.95 seconds
Started Jun 24 04:37:29 PM PDT 24
Finished Jun 24 04:38:20 PM PDT 24
Peak memory 196396 kb
Host smart-498fe37f-8f9a-4e1b-969b-ae37c999c564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148536285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.148536285
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.471199685
Short name T280
Test name
Test status
Simulation time 101415289 ps
CPU time 0.85 seconds
Started Jun 24 04:37:18 PM PDT 24
Finished Jun 24 04:38:01 PM PDT 24
Peak memory 198408 kb
Host smart-6e3724bf-e111-4902-8c74-da590552f0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471199685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.471199685
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.2084954659
Short name T29
Test name
Test status
Simulation time 26431625255 ps
CPU time 585.6 seconds
Started Jun 24 04:37:21 PM PDT 24
Finished Jun 24 04:47:50 PM PDT 24
Peak memory 216560 kb
Host smart-66aa9e41-6fbe-4030-9332-b40906bc94b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084954659 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.2084954659
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.1649662555
Short name T271
Test name
Test status
Simulation time 12001162161 ps
CPU time 21.91 seconds
Started Jun 24 04:37:24 PM PDT 24
Finished Jun 24 04:38:35 PM PDT 24
Peak memory 200532 kb
Host smart-297583e6-6c03-43f2-bd5c-4540b25626ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649662555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.1649662555
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.2682279262
Short name T855
Test name
Test status
Simulation time 84047933273 ps
CPU time 36.77 seconds
Started Jun 24 04:37:19 PM PDT 24
Finished Jun 24 04:38:41 PM PDT 24
Peak memory 200568 kb
Host smart-c897c7e6-6e34-4ce9-bb3d-939782fc5a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682279262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.2682279262
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.2149793215
Short name T551
Test name
Test status
Simulation time 65819366 ps
CPU time 0.57 seconds
Started Jun 24 04:37:29 PM PDT 24
Finished Jun 24 04:38:25 PM PDT 24
Peak memory 194456 kb
Host smart-cf950e87-aa58-4312-9c0f-aa2e9dbbdce1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149793215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.2149793215
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.3864725517
Short name T1052
Test name
Test status
Simulation time 137980702762 ps
CPU time 73.18 seconds
Started Jun 24 04:37:19 PM PDT 24
Finished Jun 24 04:39:17 PM PDT 24
Peak memory 200544 kb
Host smart-5875f2a3-b58c-4635-83a8-58a05e4eb52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864725517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.3864725517
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.1075189740
Short name T900
Test name
Test status
Simulation time 10666555095 ps
CPU time 16.66 seconds
Started Jun 24 04:37:28 PM PDT 24
Finished Jun 24 04:38:35 PM PDT 24
Peak memory 200036 kb
Host smart-e9dc2440-4e09-47bf-a984-c74978a95a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075189740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.1075189740
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.500599029
Short name T938
Test name
Test status
Simulation time 347838682004 ps
CPU time 41.21 seconds
Started Jun 24 04:37:24 PM PDT 24
Finished Jun 24 04:38:55 PM PDT 24
Peak memory 200384 kb
Host smart-dbdfda59-004d-458c-8faf-62c10db52cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500599029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.500599029
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.3019206008
Short name T638
Test name
Test status
Simulation time 13411397399 ps
CPU time 24.88 seconds
Started Jun 24 04:37:29 PM PDT 24
Finished Jun 24 04:38:48 PM PDT 24
Peak memory 200448 kb
Host smart-956cafec-eed2-419a-b29d-6e0dc5bc1ed7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019206008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.3019206008
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.1123838503
Short name T882
Test name
Test status
Simulation time 132285233877 ps
CPU time 293.45 seconds
Started Jun 24 04:37:28 PM PDT 24
Finished Jun 24 04:43:12 PM PDT 24
Peak memory 200412 kb
Host smart-778cba66-4170-4cdc-9312-806a12a4788b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1123838503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.1123838503
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.1555414948
Short name T417
Test name
Test status
Simulation time 933445175 ps
CPU time 0.97 seconds
Started Jun 24 04:37:28 PM PDT 24
Finished Jun 24 04:38:20 PM PDT 24
Peak memory 196508 kb
Host smart-22acadfa-f9f0-4ebf-a437-47b462c31bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555414948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.1555414948
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.2272201147
Short name T961
Test name
Test status
Simulation time 5526546864 ps
CPU time 48.15 seconds
Started Jun 24 04:37:25 PM PDT 24
Finished Jun 24 04:39:02 PM PDT 24
Peak memory 198748 kb
Host smart-f075acc2-da37-47de-ad24-e8c43715b83b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2272201147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.2272201147
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.3061043790
Short name T1017
Test name
Test status
Simulation time 92746924936 ps
CPU time 168.59 seconds
Started Jun 24 04:37:30 PM PDT 24
Finished Jun 24 04:41:13 PM PDT 24
Peak memory 200520 kb
Host smart-b20989a4-b361-4e44-8cbb-2bf60df91a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061043790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.3061043790
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.3956499145
Short name T321
Test name
Test status
Simulation time 53089060972 ps
CPU time 31.98 seconds
Started Jun 24 04:37:28 PM PDT 24
Finished Jun 24 04:38:51 PM PDT 24
Peak memory 196344 kb
Host smart-fdc5a46d-e032-41ac-af03-f4a634b49de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956499145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.3956499145
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.3583762271
Short name T659
Test name
Test status
Simulation time 801974658 ps
CPU time 1.1 seconds
Started Jun 24 04:37:29 PM PDT 24
Finished Jun 24 04:38:20 PM PDT 24
Peak memory 198808 kb
Host smart-bc45aa90-cc85-43fe-bcdd-8fb3f2378e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583762271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3583762271
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.3672607158
Short name T320
Test name
Test status
Simulation time 58493669336 ps
CPU time 550.32 seconds
Started Jun 24 04:37:27 PM PDT 24
Finished Jun 24 04:47:29 PM PDT 24
Peak memory 216992 kb
Host smart-ece18d1d-3b9e-44cd-a0c1-f447178f2d96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672607158 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.3672607158
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.1248963002
Short name T287
Test name
Test status
Simulation time 1112372686 ps
CPU time 5.2 seconds
Started Jun 24 04:37:30 PM PDT 24
Finished Jun 24 04:38:30 PM PDT 24
Peak memory 200484 kb
Host smart-6aaaa967-5c64-47ca-9260-b140fcc0edab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248963002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.1248963002
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.3232846808
Short name T1006
Test name
Test status
Simulation time 30292324463 ps
CPU time 59.09 seconds
Started Jun 24 04:37:20 PM PDT 24
Finished Jun 24 04:39:04 PM PDT 24
Peak memory 200496 kb
Host smart-535fc569-a2be-4061-8e3a-693eb0d7c900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232846808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.3232846808
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.2333836722
Short name T787
Test name
Test status
Simulation time 13476930 ps
CPU time 0.55 seconds
Started Jun 24 04:37:28 PM PDT 24
Finished Jun 24 04:38:19 PM PDT 24
Peak memory 195884 kb
Host smart-4204d7f8-b67a-4150-8e9a-a5f0aaa3c48c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333836722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.2333836722
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.2776406263
Short name T51
Test name
Test status
Simulation time 100814895967 ps
CPU time 39.69 seconds
Started Jun 24 04:37:30 PM PDT 24
Finished Jun 24 04:39:04 PM PDT 24
Peak memory 200520 kb
Host smart-094b4f15-7084-415f-a088-5c9551c3b095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776406263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.2776406263
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.271295682
Short name T668
Test name
Test status
Simulation time 104154273678 ps
CPU time 36.44 seconds
Started Jun 24 04:37:28 PM PDT 24
Finished Jun 24 04:38:55 PM PDT 24
Peak memory 200464 kb
Host smart-0ad15dbc-239f-439b-ac5f-eedb8bf01d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271295682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.271295682
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.3828620145
Short name T201
Test name
Test status
Simulation time 211780323474 ps
CPU time 94.05 seconds
Started Jun 24 04:37:27 PM PDT 24
Finished Jun 24 04:39:52 PM PDT 24
Peak memory 200544 kb
Host smart-6183b514-7b0d-41a0-b557-559bdd4d32cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828620145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.3828620145
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.1435200114
Short name T664
Test name
Test status
Simulation time 345967173121 ps
CPU time 363.35 seconds
Started Jun 24 04:37:28 PM PDT 24
Finished Jun 24 04:44:23 PM PDT 24
Peak memory 200528 kb
Host smart-976b52ad-c069-4d1a-a651-d20b9a4d11a1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435200114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.1435200114
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.3999290633
Short name T640
Test name
Test status
Simulation time 75545542807 ps
CPU time 181.33 seconds
Started Jun 24 04:37:27 PM PDT 24
Finished Jun 24 04:41:20 PM PDT 24
Peak memory 200592 kb
Host smart-07a66684-b41a-40ae-b0ba-1e1420044c56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3999290633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.3999290633
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.217013540
Short name T465
Test name
Test status
Simulation time 24185936 ps
CPU time 0.62 seconds
Started Jun 24 04:37:32 PM PDT 24
Finished Jun 24 04:38:26 PM PDT 24
Peak memory 196428 kb
Host smart-fef6a374-fb95-4803-86cf-979d769fd9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217013540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.217013540
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_perf.1051842861
Short name T824
Test name
Test status
Simulation time 14405349192 ps
CPU time 73.76 seconds
Started Jun 24 04:38:03 PM PDT 24
Finished Jun 24 04:40:21 PM PDT 24
Peak memory 200164 kb
Host smart-882273f1-3859-49e7-98ae-0f840d2a94a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1051842861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.1051842861
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.869580367
Short name T860
Test name
Test status
Simulation time 4525459572 ps
CPU time 10 seconds
Started Jun 24 04:37:30 PM PDT 24
Finished Jun 24 04:38:35 PM PDT 24
Peak memory 198640 kb
Host smart-f5ac4473-e22a-4911-870f-c5be75b030f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=869580367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.869580367
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.743659253
Short name T142
Test name
Test status
Simulation time 17350829598 ps
CPU time 14.14 seconds
Started Jun 24 04:37:25 PM PDT 24
Finished Jun 24 04:38:28 PM PDT 24
Peak memory 200504 kb
Host smart-d4ecf737-9cbf-4580-a7ab-8c6a48d0c40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743659253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.743659253
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.1428116536
Short name T918
Test name
Test status
Simulation time 44933482011 ps
CPU time 9.8 seconds
Started Jun 24 04:37:27 PM PDT 24
Finished Jun 24 04:38:28 PM PDT 24
Peak memory 196596 kb
Host smart-f7ea3b88-7d57-4d87-ac29-25aab548100f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428116536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.1428116536
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.3093288736
Short name T781
Test name
Test status
Simulation time 297198062 ps
CPU time 0.95 seconds
Started Jun 24 04:37:28 PM PDT 24
Finished Jun 24 04:38:20 PM PDT 24
Peak memory 199068 kb
Host smart-c2766fe4-bbb9-44e4-a68e-21bfd4c1fd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093288736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.3093288736
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.1429435674
Short name T691
Test name
Test status
Simulation time 174606668707 ps
CPU time 191.57 seconds
Started Jun 24 04:37:28 PM PDT 24
Finished Jun 24 04:41:31 PM PDT 24
Peak memory 200492 kb
Host smart-aecc6ff5-39e0-4cef-b76c-814999bb10bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429435674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.1429435674
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.2943004833
Short name T545
Test name
Test status
Simulation time 26027046500 ps
CPU time 134.37 seconds
Started Jun 24 04:37:30 PM PDT 24
Finished Jun 24 04:40:39 PM PDT 24
Peak memory 208856 kb
Host smart-7587690a-3b46-453d-ba43-8be8199c1bd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943004833 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.2943004833
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.3457048603
Short name T921
Test name
Test status
Simulation time 3225439053 ps
CPU time 2.2 seconds
Started Jun 24 04:38:03 PM PDT 24
Finished Jun 24 04:39:10 PM PDT 24
Peak memory 199316 kb
Host smart-b73c7ef8-f0b4-41b9-a152-d17be37e250e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457048603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.3457048603
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.2552294782
Short name T1003
Test name
Test status
Simulation time 60105242487 ps
CPU time 104.27 seconds
Started Jun 24 04:37:28 PM PDT 24
Finished Jun 24 04:40:03 PM PDT 24
Peak memory 200552 kb
Host smart-8f65ca9f-0b7e-49ee-9c3a-570afc9c41d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552294782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.2552294782
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.4058332059
Short name T113
Test name
Test status
Simulation time 13391178 ps
CPU time 0.58 seconds
Started Jun 24 04:35:17 PM PDT 24
Finished Jun 24 04:35:20 PM PDT 24
Peak memory 195860 kb
Host smart-b6be585c-caff-405a-8b1f-8453e3f10ded
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058332059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.4058332059
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.1783379813
Short name T764
Test name
Test status
Simulation time 119748845746 ps
CPU time 187.69 seconds
Started Jun 24 04:35:07 PM PDT 24
Finished Jun 24 04:38:16 PM PDT 24
Peak memory 200524 kb
Host smart-756318c4-cdfc-44a8-a9e6-c7218faba56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783379813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.1783379813
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.2582049846
Short name T1000
Test name
Test status
Simulation time 81435238957 ps
CPU time 100.22 seconds
Started Jun 24 04:35:09 PM PDT 24
Finished Jun 24 04:36:50 PM PDT 24
Peak memory 200520 kb
Host smart-34adbf49-1947-4913-8ad5-27b5536c0c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582049846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.2582049846
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_intr.1103719508
Short name T472
Test name
Test status
Simulation time 112629291632 ps
CPU time 67.8 seconds
Started Jun 24 04:35:16 PM PDT 24
Finished Jun 24 04:36:26 PM PDT 24
Peak memory 200528 kb
Host smart-cef4587b-4bab-49a5-96d0-ae146499c5d7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103719508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.1103719508
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.3603684353
Short name T862
Test name
Test status
Simulation time 52251491605 ps
CPU time 205.19 seconds
Started Jun 24 04:35:22 PM PDT 24
Finished Jun 24 04:38:48 PM PDT 24
Peak memory 200480 kb
Host smart-f655ed50-ff51-4509-92df-d35baf0a6a1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3603684353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.3603684353
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.3911817698
Short name T1016
Test name
Test status
Simulation time 14215791287 ps
CPU time 24.57 seconds
Started Jun 24 04:35:12 PM PDT 24
Finished Jun 24 04:35:38 PM PDT 24
Peak memory 199960 kb
Host smart-e8a7e638-43f2-4435-8b3a-76db08c566b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911817698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.3911817698
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_perf.332998908
Short name T837
Test name
Test status
Simulation time 8269515651 ps
CPU time 113.74 seconds
Started Jun 24 04:35:14 PM PDT 24
Finished Jun 24 04:37:10 PM PDT 24
Peak memory 200440 kb
Host smart-0b851792-f0d4-4c46-8f09-08b9fcecb44d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=332998908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.332998908
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.816826990
Short name T592
Test name
Test status
Simulation time 6358208302 ps
CPU time 10.46 seconds
Started Jun 24 04:35:10 PM PDT 24
Finished Jun 24 04:35:29 PM PDT 24
Peak memory 198648 kb
Host smart-cc35170a-f95e-497b-aac4-b6940b9d9456
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=816826990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.816826990
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.1973146436
Short name T935
Test name
Test status
Simulation time 15736037092 ps
CPU time 30.59 seconds
Started Jun 24 04:35:14 PM PDT 24
Finished Jun 24 04:35:47 PM PDT 24
Peak memory 200440 kb
Host smart-298d308d-9aeb-4062-84c4-4e31f71fdb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973146436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.1973146436
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.2653148713
Short name T549
Test name
Test status
Simulation time 1950165525 ps
CPU time 3.77 seconds
Started Jun 24 04:35:17 PM PDT 24
Finished Jun 24 04:35:23 PM PDT 24
Peak memory 195920 kb
Host smart-00b71138-fdc7-4f83-86f4-5cdefe91a319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653148713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.2653148713
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.2300760915
Short name T866
Test name
Test status
Simulation time 535899022 ps
CPU time 2.14 seconds
Started Jun 24 04:35:29 PM PDT 24
Finished Jun 24 04:35:32 PM PDT 24
Peak memory 199004 kb
Host smart-8c326f01-65b6-4dc5-8734-8bc55d5420c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300760915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.2300760915
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.2167408219
Short name T871
Test name
Test status
Simulation time 153313993842 ps
CPU time 134.61 seconds
Started Jun 24 04:35:30 PM PDT 24
Finished Jun 24 04:37:45 PM PDT 24
Peak memory 200548 kb
Host smart-5a3534bf-c882-4caa-8ce9-ecb8c22d74ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167408219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.2167408219
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.1274636445
Short name T319
Test name
Test status
Simulation time 2760904617 ps
CPU time 2.58 seconds
Started Jun 24 04:35:09 PM PDT 24
Finished Jun 24 04:35:12 PM PDT 24
Peak memory 200460 kb
Host smart-d6a808e0-0703-462e-a2e9-5653ff4b8977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274636445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.1274636445
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.3087778868
Short name T788
Test name
Test status
Simulation time 18908983844 ps
CPU time 15.01 seconds
Started Jun 24 04:35:07 PM PDT 24
Finished Jun 24 04:35:23 PM PDT 24
Peak memory 197652 kb
Host smart-738f2bdb-96f0-4a55-8013-76ba9d2af88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087778868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.3087778868
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.3126764182
Short name T602
Test name
Test status
Simulation time 118417210989 ps
CPU time 170.7 seconds
Started Jun 24 04:37:26 PM PDT 24
Finished Jun 24 04:41:05 PM PDT 24
Peak memory 200628 kb
Host smart-c0558128-ac86-418d-9b16-969a81d88d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126764182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.3126764182
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.3457313779
Short name T1039
Test name
Test status
Simulation time 116480574871 ps
CPU time 19.62 seconds
Started Jun 24 04:38:02 PM PDT 24
Finished Jun 24 04:39:27 PM PDT 24
Peak memory 200220 kb
Host smart-2c860034-1971-47b8-a601-59ff7166b397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457313779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.3457313779
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.1035930354
Short name T792
Test name
Test status
Simulation time 50340591274 ps
CPU time 840.47 seconds
Started Jun 24 04:37:35 PM PDT 24
Finished Jun 24 04:52:30 PM PDT 24
Peak memory 217384 kb
Host smart-6dba3b6f-3362-4082-b1e9-3f2e19bcd01e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035930354 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.1035930354
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.2841455718
Short name T1092
Test name
Test status
Simulation time 129120524812 ps
CPU time 43.81 seconds
Started Jun 24 04:37:34 PM PDT 24
Finished Jun 24 04:39:13 PM PDT 24
Peak memory 200452 kb
Host smart-4fb298a2-0a36-496f-a7fa-45e42f54d23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841455718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.2841455718
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.3980812969
Short name T332
Test name
Test status
Simulation time 208330074137 ps
CPU time 1002.14 seconds
Started Jun 24 04:37:35 PM PDT 24
Finished Jun 24 04:55:12 PM PDT 24
Peak memory 225972 kb
Host smart-cb32d1e9-37b2-4f58-829c-bcc7b2d84555
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980812969 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.3980812969
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.1865594979
Short name T210
Test name
Test status
Simulation time 17039378648 ps
CPU time 26.4 seconds
Started Jun 24 04:37:36 PM PDT 24
Finished Jun 24 04:38:56 PM PDT 24
Peak memory 200432 kb
Host smart-26a58ed0-234f-4f9c-b3a8-67d09b18c864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865594979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.1865594979
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.2268811825
Short name T53
Test name
Test status
Simulation time 134957819978 ps
CPU time 2069.05 seconds
Started Jun 24 04:37:35 PM PDT 24
Finished Jun 24 05:12:59 PM PDT 24
Peak memory 227220 kb
Host smart-468f4967-7f55-41da-bc61-773de119e671
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268811825 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.2268811825
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.2111067201
Short name T929
Test name
Test status
Simulation time 9733738559 ps
CPU time 31.63 seconds
Started Jun 24 04:37:35 PM PDT 24
Finished Jun 24 04:39:01 PM PDT 24
Peak memory 200472 kb
Host smart-2c549efa-d3c9-4d10-8e0f-726e65333d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111067201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.2111067201
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.2244258892
Short name T55
Test name
Test status
Simulation time 289506184145 ps
CPU time 1240.72 seconds
Started Jun 24 04:37:36 PM PDT 24
Finished Jun 24 04:59:15 PM PDT 24
Peak memory 231348 kb
Host smart-1bf53abf-2dc3-4468-a410-ba9847695b3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244258892 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.2244258892
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.2247423527
Short name T288
Test name
Test status
Simulation time 168566049778 ps
CPU time 116.17 seconds
Started Jun 24 04:37:38 PM PDT 24
Finished Jun 24 04:40:30 PM PDT 24
Peak memory 200508 kb
Host smart-7ce9405f-3e02-4ccc-adfc-e1923926801c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247423527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.2247423527
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.1923303754
Short name T95
Test name
Test status
Simulation time 90155519526 ps
CPU time 34.63 seconds
Started Jun 24 04:37:34 PM PDT 24
Finished Jun 24 04:39:04 PM PDT 24
Peak memory 200524 kb
Host smart-9047f93c-3e47-4162-856f-af6c2959d3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923303754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.1923303754
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.2600217682
Short name T235
Test name
Test status
Simulation time 31430201004 ps
CPU time 24.33 seconds
Started Jun 24 04:37:37 PM PDT 24
Finished Jun 24 04:38:58 PM PDT 24
Peak memory 200452 kb
Host smart-3eb94d2b-4ee6-4fef-ad63-335eaec7fe43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600217682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.2600217682
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.2675455228
Short name T99
Test name
Test status
Simulation time 77976119492 ps
CPU time 135.09 seconds
Started Jun 24 04:37:36 PM PDT 24
Finished Jun 24 04:40:45 PM PDT 24
Peak memory 217060 kb
Host smart-d78d55e4-a8b6-4014-9278-4c06e8fa862e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675455228 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.2675455228
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.2455384785
Short name T226
Test name
Test status
Simulation time 10282272809 ps
CPU time 18.11 seconds
Started Jun 24 04:37:37 PM PDT 24
Finished Jun 24 04:38:52 PM PDT 24
Peak memory 200512 kb
Host smart-88ea50d1-77d8-4412-9390-470af371f1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455384785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.2455384785
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.2938752568
Short name T728
Test name
Test status
Simulation time 22681753128 ps
CPU time 233.95 seconds
Started Jun 24 04:37:35 PM PDT 24
Finished Jun 24 04:42:23 PM PDT 24
Peak memory 217036 kb
Host smart-6ced55b0-2654-4a50-97b8-577b877aff70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938752568 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.2938752568
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.3893785263
Short name T282
Test name
Test status
Simulation time 59260858189 ps
CPU time 35.48 seconds
Started Jun 24 04:37:35 PM PDT 24
Finished Jun 24 04:39:05 PM PDT 24
Peak memory 200560 kb
Host smart-c4b343df-4941-4994-8848-88eb61cc5362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893785263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.3893785263
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.356181938
Short name T720
Test name
Test status
Simulation time 20860124584 ps
CPU time 377.77 seconds
Started Jun 24 04:37:37 PM PDT 24
Finished Jun 24 04:44:52 PM PDT 24
Peak memory 216656 kb
Host smart-3c7af089-7e59-4ede-ac2c-e01273a78c36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356181938 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.356181938
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.3945727751
Short name T512
Test name
Test status
Simulation time 13296467 ps
CPU time 0.67 seconds
Started Jun 24 04:35:32 PM PDT 24
Finished Jun 24 04:35:34 PM PDT 24
Peak memory 195284 kb
Host smart-7331341a-2918-47c2-8d7d-7ec32b7614bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945727751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.3945727751
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.1169613211
Short name T743
Test name
Test status
Simulation time 60529981875 ps
CPU time 99.46 seconds
Started Jun 24 04:35:28 PM PDT 24
Finished Jun 24 04:37:09 PM PDT 24
Peak memory 200520 kb
Host smart-c71b63d0-d992-4bc1-b656-542d9ff4f24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169613211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.1169613211
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.2258996340
Short name T762
Test name
Test status
Simulation time 30481304098 ps
CPU time 12.16 seconds
Started Jun 24 04:35:11 PM PDT 24
Finished Jun 24 04:35:24 PM PDT 24
Peak memory 200864 kb
Host smart-c61f568e-ac7d-48e1-bba3-e5fd16782ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258996340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.2258996340
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.1501533750
Short name T273
Test name
Test status
Simulation time 95593026302 ps
CPU time 136.83 seconds
Started Jun 24 04:35:14 PM PDT 24
Finished Jun 24 04:37:33 PM PDT 24
Peak memory 200524 kb
Host smart-543ed1f0-ebbe-4999-b942-6edaec75ef96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501533750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.1501533750
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.1059613075
Short name T122
Test name
Test status
Simulation time 51489797958 ps
CPU time 26.1 seconds
Started Jun 24 04:35:11 PM PDT 24
Finished Jun 24 04:35:39 PM PDT 24
Peak memory 200440 kb
Host smart-904ffb1e-b266-4f00-b1c5-96684c943827
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059613075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.1059613075
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.3594780469
Short name T1036
Test name
Test status
Simulation time 122684319203 ps
CPU time 202.67 seconds
Started Jun 24 04:35:11 PM PDT 24
Finished Jun 24 04:38:35 PM PDT 24
Peak memory 200504 kb
Host smart-0be664b7-d757-47e6-a9dd-23d682e2851f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3594780469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.3594780469
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.3575897548
Short name T678
Test name
Test status
Simulation time 3565734681 ps
CPU time 2.8 seconds
Started Jun 24 04:35:11 PM PDT 24
Finished Jun 24 04:35:15 PM PDT 24
Peak memory 199236 kb
Host smart-f446ed50-944c-4f58-9abf-edf60264837a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575897548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.3575897548
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_perf.3923847084
Short name T622
Test name
Test status
Simulation time 9580752650 ps
CPU time 25.03 seconds
Started Jun 24 04:35:20 PM PDT 24
Finished Jun 24 04:35:46 PM PDT 24
Peak memory 200440 kb
Host smart-f067fc35-1f90-4b5f-91f3-01cc3425e6c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3923847084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.3923847084
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.1604186208
Short name T44
Test name
Test status
Simulation time 4765560575 ps
CPU time 18.09 seconds
Started Jun 24 04:35:22 PM PDT 24
Finished Jun 24 04:35:41 PM PDT 24
Peak memory 199700 kb
Host smart-0a10f6fe-ca8b-4e00-a4c0-ca740571ace6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1604186208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.1604186208
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.2537945964
Short name T590
Test name
Test status
Simulation time 143243224213 ps
CPU time 54.1 seconds
Started Jun 24 04:35:15 PM PDT 24
Finished Jun 24 04:36:12 PM PDT 24
Peak memory 200836 kb
Host smart-8c40c5a4-ffc4-43b0-b221-3bc0eca17099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537945964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.2537945964
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.2727753525
Short name T371
Test name
Test status
Simulation time 44649153512 ps
CPU time 15.96 seconds
Started Jun 24 04:35:10 PM PDT 24
Finished Jun 24 04:35:28 PM PDT 24
Peak memory 196588 kb
Host smart-d42b1cff-5a4b-4d93-9b94-1d703e8df9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727753525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.2727753525
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.52049779
Short name T780
Test name
Test status
Simulation time 470316889 ps
CPU time 2.08 seconds
Started Jun 24 04:35:13 PM PDT 24
Finished Jun 24 04:35:16 PM PDT 24
Peak memory 200096 kb
Host smart-f29ad185-abd3-4808-a03a-917288c051fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52049779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.52049779
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.2030728310
Short name T197
Test name
Test status
Simulation time 170593112073 ps
CPU time 1053.56 seconds
Started Jun 24 04:35:13 PM PDT 24
Finished Jun 24 04:52:48 PM PDT 24
Peak memory 216952 kb
Host smart-bdd4dada-9210-4ff6-8547-545d2577c7ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030728310 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.2030728310
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.2343576243
Short name T110
Test name
Test status
Simulation time 7620979276 ps
CPU time 17.27 seconds
Started Jun 24 04:35:15 PM PDT 24
Finished Jun 24 04:35:35 PM PDT 24
Peak memory 200660 kb
Host smart-a361fd1e-8081-4a90-b7c9-56330a886c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343576243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.2343576243
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.1573086871
Short name T732
Test name
Test status
Simulation time 10573996689 ps
CPU time 19.74 seconds
Started Jun 24 04:35:07 PM PDT 24
Finished Jun 24 04:35:28 PM PDT 24
Peak memory 200464 kb
Host smart-2bbf353f-d405-4efb-ae93-d17afe41340f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573086871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.1573086871
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.1250277962
Short name T119
Test name
Test status
Simulation time 109761497155 ps
CPU time 44.1 seconds
Started Jun 24 04:37:37 PM PDT 24
Finished Jun 24 04:39:18 PM PDT 24
Peak memory 200576 kb
Host smart-6bbe211e-d351-44c7-805c-e8060261053c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250277962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.1250277962
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.75377444
Short name T106
Test name
Test status
Simulation time 8625800182 ps
CPU time 89.2 seconds
Started Jun 24 04:37:37 PM PDT 24
Finished Jun 24 04:40:03 PM PDT 24
Peak memory 208800 kb
Host smart-1b4528ae-0058-43e6-b16c-c4cc3bf57e53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75377444 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.75377444
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.1001221194
Short name T580
Test name
Test status
Simulation time 17409449214 ps
CPU time 11.17 seconds
Started Jun 24 04:37:35 PM PDT 24
Finished Jun 24 04:38:41 PM PDT 24
Peak memory 200604 kb
Host smart-0610196c-6b68-4d34-81bc-18a938332a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001221194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.1001221194
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.2213247388
Short name T660
Test name
Test status
Simulation time 359416339548 ps
CPU time 495.02 seconds
Started Jun 24 04:37:37 PM PDT 24
Finished Jun 24 04:46:49 PM PDT 24
Peak memory 217036 kb
Host smart-e1d99b38-d2b2-4302-9940-8e233d3b19f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213247388 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.2213247388
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.2133862674
Short name T245
Test name
Test status
Simulation time 157126947875 ps
CPU time 111.21 seconds
Started Jun 24 04:37:36 PM PDT 24
Finished Jun 24 04:40:25 PM PDT 24
Peak memory 200540 kb
Host smart-e3e74690-43cf-40a2-a98f-071e68c49cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133862674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.2133862674
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.3686124397
Short name T1054
Test name
Test status
Simulation time 61743482574 ps
CPU time 632.53 seconds
Started Jun 24 04:37:34 PM PDT 24
Finished Jun 24 04:49:02 PM PDT 24
Peak memory 208872 kb
Host smart-13ddcb27-a181-4ff9-82b4-de349b097d7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686124397 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.3686124397
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.3971087517
Short name T120
Test name
Test status
Simulation time 87433111746 ps
CPU time 147.73 seconds
Started Jun 24 04:37:35 PM PDT 24
Finished Jun 24 04:40:57 PM PDT 24
Peak memory 200540 kb
Host smart-c4682493-fbc7-450e-966e-a4a0a7030af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971087517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.3971087517
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.2804166261
Short name T352
Test name
Test status
Simulation time 9036348637 ps
CPU time 7.68 seconds
Started Jun 24 04:37:37 PM PDT 24
Finished Jun 24 04:38:42 PM PDT 24
Peak memory 199192 kb
Host smart-c327f213-5ffa-4737-9fcf-df8869aa2655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804166261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.2804166261
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.204758145
Short name T212
Test name
Test status
Simulation time 31322684839 ps
CPU time 52.56 seconds
Started Jun 24 04:37:38 PM PDT 24
Finished Jun 24 04:39:27 PM PDT 24
Peak memory 200464 kb
Host smart-461a18ec-b1ab-41f5-a277-35a67cbad20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204758145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.204758145
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.2573552622
Short name T396
Test name
Test status
Simulation time 132336895646 ps
CPU time 904.54 seconds
Started Jun 24 04:37:37 PM PDT 24
Finished Jun 24 04:53:39 PM PDT 24
Peak memory 216088 kb
Host smart-d59a26e6-9cf5-4af4-a61d-cf026fea63d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573552622 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.2573552622
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.1897174051
Short name T754
Test name
Test status
Simulation time 63432441303 ps
CPU time 7.53 seconds
Started Jun 24 04:37:38 PM PDT 24
Finished Jun 24 04:38:42 PM PDT 24
Peak memory 200260 kb
Host smart-9e43bef5-66d6-47d1-b7c9-0d725063e013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897174051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.1897174051
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.752189415
Short name T447
Test name
Test status
Simulation time 57839376637 ps
CPU time 927.81 seconds
Started Jun 24 04:37:37 PM PDT 24
Finished Jun 24 04:54:02 PM PDT 24
Peak memory 212972 kb
Host smart-c6513521-5f09-4dd4-b5a4-fb3a61ba3f91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752189415 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.752189415
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.2658504185
Short name T805
Test name
Test status
Simulation time 17608307198 ps
CPU time 28.59 seconds
Started Jun 24 04:37:38 PM PDT 24
Finished Jun 24 04:39:03 PM PDT 24
Peak memory 200472 kb
Host smart-470f26c3-6491-4a0f-b85c-4c38a263a569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658504185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.2658504185
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.4220222871
Short name T227
Test name
Test status
Simulation time 123435414489 ps
CPU time 179.62 seconds
Started Jun 24 04:37:39 PM PDT 24
Finished Jun 24 04:41:34 PM PDT 24
Peak memory 200512 kb
Host smart-bd828520-c752-42d1-a41a-8ec22818ff49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220222871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.4220222871
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.1322659624
Short name T34
Test name
Test status
Simulation time 29902190488 ps
CPU time 180.02 seconds
Started Jun 24 04:37:40 PM PDT 24
Finished Jun 24 04:41:38 PM PDT 24
Peak memory 208768 kb
Host smart-e284c1bf-b568-434c-a708-c05d9555a748
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322659624 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.1322659624
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.2641707934
Short name T155
Test name
Test status
Simulation time 129825460703 ps
CPU time 100.58 seconds
Started Jun 24 04:37:39 PM PDT 24
Finished Jun 24 04:40:15 PM PDT 24
Peak memory 200432 kb
Host smart-8650c673-cfce-4241-97e1-17003d054417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641707934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.2641707934
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.920157027
Short name T404
Test name
Test status
Simulation time 35846187 ps
CPU time 0.61 seconds
Started Jun 24 04:35:23 PM PDT 24
Finished Jun 24 04:35:24 PM PDT 24
Peak memory 195860 kb
Host smart-6fcca91e-a5bc-423b-8954-03d76f5e2ce6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920157027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.920157027
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.2202268787
Short name T906
Test name
Test status
Simulation time 60461998405 ps
CPU time 60.76 seconds
Started Jun 24 04:35:13 PM PDT 24
Finished Jun 24 04:36:16 PM PDT 24
Peak memory 200524 kb
Host smart-3b8a8498-587a-4344-8d8b-0d251b98ec68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202268787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.2202268787
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.3865256003
Short name T178
Test name
Test status
Simulation time 187597262973 ps
CPU time 118.48 seconds
Started Jun 24 04:35:32 PM PDT 24
Finished Jun 24 04:37:32 PM PDT 24
Peak memory 200572 kb
Host smart-82087b43-fd14-4b05-beb1-e2d0074224b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865256003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.3865256003
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.4207408002
Short name T216
Test name
Test status
Simulation time 148230087373 ps
CPU time 58.7 seconds
Started Jun 24 04:35:14 PM PDT 24
Finished Jun 24 04:36:15 PM PDT 24
Peak memory 200424 kb
Host smart-0884c7ae-d3cf-4ea5-90af-f3e366d75b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207408002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.4207408002
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.1993881860
Short name T20
Test name
Test status
Simulation time 44536900237 ps
CPU time 42.71 seconds
Started Jun 24 04:35:14 PM PDT 24
Finished Jun 24 04:35:59 PM PDT 24
Peak memory 200360 kb
Host smart-18c0cdb3-ec85-46d1-9b3d-4a54ef6fca2c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993881860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.1993881860
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.313849148
Short name T462
Test name
Test status
Simulation time 170984380253 ps
CPU time 361.45 seconds
Started Jun 24 04:35:28 PM PDT 24
Finished Jun 24 04:41:30 PM PDT 24
Peak memory 200628 kb
Host smart-5e386dd1-44e9-4bba-8cdf-82a4d9d505fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=313849148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.313849148
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.3515147149
Short name T454
Test name
Test status
Simulation time 8305271713 ps
CPU time 7.24 seconds
Started Jun 24 04:35:09 PM PDT 24
Finished Jun 24 04:35:17 PM PDT 24
Peak memory 200400 kb
Host smart-a5cf5bda-470d-4eb0-8510-fa842b8e9223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515147149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.3515147149
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_perf.2563915448
Short name T387
Test name
Test status
Simulation time 14538723562 ps
CPU time 446.9 seconds
Started Jun 24 04:35:15 PM PDT 24
Finished Jun 24 04:42:45 PM PDT 24
Peak memory 200496 kb
Host smart-4c3d0a2d-cc7c-4022-9854-75859a304d45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2563915448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.2563915448
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.334901475
Short name T618
Test name
Test status
Simulation time 1905748778 ps
CPU time 7.19 seconds
Started Jun 24 04:35:13 PM PDT 24
Finished Jun 24 04:35:22 PM PDT 24
Peak memory 198576 kb
Host smart-16526901-ba84-40a9-9169-242e8459d06d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=334901475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.334901475
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.643352187
Short name T705
Test name
Test status
Simulation time 68663035346 ps
CPU time 49.13 seconds
Started Jun 24 04:35:13 PM PDT 24
Finished Jun 24 04:36:04 PM PDT 24
Peak memory 200276 kb
Host smart-aad8f3e8-dcb1-4a27-bae6-e878f4d067e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643352187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.643352187
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.196844677
Short name T470
Test name
Test status
Simulation time 38939640139 ps
CPU time 64.87 seconds
Started Jun 24 04:35:22 PM PDT 24
Finished Jun 24 04:36:28 PM PDT 24
Peak memory 196328 kb
Host smart-bbef3bd3-de36-4730-9922-8c166f6c337d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196844677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.196844677
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.2742406465
Short name T1090
Test name
Test status
Simulation time 947986468 ps
CPU time 2.43 seconds
Started Jun 24 04:35:26 PM PDT 24
Finished Jun 24 04:35:29 PM PDT 24
Peak memory 199920 kb
Host smart-9eeacc3f-001f-4aea-bc8c-43ad56be52a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742406465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.2742406465
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.661995633
Short name T936
Test name
Test status
Simulation time 247000770258 ps
CPU time 576.87 seconds
Started Jun 24 04:35:18 PM PDT 24
Finished Jun 24 04:44:56 PM PDT 24
Peak memory 216984 kb
Host smart-510e86da-211d-4d7f-ae9f-bf7a5c144293
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661995633 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.661995633
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.187485477
Short name T630
Test name
Test status
Simulation time 946358721 ps
CPU time 4.01 seconds
Started Jun 24 04:35:14 PM PDT 24
Finished Jun 24 04:35:21 PM PDT 24
Peak memory 199868 kb
Host smart-5647af3a-756e-4071-baf0-784c4f650f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187485477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.187485477
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.2990610718
Short name T1077
Test name
Test status
Simulation time 15699712711 ps
CPU time 10.03 seconds
Started Jun 24 04:35:16 PM PDT 24
Finished Jun 24 04:35:29 PM PDT 24
Peak memory 200576 kb
Host smart-7be2f8d9-49c1-4d20-ada4-ead3e095a5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990610718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.2990610718
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.1751870016
Short name T594
Test name
Test status
Simulation time 88294264644 ps
CPU time 34.61 seconds
Started Jun 24 04:37:42 PM PDT 24
Finished Jun 24 04:39:13 PM PDT 24
Peak memory 200496 kb
Host smart-ec8e5d2b-576d-4e18-a577-84b5403f0ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751870016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.1751870016
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.343527773
Short name T547
Test name
Test status
Simulation time 10118679861 ps
CPU time 78.78 seconds
Started Jun 24 04:37:43 PM PDT 24
Finished Jun 24 04:39:58 PM PDT 24
Peak memory 208812 kb
Host smart-2eea52c3-92bc-4583-b8cd-082318f616a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343527773 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.343527773
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.1016669711
Short name T799
Test name
Test status
Simulation time 69730514944 ps
CPU time 210.86 seconds
Started Jun 24 04:37:39 PM PDT 24
Finished Jun 24 04:42:05 PM PDT 24
Peak memory 217376 kb
Host smart-e23bc4cd-aec1-4bd3-835b-d6211dc58d33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016669711 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.1016669711
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.4009458672
Short name T1026
Test name
Test status
Simulation time 24200124243 ps
CPU time 26.43 seconds
Started Jun 24 04:37:40 PM PDT 24
Finished Jun 24 04:39:05 PM PDT 24
Peak memory 200476 kb
Host smart-dc20c946-23e8-444f-a69c-7ba4f59a8aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009458672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.4009458672
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.381312508
Short name T488
Test name
Test status
Simulation time 57815821435 ps
CPU time 459.01 seconds
Started Jun 24 04:37:39 PM PDT 24
Finished Jun 24 04:46:14 PM PDT 24
Peak memory 216936 kb
Host smart-4f54fbeb-4055-414d-94a1-77938c804d62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381312508 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.381312508
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.3395286158
Short name T136
Test name
Test status
Simulation time 22673742346 ps
CPU time 10.27 seconds
Started Jun 24 04:37:40 PM PDT 24
Finished Jun 24 04:38:48 PM PDT 24
Peak memory 200608 kb
Host smart-b119d726-075f-4573-88bd-b62dcfcf0bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395286158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.3395286158
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.3367194042
Short name T56
Test name
Test status
Simulation time 509161409511 ps
CPU time 2192.52 seconds
Started Jun 24 04:37:45 PM PDT 24
Finished Jun 24 05:15:18 PM PDT 24
Peak memory 225180 kb
Host smart-b68d1b2d-8fa6-4ff2-8236-8ac3e4a3f265
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367194042 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.3367194042
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.1550004940
Short name T243
Test name
Test status
Simulation time 345842852796 ps
CPU time 105.46 seconds
Started Jun 24 04:37:38 PM PDT 24
Finished Jun 24 04:40:20 PM PDT 24
Peak memory 200532 kb
Host smart-3c6d0f86-5b3f-4aa1-ae94-bbdae596074e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550004940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.1550004940
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.2524656517
Short name T6
Test name
Test status
Simulation time 112327532394 ps
CPU time 193.19 seconds
Started Jun 24 04:37:42 PM PDT 24
Finished Jun 24 04:41:52 PM PDT 24
Peak memory 200556 kb
Host smart-5fb41e3d-4cfd-4ec8-82f8-2c006ed086fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524656517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.2524656517
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.2937935998
Short name T103
Test name
Test status
Simulation time 38109265026 ps
CPU time 532.74 seconds
Started Jun 24 04:37:43 PM PDT 24
Finished Jun 24 04:47:38 PM PDT 24
Peak memory 208736 kb
Host smart-d7420b18-fa3f-4761-86be-02dc43738159
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937935998 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.2937935998
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.3225071345
Short name T294
Test name
Test status
Simulation time 9551003564 ps
CPU time 13.79 seconds
Started Jun 24 04:37:41 PM PDT 24
Finished Jun 24 04:38:52 PM PDT 24
Peak memory 200272 kb
Host smart-fadd8018-9682-4f48-9a8d-7269b6750130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225071345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.3225071345
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.617555748
Short name T275
Test name
Test status
Simulation time 49036906257 ps
CPU time 63.79 seconds
Started Jun 24 04:37:43 PM PDT 24
Finished Jun 24 04:39:43 PM PDT 24
Peak memory 200436 kb
Host smart-dfe95cab-ee63-4068-bfab-a7daacbb4908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617555748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.617555748
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.978024515
Short name T927
Test name
Test status
Simulation time 22391547619 ps
CPU time 477.02 seconds
Started Jun 24 04:37:45 PM PDT 24
Finished Jun 24 04:46:43 PM PDT 24
Peak memory 208808 kb
Host smart-87acb220-f133-4d17-8920-2cc59e736703
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978024515 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.978024515
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.4116126296
Short name T48
Test name
Test status
Simulation time 96049561715 ps
CPU time 96.76 seconds
Started Jun 24 04:37:40 PM PDT 24
Finished Jun 24 04:40:15 PM PDT 24
Peak memory 200544 kb
Host smart-e720ce62-75fa-48ac-8e1c-60f3cb420542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116126296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.4116126296
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.3150058473
Short name T595
Test name
Test status
Simulation time 32312383401 ps
CPU time 20.46 seconds
Started Jun 24 04:37:42 PM PDT 24
Finished Jun 24 04:39:00 PM PDT 24
Peak memory 200504 kb
Host smart-31219f18-c6c6-45b6-8e48-3bf3bdf20c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150058473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.3150058473
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.4122953852
Short name T330
Test name
Test status
Simulation time 31737496926 ps
CPU time 1152.72 seconds
Started Jun 24 04:37:41 PM PDT 24
Finished Jun 24 04:57:51 PM PDT 24
Peak memory 208832 kb
Host smart-94e2d086-990e-4652-8c37-327ba3df1f86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122953852 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.4122953852
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.1070489055
Short name T345
Test name
Test status
Simulation time 21255730 ps
CPU time 0.55 seconds
Started Jun 24 04:35:15 PM PDT 24
Finished Jun 24 04:35:18 PM PDT 24
Peak memory 195884 kb
Host smart-2f0a299d-47e4-43dd-b3f7-ca0393d40da8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070489055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.1070489055
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.262735749
Short name T1062
Test name
Test status
Simulation time 47590507677 ps
CPU time 21.25 seconds
Started Jun 24 04:35:18 PM PDT 24
Finished Jun 24 04:35:41 PM PDT 24
Peak memory 200488 kb
Host smart-083713b1-e419-4f4c-a3f7-d8c885acb5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262735749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.262735749
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.3203481008
Short name T169
Test name
Test status
Simulation time 52779788916 ps
CPU time 121.07 seconds
Started Jun 24 04:35:13 PM PDT 24
Finished Jun 24 04:37:16 PM PDT 24
Peak memory 200520 kb
Host smart-3066999c-9c58-424f-a100-7999424665e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203481008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.3203481008
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.3347701504
Short name T667
Test name
Test status
Simulation time 113849708748 ps
CPU time 184.44 seconds
Started Jun 24 04:35:21 PM PDT 24
Finished Jun 24 04:38:27 PM PDT 24
Peak memory 200432 kb
Host smart-a54491b4-f90f-4dd6-b5fd-e846b8cff308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347701504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.3347701504
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.3292181698
Short name T379
Test name
Test status
Simulation time 10836809064 ps
CPU time 23.22 seconds
Started Jun 24 04:35:11 PM PDT 24
Finished Jun 24 04:35:36 PM PDT 24
Peak memory 200388 kb
Host smart-bd471473-eed4-4e8c-9a48-7bb03ef4483b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292181698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.3292181698
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.963429178
Short name T455
Test name
Test status
Simulation time 136635467445 ps
CPU time 363.4 seconds
Started Jun 24 04:35:30 PM PDT 24
Finished Jun 24 04:41:34 PM PDT 24
Peak memory 200476 kb
Host smart-44de12b8-553d-42ea-b1ec-46fd037f0b8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=963429178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.963429178
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.676039370
Short name T903
Test name
Test status
Simulation time 13976938739 ps
CPU time 11.02 seconds
Started Jun 24 04:35:15 PM PDT 24
Finished Jun 24 04:35:28 PM PDT 24
Peak memory 200524 kb
Host smart-e645df34-4f59-4625-aa58-63af7c2c281b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676039370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.676039370
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_perf.461102088
Short name T1056
Test name
Test status
Simulation time 8968208174 ps
CPU time 474.34 seconds
Started Jun 24 04:35:28 PM PDT 24
Finished Jun 24 04:43:23 PM PDT 24
Peak memory 200548 kb
Host smart-7c102f4d-094c-4104-9354-5dea0f8c1625
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=461102088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.461102088
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.1121071466
Short name T774
Test name
Test status
Simulation time 3816164014 ps
CPU time 27.89 seconds
Started Jun 24 04:35:23 PM PDT 24
Finished Jun 24 04:35:52 PM PDT 24
Peak memory 198748 kb
Host smart-47d8a81b-6ab3-42bd-adcf-dbd85a460b7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1121071466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.1121071466
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.3583417734
Short name T115
Test name
Test status
Simulation time 114060086281 ps
CPU time 158.14 seconds
Started Jun 24 04:35:12 PM PDT 24
Finished Jun 24 04:37:52 PM PDT 24
Peak memory 200440 kb
Host smart-3b9a08cf-4306-4cad-a4b7-cb165b9553ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583417734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.3583417734
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.1654661173
Short name T730
Test name
Test status
Simulation time 5086165614 ps
CPU time 4.45 seconds
Started Jun 24 04:35:17 PM PDT 24
Finished Jun 24 04:35:23 PM PDT 24
Peak memory 196576 kb
Host smart-724320a3-9537-43ca-89dc-2c5a12dd35e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654661173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.1654661173
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.2732990473
Short name T643
Test name
Test status
Simulation time 878739945 ps
CPU time 5.22 seconds
Started Jun 24 04:35:25 PM PDT 24
Finished Jun 24 04:35:31 PM PDT 24
Peak memory 200152 kb
Host smart-e5899154-d40b-4d35-9575-702f23b97c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732990473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.2732990473
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.2626002512
Short name T543
Test name
Test status
Simulation time 351420898792 ps
CPU time 143.51 seconds
Started Jun 24 04:35:17 PM PDT 24
Finished Jun 24 04:37:43 PM PDT 24
Peak memory 200968 kb
Host smart-52db9ff5-7678-4923-a87a-fabffed15a01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626002512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.2626002512
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.1232729095
Short name T283
Test name
Test status
Simulation time 8621664578 ps
CPU time 9.62 seconds
Started Jun 24 04:35:17 PM PDT 24
Finished Jun 24 04:35:29 PM PDT 24
Peak memory 200576 kb
Host smart-b97c1de7-0ec7-4376-8761-fc1f9c7a80f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232729095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.1232729095
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.661481720
Short name T573
Test name
Test status
Simulation time 14336828995 ps
CPU time 20.04 seconds
Started Jun 24 04:35:20 PM PDT 24
Finished Jun 24 04:35:41 PM PDT 24
Peak memory 200680 kb
Host smart-cedd92b2-5da9-4f5d-8eb5-77f332d303be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661481720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.661481720
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.787732910
Short name T256
Test name
Test status
Simulation time 54271475777 ps
CPU time 76.09 seconds
Started Jun 24 04:37:42 PM PDT 24
Finished Jun 24 04:39:55 PM PDT 24
Peak memory 200472 kb
Host smart-c46da5c0-f24a-4a17-880b-7f7d4a5d52be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787732910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.787732910
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.2933725865
Short name T731
Test name
Test status
Simulation time 199212015498 ps
CPU time 34.24 seconds
Started Jun 24 04:37:38 PM PDT 24
Finished Jun 24 04:39:09 PM PDT 24
Peak memory 200548 kb
Host smart-09ca0931-9dd9-4f7c-a084-c42326bec319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933725865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.2933725865
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.2712493976
Short name T850
Test name
Test status
Simulation time 75666755465 ps
CPU time 172.19 seconds
Started Jun 24 04:37:40 PM PDT 24
Finished Jun 24 04:41:30 PM PDT 24
Peak memory 216664 kb
Host smart-54362b9a-0dc7-448d-a4b1-8402035443b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712493976 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.2712493976
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.2791365734
Short name T727
Test name
Test status
Simulation time 15938336832 ps
CPU time 14.25 seconds
Started Jun 24 04:37:47 PM PDT 24
Finished Jun 24 04:39:00 PM PDT 24
Peak memory 200604 kb
Host smart-9167a179-fd00-46c5-bcfc-405eb457902d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791365734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.2791365734
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.2076988855
Short name T711
Test name
Test status
Simulation time 221317100335 ps
CPU time 84.58 seconds
Started Jun 24 04:37:52 PM PDT 24
Finished Jun 24 04:40:20 PM PDT 24
Peak memory 200576 kb
Host smart-e168773c-1210-42a7-bdd8-9152847c7675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076988855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.2076988855
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.925023717
Short name T1072
Test name
Test status
Simulation time 78051046432 ps
CPU time 684.37 seconds
Started Jun 24 04:37:49 PM PDT 24
Finished Jun 24 04:50:15 PM PDT 24
Peak memory 216964 kb
Host smart-b83efa3f-00df-4c6f-8f1e-d951a32ab932
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925023717 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.925023717
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.3615410916
Short name T1080
Test name
Test status
Simulation time 124098435951 ps
CPU time 243.78 seconds
Started Jun 24 04:37:47 PM PDT 24
Finished Jun 24 04:42:50 PM PDT 24
Peak memory 200576 kb
Host smart-69b3742c-b73f-46aa-942c-9e643c8e5844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615410916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.3615410916
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.936577250
Short name T833
Test name
Test status
Simulation time 40163412326 ps
CPU time 183.89 seconds
Started Jun 24 04:37:47 PM PDT 24
Finished Jun 24 04:41:49 PM PDT 24
Peak memory 208732 kb
Host smart-b480758d-d583-4c05-98da-88e9537a08d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936577250 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.936577250
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.2019094905
Short name T1081
Test name
Test status
Simulation time 34422856091 ps
CPU time 53.54 seconds
Started Jun 24 04:37:46 PM PDT 24
Finished Jun 24 04:39:39 PM PDT 24
Peak memory 200168 kb
Host smart-b1c5e231-eed7-411f-bbd3-c7646af781c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019094905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.2019094905
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.2963398429
Short name T654
Test name
Test status
Simulation time 24764225877 ps
CPU time 379.71 seconds
Started Jun 24 04:37:50 PM PDT 24
Finished Jun 24 04:45:11 PM PDT 24
Peak memory 216952 kb
Host smart-fa2b5406-9ca4-4887-80fb-659fa28a524c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963398429 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.2963398429
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.4205602481
Short name T919
Test name
Test status
Simulation time 21419002260 ps
CPU time 32.3 seconds
Started Jun 24 04:37:51 PM PDT 24
Finished Jun 24 04:39:24 PM PDT 24
Peak memory 200412 kb
Host smart-f6abc9a1-387c-460d-a8df-f379cde4ed3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205602481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.4205602481
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.1484966310
Short name T671
Test name
Test status
Simulation time 183833410863 ps
CPU time 201.38 seconds
Started Jun 24 04:37:49 PM PDT 24
Finished Jun 24 04:42:13 PM PDT 24
Peak memory 216952 kb
Host smart-c44351e1-a07c-4abd-9518-43302926ae19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484966310 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.1484966310
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.3069529970
Short name T729
Test name
Test status
Simulation time 11208879884 ps
CPU time 16.74 seconds
Started Jun 24 04:37:50 PM PDT 24
Finished Jun 24 04:39:08 PM PDT 24
Peak memory 200464 kb
Host smart-b0d430e6-ccd7-45d9-ac2d-dee2bc40a92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069529970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.3069529970
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.2077490662
Short name T624
Test name
Test status
Simulation time 45653313 ps
CPU time 0.58 seconds
Started Jun 24 04:35:18 PM PDT 24
Finished Jun 24 04:35:20 PM PDT 24
Peak memory 195896 kb
Host smart-1bc542d4-c970-4685-b02c-72dad46d8b31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077490662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.2077490662
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.3029506385
Short name T750
Test name
Test status
Simulation time 148887751116 ps
CPU time 222.65 seconds
Started Jun 24 04:35:31 PM PDT 24
Finished Jun 24 04:39:15 PM PDT 24
Peak memory 200484 kb
Host smart-3c2fddd5-d6b0-4492-8a75-0a25afce59ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029506385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.3029506385
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.477861739
Short name T1
Test name
Test status
Simulation time 124842545727 ps
CPU time 207.09 seconds
Started Jun 24 04:35:14 PM PDT 24
Finished Jun 24 04:38:43 PM PDT 24
Peak memory 200456 kb
Host smart-272ace40-134b-4fa7-a745-6f822ee49173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477861739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.477861739
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.1439901324
Short name T1075
Test name
Test status
Simulation time 30375468659 ps
CPU time 13.11 seconds
Started Jun 24 04:35:19 PM PDT 24
Finished Jun 24 04:35:34 PM PDT 24
Peak memory 199792 kb
Host smart-c40cd134-a0c0-4dd2-9fcf-0d2b2c36954c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439901324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.1439901324
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.1932156738
Short name T655
Test name
Test status
Simulation time 41626322766 ps
CPU time 47.09 seconds
Started Jun 24 04:35:34 PM PDT 24
Finished Jun 24 04:36:22 PM PDT 24
Peak memory 200544 kb
Host smart-fc3facdc-0d34-42e9-ab8a-5b9cc4b6db36
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932156738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.1932156738
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.2205609689
Short name T883
Test name
Test status
Simulation time 26102470508 ps
CPU time 94.03 seconds
Started Jun 24 04:35:19 PM PDT 24
Finished Jun 24 04:36:54 PM PDT 24
Peak memory 200492 kb
Host smart-82e665b0-c9e1-466e-b3fb-0abc61eca3ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2205609689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.2205609689
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.651894674
Short name T449
Test name
Test status
Simulation time 6585658545 ps
CPU time 12.62 seconds
Started Jun 24 04:35:30 PM PDT 24
Finished Jun 24 04:35:43 PM PDT 24
Peak memory 200300 kb
Host smart-17629b22-c611-43f3-b8b9-78d7089a1809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651894674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.651894674
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.2373156174
Short name T96
Test name
Test status
Simulation time 7171320642 ps
CPU time 10.39 seconds
Started Jun 24 04:35:16 PM PDT 24
Finished Jun 24 04:35:29 PM PDT 24
Peak memory 197920 kb
Host smart-e9bd5391-6e67-4b34-b1ae-1d67b990b909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373156174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.2373156174
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.1077230088
Short name T506
Test name
Test status
Simulation time 12324722018 ps
CPU time 752.26 seconds
Started Jun 24 04:35:15 PM PDT 24
Finished Jun 24 04:47:50 PM PDT 24
Peak memory 200504 kb
Host smart-0eced33f-6358-4eff-acff-383161544d23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1077230088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.1077230088
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.2252777699
Short name T693
Test name
Test status
Simulation time 1503069081 ps
CPU time 1.23 seconds
Started Jun 24 04:35:28 PM PDT 24
Finished Jun 24 04:35:29 PM PDT 24
Peak memory 196080 kb
Host smart-3065f2c0-c0ac-4014-a596-cdc606ea91fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2252777699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.2252777699
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.1208877563
Short name T798
Test name
Test status
Simulation time 8123028186 ps
CPU time 13.03 seconds
Started Jun 24 04:35:32 PM PDT 24
Finished Jun 24 04:35:45 PM PDT 24
Peak memory 200544 kb
Host smart-6d021423-4605-49dc-bf23-116fff969f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208877563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.1208877563
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.3576990320
Short name T92
Test name
Test status
Simulation time 2130998221 ps
CPU time 1.65 seconds
Started Jun 24 04:35:21 PM PDT 24
Finished Jun 24 04:35:23 PM PDT 24
Peak memory 196164 kb
Host smart-bb68afa9-979e-4705-bb29-fed27a2b019e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576990320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.3576990320
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.2205014004
Short name T1023
Test name
Test status
Simulation time 5715116421 ps
CPU time 9.34 seconds
Started Jun 24 04:35:12 PM PDT 24
Finished Jun 24 04:35:23 PM PDT 24
Peak memory 200236 kb
Host smart-576c066f-76bf-4193-acf1-238d9011367f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205014004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.2205014004
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.3595602576
Short name T812
Test name
Test status
Simulation time 46536316991 ps
CPU time 77.16 seconds
Started Jun 24 04:35:32 PM PDT 24
Finished Jun 24 04:36:50 PM PDT 24
Peak memory 200588 kb
Host smart-03c37d23-82d8-4215-a28b-a3f5c3adad06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595602576 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.3595602576
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.600254063
Short name T808
Test name
Test status
Simulation time 6362699761 ps
CPU time 20.08 seconds
Started Jun 24 04:35:16 PM PDT 24
Finished Jun 24 04:35:39 PM PDT 24
Peak memory 199924 kb
Host smart-bdff66ea-118b-413c-8c96-602d21e60554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600254063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.600254063
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.1109070218
Short name T334
Test name
Test status
Simulation time 37464874718 ps
CPU time 14.12 seconds
Started Jun 24 04:35:24 PM PDT 24
Finished Jun 24 04:35:39 PM PDT 24
Peak memory 200468 kb
Host smart-c6c5713d-1916-4165-ac4a-3101b81ae786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109070218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.1109070218
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.1579939134
Short name T154
Test name
Test status
Simulation time 142301174591 ps
CPU time 60.76 seconds
Started Jun 24 04:37:48 PM PDT 24
Finished Jun 24 04:39:51 PM PDT 24
Peak memory 200544 kb
Host smart-8d6c82c9-183c-4fc8-9825-b5426a97c2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579939134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.1579939134
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.917158308
Short name T308
Test name
Test status
Simulation time 28888386185 ps
CPU time 290.4 seconds
Started Jun 24 04:37:54 PM PDT 24
Finished Jun 24 04:43:47 PM PDT 24
Peak memory 217004 kb
Host smart-652234f7-56e8-4601-994c-fdc0d7d0c9b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917158308 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.917158308
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.1263351194
Short name T196
Test name
Test status
Simulation time 71224223391 ps
CPU time 46.99 seconds
Started Jun 24 04:37:46 PM PDT 24
Finished Jun 24 04:39:33 PM PDT 24
Peak memory 200484 kb
Host smart-9baeed78-be0b-47d3-8700-ca7e8b035457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263351194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.1263351194
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.1810406586
Short name T30
Test name
Test status
Simulation time 46756194339 ps
CPU time 647.41 seconds
Started Jun 24 04:37:54 PM PDT 24
Finished Jun 24 04:49:44 PM PDT 24
Peak memory 216784 kb
Host smart-2a5941f7-9c21-4d4b-ba24-75b849889920
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810406586 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.1810406586
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.1462981611
Short name T327
Test name
Test status
Simulation time 68890174320 ps
CPU time 26.86 seconds
Started Jun 24 04:37:50 PM PDT 24
Finished Jun 24 04:39:18 PM PDT 24
Peak memory 200440 kb
Host smart-cb2e743c-b44b-4810-8753-db34572255ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462981611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.1462981611
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.3673979289
Short name T58
Test name
Test status
Simulation time 27470661333 ps
CPU time 225.76 seconds
Started Jun 24 04:37:47 PM PDT 24
Finished Jun 24 04:42:32 PM PDT 24
Peak memory 216080 kb
Host smart-b2e410dc-cb08-4c36-bcae-3c856d4aec98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673979289 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.3673979289
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.2832190443
Short name T518
Test name
Test status
Simulation time 24925547782 ps
CPU time 36.94 seconds
Started Jun 24 04:37:54 PM PDT 24
Finished Jun 24 04:39:34 PM PDT 24
Peak memory 200284 kb
Host smart-ce73fb8a-6c10-40cf-b6a9-8ee04237e28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832190443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.2832190443
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.1369815151
Short name T291
Test name
Test status
Simulation time 186326524507 ps
CPU time 526.59 seconds
Started Jun 24 04:37:54 PM PDT 24
Finished Jun 24 04:47:43 PM PDT 24
Peak memory 214744 kb
Host smart-c0cd4471-d471-4685-b58a-2a347d9dacfd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369815151 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.1369815151
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.17866958
Short name T324
Test name
Test status
Simulation time 70549988366 ps
CPU time 632.99 seconds
Started Jun 24 04:37:48 PM PDT 24
Finished Jun 24 04:49:23 PM PDT 24
Peak memory 216940 kb
Host smart-79a1b952-3781-4973-b913-0653e718b5c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17866958 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.17866958
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.663808428
Short name T913
Test name
Test status
Simulation time 50639089238 ps
CPU time 17.85 seconds
Started Jun 24 04:37:55 PM PDT 24
Finished Jun 24 04:39:15 PM PDT 24
Peak memory 200528 kb
Host smart-20baef5f-5e29-43ed-ac5a-580f94241580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663808428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.663808428
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.3623899048
Short name T419
Test name
Test status
Simulation time 71775984860 ps
CPU time 112.87 seconds
Started Jun 24 04:37:57 PM PDT 24
Finished Jun 24 04:40:54 PM PDT 24
Peak memory 200552 kb
Host smart-c8a6938d-9973-4165-8933-e43dde8ab71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623899048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.3623899048
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.1765781336
Short name T976
Test name
Test status
Simulation time 32433291258 ps
CPU time 104.96 seconds
Started Jun 24 04:37:54 PM PDT 24
Finished Jun 24 04:40:42 PM PDT 24
Peak memory 216976 kb
Host smart-6c8a0e86-fe2a-40d8-bad2-962e92aba472
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765781336 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.1765781336
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.617473135
Short name T93
Test name
Test status
Simulation time 97079714505 ps
CPU time 146.63 seconds
Started Jun 24 04:37:54 PM PDT 24
Finished Jun 24 04:41:23 PM PDT 24
Peak memory 200548 kb
Host smart-3781628f-e7b7-4ad4-ad1d-d7bf6ef34a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617473135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.617473135
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.2057027604
Short name T32
Test name
Test status
Simulation time 17393206749 ps
CPU time 192.46 seconds
Started Jun 24 04:37:53 PM PDT 24
Finished Jun 24 04:42:09 PM PDT 24
Peak memory 216064 kb
Host smart-04f802d1-896a-4f6d-a2f2-f7e10422ace7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057027604 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.2057027604
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.1852918674
Short name T200
Test name
Test status
Simulation time 19635733269 ps
CPU time 16.57 seconds
Started Jun 24 04:37:53 PM PDT 24
Finished Jun 24 04:39:13 PM PDT 24
Peak memory 200180 kb
Host smart-75446234-4541-4958-812f-aaaf96c55795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852918674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.1852918674
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.1071534282
Short name T222
Test name
Test status
Simulation time 71477994102 ps
CPU time 119.62 seconds
Started Jun 24 04:37:54 PM PDT 24
Finished Jun 24 04:40:56 PM PDT 24
Peak memory 200464 kb
Host smart-12e7e891-fbf4-485b-afab-c40e115b5b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071534282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.1071534282
Directory /workspace/99.uart_fifo_reset/latest
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