Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	94118	1			T1	2		T2	1		T3	121
all_values[1]	94118	1			T1	2		T2	1		T3	121
all_values[2]	94118	1			T1	2		T2	1		T3	121
all_values[3]	94118	1			T1	2		T2	1		T3	121
all_values[4]	94118	1			T1	2		T2	1		T3	121
all_values[5]	94118	1			T1	2		T2	1		T3	121
all_values[6]	94118	1			T1	2		T2	1		T3	121
all_values[7]	94118	1			T1	2		T2	1		T3	121
all_values[8]	94118	1			T1	2		T2	1		T3	121

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

439591

1

T1

18

T2

5

T3

683

auto[1]

407471

1

T2

4

T3

406

T4

30

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

770883

1

T1

13

T2

7

T3

1040

auto[1]

76179

1

T1

5

T2

2

T3

49

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	34253	1			T3	81		T5	6		T7	12
all_values[0]	auto[0]	auto[1]	19838	1			T1	2		T3	36		T4	10
all_values[0]	auto[1]	auto[0]	21634	1			T3	1		T7	8		T8	234
all_values[0]	auto[1]	auto[1]	18393	1			T2	1		T3	3		T4	2
all_values[1]	auto[0]	auto[0]	44086	1			T1	2		T2	1		T3	117
all_values[1]	auto[0]	auto[1]	1623	1			T5	7		T8	5		T29	3
all_values[1]	auto[1]	auto[0]	46942	1			T3	4		T4	2		T5	2
all_values[1]	auto[1]	auto[1]	1467	1			T9	13		T28	1		T104	3
all_values[2]	auto[0]	auto[0]	45875	1			T1	1		T3	39		T4	10
all_values[2]	auto[0]	auto[1]	2111	1			T1	1		T3	3		T5	2
all_values[2]	auto[1]	auto[0]	44228	1			T2	1		T3	76		T4	1
all_values[2]	auto[1]	auto[1]	1904	1			T3	3		T4	1		T7	2
all_values[3]	auto[0]	auto[0]	48458	1			T1	2		T2	1		T3	86
all_values[3]	auto[0]	auto[1]	285	1			T14	1		T15	1		T119	1
all_values[3]	auto[1]	auto[0]	45102	1			T3	35		T4	12		T5	15
all_values[3]	auto[1]	auto[1]	273	1			T12	2		T13	1		T79	1
all_values[4]	auto[0]	auto[0]	47389	1			T1	2		T3	117		T4	12
all_values[4]	auto[0]	auto[1]	385	1			T15	2		T16	4		T17	3
all_values[4]	auto[1]	auto[0]	45976	1			T2	1		T3	4		T5	9
all_values[4]	auto[1]	auto[1]	368	1			T13	4		T16	12		T17	6
all_values[5]	auto[0]	auto[0]	48968	1			T1	2		T2	1		T3	39
all_values[5]	auto[0]	auto[1]	149	1			T8	2		T32	2		T35	1
all_values[5]	auto[1]	auto[0]	44832	1			T3	82		T5	17		T7	3
all_values[5]	auto[1]	auto[1]	169	1			T32	4		T35	3		T107	3
all_values[6]	auto[0]	auto[0]	48853	1			T1	2		T2	1		T3	117
all_values[6]	auto[0]	auto[1]	154	1			T8	1		T32	5		T80	1
all_values[6]	auto[1]	auto[0]	44957	1			T3	4		T4	12		T7	20
all_values[6]	auto[1]	auto[1]	154	1			T8	2		T32	4		T80	3
all_values[7]	auto[0]	auto[0]	47637	1			T1	2		T2	1		T3	4
all_values[7]	auto[0]	auto[1]	271	1			T15	3		T17	1		T32	4
all_values[7]	auto[1]	auto[0]	45929	1			T3	117		T7	21		T8	266
all_values[7]	auto[1]	auto[1]	281	1			T7	1		T13	1		T16	1
all_values[8]	auto[0]	auto[0]	34720	1			T3	43		T7	2		T8	509
all_values[8]	auto[0]	auto[1]	14536	1			T1	2		T3	1		T4	12
all_values[8]	auto[1]	auto[0]	31044	1			T3	74		T5	8		T7	18
all_values[8]	auto[1]	auto[1]	13818	1			T2	1		T3	3		T5	2