Summary for Variable cp_dir
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_dir
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[UartTx] |
2181 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
auto[UartRx] |
2181 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_rst_pos
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
11 |
0 |
11 |
100.00 |
User Defined Bins for cp_rst_pos
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0] |
4001 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
2 |
values[1] |
31 |
1 |
|
|
T8 |
1 |
|
T20 |
1 |
|
T37 |
1 |
values[2] |
32 |
1 |
|
|
T8 |
1 |
|
T15 |
1 |
|
T34 |
1 |
values[3] |
25 |
1 |
|
|
T15 |
1 |
|
T35 |
1 |
|
T52 |
1 |
values[4] |
24 |
1 |
|
|
T310 |
1 |
|
T142 |
1 |
|
T254 |
2 |
values[5] |
29 |
1 |
|
|
T8 |
1 |
|
T32 |
1 |
|
T33 |
1 |
values[6] |
34 |
1 |
|
|
T8 |
1 |
|
T35 |
1 |
|
T36 |
1 |
values[7] |
31 |
1 |
|
|
T20 |
1 |
|
T31 |
1 |
|
T33 |
1 |
values[8] |
51 |
1 |
|
|
T20 |
1 |
|
T15 |
1 |
|
T33 |
1 |
values[9] |
48 |
1 |
|
|
T20 |
2 |
|
T15 |
1 |
|
T31 |
1 |
values[10] |
42 |
1 |
|
|
T20 |
2 |
|
T32 |
3 |
|
T33 |
1 |
Summary for Cross uart_reset_cg_cc
Samples crossed: cp_dir cp_rst_pos
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
22 |
0 |
22 |
100.00 |
|
Automatically Generated Cross Bins for uart_reset_cg_cc
Bins
cp_dir | cp_rst_pos | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[UartTx] |
values[0] |
2061 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
auto[UartTx] |
values[1] |
10 |
1 |
|
|
T20 |
1 |
|
T107 |
1 |
|
T108 |
1 |
auto[UartTx] |
values[2] |
13 |
1 |
|
|
T8 |
1 |
|
T334 |
2 |
|
T106 |
2 |
auto[UartTx] |
values[3] |
11 |
1 |
|
|
T15 |
1 |
|
T53 |
2 |
|
T335 |
2 |
auto[UartTx] |
values[4] |
8 |
1 |
|
|
T310 |
1 |
|
T142 |
1 |
|
T254 |
2 |
auto[UartTx] |
values[5] |
5 |
1 |
|
|
T107 |
1 |
|
T110 |
1 |
|
T203 |
1 |
auto[UartTx] |
values[6] |
7 |
1 |
|
|
T35 |
1 |
|
T52 |
1 |
|
T54 |
1 |
auto[UartTx] |
values[7] |
8 |
1 |
|
|
T36 |
1 |
|
T37 |
1 |
|
T107 |
1 |
auto[UartTx] |
values[8] |
16 |
1 |
|
|
T33 |
1 |
|
T34 |
1 |
|
T36 |
1 |
auto[UartTx] |
values[9] |
21 |
1 |
|
|
T34 |
1 |
|
T37 |
1 |
|
T319 |
1 |
auto[UartTx] |
values[10] |
17 |
1 |
|
|
T20 |
1 |
|
T32 |
2 |
|
T34 |
2 |
auto[UartRx] |
values[0] |
1940 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
auto[UartRx] |
values[1] |
21 |
1 |
|
|
T8 |
1 |
|
T37 |
1 |
|
T92 |
1 |
auto[UartRx] |
values[2] |
19 |
1 |
|
|
T15 |
1 |
|
T34 |
1 |
|
T36 |
1 |
auto[UartRx] |
values[3] |
14 |
1 |
|
|
T35 |
1 |
|
T52 |
1 |
|
T93 |
1 |
auto[UartRx] |
values[4] |
16 |
1 |
|
|
T334 |
1 |
|
T109 |
2 |
|
T53 |
1 |
auto[UartRx] |
values[5] |
24 |
1 |
|
|
T8 |
1 |
|
T32 |
1 |
|
T33 |
1 |
auto[UartRx] |
values[6] |
27 |
1 |
|
|
T8 |
1 |
|
T36 |
1 |
|
T107 |
1 |
auto[UartRx] |
values[7] |
23 |
1 |
|
|
T20 |
1 |
|
T31 |
1 |
|
T33 |
1 |
auto[UartRx] |
values[8] |
35 |
1 |
|
|
T20 |
1 |
|
T15 |
1 |
|
T34 |
2 |
auto[UartRx] |
values[9] |
27 |
1 |
|
|
T20 |
2 |
|
T15 |
1 |
|
T31 |
1 |
auto[UartRx] |
values[10] |
25 |
1 |
|
|
T20 |
1 |
|
T32 |
1 |
|
T33 |
1 |