Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1989	1			T1	1		T2	21		T3	3
auto[BaudRate115200]	1602	1			T1	1		T2	6		T4	1
auto[BaudRate230400]	1659	1			T2	3		T5	2		T7	1
auto[BaudRate128Kbps]	1608	1			T2	6		T4	3		T5	1
auto[BaudRate256Kbps]	1833	1			T2	9		T3	1		T4	1
auto[BaudRate1Mbps]	1558	1			T2	9		T4	1		T8	3
auto[BaudRate1p5Mbps]	1093	1			T2	6		T3	1		T4	1

---

Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1640	1			T4	7		T10	19		T294	2
freqs[25]	951	1			T11	1		T104	9		T113	7
freqs[48]	391	1			T8	26		T28	9		T41	6
freqs[50]	404	1			T9	38		T38	2		T15	18
freqs[100]	1056	1			T3	5		T39	5		T40	19

---

Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	269	1			T10	4		T294	1		T112	1
auto[BaudRate9600]	freqs[25]	129	1			T113	1		T266	1		T148	1
auto[BaudRate9600]	freqs[48]	83	1			T8	3		T28	2		T336	2
auto[BaudRate9600]	freqs[50]	62	1			T9	4		T38	1		T15	1
auto[BaudRate9600]	freqs[100]	167	1			T3	3		T40	3		T174	1
auto[BaudRate115200]	freqs[24]	245	1			T4	1		T10	1		T112	3
auto[BaudRate115200]	freqs[25]	130	1			T104	1		T113	1		T266	1
auto[BaudRate115200]	freqs[48]	51	1			T8	2		T28	2		T159	5
auto[BaudRate115200]	freqs[50]	67	1			T9	5		T15	2		T122	3
auto[BaudRate115200]	freqs[100]	124	1			T40	2		T174	2		T117	7
auto[BaudRate230400]	freqs[24]	228	1			T10	3		T112	2		T337	6
auto[BaudRate230400]	freqs[25]	150	1			T104	2		T113	3		T248	2
auto[BaudRate230400]	freqs[48]	45	1			T8	2		T28	1		T41	3
auto[BaudRate230400]	freqs[50]	57	1			T9	9		T15	3		T122	1
auto[BaudRate230400]	freqs[100]	176	1			T39	3		T40	2		T174	3
auto[BaudRate128Kbps]	freqs[24]	220	1			T4	3		T10	3		T112	3
auto[BaudRate128Kbps]	freqs[25]	149	1			T104	3		T113	2		T14	1
auto[BaudRate128Kbps]	freqs[48]	47	1			T8	3		T28	1		T41	1
auto[BaudRate128Kbps]	freqs[50]	37	1			T9	4		T38	1		T15	1
auto[BaudRate128Kbps]	freqs[100]	158	1			T39	1		T40	6		T174	1
auto[BaudRate256Kbps]	freqs[24]	259	1			T4	1		T10	4		T294	1
auto[BaudRate256Kbps]	freqs[25]	169	1			T11	1		T104	2		T14	2
auto[BaudRate256Kbps]	freqs[48]	52	1			T8	5		T41	1		T159	9
auto[BaudRate256Kbps]	freqs[50]	64	1			T9	4		T15	4		T122	1
auto[BaudRate256Kbps]	freqs[100]	135	1			T3	1		T40	1		T134	1
auto[BaudRate1Mbps]	freqs[24]	259	1			T4	1		T10	3		T112	2
auto[BaudRate1Mbps]	freqs[25]	125	1			T104	1		T14	3		T148	2
auto[BaudRate1Mbps]	freqs[48]	52	1			T8	3		T28	2		T301	1
auto[BaudRate1Mbps]	freqs[50]	57	1			T9	7		T15	4		T127	1
auto[BaudRate1Mbps]	freqs[100]	152	1			T40	5		T174	1		T117	4
auto[BaudRate1p5Mbps]	freqs[25]	99	1			T14	3		T248	2		T118	3
auto[BaudRate1p5Mbps]	freqs[48]	61	1			T8	8		T28	1		T41	1
auto[BaudRate1p5Mbps]	freqs[50]	60	1			T9	5		T15	3		T283	1
auto[BaudRate1p5Mbps]	freqs[100]	144	1			T3	1		T39	1		T174	2

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded