Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	94118	1			T1	2		T2	1		T3	121
all_pins[1]	94118	1			T1	2		T2	1		T3	121
all_pins[2]	94118	1			T1	2		T2	1		T3	121
all_pins[3]	94118	1			T1	2		T2	1		T3	121
all_pins[4]	94118	1			T1	2		T2	1		T3	121
all_pins[5]	94118	1			T1	2		T2	1		T3	121
all_pins[6]	94118	1			T1	2		T2	1		T3	121
all_pins[7]	94118	1			T1	2		T2	1		T3	121
all_pins[8]	94118	1			T1	2		T2	1		T3	121

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	809419	1			T1	18		T2	7		T3	1080
values[0x1]	37643	1			T2	2		T3	9		T4	4
transitions[0x0=>0x1]	29394	1			T2	1		T3	7		T4	4
transitions[0x1=>0x0]	29207	1			T2	1		T3	8		T4	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	75644	1			T1	2		T3	118		T4	10
all_pins[0]	values[0x1]	18474	1			T2	1		T3	3		T4	2
all_pins[0]	transitions[0x0=>0x1]	18046	1			T2	1		T3	3		T4	2
all_pins[0]	transitions[0x1=>0x0]	1042	1			T28	1		T79	2		T15	3
all_pins[1]	values[0x0]	92648	1			T1	2		T2	1		T3	121
all_pins[1]	values[0x1]	1470	1			T9	13		T28	1		T104	3
all_pins[1]	transitions[0x0=>0x1]	1384	1			T9	13		T104	3		T79	2
all_pins[1]	transitions[0x1=>0x0]	1870	1			T3	3		T4	1		T7	2
all_pins[2]	values[0x0]	92162	1			T1	2		T2	1		T3	118
all_pins[2]	values[0x1]	1956	1			T3	3		T4	1		T7	2
all_pins[2]	transitions[0x0=>0x1]	1903	1			T3	3		T4	1		T7	2
all_pins[2]	transitions[0x1=>0x0]	220	1			T12	2		T13	1		T79	1
all_pins[3]	values[0x0]	93845	1			T1	2		T2	1		T3	121
all_pins[3]	values[0x1]	273	1			T12	2		T13	1		T79	1
all_pins[3]	transitions[0x0=>0x1]	233	1			T12	2		T13	1		T79	1
all_pins[3]	transitions[0x1=>0x0]	328	1			T13	4		T16	12		T17	6
all_pins[4]	values[0x0]	93750	1			T1	2		T2	1		T3	121
all_pins[4]	values[0x1]	368	1			T13	4		T16	12		T17	6
all_pins[4]	transitions[0x0=>0x1]	311	1			T13	4		T16	12		T17	4
all_pins[4]	transitions[0x1=>0x0]	156	1			T16	1		T32	3		T34	1
all_pins[5]	values[0x0]	93905	1			T1	2		T2	1		T3	121
all_pins[5]	values[0x1]	213	1			T16	1		T17	2		T32	4
all_pins[5]	transitions[0x0=>0x1]	163	1			T16	1		T17	2		T32	4
all_pins[5]	transitions[0x1=>0x0]	689	1			T4	1		T7	4		T8	2
all_pins[6]	values[0x0]	93379	1			T1	2		T2	1		T3	121
all_pins[6]	values[0x1]	739	1			T4	1		T7	4		T8	2
all_pins[6]	transitions[0x0=>0x1]	693	1			T4	1		T7	4		T8	2
all_pins[6]	transitions[0x1=>0x0]	235	1			T7	1		T13	1		T16	1
all_pins[7]	values[0x0]	93837	1			T1	2		T2	1		T3	121
all_pins[7]	values[0x1]	281	1			T7	1		T13	1		T16	1
all_pins[7]	transitions[0x0=>0x1]	141	1			T7	1		T16	1		T17	1
all_pins[7]	transitions[0x1=>0x0]	13729	1			T2	1		T3	3		T5	2
all_pins[8]	values[0x0]	80249	1			T1	2		T3	118		T4	12
all_pins[8]	values[0x1]	13869	1			T2	1		T3	3		T5	2
all_pins[8]	transitions[0x0=>0x1]	6520	1			T3	1		T7	2		T8	16
all_pins[8]	transitions[0x1=>0x0]	10938	1			T3	2		T4	1		T5	6