Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	6247205	1			T3	1		T4	25		T5	27
all_levels[1]	1620034	1			T3	205		T7	1		T8	12007
all_levels[2]	304713	1			T5	1		T7	2		T8	1728
all_levels[3]	339544	1			T5	3		T8	483		T9	54
all_levels[4]	459838	1			T7	2		T8	495		T9	61
all_levels[5]	298296	1			T8	638		T9	59		T10	2
all_levels[6]	172626	1			T4	3		T8	483		T9	54
all_levels[7]	182764	1			T8	537		T9	50		T10	6
all_levels[8]	333903	1			T8	642		T9	56		T28	4
all_levels[9]	423740	1			T5	2		T8	428		T9	63
all_levels[10]	203874	1			T4	5		T8	422		T9	48
all_levels[11]	166704	1			T7	1		T8	533		T9	58
all_levels[12]	170856	1			T5	1		T8	401		T9	45
all_levels[13]	753918	1			T5	2		T8	484		T9	49
all_levels[14]	291879	1			T7	1		T8	638		T9	60
all_levels[15]	190052	1			T5	1		T7	1		T8	595
all_levels[16]	194228	1			T7	4		T8	1057		T9	51
all_levels[17]	193479	1			T7	1		T8	1213		T9	55
all_levels[18]	229642	1			T4	2		T7	1		T8	1297
all_levels[19]	596256	1			T8	1373		T9	46		T28	4
all_levels[20]	348901	1			T7	3		T8	1762		T9	54
all_levels[21]	226960	1			T3	104		T7	1		T8	1761
all_levels[22]	154138	1			T7	2		T8	1738		T9	51
all_levels[23]	170407	1			T5	1		T8	1325		T9	54
all_levels[24]	208360	1			T5	2		T7	19		T8	1520
all_levels[25]	176515	1			T8	1618		T9	66		T28	2
all_levels[26]	151624	1			T7	4		T8	1493		T9	57
all_levels[27]	322510	1			T7	5		T8	506		T9	51
all_levels[28]	208979	1			T7	2		T8	729		T9	52
all_levels[29]	253104	1			T7	2		T8	728		T9	58
all_levels[30]	240382	1			T7	1		T8	701		T9	52
all_levels[31]	423033	1			T4	2		T7	3		T8	702
all_levels[32]	11386292	1			T3	90		T4	4		T7	17

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27640741

1

T3

394

T4

41

T5

36

auto[1]

4015

1

T3

6

T5

4

T7

1

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	6244897	1			T4	25		T5	25		T7	3
all_levels[0]	auto[1]	2308	1			T3	1		T5	2		T8	2
all_levels[1]	auto[0]	1619726	1			T3	204		T7	1		T8	12004
all_levels[1]	auto[1]	308	1			T3	1		T8	3		T30	1
all_levels[2]	auto[0]	304683	1			T5	1		T7	2		T8	1728
all_levels[2]	auto[1]	30	1			T185	3		T171	2		T284	1
all_levels[3]	auto[0]	339437	1			T5	1		T8	483		T9	54
all_levels[3]	auto[1]	107	1			T5	2		T272	1		T41	1
all_levels[4]	auto[0]	459814	1			T7	2		T8	495		T9	61
all_levels[4]	auto[1]	24	1			T29	1		T172	1		T134	1
all_levels[5]	auto[0]	298273	1			T8	638		T9	59		T10	2
all_levels[5]	auto[1]	23	1			T30	2		T119	1		T118	1
all_levels[6]	auto[0]	172599	1			T4	3		T8	483		T9	54
all_levels[6]	auto[1]	27	1			T99	1		T127	2		T115	1
all_levels[7]	auto[0]	182625	1			T8	537		T9	50		T10	6
all_levels[7]	auto[1]	139	1			T20	1		T12	2		T175	3
all_levels[8]	auto[0]	333866	1			T8	642		T9	56		T28	4
all_levels[8]	auto[1]	37	1			T97	1		T171	3		T273	1
all_levels[9]	auto[0]	423720	1			T5	2		T8	428		T9	63
all_levels[9]	auto[1]	20	1			T175	1		T282	1		T198	1
all_levels[10]	auto[0]	203850	1			T4	5		T8	422		T9	48
all_levels[10]	auto[1]	24	1			T37	1		T333	2		T132	4
all_levels[11]	auto[0]	166682	1			T7	1		T8	533		T9	58
all_levels[11]	auto[1]	22	1			T172	1		T117	1		T338	2
all_levels[12]	auto[0]	170835	1			T5	1		T8	401		T9	45
all_levels[12]	auto[1]	21	1			T79	1		T284	1		T125	3
all_levels[13]	auto[0]	753898	1			T5	2		T8	484		T9	49
all_levels[13]	auto[1]	20	1			T173	1		T116	3		T146	1
all_levels[14]	auto[0]	291848	1			T7	1		T8	638		T9	60
all_levels[14]	auto[1]	31	1			T30	1		T42	1		T252	3
all_levels[15]	auto[0]	189993	1			T5	1		T7	1		T8	595
all_levels[15]	auto[1]	59	1			T40	1		T268	1		T45	2
all_levels[16]	auto[0]	194199	1			T7	4		T8	1057		T9	51
all_levels[16]	auto[1]	29	1			T119	1		T127	1		T279	6
all_levels[17]	auto[0]	193445	1			T7	1		T8	1213		T9	55
all_levels[17]	auto[1]	34	1			T248	1		T134	2		T127	1
all_levels[18]	auto[0]	229621	1			T4	2		T7	1		T8	1297
all_levels[18]	auto[1]	21	1			T80	1		T215	2		T339	1
all_levels[19]	auto[0]	596243	1			T8	1373		T9	46		T28	4
all_levels[19]	auto[1]	13	1			T340	1		T197	1		T341	1
all_levels[20]	auto[0]	348878	1			T7	3		T8	1762		T9	54
all_levels[20]	auto[1]	23	1			T148	2		T172	1		T116	1
all_levels[21]	auto[0]	226930	1			T3	102		T7	1		T8	1761
all_levels[21]	auto[1]	30	1			T3	2		T112	1		T170	1
all_levels[22]	auto[0]	154117	1			T7	2		T8	1738		T9	51
all_levels[22]	auto[1]	21	1			T29	1		T333	1		T342	2
all_levels[23]	auto[0]	170391	1			T5	1		T8	1325		T9	54
all_levels[23]	auto[1]	16	1			T175	2		T132	1		T123	1
all_levels[24]	auto[0]	208338	1			T5	2		T7	19		T8	1520
all_levels[24]	auto[1]	22	1			T28	1		T343	2		T221	1
all_levels[25]	auto[0]	176496	1			T8	1618		T9	66		T28	2
all_levels[25]	auto[1]	19	1			T259	4		T41	1		T103	2
all_levels[26]	auto[0]	151610	1			T7	4		T8	1493		T9	57
all_levels[26]	auto[1]	14	1			T175	1		T123	1		T106	1
all_levels[27]	auto[0]	322497	1			T7	5		T8	506		T9	51
all_levels[27]	auto[1]	13	1			T45	1		T188	1		T311	1
all_levels[28]	auto[0]	208969	1			T7	2		T8	729		T9	52
all_levels[28]	auto[1]	10	1			T45	1		T344	1		T345	1
all_levels[29]	auto[0]	253097	1			T7	2		T8	728		T9	58
all_levels[29]	auto[1]	7	1			T346	2		T237	1		T347	1
all_levels[30]	auto[0]	240366	1			T7	1		T8	701		T9	52
all_levels[30]	auto[1]	16	1			T15	1		T204	1		T348	1
all_levels[31]	auto[0]	423020	1			T4	2		T7	3		T8	702
all_levels[31]	auto[1]	13	1			T9	1		T103	1		T153	1
all_levels[32]	auto[0]	11385778	1			T3	88		T4	4		T7	16
all_levels[32]	auto[1]	514	1			T3	2		T7	1		T8	1