Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	691	1			T8	4		T15	4		T32	14
all_values[1]	691	1			T8	4		T15	4		T32	14
all_values[2]	691	1			T8	4		T15	4		T32	14
all_values[3]	691	1			T8	4		T15	4		T32	14
all_values[4]	691	1			T8	4		T15	4		T32	14
all_values[5]	691	1			T8	4		T15	4		T32	14
all_values[6]	691	1			T8	4		T15	4		T32	14
all_values[7]	691	1			T8	4		T15	4		T32	14
all_values[8]	691	1			T8	4		T15	4		T32	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3339

1

T8

24

T15

27

T32

64

auto[1]

2880

1

T8

12

T15

9

T32

62

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2061

1

T8

13

T15

11

T32

24

auto[1]

4158

1

T8

23

T15

25

T32

102

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3653

1

T8

22

T15

23

T32

62

auto[1]

2566

1

T8

14

T15

13

T32

64

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	210	1			T8	1		T15	3		T32	2
all_values[0]	auto[0]	auto[1]	auto[1]	202	1			T8	2		T32	7		T35	2
all_values[0]	auto[1]	auto[0]	auto[1]	156	1			T8	1		T15	1		T32	3
all_values[0]	auto[1]	auto[1]	auto[1]	123	1			T32	2		T35	2		T37	2
all_values[1]	auto[0]	auto[0]	auto[0]	203	1			T8	1		T32	3		T80	2
all_values[1]	auto[0]	auto[1]	auto[0]	193	1			T15	1		T32	1		T80	1
all_values[1]	auto[1]	auto[0]	auto[1]	167	1			T8	3		T15	1		T32	4
all_values[1]	auto[1]	auto[1]	auto[1]	128	1			T15	2		T32	6		T37	1
all_values[2]	auto[0]	auto[0]	auto[0]	164	1			T8	1		T32	2		T35	1
all_values[2]	auto[0]	auto[0]	auto[1]	72	1			T32	2		T80	2		T35	1
all_values[2]	auto[0]	auto[1]	auto[0]	113	1			T35	1		T107	2		T108	4
all_values[2]	auto[0]	auto[1]	auto[1]	59	1			T15	3		T32	1		T80	1
all_values[2]	auto[1]	auto[0]	auto[1]	160	1			T8	1		T15	1		T32	5
all_values[2]	auto[1]	auto[1]	auto[1]	123	1			T8	2		T32	4		T80	1
all_values[3]	auto[0]	auto[0]	auto[0]	133	1			T8	1		T80	1		T35	4
all_values[3]	auto[0]	auto[0]	auto[1]	76	1			T15	1		T32	4		T107	4
all_values[3]	auto[0]	auto[1]	auto[0]	115	1			T8	1		T32	2		T35	2
all_values[3]	auto[0]	auto[1]	auto[1]	67	1			T15	1		T80	1		T37	2
all_values[3]	auto[1]	auto[0]	auto[1]	150	1			T8	2		T15	2		T32	4
all_values[3]	auto[1]	auto[1]	auto[1]	150	1			T32	4		T35	4		T37	2
all_values[4]	auto[0]	auto[0]	auto[0]	151	1			T8	2		T15	2		T32	1
all_values[4]	auto[0]	auto[0]	auto[1]	69	1			T35	2		T37	1		T107	1
all_values[4]	auto[0]	auto[1]	auto[0]	134	1			T8	1		T32	4		T35	3
all_values[4]	auto[0]	auto[1]	auto[1]	53	1			T35	2		T109	1		T110	1
all_values[4]	auto[1]	auto[0]	auto[1]	153	1			T15	2		T32	7		T80	2
all_values[4]	auto[1]	auto[1]	auto[1]	131	1			T8	1		T32	2		T35	2
all_values[5]	auto[0]	auto[0]	auto[0]	147	1			T8	1		T15	3		T32	2
all_values[5]	auto[0]	auto[0]	auto[1]	63	1			T8	2		T32	1		T35	1
all_values[5]	auto[0]	auto[1]	auto[0]	125	1			T15	1		T32	4		T80	4
all_values[5]	auto[0]	auto[1]	auto[1]	66	1			T32	2		T35	1		T107	2
all_values[5]	auto[1]	auto[0]	auto[1]	152	1			T8	1		T32	1		T35	1
all_values[5]	auto[1]	auto[1]	auto[1]	138	1			T32	4		T35	1		T37	1
all_values[6]	auto[0]	auto[0]	auto[0]	149	1			T8	1		T15	4		T32	5
all_values[6]	auto[0]	auto[0]	auto[1]	74	1			T8	1		T32	3		T80	1
all_values[6]	auto[0]	auto[1]	auto[0]	126	1			T35	3		T37	1		T107	1
all_values[6]	auto[0]	auto[1]	auto[1]	65	1			T8	1		T32	1		T80	1
all_values[6]	auto[1]	auto[0]	auto[1]	139	1			T32	2		T35	3		T37	1
all_values[6]	auto[1]	auto[1]	auto[1]	138	1			T8	1		T32	3		T80	2
all_values[7]	auto[0]	auto[0]	auto[0]	176	1			T8	2		T37	4		T107	2
all_values[7]	auto[0]	auto[0]	auto[1]	61	1			T15	2		T32	2		T80	1
all_values[7]	auto[0]	auto[1]	auto[0]	132	1			T8	2		T35	5		T107	3
all_values[7]	auto[0]	auto[1]	auto[1]	66	1			T32	4		T35	1		T37	1
all_values[7]	auto[1]	auto[0]	auto[1]	145	1			T15	2		T32	3		T80	3
all_values[7]	auto[1]	auto[1]	auto[1]	111	1			T32	5		T35	3		T37	2
all_values[8]	auto[0]	auto[0]	auto[1]	212	1			T8	2		T15	1		T32	6
all_values[8]	auto[0]	auto[1]	auto[1]	177	1			T15	1		T32	3		T80	1
all_values[8]	auto[1]	auto[0]	auto[1]	157	1			T8	1		T15	2		T32	2
all_values[8]	auto[1]	auto[1]	auto[1]	145	1			T8	1		T32	3		T80	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal